LT3741/LT3741-1

High Power, Constant

Current, Constant Voltage,
Step-Down Controller
FEATURES DESCRIPTION
nn Control Pin Provides Accurate Control of Regulated The LT®3741 and LT3741-1 are fixed frequency synchro-
Output Current nous step-down DC/DC controllers designed to accurately
nn ±1.5% Voltage Regulation Accuracy regulate the output current at up to 20A. The average current-
nn ±6% Current Regulation Accuracy mode controller will maintain inductor current regulation
nn 6V to 36V Input Voltage Range over a wide output voltage range of 0V to (VIN – 2V). The
nn Wide Output Voltage Range Up to (V – 2V) regulated current is set by an analog voltage on the CTRL
IN
nn Average Current Mode Control pins and an external sense resistor. Due to its unique
nn <1µA Shutdown Current topology, the LT3741 is capable of sourcing and sinking
nn Up to 94% Efficiency current. If sinking current is not required, or for parallel
nn Additional Pin for Thermal Control of Load Current applications, use the LT3741-1. The regulated voltage and
nn Thermally Enhanced 4mm × 4mm QFN and 20-Pin overvoltage protection are set with a voltage divider from
FE Package the output to the FB pin. Soft-Start is provided to allow a
gradual increase in the regulated current during startup.
The switching frequency is programmable from 200kHz to
APPLICATIONS 1MHz through an external resistor on the RT pin or through
nn General Purpose Industrial the use of the SYNC pin and an external clock signal.
nn Super-Cap Charging Additional Features include an accurate external reference
nn Applications Needing Extreme Short-Circuit Protec-
voltage for use with the CTRL pins, an accurate UVLO/EN
tion and/or Accurate Output Current Limit pin that allows for programmable UVLO hysteresis, and
nn Constant Current or Constant Voltage Source
thermal shutdown.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 7199560, 7321203 and others pending.

TYPICAL APPLICATION
10V/20A Constant Current, Constant Voltage Step-Down Converter

EN/UVLO EN/UVLO VIN VIN VOUT vs IOUT

14V TO 36V
RT 1µF 100µF 12
82.5k SYNC
HG 10
LT3741 220nF
VREF
CBOOT 2.2µH 2.5mΩ VOUT
10nF 8
SW 10V
20A
VOUT (V)

CTRL1
VCC_INT 6
VC
22µF
RHOT 39.2k 4
LG 150µF
45.3k 5.6nF ×2
GND
2 VIN = 18V
CTRL2 SENSE+ VOUT = 10V
SENSE– 88.7k ILIMIT = 20A
RNTC 0
SS FB 0 2 4 6 8 10 12 14 16 18 20 22
10nF
12.1k IOUT (A)
3741 TA01b
3741 TA01a

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LT3741/LT3741-1
ABSOLUTE MAXIMUM RATINGS (Note 1)
VIN Voltage.................................................................40V
EN/UVLO Voltage.........................................................6V
VREF Voltage................................................................3V
CTRL1 and CTRL2 Voltage...........................................3V
SENSE+ Voltage.........................................................40V
SENSE– Voltage.........................................................40V
VC Voltage...................................................................3V
SW Voltage................................................................40V
CBOOT.......................................................................46V
RT Voltage...................................................................3V
FB Voltage....................................................................3V
SS Voltage...................................................................6V
VCC_INT Voltage............................................................6V
SYNC Voltage...............................................................6V
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
TSSOP............................................................... 300°C

PIN CONFIGURATION
TOP VIEW
TOP VIEW
VCC_INT

CBOOT

VCC_INT 1 20 LG
SW
VIN

LG

20 19 18 17 16 GND 2 19 CBOOT
VIN 3 18 SW
EN/UVLO 1 15 HG
EN/UVLO 4 17 HG
VREF 2 14 GND
VREF 5 21 16 GND
21
CTRL2 3 13 SYNC GND
GND CTRL2 6 15 SYNC
GND 4 12 RT
GND 7 14 RT
CTRL1 5 11 GND
CTRL1 8 13 VC
6 7 8 9 10 SS 9 12 SENSE–
FB 10 11 SENSE+
SS
FB
SENSE+
SENSE–
VC

FE PACKAGE
UF PACKAGE 20-LEAD PLASTIC TSSOP
20-LEAD (4mm × 4mm) PLASTIC QFN TJMAX = 125°C, qJA = 38°C/W
TJMAX = 125°C, qJA = 37°C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB

ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3741EUF#PBF LT3741EUF#TRPBF 3741 20-Lead (4mm × 4mm) Plastic QFN –40°C to 125°C
LT3741IUF#PBF LT3741IUF#TRPBF 3741 20-Lead (4mm × 4mm) Plastic QFN –40°C to 125°C
LT3741EFE#PBF LT3741EFE#TRPBF LT3741FE 20-Lead Plastic TSSOP –40°C to 125°C
LT3741IFE#PBF LT3741IFE#TRPBF LT3741FE 20-Lead Plastic TSSOP –40°C to 125°C
LT3741EUF-1#PBF LT3741EUF-1#TRPBF 37411 20-Lead (4mm × 4mm) Plastic QFN –40°C to 125°C
LT3741IUF-1#PBF LT3741IUF-1#TRPBF 37411 20-Lead (4mm × 4mm) Plastic QFN –40°C to 125°C
LT3741EFE-1#PBF LT3741EFE-1#TRPBF LT3741FE-1 20-Lead Plastic TSSOP –40°C to 125°C
LT3741IFE-1#PBF LT3741IFE-1#TRPBF LT3741FE-1 20-Lead Plastic TSSOP –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
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ELECTRICAL
CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VEN/UVLO = 5V, VSYNC = 0V unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Input Voltage Range l 6 36 V
VIN Pin Quiescent Current (Note 2)
Non-Switching Operation Not Switching 1.8 2.5 mA
Shutdown Mode VEN/UVLO = 0V, RT = 40kΩ l 0.1 1 µA
EN/UVLO Pin Falling Threshold 1.49 1.55 1.61 V
EN/UVLO Hysteresis 130 mV
EN/UVLO Pin Current VIN = 6V, EN/UVLO = 1.45V 5.5 µA
SYNC Pin Threshold 1 V
CTRL1 Pin Control Range 0 1.5 V
CTRL1 Pin Current CTRL1 = 1.5V –100 nA
Reference
Reference Voltage (VREF Pin) l 1.94 2 2.06 V
Inductor Current Sensing
Full Range SENSE+ to SENSE– VCTRL1 = 1.5V l 48 51 54 mV
SENSE+ Pin Current VSENSE + = 6V 50 nA
SENSE– Pin Current With VOUT ~ 4V, VCTRL1 = 0V, VSENSE– = 6V 10 µA
Internal VCC Regulator (VCC_INT Pin)
Regulation Voltage l 4.7 5 5.2 V
NMOS FET Driver
Non-Overlap time HG to LG (Note 3) 100 ns
Non-Overlap time LG to HG (Note 3) 60 ns
Minimum On-Time LG (Note 3) 50 ns
Minimum On-Time HG (Note 3) 80 ns
Minimum Off-Time LG (Note 3) 65 ns
High Side Driver Switch On-Resistance VCBOOT – VSW = 5V
Gate Pull Up 2.3 Ω
Gate Pull Down 1.3 Ω
Low Side Driver Switch On-Resistance VCC_INT = 5V
Gate Pull Up 2.3 Ω
Gate Pull Down 1 Ω
Switching Frequency
fSW RT = 40kΩ l 900 1000 1070 kHz
RT = 200kΩ 185 200 233 kHz
Soft-Start
Charging Current 11 µA
Voltage Regulation Amplifier
Input Bias Current FB = 1.3V 850 nA
gm 800 µA/V
Feedback Regulation Voltage CTRL1 = 1.5V, ISENSE– = 23µA, VSENSE+ = 2V l 1.192 1.21 1.228 V

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LT3741/LT3741-1
ELECTRICAL
CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VEN/UVLO = 5V, VSYNC = 0V unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Current Control Loop gm Amp
Offset Voltage VCM =4V l –3 0 3 mV
Input Common Mode Range
VCM(LOW) 0 V
VCM(HIGH) VCM(HIGH) Measured from VIN to VCM 2 V
Output Impedance 3.5 MΩ
gm 375 475 625 µA/V
Differential Gain 1.7 V/mV

Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3741E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3741I is guaranteed to meet performance specifications over the –40°C
to 125°C operating junction temperature range.
Note 3: The minimum on, off, and nonoverlap times are guaranteed by
design and are not tested.

TYPICAL PERFORMANCE CHARACTERISTICS

EN/UVLO Threshold (Falling) EN/UVLO Pin Current
1.70 10

1.64 8
EN/UVLO PIN CURRENT (µA)
EN/UVLO THRESHOLD (V)

1.58 6
–50°C

1.52 4
130°C

1.46 2 25°C
130°C
–50°C
1.40 0
6 12 18 24 30 36 6 12 18 24 30 36
VIN (V) VIN (V)
3741 G01 3741 G02

IQ in Shutdown Quiescent Current (Non-Switching)

0.5 2.0

0.4 1.6
QUIESCENT CURRENT (mA)

0.3 1.2
IQ (µA)

130°C
0.2 0.8

0.1 0.4 TA = 25°C

TA = 130°C
25°C TA = –50°C
0 0
0 8 16 24 32 40 6 12 18 24 30 36
VIN (V) VIN (V)
3741 G03 3741 G04

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TYPICAL PERFORMANCE CHARACTERISTICS
VREF Pin Voltage VREF Current Limit RT Pin Current Limit
2.06 1.6 90

2.05
80
2.04 1.4
VIN = 36V TA = 25°C
VREF VOLTAGE (V)

2.03 70

ILIMIT (mA)

ILIMIT (µA)
TA = 130°C
VIN = 6V
2.02 1.2

2.01 60
TA = –50°C
2.00 1.0
50
1.99

1.98 0.8 40
–50 –15 20 55 90 125 6 12 18 24 30 36 –50 –15 20 55 90 125
TEMPERATURE (°C) VIN (V) TEMPERATURE (°C)
3741 G05 3741 G06 3741 G08

Soft-Start Pin Current VCC_INT Current Limit Internal UVLO

14 6 5.0

13
5
12 4.5
VIN = 36V
4
11
VCC_INT (V)

VIN = 6V
ISS (µA)

VIN (V)
10 3 4.0

9
2
8 3.5
1
7 VIN = 12V
TA = 25°C
6 0 3.0
–50 –15 20 55 90 125 0 10 20 30 40 50 60 –50 –15 20 55 90 125
TEMPERATURE (°C) ILOAD (mA) TEMPERATURE (°C)
3741 G09 3741 G07 3741 G10

CBOOT-SW UVLO Voltage VCC_INT UVLO VCC_INT Load Reg at 12V

3.00 4.00 6.0

2.75 3.75
5.6

2.50 3.50
VOLTAGE (V)

5.2
VCC_INT (V)
UVLO (V)

2.25 3.25
25°C
4.8
2.00 3.00

4.4
1.75 2.75

1.50 2.50 4.0

–50 –15 20 55 90 125 –50 –15 20 55 90 125 0 10 20 30 40 50 60
TEMPERATURE (°C) TEMPERATURE (°C) ILOAD (mA)
3741 G11 3741 G12 3741 G13

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 LT3741/LT3741-1
TYPICAL PERFORMANCE CHARACTERISTICS
Regulated Current vs VFB Overvoltage Threshold Overvoltage Timeout
150 1.75 19

100

OVERVOLTAGE THRESHOLD (V)

1.65 17

OVERVOLTAGE TIMEOUT (µs)

CONTROL CURRENT (%)

50
1.55 15
0
LT3741-1
1.45 13
–50

1.35 11
–100
LT3741

–150 1.25 9
1.10 1.15 1.20 1.25 1.30 1.35 –50 –25 0 25 50 75 100 125 –50 –15 20 55 90 125
VFB (V) TEMPERATURE (°C) TEMPERATURE (°C)
3741 G14 3741 G15 3741 G16

Regulated Sense Voltage Common Mode Lockout HG Driver RDS(ON)

60 2.5 5
MEASURED VIN – VOUT

50
2.0 VIN = 6V 4
VSENSE+ – VSENSE– (mV)

40
CM LOCKOUT (V)

RDS(ON) (Ω)
1.5 VIN = 36V
PULL-UP
30
1.0 2
20
PULL-DOWN
0.5 1
10

0 0 0
0 0.5 1.0 1.5 2.0 –50 –15 20 55 90 125 –50 –15 20 55 90 125
VCTRL (V) TEMPERATURE (°C) TEMPERATURE (°C)
3741 G17 3741 G18 3741 G20

LG Driver RDS(ON) Minimum Off-Time Non-Overlap Time

5 300 150

4 240 120
HG HG TO LG
NON-OVERLAP TIME (ns)
MINIMUM OFF-TIME (ns)

3 180 90
RDS(ON) (Ω)

PULL-UP
LG TO HG
2 120 60

PULL-DOWN LG
1 60 30

0 0 0
–50 –15 20 55 90 125 –50 –15 20 55 90 125 –50 –15 20 55 90 125
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
3741 G21 3741 G25 3741 G23

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TYPICAL PERFORMANCE CHARACTERISTICS
Minimum On-Time Oscillator Frequency Overcurrent Threshold
150 1.5 120
1.2MHz
100
120 1.2
MINIMUM ON-TIME (ns)

VSENSE+ – VSENSE– (mV)

FREQUENCY (MHz)
900kHz 80
90 0.9
HG 60
60 0.6
40
LG
30 0.3 220kHz
20

0 0 0
–50 –15 20 55 90 125 –50 –15 20 55 90 125 0 0.75 1.5 2.25 3.0
TEMPERATURE (°C) TEMPERATURE (°C) CTRL_H (V)
3741 G24 3741 G36 3741 G28

Current Regulation Accuracy Current Regulation Accuracy

CTRL1 = 1.5V, VIN = 12V CTRL1 = 0.75V, VIN = 12V VOUT vs IOUT
3 6 6

2 4 5

1 2 4
ACCURACY (%)

ACCURACY (%)

VOUT (V)
0 0 3
25°C
25°C
–1 –2 2

–2 –4 1 VIN = 20V
VOUT = 5V
ILIMIT = 24A
–3 –6 0
0 2.5 5.0 7.5 10 0 2.5 5.0 7.5 10 0 2 4 6 8 10 12 14 16 18 20 22 24 26
OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) IOUT (A)
3741 G26 3741 G27 3741 G19

VOUT vs IOUT VOUT vs IOUT

25 12

10
20

8
15
VOUT (V)
VOUT (V)

6
10
4

5 V = 25V
IN 2 VIN = 24V
VOUT = 20V VOUT = 10V
ILIMIT = 9.5A ILIMIT = 18A
0 0
0 1 2 3 4 5 6 7 8 9 10 0 2 4 6 8 10 12 14 16 18 20
IOUT (A) IOUT (A)
3741 G22 3741 G33

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LT3741/LT3741-1
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency and Power Loss Efficiency and Power Loss Efficiency and Power Loss
vs Load Current vs Load Current vs Load Current
100 100 100
LT3741
LT3741
90
95 90
LT3741-1 LT3741-1
LT3741-1
80 LT3741

EFFICIENCY (%)
EFFICIENCY (%)
EFFICIENCY (%)

90 80
70
85 70
60

80 60
50
VIN = 20V VIN = 25V VIN = 24V
VOUT = 5V VOUT = 20V VOUT = 10V
40 75 50
0.1 1 10 100 0.1 1 10 0.1 1 10 100
LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)
3741 G29 3741 G30 3741 G37

Voltage Regulation with 10A

5A Load Step Recovery Regulated Inductor Current

VOUT
20mV/DIV VOUT
AC-COUPLED 2V/DIV

IL
IL
2A/DIV
5A/DIV

3741 G31 3741 G34

20ms/DIV 100µs/DIV
COUT = 470µF

Shutdown and Recovery

Common Mode Lockout — LT3741 1.5nF Soft-Start Capacitor

EN/UVLO
5V/DIV
VOUT
2V/DIV IL
5A/DIV

IL
200mA/DIV VOUT
2V/DIV

3741 G32
1ms/DIV 3741 G35 100µs/DIV
VIN = 7V COUT = 1mF
VOUT = 5V
10A LOAD
18A CURRENT LIMIT

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PIN FUNCTIONS (QFN/TSSOP)
EN/UVLO (Pin 1/Pin 4): Enable Pin. The EN/UVLO pin
acts as an enable pin and turns on the internal current
bias core and subregulators at 1.55V. The pin does
not have any pull-up or pull-down, requiring a voltage
bias for normal part operation. Full shutdown occurs at
approximately 0.5V.
VREF (Pin 2/Pin 5): Buffered 2V reference capable of
0.5mA drive.
CTRL2 (Pin 3/Pin 6): Thermal control input used to reduce
the regulated current level.
GND (Pins 4,11,14, Exposed Pad Pin 21/Pins 2,7,16,
Exposed Pad Pin 21): Ground. The exposed pad must be
soldered to the PCB
CTRL1 (Pin 5/Pin 8): The CTRL1 pin sets the high level
regulated output current and overcurrent. The maximum
input voltage is internally clamped to 1.5V. The overcurrent
set point is equal to the high level regulated current level set
by the CTRL1 pin with an additional 23mV offset between
the SENSE+ and SENSE– pins.
SS (Pin 6/Pin 9): The Soft-Start Pin. Place an external
capacitor to ground to limit the regulated current during
start-up conditions. The soft-start pin has a 11µA charg-
ing current. This pin controls regulated output current
determined by CTRL1.
FB (Pin 7/Pin 10): Feedback Pin for Voltage Regulation
and Overvoltage Protection. The feedback voltage is 1.21V.
Overvoltage is also sensed through the FB pin. When the
feedback voltage exceeds 1.5V, the overvoltage lockout
prevents switching for 13μs to allow the inductor current
to discharge.
SENSE+ (Pin 8/Pin 11): SENSE+ is the inverting input of
the average current mode loop error amplifier. This pin is
connected to the external current sense resistor, RS . The
voltage drop between SENSE+ and SENSE– referenced to
the voltage drop across an internal resistor produces the
input voltages to the current regulation loop.
SENSE– (Pin 9/Pin 12): SENSE– is the non-inverting
input of the average current mode loop error amplifier.
The reference current, based on CTRL1 or CTRL2 flows
out of the pin to the output side of the sense resistor, RS .
For more information www.linear.com/LT3741
LT3741/LT3741-1
VC (Pin 10/Pin 13): VC provides the necessary comp­
ensation for the average current loop stability. Typical
compensation values are 20k to 50k for the resistor and
2nF to 5nF for the capacitor.
RT (Pin 12/Pin 14): A resistor to ground sets the switching
frequency between 200kHz and 1MHz. When using the
SYNC function, set the frequency to be 20% lower than
the SYNC pulse frequency. This pin is current limited to
60µA. Do not leave this pin open.
SYNC (Pin 13/Pin 15): Frequency Synchronization Pin.
This pin allows the switching frequency to be synchronized
to an external clock. The RT resistor should be chosen to
operate the internal clock at 20% slower than the SYNC
pulse frequency. This pin should be grounded when not
in use. When laying out board, avoid noise coupling to
or from SYNC trace.
HG (Pin 15/Pin 17): HG is the top-FET gate drive signal
that controls the state of the high-side external power
FET. The driver pull-up impedance is 2.3Ω and pull-down
impedance is 1.3Ω.
SW (Pin 16/Pin 18): The SW pin is used internally as the
lower-rail for the floating high-side driver. Externally, this
node connects the two power-FETs and the inductor.
CBOOT (Pin 17/Pin 19): The CBOOT pin provides a float-
ing 5V regulated supply for the high-side FET driver. An
external Schottky diode is required from the VCC_INT pin
to the CBOOT pin to charge the CBOOT capacitor when
the switch-pin is near ground.
LG (Pin 18/Pin 20): LG is the bottom-FET gate drive signal
that controls the state of the low-side external power-FET.
The driver pull-up impedance is 2.3Ω and pull-down
impedance is 1.0Ω.
VCC_INT (Pin 19/Pin 1): A regulated 5V output for charging
the CBOOT capacitor. VCC_INT also provides the power
for the digital and switching subcircuits. Below 6V VIN,
tie this pin to the rail. VCC_INT is current limited to 50mA.
Shutdown operation disables the output voltage drive.
VIN (Pin 20/Pin 3): Input Supply Pin. Must be locally
bypassed with a 4.7μF low-ESR capacitor to ground.
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LT3741/LT3741-1
BLOCK DIAGRAM (QFN Package)
VIN
VIN
20 VIN
402k 1µF 47µF
EN/UVLO
1
INTERNAL
133k VCC_INT
REGULATOR
19
AND 10µF
VREF UVLO
2 2V REFERENCE
100nF
HIGH SIDE
CBOOT
DRIVER 17
SYNC
SYNC 13 – HG
15 0.1µF
RT OSCILLATOR
12 SYNCRONOUS SW
R Q 16
82.5k CONTROLLER
+ S
LG
18
PWM 2.4µH
COMPARATOR
LOW SIDE
DRIVER
– SENSE+
8
RS
1.5V 3k 5mΩ
+ SENSE–
CURRENT gm AMP 9 VOUT
MIRROR gm = 475µA/V
+ RO = 3.5M
150µF
×2
CTRL1 + 11µA IOUT = 40µA
5

– 40.2k
– FB
CTRL BUFFER 7
SS 10k
6
90k + 1.21V
100nF
CTRL2 VOLTAGE
3 REGULATOR
VC AMP
10 gm = 850µA/V
40.2k
5.6µF 3741 F01

Figure 1. Block Diagram, LT3741

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 LT3741/LT3741-1
BLOCK DIAGRAM (QFN Package)

VIN
VIN
20 VIN
402k 1µF 47µF
EN/UVLO
1
INTERNAL
133k VCC_INT
REGULATOR
19
AND 10µF
VREF UVLO
2 2V REFERENCE
100nF
HIGH SIDE
CBOOT
DRIVER 17
SYNC
SYNC 13 – HG
15 0.1µF
RT OSCILLATOR
12 SYNCRONOUS SW
R Q 16
82.5k CONTROLLER
+ S
LG
18
PWM 2.4µH
COMPARATOR
LOW SIDE
DRIVER
ZERO CROSS
COMPARATOR

+ –
– SENSE+
8
RS
1.5V 3k 5mΩ
+ SENSE–
CURRENT gm AMP 9 VOUT
MIRROR gm = 475µA/V
+ RO = 3.5M
150µF
×2
CTRL1 + 11µA IOUT = 40µA
5

– 40.2k
– FB
CTRL BUFFER 7
SS 10k
6
90k + 1.21V
100nF
CTRL2 VOLTAGE
3 REGULATOR
VC AMP
10 gm = 850µA/V
40.2k
5.6µF 3741 F01

Figure 2. Block Diagram, LT3741-1

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LT3741/LT3741-1
OPERATION
The LT3741 utilizes fixed-frequency, average current
mode control to accurately regulate the inductor current,
independently from the output voltage. This is an ideal solu-
tion for applications requiring a regulated current source.
The control loop will regulate the current in the inductor
at an accuracy of ±6%. Once the output has reached the
regulation voltage determined by the resistor divider from
the output to the FB pin and ground, the inductor current
will be reduced by the voltage regulation loop. In voltage
regulation, the output voltage has an accuracy of ±1.5%.
For additional operation information, refer to the Block
Diagram in Figure 1.
The current control loop has two reference inputs, deter-
mined by the voltage at the analog control pins, CTRL1 and
CTRL2. The lower of the two analog voltages on CTRL1
and CTRL2 determines the regulated output current. The
analog voltage at the CTRL1 pin is buffered and produces
a reference voltage across an internal resistor. The internal
buffer has a 1.5V clamp on the output, limiting the analog
control range of the CTRL1 and CTRL2 pins from 0V to
1.5V – corresponding to a 0mV to 51mV range on the
sense resistor, RS. The average current-mode control
loop uses the internal reference voltage to regulate the
inductor current, as a voltage drop across the external
sense resistor, RS.
A 2V reference voltage is provided on the VREF pin to al-
low the use of a resistor voltage divider to the CTRL1 and
CTRL2 pins. The VREF pin can supply up to 500μA and is
current limited to 1mA.
The error amplifier for the average current-mode control
loop has a common mode lockout that regulates the induc-
tor current so that the error amplifier is never operated out
of the common mode range. The common mode range is
from 0V to 2V below the VIN supply rail.
The overcurrent set point is equal to the regulated current
level set by the CTRL1 pin with an additional 23mV offset
between the SENSE+ and SENSE– pins. The overcurrent
is limited on a cycle-by-cycle basis; shutting switching
down once the overcurrent level is reached. Overcurrent
is not soft-started.
The regulated output voltage is set with a resistor divider
from the output back to the FB pin. The reference at the
FB pin is 1.21V. If the output voltage level is high enough
to engage the voltage loop, the regulated inductor current
will be reduced to support the load at the output. If the
voltage at the FB pin reaches 1.5V (~25% higher than the
regulation level), an internal overvoltage flag is set, shut-
ting down switching for 13μs.
The EN/UVLO pin functions as a precision shutdown
pin. When the voltage at the EN/UVLO pin is lower than
1.55V, the internal reset flag is asserted and switching is
terminated. Full shutdown occurs at approximately 0.5V
with a quiescent current of less than 1μA in full shutdown.
The EN/UVLO pin has 130mV of built-in hysteresis. In
addition, a 5.5µA current source is connected to this pin
that allows any amount of hysteresis to be added with a
series resistor or resistor divider from VIN.
During startup, the SS pin is held low until the internal
reset goes low. Once reset goes low, the capacitor at the
soft-start pin is charged with an 11μA current source.
The internal buffers for the CTRL1 and CTRL2 signals are
limited by the voltage at the soft-start pin, slowly ramping
the regulated inductor current to the current determined
by the voltage at the CTRL1 or CTRL2 pins.
The thermal shutdown is set at 163°C with 8°C hysteresis.
During thermal shutdown, all switching is terminated and
the part is in reset (forcing the SS pin low).
The switching frequency is determined by a resistor at
the RT pin. The RT pin is also limited to 60µA, while not
recommended, this limits the switching frequency to 2MHz
when the RT pin is shorted to ground. The LT3741 may
also be synchronized to an external clock through the use
of the SYNC pin.

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12 For more information www.linear.com/LT3741

 LT3741/LT3741-1
APPLICATIONS INFORMATION
Programming Inductor Current Inductor Selection
The analog voltage at the CTRL1 pin is buffered and pro- Size the inductor to have approximately 30% peak-to-peak
duces a reference voltage, VCTRL, across an internal resistor. ripple. The overcurrent set point is equal to the high level
The regulated average inductor current is determined by: regulated current level set by the CTRL1 pin with an addi-
VCTRL1 tional 23mV offset between the SENSE+ and SENSE– pins.
IO = The saturation current for the inductor should be at least
30 •RS 20% higher than the maximum regulated current. The fol-

lowing equation sizes the inductor for best performance:
where RS is the external sense resistor and IO is the aver-
age inductor current, which is equal to the output current. VIN • VO – VO2
Figure 2 shows the maximum output current vs RS. The L=
maximum power dissipation in the resistor will be:
0.3 • fS •IO • VIN

PRS =
(0.05V )2 where VO is the output voltage, IO is the maximum regulated
RS current in the inductor and fS is the switching frequency.
Using this equation, the inductor will have approximately
Table 1 contains several resistors values, the correspond- 15% ripple at maximum regulated current.
ing maximum current and power dissipation in the sense Table 2. Recommended Inductor Manufacturers
resistor. Susumu, Panasonic and Vishay offer accurate VENDOR WEBSITE
sense resistors. Figure 3 shows the power dissipation in RS. Coilcraft www.coilcraft.com
Table 1. Sense Resistor Values Sumida www.sumida.com
MAXIMUM OUTPUT Vishay www.vishay.com
CURRENT (A) RESISTOR, RS (mΩ) POWER DISSIPATION (W) Wurth Electronics www.we-online.com
1 50 0.05 NEC-Tokin www.nec-tokin.com
5 10 0.25
10 5 0.5
1.4
25 2 1.25
1.2
POWER DISSIPATION (W)

1.0
30
0.8
25
MAXIMUM OUTPUT CURRENT (A)

0.6

20 0.4

15 0.2

0
10 0 2 4 6 8 10 12 14 16 18 20
RS (mΩ)
5 3741 F03

Figure 3. Power Dissipation in RS

0
0 2 4 6 8 10 12 14 16 18 20
RS (mΩ) Switching MOSFET Selection
3741 F02

Figure 2. RS Value Selection for Regulated Output Current When selecting switching MOSFETs, the following pa-
rameters are critical in determining the best devices for
a given application: total gate charge (QG), on-resistance
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LT3741/LT3741-1
APPLICATIONS INFORMATION
(RDS(ON)), gate to drain charge (QGD), gate-to-source
charge (QGS), gate resistance (RG), breakdown voltages
(maximum VGS and VDS) and drain current (maximum ID).
The following guidelines provide information to make the
selection process easier.
Both of the switching MOSFETs need to have their maximum
rated drain currents greater than the maximum inductor current.
The following equation calculates the peak inductor current:
VIN • VO – VO2
IMAX =IO +
2 • fS •L • VIN
where VIN is the input voltage, L is the inductance value, VO
is the output voltage, IO is the regulated output current and fS
is the switching frequency. During MOSFET selection, notice
that the maximum drain current is temperature dependant.
Most data sheets include a table or graph of the maximum
rated drain current vs temperature.
The maximum VDS should be selected to be higher than the
maximum input supply voltage (including transient) for both
MOSFETs. The signals driving the gates of the switching
MOSFETs have a maximum voltage of 5V with respect to the
source. During start-up and recovery conditions, the gate drive
signals may be as low as 3V. To ensure that the LT3741 recov-
ers properly, the maximum threshold should be less than 2V.
For a robust design, select the maximum VGS greater than 7V.
Power losses in the switching MOSFETs are related to the
on-resistance, RDS(ON); the transitional loss related to the gate
resistance, RG; gate-to-drain capacitance, QGD and gate-to-
source capacitance, QGS. Power loss to the on-resistance is
an Ohmic loss, I2 RDS(ON), and usually dominates for input
voltages less than ~15V. Power losses to the gate capacitance
dominate for voltages greater than ~12V. When operating at
higher input voltages, efficiency can be optimized by selecting
a high side MOSFET with higher RDS(ON) and lower CGD. The
power loss in the high side MOSFET can be approximated by:
PLOSS = (ohmic loss) + (transition loss)
PLOSS
( VO ) •I 2
RDS(ON) • +
O T
VIN
VIN •IOUT
5V
(
• (QGD +QGS ) • ( 2 •RG +RPU +RPD ) • fS )
14 For more information www.linear.com/LT3741
where rT is a temperature-dependant term of the MOS-
FET’s on-resistance. Using 70°C as the maximum ambient
operating temperature, rT is roughly equal to 1.3. RPD and
RPU are the LT3741 high side gate driver output imped-
ance, 1.3Ω and 2.3Ω respectively.
A good approach to MOSFET sizing is to select a high side
MOSFET, then select the low side MOSFET. The trade-
off between RDS(ON), QG, QGD and QGS for the high side
MOSFET is shown in the following example. VO is equal
to 4V. Comparing two N-channel MOSFETs, with a rated
VDS of 40V and in the same package, but with 8× different
RDS(ON) and 4.5× different QG and QGD:
M1: RDS(ON) = 2.3mΩ, QG = 45.5nC,
QGS = 13.8nC, QGD = 14.4nC , RG = 1Ω
M2: RDS(ON) = 18mΩ, QG = 10nC,
QGS = 4.5nC, QGD = 3.1nC , RG = 3.5Ω
Power loss for both MOSFETs is shown in Figure 4. Ob-
serve that while the RDS(ON) of M1 is eight times lower, the
power loss at low input voltages is equal, but four times
higher at high input voltages than the power loss for M2.
Power loss within the low side MOSFET is almost entirely
from the RDS(ON) of the FET. Select a low side FET with
the lowest RDS(ON) while keeping the total gate charge QG
to 30nC or less.
Another power loss related to switching MOSFET selection
is the power lost to driving the gates. The total gate charge,
QG, must be charged and discharged each switching cycle.
The power is lost to the internal LDO within the LT3741.
The power lost to the charging of the gates is:
PLOSS_LDO ≈ (VIN – 5V) • (QGLG + QGHG) • fS
where QGLG is the low side gate charge and QGHG is the
high side gate charge.
Whenever possible, utilize a switching MOSFET that
minimizes the total gate charge to limit the internal power
dissipation of the LT3741.
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 LT3741/LT3741-1
APPLICATIONS INFORMATION
7 2.5

6
2.0

MOSFET POWER LOSS (W)

MOSFET POWER LOSS (W)

5
TOTAL 1.5
4 TOTAL
TRANSITIONAL
3 1.0
TRANSITIONAL
2
0.5 OHMIC
1
OHMIC
0 0
0 10 20 30 40 0 10 20 30 40
INPUT VOLTAGE (V) INPUT VOLTAGE (V)
3741 F04a 3741 F04b

Figure 4a. Power Loss Example for M1 Figure 4b. Power Loss Example for M2
Figure 4

Table 3. Recommended Switching FETs 20µF/A of load current should be used in most designs.
VIN VOUT IOUT The capacitors also need to be surge rated to the maximum
(V) (V) (A) TOP FET BOTTOM FET MANUFACTURER output current. To achieve the lowest possible ESR, several
8 4 5-10 RJK0365DPA RJK0330DPB Renesas low ESR capacitors should be used in parallel. Many ap-
24 4 5 RJK0368DPA RJK0332DPB www.renesas.com plications benefit from the use of high density POSCAP
24 2-4 20 RJK0365DPA RJK0346DPA capacitors, which are easily destroyed when exposed to
12 2-4 10 FDMS8680 FDMS8672AS Fairchild overvoltage conditions. To prevent this, select POSCAP
www.fairchildsemi. capacitors that have a voltage rating that is at least 50%
com
higher than the regulated voltage
36 4 20 Si7884BDP SiR470DP Vishay
www.vishay.com
24 4 40 PSMN4R0- RJK0346DPA NXP/Philips
CBOOT Capacitor Selection
30YL www.nxp.com The CBOOT capacitor must be sized less than 220nF and
more than 50nF to ensure proper operation of the LT3741.
Input Capacitor Selection Use 220nF for high current switching MOSFETs with high
gate charge.
The input capacitor should be sized at 4µF for every 1A
of output current and placed very close to the high side VCC_INT Capacitor Selection
MOSFET. A small 1µF ceramic capacitor should be placed
near the VIN and ground pins of the LT3741 for optimal The bypass capacitor for the VCC_INT pin should be larger
noise immunity. The input capacitor should have a ripple than 5µF for stability and has no ESR requirement. It is
current rating equal to half of the maximum output current. recommended that the ESR be lower than 50mΩ to reduce
It is recommended that several low ESR ceramic capacitors noise within the LT3741. For driving MOSFETs with gate
be used as the input capacitance. Use only type X5R or charges larger than 10nC, use 0.5µF/nC of total gate charge.
X7R capacitors as they maintain their capacitance over a
wide range of operating voltages and temperatures. Soft-Start
Unlike conventional voltage regulators, the LT3741 utilizes
Output Capacitor Selection the soft-start function to control the regulated inductor cur-
The output capacitors need to have very low ESR (equivalent rent. The charging current is 11µA and reduces the regulated
series resistance) to reduce output ripple. A minimum of current when the SS pin voltage is lower than CTRL1.
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For more information www.linear.com/LT3741 15

LT3741/LT3741-1
APPLICATIONS INFORMATION
Output Current Regulation leave this pin open under any condition. The RT pin is also
current limited to 60µA. See Table 4 and Figure 8 for resis-
To adjust the regulated load current, an analog voltage is
tor values and the corresponding switching frequencies.
applied to the CTRL1 pin. Figure 5 shows the regulated
voltage across the sense resistor for control voltages up Table 4. Switching Frequency
to 2V. Figure 6 shows the CTRL1 voltage created by a volt- SWITCHING FREQUENCY (MHz) RT (kΩ)
age divider from VREF to ground. When sizing the resistor 1 40.2
divider, please be aware that the VREF pin is current limited 0.750 53.6
to 500µA. Above 1.5V, the control voltage has no effect 0.5 82.5
on the regulated inductor current. 0.3 143
0.2 200
60

50
Thermal Shutdown
VSENSE+ – VSENSE– (mV)

40
VREF

30 LT3741 R2

CTRL1
20
R1
10
3741 F06

0
0 0.5 1.0 1.5 2.0
Figure 6. Analog Control of Inductor Current
VCTRL (V)
3741 F05

Figure 5. Sense Voltage vs CTRL Voltage VOUT

LT3741
Voltage Regulation and Overvoltage Protection R2

FB
The LT3741 uses the FB pin to regulate the output voltage R1
and to provide a high speed overvoltage lockout to avoid
high voltage conditions. The regulated output voltage
3741 F07

is programmed using a resistor divider from the output Figure 7. Output Voltage Regulation and Overvoltage Protection
and ground (Figure 7). When the output voltage exceeds Feedback Connections
125% of the regulated voltage level (1.5V at the FB pin),
the internal overvoltage flag is set, terminating switching. 1.2

The regulated output voltage must be greater than 1.5V

1.0
and is set by the equation:
FREQUENCY (MHz)

0.8
R2
VOUT = 1.21V 1+
R1 0.6

0.4
Programming Switching Frequency
0.2
The LT3741 has an operational switching frequency range
between 200kHz and 1MHz. This frequency is programmed 0
0 50 100 150 200 250 300 350 400 450 500
with an external resistor from the RT pin to ground. Do not RT (kΩ)
3743 F08

Figure 8. Frequency vs RT Resistance

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16 For more information www.linear.com/LT3741

 LT3741/LT3741-1
APPLICATIONS INFORMATION
The internal thermal shutdown within the LT3741 engages VIN VIN
at 163°C and terminates switching and resets soft-start.
LT3741 R2
When the part has cooled to 155°C, the internal reset is
cleared and soft-start is allowed to charge. EN/UVLO

R1

Switching Frequency Synchronization 3741 F09

The nominal switching frequency of the LT3741 is deter-
mined by the resistor from the RT pin to ground and may
be set from 200kHz to 1MHz. The internal oscillator may
also be synchronized to an external clock through the
SYNC pin. The external clock applied to the SYNC pin must
have a logic low below 0.3V and a logic high higher than
1.25V. The input frequency must be 20% higher than the
frequency determined by the resistor at the RT pin. Input
signals outside of these specified parameters will cause
erratic switching behavior and subharmonic oscillations.
Synchronization is tested at 500kHz with a 200k RT resistor.
Operation under other conditions is guaranteed by design.
When synchronizing to an external clock, please be aware
that there will be a fixed delay from the input clock edge to
the edge of switch. The SYNC pin must be grounded if the
synchronization to an external clock is not required. When
SYNC is grounded, the switching frequency is determined
by the resistor at the RT pin.
Shutdown and UVLO
The LT3741 has an internal UVLO that terminates switching,
resets all synchronous logic, and discharges the soft-start
capacitor for input voltages below 4.2V. The LT3741 also
has a precision shutdown at 1.55V on the EN/UVLO pin.
Partial shutdown occurs at 1.55V and full shutdown is
guaranteed below 0.5V with <1µA IQ in the full shutdown
state. Below 1.55V, an internal current source provides
5.5µA of pull-down current to allow for programmable
Figure 9. UVLO Configuration
The EN/UVLO pin has an absolute maximum voltage of
6V. To accommodate the largest range of applications,
there is an internal Zener diode that clamps this pin. For
applications where the supply range is greater than 4:1,
size R2 greater than 375k.
Load Current Derating Using the CTRL2 Pin
The LT3741 is designed specifically for driving high power
loads. In high current applications, derating the maximum
current based on operating temperature prevents damage
to the load. In addition, many applications have thermal
limitations that will require the regulated current to be re-
duced based on load and/or board temperature. To achieve
this, the LT3741 uses the CTRL2 pin to reduce the effective
regulated current in the load. While CTRL1 programs the
regulated current in the load, CTRL2 can be configured to
reduce this regulated current based on the analog voltage
at the CTRL2 pin. The load/board temperature derating is
programmed using a resistor divider with a temperature
dependant resistance (Figure 10). When the board/load
temperature rises, the CTRL2 voltage will decrease. To
reduce the regulated current, the CTRL2 voltage must be
lower than voltage at the CTRL1 pin.
RV RV
VREF

UVLO hysteresis. The following equations determine the R2 LT3741 RNTC RNTC RX RNTC RNTC RX

voltage divider resistors for programming the UVLO volt- CTRL2 3741 F10

age and hysteresis as configured in Figure 9. R1 A B C D

(OPTION A TO D)
VHYST VUVLO
R2 = –
5.5µA 66µA Figure 10. Load Current Derating vs Temperature
Using NTC Resistor
1.55V •R2
R1=
VUVLO – 1.55V

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LT3741/LT3741-1
APPLICATIONS INFORMATION
Average Current Mode Control Compensation the error amplifier will be the compensation resistor, RC.
Use the following equation as a good starting point for
The use of average current mode control allows for precise
compensation component sizing:
regulation of the inductor and load currents. Figure 11
shows the average current mode control loop used in the fS •L •1000V 0.002
RC = [Ω], CC = [F]
LT3741, where the regulation current is programmed by VO •RS fS
a current source and a 3k resistor.
where fS is the switching frequency, L is the inductance
VCTRL • 11µA/V
3k value, VO is the output voltage and RS is the sense resistor.
For most applications, a 4.7nF compensation capacitor
L RS
MODULATOR is adequate and provides excellent phase margin with
optimized bandwidth. Please refer to Table 6 for recom-
LOAD mended compensation values.
+
gm
ERROR AMP Board Layout Considerations
RC – 3741 F11

Average current mode control is relatively immune to the

CC
Figure 11. LT3741 Average Current Mode Control Scheme
To design the compensation network, the maximum com-
pensation resistor needs to be calculated. In current mode
controllers, the ratio of the sensed inductor current ramp
to the slope compensation ramp determines the stability
of the current regulation loop above 50% duty cycle. In
the same way, average current mode controllers require
the slope of the error voltage to not exceed the PWM ramp
slope during the switch off-time.
Since the closed-loop gain at the switching frequency
produces the error signal slope, the output impedance of
switching noise associated with other types of control
schemes. Placing the sense resistor as close as possible
to the SENSE+ and SENSE– pins avoids noise issues. Due
to sense resistor ESL (equivalent series inductance), a
10Ω resistor in series with the SENSE+ and SENSE– pins
with a 33nF capacitor placed between the SENSE pins is
recommended. Utilizing a good ground plane underneath
the switching components will minimize interplane noise
coupling. To dissipate the heat from the switching com-
ponents, use a large area for the switching mode while
keeping in mind that this negatively affects the radiated
noise.

Table 6. Recommended Compensation Values

VIN (V) VO (V) IL (A) fSW (MHz) L (µH) RS (mΩ) RC (kΩ) CC (nF)
12 4 5 0.5 1.5 5 47.5 4.7
12 4 10 0.5 1.5 5 47.5 4.7
12 5 20 0.25 1.8 2.5 38.3 8.2
24 4 2 0.5 1.0 2.5 52.3 4.7
24 4 20 0.5 1.0 2.5 52.3 4.7

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18 For more information www.linear.com/LT3741

 LT3741/LT3741-1
TYPICAL APPLICATIONS
20A Super Capacitor Charger with 5V Regulated Output

VIN VIN
EN/UVLO EN/UVLO
10V TO 36V
1µF 100µF

RT HG M1
82.5k SYNC 100nF
L1 R1 VOUT
CBOOT 1.0µH 20A MAXIMUM
2.5mΩ
VREF SW
2.2µF LT3741 150µF
VCC_INT ×2
10Ω 10Ω
22µF
RHOT CTRL1 LG M2
50k
45.3k
GND
CTRL2 SENSE+
33nF
RNTC
470k
SS SENSE– 38.3k
10nF FB
VC
12.1k
47.5k L1: IHLP4040DZER1R0M01
3741 TA02
M1: RJK0365DPA
4.7nF M2: RJK0346DPA
R1: VISHAY WSL25122L500FEA

Efficiency and Power Loss

vs Load Current VOUT vs IOUT
100 6

LT3741
90 5

LT3741-1
80 4
EFFICIENCY (%)

VOUT (V)

70 3

60 2

50 1 VIN = 20V
VIN = 20V VOUT = 5V
VOUT = 5V ILIMIT = 20A
40 0
0.1 1 10 100 0 2 4 6 8 10 12 14 16 18 20 22 24 26
LOAD CURRENT (A) IOUT (A)
3741 TA02b 3741 TA02c

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For more information www.linear.com/LT3741 19

LT3741/LT3741-1
TYPICAL APPLICATIONS
20A LED Driver LED Current Waveforms 10A to
20A Current Step
VIN VIN
EN/UVLO EN/UVLO
12V TO 36V 1.5V
1µF 100µF CTRL1
1V/DIV
RT HG M1 0.75V
82.5k SYNC 150nF
L1 R1 VOUT 20A
CBOOT 1.1µH 2.5mΩ 6V, 20A MAXIMUM
ILED
VREF SW 5A/DIV
2.2µF RHOT LT3741 680µF
D1
45.3k VCC_INT 10A
22µF
CONTROL LG M2
CTRL1
INPUT
GND 10Ω 10Ω
3741 TA03b
1ms/DIV
CTRL2 +
SENSE
RNTC 33nF
470k SENSE– 47.5k
SS FB
10nF VCH
L1: MVR1261C-112ML 12.1k
M1: VISHAY SiR462DP
82.5k M2: VISHAY SiR462DP 3741 TA03

4.7nF R1: VISHAY WSL25122L500FEA

10A Single-Cell Lithium-Ion Battery Charger

VIN VIN
EN/UVLO
24V
µCONTROLLER 1µF 33µF
CTRL1 HG M1
220nF
RT L1 1% VOUT
CBOOT 2.2µH 5mΩ 4.2V, 10A MAXIMUM
82.5k SYNC
SW
LT3741-1 +
VCC_INT 3.6V
VREF
2.2µF 22µF
LG M2
RHOT GND 10Ω 10Ω
45.3k
CTRL2 SENSE+
RNTC 22nF
470k SENSE– 30.1k
SS FB
1nF VC
L1: IHLP4040DZER2R2M01 12.7k
82.5k M1: RJK0365DPA
3741 TA04
M2: RJKO346DPA
8.2nF

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20 For more information www.linear.com/LT3741

 LT3741/LT3741-1
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LT3741#packaging for the most recent package drawings.

UF Package
20-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1710 Rev A)

0.70 ±0.05

4.50 ±0.05
3.10 ±0.05
2.45 ±0.05
2.00 REF

2.45 ±0.05

PACKAGE OUTLINE

0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS PIN 1 NOTCH
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED R = 0.20 TYP
BOTTOM VIEW—EXPOSED PAD OR 0.35 × 45°
0.75 ±0.05 R = 0.05 R = 0.115 CHAMFER
4.00 ±0.10 TYP TYP
19 20

PIN 1 0.40 ±0.10

TOP MARK
(NOTE 6) 1

2.45 ±0.10 2
4.00 ±0.10 2.00 REF

2.45 ±0.10

(UF20) QFN 01-07 REV A

0.200 REF 0.25 ±0.05

0.00 – 0.05 0.50 BSC
NOTE:
1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220
VARIATION (WGGD-1)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE

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LT3741/LT3741-1
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LT3741#packaging for the most recent package drawings.

FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev J)
Exposed Pad Variation CB

6.40 – 6.60*
3.86 (.252 – .260)
(.152) 3.86
(.152)
20 1918 17 16 15 14 13 12 11

6.60 ±0.10
2.74
4.50 ±0.10 (.108)
6.40
SEE NOTE 4 2.74 (.252)
(.108) BSC
0.45 ±0.05

1.05 ±0.10

0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8 9 10
1.20
4.30 – 4.50* (.047)
(.169 – .177) 0.25 MAX
REF
0° – 8°

0.65
0.09 – 0.20 0.50 – 0.75 (.0256) 0.05 – 0.15
(.0035 – .0079) (.020 – .030) BSC (.002 – .006)
0.195 – 0.30
FE20 (CB) TSSOP REV J 1012
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
MILLIMETERS FOR EXPOSED PAD ATTACHMENT
2. DIMENSIONS ARE IN
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
3. DRAWING NOT TO SCALE SHALL NOT EXCEED 0.150mm (.006") PER SIDE

37411ff

22 For more information www.linear.com/LT3741

 LT3741/LT3741-1
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 8/10 Revised to ±1.5% Voltage Regulation Accuracy in Features section 1
Revised Absolute Maximum Ratings to delete CBOOT-SW Voltage 2
Updated Electrical Characteristics section 3, 4
Updated RT, HG and LG pin descriptions 10
Updated Block Diagram 11
Revised text, added a paragraph and revised equations in Applications Information section 13, 14
Revised Table 4 and Switching Frequency Synchronization paragraph in the Applications Information section 16, 17
Revised Typical Applications drawings and added vendor part numbers 19, 20, 24
Updated Related Parts 24
B 9/10 Revised Voltage Regulator Amp value to gm = 800µA/V on Figure 1 Block Diagram 11
C 5/13 Added LT3741-1 Option All
Added LT3741-1 Option to Order Information 2
Clarified Non-Overlap and CTRL Current Specifications 3
Clarified Regulated Current vs VFB Graph 6
Clarified Efficiency Graphs 8
Clarified Common Mode Lockout Graph 9
Added LT3741-1 Block Diagram 11
Clarified Efficiency Graph 19
Clarified Part Number on Schematic 20
D 9/13 Corrected package descriptions in Order Information section 2
E 1/14 Corrected package in Block Diagram 11
F 10/15 Revised UVLO Hysteresis Equation 17

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Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
For more
tion that the interconnection information
of its circuits www.linear.com/LT3741
as described herein will not infringe on existing patent rights. 23
LT3741/LT3741-1
TYPICAL APPLICATION
20V Regulated Output with 5A Current Limit

VIN VIN
EN/UVLO EN/UVLO
36V
1µF 22µF

RT HG M1
82.5k SYNC 100nF
L1 VOUT
CBOOT 8.2µH 10mΩ 10A MAXIMUM
VREF SW
2.2µF LT3741-1 220µF
VCC_INT
RHOT 10Ω 10Ω
22µF
45.3k LG M2
CONTROL CTRL1 GND
INPUT
CTRL2 SENSE+
10nF
RNTC
470k
SS SENSE– 187k
10nF FB
VC
L1: IHLP5050FDER8RZM01 12.1k
30.1k M1: Si7884BDP
M2: SiR470DP
3.9nF

VIN VIN
EN/UVLO EN/UVLO
36V
1µF 22µF

RT HG M1
82.5k SYNC 100nF
L1
CBOOT 8.2µH 10mΩ
VREF SW
2.2µF LT3741-1
VCC_INT
RHOT 10Ω 10Ω
22µF
45.3k LG M2
CONTROL CTRL1 GND
INPUT
CTRL2 SENSE+
10nF
RNTC
470k
SS SENSE–
10nF FB
VC 3741 TA05

L1: IHLP5050FDER8RZM01
30.1k M1: Si7884BDP
M2: SiR470DP
3.9nF

RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LT3743 Synchronous Step-Down LED Driver 92% Efficiency, IOUT to 20A, VIN: 5.5V to 36V, IQ = 2mA, ISD < 1µA, 4mm × 5mm
QFN-28, TSSOP-28E

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24 Linear Technology Corporation

LT 1015 REV F • PRINTED IN USA

1630 McCarthy Blvd., Milpitas, CA 95035-7417

For more information www.linear.com/LT3741
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LT3741  LINEAR TECHNOLOGY CORPORATION 2010