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Logic Design: Chap. 4.2, Appendix A
Logic Design: Chap. 4.2, Appendix A
(jinsoo.kim@snu.ac.kr)
Systems Software &
Architecture Lab.
Seoul National University Logic Design
Fall 2019
▪ Combinational elements
• Operate on data
• Output is a function of input
Voltage
Time
4190.308: Computer Architecture | Fall 2019 | Jin-Soo Kim (jinsoo.kim@snu.ac.kr) 3
▪ Three components required to implement a digital system
• Combinational elements to compute Boolean functions
• Sequential elements to store bits
• Clock signals to regulate the updating of the memory elements
Sequential
elements
Combinational
In Out
…
elements
Clock
4190.308: Computer Architecture | Fall 2019 | Jin-Soo Kim (jinsoo.kim@snu.ac.kr) 4
▪ Outputs are Boolean functions of inputs And
a
▪ Respond continuously to changes in inputs b
out
(with some, small delay)
out = a & b
Or
Rising Delay Falling Delay a
a && b b out
b
out = a | b
Voltage
a Not
a out
out = ~a
4190.308: Computer Architecture | Fall 2019 | Jin-Soo Kim (jinsoo.kim@snu.ac.kr) 5
▪ Acyclic network of logic gates
• Continuously responds to changes on primary inputs
• Primary outputs become (after some delay) Boolean functions of primary inputs
Acyclic Network
Inputs Outputs
Shifter
Edge-triggered D flip-flop
4-bit register
Clk
D Q
D 1 0 1
Clk
Q 1 0
Clk
D Q Write
Write
Clk D 1 0 1
Q 1 1
Clock
4190.308: Computer Architecture | Fall 2019 | Jin-Soo Kim (jinsoo.kim@snu.ac.kr) 11
▪ Stores data bits
▪ For most of time acts as barrier between input and output
▪ As clock rises, loads input
State = x State = y
Rising
Input = y Output = x Output = y
clock
x y
Comb. Logic
0 Clock
A Load
L 0
Out In x0 x1 x2 x3 x4 x5
U MUX
Load
Clock
▪ Multiple ports
• Can read and/or write multiple words
in one cycle
• Each has separate address and data input/output
• Data is written to the register
Clock
only when RegWrite signal is enabled
00010 x2
Rising
clock
00110 x6 0x12
0x12
1
Clock Clock
▪ Storage
• Registers
– Hold single words, Loaded as clock rises
• Random-access memories
– Hold multiple words
– Possibly multiple read or write ports
– Read word when address input changes
– Write word as clock rises
4190.308: Computer Architecture | Fall 2019 | Jin-Soo Kim (jinsoo.kim@snu.ac.kr) 18