IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO.
3, MARCH 1998
A 1.6-GHz CMOS PLL with On-Chip Loop Filter
James F. Parker and Daniel Ray
Abstract— A 1.6-GHz phase locked loop (PLL) has been fab-
ricated in a 0.6-m CMOS technology. The PLL consists of an
LC-tank circuit, divider, phase detector with charge pump, and
an on-chip passive loop filter. When the oscillator is open loop,
it exhibits 0115 dBc/Hz phase noise at a 600-kHz offset from
the carrier. The PLL occupies an active area of 1.6 mm2 and
dissipates 90 mW from a single 3-V supply.
Index Terms— CMOS analog integrated circuit, phase-locked
loop, phase noise.
I. INTRODUCTION
T HE demand for wireless electronics has led to increased
integration levels in RF IC’s. To date, the majority of
RF IC’s have been realized in bipolar or GaAs technologies.
These technologies are well-suited for integration of low-noise
amplifiers (LNA’s), mixers, and oscillators that comprise an
RF front-end circuit [1]–[7]. However, most wireless baseband
signal processing uses CMOS technologies. Thus, there are
currently efforts to integrate most RF functions in CMOS with
the goal of realizing single-chip RF-to-baseband systems [8].
A key circuit in an RF front-end is a gigahertz-range
phase locked loop (PLL) used for frequency translation of
the RF input signal. In part, this high-speed PLL consists
of a low phase-noise oscillator and a high-speed frequency
divider. Early bipolar and GaAs implementations of these
functions often required off-chip components [2]. With the
development of on-chip spiral inductors [1], both the oscillator
and frequency divider could be completely integrated [5]–[6].
However, development of gigahertz oscillators and high-speed
frequency dividers in CMOS was only recently made possible
with the emergence of submicrometer technologies.
In this paper, an integrated 1.6-GHz CMOS PLL with on-
chip loop filter is described. It consists of an LC voltage
controlled oscillator (VCO) with on-chip spiral inductors,
frequency divider, phase detector with charge pump, and an
on-chip passive loop filter. A completely integrated CMOS
RF PLL has not been previously reported in the literature,
although there is published work in the area of both CMOS
RF VCO and high-speed frequency-divider design [9]–[13].
Further, many previously reported oscillators require special
substrate etching [9], [11] or external components [10] to ob-
tain their required phase-noise performance. In this work, the
inductors are integrated on-chip and require no special etching
processes. Although the loop filter is integrated, reference-tone
feedthrough is better than 80 dBc. This result is achieved
largely because the PLL uses a 61.5-MHz reference frequency.
Manuscript received August 5, 1997; revised October 17, 1997.
The authors are with Level One Communications, Inc., Sacramento, CA
95827 USA.
Publisher Item Identifier S 0018-9200(98)01710-7.
0018–9200/98$10.00  1998 IEEE
337
Fig. 1. Block diagram of a typical PLL.
An on-chip loop filter is important because it minimizes
required pin count, and this is crucial for single-chip RF-to-
baseband systems. Finally, the phase noise of the oscillator is
115 dBc/Hz at a 600-kHz offset from the 1.6-GHz carrier.
This noise performance meets or exceeds many previously
reported results of oscillators using integrated spiral inductors
[5], [9], [11]–[12].
The paper is divided into four additional parts. Section II
describes background information. Section III describes the
circuits that comprise the PLL. This section includes a descrip-
tion of the required PLL capture range and a derivation of the
LC oscillator’s phase noise. Section IV describes the measured
performance of the PLL and Section V gives conclusions.
II. BACKGROUND
A. Noise Tradeoffs in PLL Design
Fig. 1 shows a block diagram of a standard PLL. It consists
of a phase detector, charge pump, loop filter, and oscillator.
In the block diagram, the small-signal transfer function of the
phase detector is represented as , the charge pump current
as , the loop filter as , and the oscillator as .
Further, the input and output of the PLL are represented as
and , respectively, while perturbations in VCO output
phase are described by . Analysis shows that the small-
signal transfer function of is a low-pass function.
Thus, the loop tends to reject high-frequency changes in the
phase of the reference input. Conversely, the transfer function
of is a high-pass function. Thus, the loop tends to
reject low-frequency changes of phase in the oscillator output.
These results give rise to a fundamental noise tradeoff in the
PLL design [14]. If the phase-noise power of the reference
signal dominates that of the oscillator, it is desirable to
make the bandwidth of the PLL small to maximize rejection
of reference phase noise. On the other hand, if the phase-
noise power of the oscillator dominates that of the reference
input, it is desirable to make the bandwidth of the PLL large
to maximize rejection of the oscillator noise spectrum. In
this work, the reference input is crystal-based and the noise
338 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 3, MARCH 1998

(a) (b)
Fig. 3. (a) Qualitative model that describes eddy current losses. (b) Equiv-
alent circuit of (a).

(a) (b)
Fig. 2. (a) Metal spiral inductor over a silicon substrate. (b) Simple cross
section of one metal leg in (a).

limitations in the PLL arise from the nonideal oscillator, which

is based on an LC tank-circuit that uses a metal spiral inductor.
Fig. 4. Block diagram of 1.6-GHz PLL.
B. Noise Sources in Spiral Inductors
Fig. 2(a) shows an example of a metal spiral inductor
fabricated over a silicon substrate. Fig. 2(b) shows a simple
cross section of one of the inductor legs in Fig. 2(a). One
source of noise in the inductor is due to the series resistance
of its metal lines, shown as in Fig. 2(b). This resistance
can be minimized by making the metal lines as wide and thick
as possible. However, the use of wide metal lines increases the
inductor’s parasitic capacitance to the substrate, which lowers
the maximum oscillation frequency that can be achieved.
Furthermore, the inductor’s parasitic capacitance has a series
resistance due to the lossy substrate. This additional resistor Fig. 5. Circuit schematic of LC oscillator.
is a second source of noise in the inductor and is shown as
in Fig. 2(b). However, if the substrate consists of highly
doped bulk material under a thin epitaxial layer, this resistor Fig. 3(b) as and . Simple impedance transformations
can be ignored. The third source of noise results from magnetic show that will be less than its desired value of , while
field lines that induce eddy currents in the substrate [13]. By will be larger than . Thus, the effect of is to
the law of Faraday–Lenz, the time-varying current flowing in decrease the quality factor of the inductor, defined as the ratio
the inductor produces a time-varying magnetic field. This of its reactance to resistance at the oscillation frequency. The
magnetic field induces an eddy current in the substrate magnitude of this -reduction is usually predicted with an
that opposes the current flow in the inductor. These eddy electromagnetic simulation tool.
currents see an equivalent resistance in the substrate, shown as
in Fig. 2(b), which increases the noise of the inductor. III. CIRCUIT DESCRIPTION
Fig. 3(a) shows a qualitative model that describes eddy cur-
Fig. 4 shows a block diagram of the 1.6-GHz PLL. It
rent losses in the substrate. The model consists of a transformer
consists of a phase detector, charge pump, passive loop filter,
with primary inductance , equivalent series resistance ,
a voltage-controlled LC-oscillator, and a divide-by-26 circuit.
secondary winding , and secondary load . In the
The reference frequency is crystal based and is 61.5 MHz. The
model, and represent the desired value of the spiral
divider ratio and the resulting crystal frequency were set by
inductor and the equivalent resistance of its metal lines.
system-level requirements.
represents magnetic flux that is coupled to the substrate in
the form of eddy currents. represents the equivalent
resistive losses seen by the eddy currents in the substrate. A. LC Oscillator
If the substrate acts as a good insulator, approaches Fig. 5 shows the schematic of the LC oscillator. It consists
infinity, which open circuits the secondary winding and leaves of cross-coupled transistors M1–M2, current source M3, and
the values of and unchanged. If the substrate acts as an LC-tank circuit. M1–M2 create a small-signal negative
a good conductor, then is driven toward zero, which resistance to insure initial oscillation start-up and also provide
reduces the inductance seen at the input of the transformer in large-signal amplitude regulation. The tank circuit capacitance
Fig. 3(a). In practice, lies between 0 and infinity. Thus, consists of poly-poly ac-coupling capacitors , varactors
when the value of is impedance transformed across and , and a binary-weighted capacitor array . The induc-
, it results in new values for these components, shown in tors are 2 nH. To minimize metal resistance, the
PARKER AND RAY: 1.6-GHz CMOS PLL WITH ON-CHIP LOOP FILTER
Fig. 6. Simplified schematic of a single array element in CBW .
inductors are fabricated with 14- m wide metal lines from the
top two metal layers in the three-metal process.
The pull range of the oscillator must cover variations due to
processing and temperature. The varactors , which consist
of diodes, are used to compensate for temperature
variations in the VCO frequency. In Fig. 5, the oscillation
frequency is defined as
(1)
where and are the equivalent transformed values
shown in Fig. 3(b) and is the equivalent capacitance in
parallel with the inductors. is dominated by the metal-
line resistance of the inductors and varies by roughly 30%
over temperature. In (1), the small-signal sensitivity of to
perturbations in is . Thus, if the nominal -factor
of the inductor is 3.3, the oscillation frequency will vary by
3% over temperature. To cover this variation, the varactors in
Fig. 5 are sized to yield a tuning range of 3.5%.
1) Binary-Weighted Capacitor Array: In Fig. 5, is
used to overcome process variations in the integrated LC tank
circuit. consists of a binary-weighted array of poly-poly
capacitors controlled by a 6-b digital word. Fig. 6 shows a
simplified schematic of one of these array elements. It consists
of two identical poly-poly unit-capacitors of value fF:
S1, which is a minimum channel-length switch, and some
parasitic capacitors , which are described shortly. When
is high, S1 ties the bottom plates of the unit capacitors
together with its drain-to-source resistance. Because the array
element is driven differentially, the resistance of S1 is split
equally among the unit capacitors. The quality factor of
is designed to be nominally equal to 15. This insures the
resistance of the switch has a negligible impact on the overall
of the tank circuit. When is low, the differential inputs
see the series combination of and to ground. consists
of the bottom-plate capacitance of as well as the junction
capacitance of the switch. Through careful layout, is made
equal to 14 fF. This means the ratio of capacitance seen at the
inputs when the switch is on to when it is off is 2.5 : 1. With
the addition of to the voltage dependent capacitance of
the varactors, the pull range of the VCO is extended from
3.5% to 11.5%. Since the oscillation frequency varies as a
function of one over the square root of LC, an additional
8% in frequency-control range due to covers a 16%
variation in the LC product of the tank circuit.
339
Fig. 7. Noise model of oscillator.
2) Noise Model of Oscillator: Fig. 7 shows a simplified
small-signal model used to estimate the phase noise of the
oscillator. It consists of the equivalent RLC tank circuit
from Figs. 3(b) and 5, negative resistance element ,
and associated noise models. As described previously,
represents the resistance of the inductor’s metal lines and
eddy current losses in the substrate. It also includes resistance
in the capacitor array and varactor. The negative resistance
element represents the transconductance of M1 and
M2 in Fig. 5.
In Fig. 7, the loop gain of the oscillator is defined as
LG and is equal to . Using these definitions, the
reciprocal of the signal-to-noise ratio (SNR) of the oscillator
is approximately equal to the following [15]:
dBc
(2)
Hz
In (2), is Boltzman’s constant, is absolute temperature,
is the PLL center frequency, is the frequency offset from
the carrier, and is the rms amplitude of the sine-wave
oscillation. It is useful to define in terms of the oscillator
bias current . If the oscillator loop gain is greater than two,
the amplitude of oscillation is well-approximated by
(3)
Substituting (3) into (2)
dBc
(4)
Hz
Equation (4) shows that phase noise is minimized primarily
by minimizing and maximizing , which makes the
tank-circuit factor large. Note that using a large bias current
also decreases the phase noise. However, the bias current is
normally limited by the power budget. Given a bias current of
12 mA, nH (by simulation), (
by simulation), and an oscillator loop gain of 2.5, (4) predicts
a phase noise of 117.7 dBc/Hz at a 600-kHz offset from
the 1.6-GHz oscillation frequency. Note that these estimated
results ignore any resistance in the varactors and capacitor
array in Fig. 5.
B. Frequency Divider
Fig. 8 shows a block diagram of the divide-by-26 function
used in the PLL. It consists of a front-end divide-by-two
circuit, a buffer amplifier, and a divide-by-13 function. The
amplifier is required to buffer the 800-MHz output signal of
the divide-by-two function from the capacitive load of the flip-
flops and logic gates that comprise the divide-by-13 circuit.
340
Fig. 8. Block diagram of divide-by-26 circuit.
Fig. 9. Circuit diagram of the flip-flop used in the divide-by-26 circuit.
1) High-Speed Flip-Flop Schematic: The high-speed flip-
flops in both the divide-by-two and divide-by-13 blocks con-
sist of identical master and slave circuits clocked on oppo-
site phases of a differential clock. Fig. 9 shows the circuit
schematic of the master section of the high-speed flip-flop.
It consists of PMOS loads (M1–M2), PMOS diode clamps
(M3–M4), gain stage (M5–M6), latching devices (M7–M8),
clocked differential pair (M9–M10), and current source (M11).
When a large differential input voltage is applied to the gates
of M5 and M6, the bias current in M11 is steered entirely
through M1 or M2. Because M1–M2 are biased in the triode
region and act as nonlinear resistors, the voltage across these
devices can be pulled within several hundred millivolts of
ground over supply and temperature. This voltage drop can
triode current source M11, which severely degrades the speed
of the flip-flop. To overcome this problem, diode-connected
PMOS devices M3–M4 are used to clamp the output voltage
at a level that insures current source M11 stays saturated. The
clamping circuit works by insuring that M3 or M4 conduct
appreciable current only when a large differential voltage is
applied at M5–M6 and M1 or M2 begin to enter the saturation
region.
2) Replica Bias Circuit: In Fig. 9, M1–M2 are biased in
the triode region with a replica bias circuit shown in Fig. 10
[16]. The replica bias circuit consists of an op amp and a
PMOS device (MRef) and current source that are matched to
the current source and PMOS devices (M1–M2) in the flip-flop
gain stage. For clarity, a partial schematic of one of the flip-
flop gain stages is also shown in Fig. 10. Through negative
feedback, the op amp forces the input reference voltage
to appear across MRef by adjusting its gate voltage . A similar circuit not shown here is used to generate the
is then applied to all the gates of the PMOS load
devices in the flip-flops. Assuming good matching, when a
zero differential input voltage is applied at the gates of M5–M6
in the flip-flop gain stage, a voltage of appears across
the PMOS loads.
With circuit analysis, it may be shown that the gain of
the flip-flop gain stage is over the of
M5–M6. To maximize the speed of the flip-flop, is
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 3, MARCH 1998
Fig. 10. Replica circuit used to bias the flip-flop PMOS loads in the triode
region.
Fig. 11. Simplified schematic of the pump-up circuit in charge pump.
made small while still insuring a gain greater than one. To
insure the gain remains greater than one over temperature,
a simple temperature compensation scheme can be used.
is proportional to the square root of and has
a temperature dependence proportional to . Thus, if
is made proportional to becomes proportional
to absolute temperature. Thus, to make the gain of the flip-
flop invariant to temperature, is made proportional to
.
C. Phase Detector, Charge Pump, and Loop Filter
The phase detector is a standard phase/frequency detector
commonly seen in the literature [3]. It consists of current-
mode logic similar to that used in the high-speed flip-flops.
Although it is not efficient with respect to power dissipation,
a fully balanced architecture was used to minimize switching
noise on the power supplies. This is crucial because power-
supply noise can couple onto the loop filter output and appear
as tones in the oscillator sidebands.
Fig. 11 shows a partial schematic of the charge pump that
supplies the pump-up current to the loop filter. It consists of
an input differential pair M1–M2, current mirror load M3,
output current source M4, and pull-up transistors M5–M6.
pump-down current. The fully balanced charge-pump inputs
are driven by the phase detector. When the pump-up signal
is driven high, the bias current is steered through M2.
The difference between and flows in M3 and is
mirrored to output device M4. When the pump-up signal is
driven low, the current in M3 begins to go to zero. Without
M5–M6, this is a long time-constant event that is not well-
controlled. To overcome this problem, M5 mirrors
PARKER AND RAY: 1.6-GHz CMOS PLL WITH ON-CHIP LOOP FILTER
Fig. 12. Schematic of loop filter.
to M6. Thus, when the pump-up signal goes low, the drain
of M6 must pull high, which quickly shuts off current
source M4.
The loop-filter schematic is shown in Fig. 12. It consists of
three resistors and capacitors that create a three-pole one-zero
network. The loop filter components were optimized based
on area and spur-suppression requirements. Thus , which
largely determines the PLL stability, was fixed at 50 pF, and
, which primarily determines the PLL bandwidth, was fixed
at 50 k . With a charge pump current of 25 A, the resulting
PLL bandwidth is 200 kHz. Remember that the reference
frequency to the PLL is 61.5 MHz and is crystal based. Thus,
a wide-bandwidth PLL is advantageous for minimizing the
noise spectrum of the oscillator. However, the disadvantage
of a wide-band PLL is that reference-tone feedthrough can
become large. Because the charge-pump updates the loop
filter at 61.5 MHz, a tone at this frequency modulates the
VCO and appears in its sidebands. To minimize this tone
power, the size of and were made large ( 3.5 pF).
Increasing the size of and tends to destabilize the
PLL and causes the spectrum of the oscillator to peak at
frequencies near the PLL bandwidth. This peaking can be
reduced at the cost of increasing reference-tone feedthrough
or increasing the size of while decreasing the PLL band-
width.
IV. MEASURED PERFORMANCE
Fig. 13 shows the measured phase noise of the open-loop
oscillator and the measured phase noise of the oscillator
when locked to a 61.5-MHz reference frequency. The phase
noise of the open-loop oscillator measures 99 dBc/Hz at
a 100 kHz offset, 105 dBc/Hz at a 200 kHz offset, and
115 dBc/Hz at a 600 kHz offset from the 1.6-GHz carrier.
The 2.7 dB discrepancy from the performance predicted by (4)
is explained by accounting for the resistance in the varactors
and capacitor array. Using (4), the measured phase noise of
the open-loop oscillator extrapolates to a factor of 3.4 for
the tank circuit. Including substrate effects, the -factor of
the unloaded inductor was estimated to be four (with aid of an
electromagnetic simulation tool). For comparison, if substrate
effects are ignored, the predicted -factor of the inductor is
4.5.
When the oscillator is locked to the crystal reference, the
spot noise measurement at 200 kHz displays 9 dB of peaking
above the open-loop noise measurement. However, this noise
peaking quickly drops off and at a frequency offset of 600 kHz,
the closed-loop phase noise measures 114 dBc/Hz, which
341
Fig. 13. Plot of measured open- and closed-loop oscillator spectra.
is within 1 dB of the measured open-loop phase noise. As
described in Section III, the noise peaking is primarily due
to the loop filter, which has several poles that are inserted to
minimize reference-tone feedthrough.
Table I compares the open-loop phase noise performance
achieved in this work with other recent literature. Note that
all phase-noise results have been normalized to a 600-kHz
offset from a 1.6-GHz oscillation frequency. There are two
key points of this comparison. First, only [5] describes a
complete RF PLL. However, this was fabricated in a bipolar
technology and used an external loop filter. Second, phase-
noise performance is a strong function of substrate resistivity
and inductor geometry. In this work, the starting wafer material
consisted of a thick 0.01- -cm silicon substrate and a thin
(10 m) 10- -cm epi layer. Thus, eddy current losses in this
work are large relative to [6] and [11], which used a more
insulating bulk material or etched away the silicon substrate. In
[13], it was found that minimizing the area of the inductor and
using circular spirals with open centers maximized inductor
quality factor. Although the starting wafer material in [13] is
similar to that used in this work, due to optimized inductor
geometry, the phase noise performance in [13] is 2 dB better
than achieved in this work. In summary, the phase noise of
this work could be improved by fabricating the PLL over
a 10–15- -cm substrate along with using a more optimal
inductor geometry.
Table II summarizes the performance of the PLL. The PLL
was fabricated in a 0.6- m three-metal two-poly process.
The active area, which excludes pads, is 1.60 mm . The
die photo is shown in Fig. 14. The phase noise of the free-
running oscillator is 115 dBc/Hz at a 600-kHz offset. The
tuning range of the oscillator is 11.5% with a maximum
gain of 40 MHz/V. The temperature coefficient of the free-
running oscillator is 430 ppm/ C. Fig. 15 shows that the loop
filter suppresses the magnitude of reference-tone feedthrough
to more than 80 dBc. From a 3-V supply, the total power
dissipation is 90 mW, of which the LC oscillator requires
36 mW and the divide-by-26 circuit requires 22.5 mW. In
Fig. 8, the divide-by-two and buffer circuits dissipate 2.4 and
4.2 mW, respectively.
342 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 3, MARCH 1998

TABLE I
COMPARISON OF PHASE NOISE PERFORMANCE WITH RECENT WORK

TABLE II
SUMMARY OF PERFORMANCE; T = 25 C

Fig. 15. Plot of measured reference-tone feedthrough.

Fig. 14. Die photo of PLL.

reducing pin count in large RF systems. In conclusion, this
work demonstrates the feasibility of CMOS circuits to realize
V. SUMMARY/CONCLUSIONS high-frequency and high-performance PLL’s.

A completely integrated 1.6-GHz CMOS RF PLL has

been described. Both the open- and closed-loop phase noise
spectrums measure better than 114 dBc/Hz at a 600-kHz
offset from the 1.6-GHz carrier. This noise performance meets
or exceeds that achieved in other recent work. Further, the
loop filter in this work is integrated, which is critical for
ACKNOWLEDGMENT
The authors gratefully acknowledge S. Luna for his layout of
the test board and subsequent characterization of the fabricated
devices. The authors also thank the reviewers for their helpful
comments.
PARKER AND RAY: 1.6-GHz CMOS PLL WITH ON-CHIP LOOP FILTER
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James F. Parker received the B.S.E.E. degree from
Brigham Young University, Provo, UT, in 1988 and
the M.S.E.E. and Ph.D. degrees from the University
of California, Davis, in 1991 and 1995, respectively.
In 1994 he joined Level One Communications,
Inc., Sacramento, CA, where he is currently a Staff
Design Engineer. At Level One, he has worked
on a variety of high-speed analog CMOS circuits
for LAN applications, including adaptive analog
equalizers, timing-recovery loops, automatic-gain-
control circuits, and linear line drivers.
Daniel Ray received the B.S.E.E. degree from the
University of Arizona, Tucson, in 1981 and the
M.S.E.E. degree from the University of California
at Berkeley in 1982.
He joined Intel Corporation in 1982, where he
worked as a Senior Design Engineer on mixed-
signal IC’s for telecommunications. In 1985, he co-
founded Level One Communications, Sacramento,
CA, where he has held a variety of design and
technical management positions. He is currently
Engineering Director for the Networking Products
group within Level One and is focused on integration-compatible communi-
cations systems and high-speed mixed-signal CMOS circuit design.