A 15 LEVEL MULTILEVEL INVERTER HAVING LESS

NUMBER OF SWITCHS USING PD-PWM TECHNIQUE

A Project Report
Submitted in the partial fulfillment of the requirements for
the award of the degree of
Bachelor of Technology
In
Electrical & Electronics Engineering
By
N .Venkateswarlu (L18AEE535)
K . Pavan kumar (Y17AEE434)
K . Steevenson (Y17AEE441)
M . Priyanka (Y17AEE449)
N . Naveen (L18AEE537)
Under the guidance of
Mr.G.Rajesh M.Tech., (Ph.D)
Asst.Professor

Department of Electrical and Electronics Engineering

Bapatla Engineering College
(Autonomous)
(Affiliated to Acharya Nagarjuna University)
BAPATLA – 522102, Andhra Pradesh, INDIA
May, 2021
 Department of Electrical and Electronics Engineering
Bapatla Engineering College, Bapatla (Autonomous)
(Affiliated to Acharya Nagarjuna University, Guntur)
Bapatla - 522102, A.P, India.

Declaration
The Thesis entitled “A 15 LEVEL MULTILEVEL INVERTER HAVING LESS
NUMBER OF SWITCHS USING PD-PWM TECHNIQUE” is a record of bonafide work
carried out by me, submitted in partial fulfillment for the award of Bachelor of Technology in
Electrical and Electronics Engineering to Acharya Nagarjuna University, Guntur. The results
and work embodied in this project report have not been submitted to any other University or
Institute for the award of any degree or diploma.

Signature of the Student

 Department of Electrical and Electronics Engineering
Bapatla Engineering College (Autonomous)
(Affiliated to Acharya Nagarjuna University, Guntur)
Bapatla - 522102, A.P, India.

Certificate

This is to certify that the thesis entitled “A 15 LEVEL MULTILEVEL INVERTER

HAVING LESS NUMBER OF SWITCHS USING PD-PWM TECHNIQUE” is being
submitted by N.venkateswarlu (L18AEE535); K.Pavan Kumar (Y17AEE434);
K.Steevenson(Y17AEE441); M.Priyanka(Y17AEE449); N.Naveen(L18AEE537) in partial
fulfillment for the award of Bachelor of Technology in Electrical and Electronics
Engineering to Bapatla Engineering College, Bapatla is a record of bonafide work carried
out under my guidance and supervision.

Signature of the HOD Signature of the Project Guide

Dr.N.Rama Devi M.Tech.,Ph.D., Mr.G.Rajesh M.Tech.,(Ph.D).
Professor Asst.Professor
Department of EEE Department of EEE
Bapatla Engineering College Bapatla Engineering College
 ACKNOWLEDGEMENTS

We would like to express our sincere gratitude and appreciation to my project guide

Mr.G.Rajesh, Asst.Professor, Bapatla Engineering college, Bapatla for his guidance and

assistance throughout the project work. The advice and constant encouragement given by him

is gratefully acknowledged.

We would like to express our gratitude Dr. N.Rama Devi. Professor and Head of EEE

department, Bapatla Engineering College, Bapatla for all her help and encouragement

throughout this work.

We would like to express our sincere thanks to Dr. V.Damodhar Naidu, Principal, Bapatla

Engineering College, Bapatla.

we are thankful to all the faculty members and staff of the Department of Electrical

Engineering is gratefully acknowledged. Finally, we thank everyone who has directly or

indirectly helped us during the course of this project work.

With Regards
N . Venkateswarlu (L18AEE535)
K . Pavan Kumar (Y17AEE434)
K . Steevenson (Y17AEE410)
M . Priyanka (Y17AEE449)
N . Naveen (L18AEE537)
 ABSTRACT

The present work is on A 15 level multilevel inverter with less number of switches. In
general we need 7 Bridges,7 Sources and 28switches to design the 15 level multilevel inverter.
But we work Asymmetric cascaded H Bridge inverter which consist of 1 Bridge, 7 switches,
and 3 Sources. in Asymmetrical MLI the DC source Magnitude are unequal and it is designed
with binary form of voltage such as 20Vdc, 40Vdc & 60Vdc. By using The phase Disposition
Pulse Width Modulation (PD-PWM) technique high &low switching frequency is used for
controlling the Power semiconductor switches with R-load in MLI. Finally we observe THD
and Harmonics in the output by using MATLAB.

i
 CONTENTS
DESCRIPTION PAGE NO

ABSTRACT ii
LIST OF FIGURES IV
ACRONYMS V

CHAPTER-1 1
1.1 Inverter
1.2 Multilevel Inverter

CHAPTER-2 2
2.1 Classification of multilevel level inverter
2.1.1 Diode clamped MLI 3
2.1.2 Flying capacitor multilevel inverter 4
2.1.3 Cascaded h-bridge multilevel inverter 5

CHAPTER -3 8
3.1 Symmetrical &asymmetrical MLI 8

3.2 Switching mode of operation for 15 level proposed inverter 10

3.3 Output voltage according to the switching ON-OFF condition 25

CHAPTER-4 26
4.1 Classifications of modulations techniques 26
4.2 Multi carrier PWM 27
4.2.1 Phase shifted PWM (PS-PWM) 27
4.2.2 Level shifted PWM (LS-PWM) 28

CHAPTER-5 31
5.1 Simulation Diagram Of 15-level ASCHBMLI 31

ii
CHAPTER 6
6.1 Simulation results for low and high switching frequency 35
6.2 THD analysis of low and high switching for ASCHMLI 36

CONCLUSION 37
REFERENCE 38

iii
 LIST OF FIGURES

Fig:2.1.1 Diode-clamped multilevel inverter circuit topologies. ------------------------------ 3

Fig:2.1.2: Capacitor-clamped multilevel inverter circuit topologies. -------------------- 5

Fig:2.1.3: 5-level single phase cascaded H-bridge multilevel inverter. --------------------- 6

Fig :3.1.1 symmetrical multilevel inverter. ------------------------------------------------------ 8

Fig:3.1.2 Asymmetrical multilevel inverter ----------------------------------------------------- 9

Fig:3.2.1 to 3.2.15 Switching of mode of operation of MLI ----------------------------------10 - 24

Fig:4.2.1 Method to generate Phase Shifted carrier signals ----------------------------------- 28

Fig:4.2.2(a) PD-PWM carrier signals ------------------------------------------------------------ 29

Fig:4.2.2(b) POD PWM carrier signals ---------------------------------------------------------- 30

Fig:4.2.2(c) APOD-PWM carrier signals -------------------------------------------------------- 30

Fig:5.1 simulation diagram of a 15 level ASCHBMLI with PD-PWM technique. --------- 31

Fig:5.3(a), 5.3(b) low and high switching frequency pulses. ---------------------------------- 33

Fig:5.4 PD-PWM switching signals generate. --------------------------------------------------- 34

Fig :6.1.1, 6.1.2 output voltage for 15 level ASCHBMLI for low and high switching ---- 35

Fig: 6.2.1, 6.2.2 THD analysis of low &high switching for ASCHMLI ---------------------- 36

iv
 ACRONYMS

MLI - Multi level inverter

NPC - Neutral point clamped

FC - Flying capacitor

CHB - cascaded H-bridge

ASCHB - Asymmetrical cascaded H-bridge

SCHB - Symmetrical cascaded H-bridge.

PWM - Pulse width modulation.

MCPWM - Multi carrier pulse width modulation.

PS-PWM - Phase shifted pulse width modulation.

LS-PWM - Level shifted PWM

PD-PWM - Phase disposition

POD- PWM - Phase opposition disposition

APOD-PWM - Alternate Phase opposition disposition

THD - Total hormonic distortion

v
 CHAPTER-1
1.1INVERTER
A device which convert DC power into AC power at desired output voltage and frequency is
called “INVERTER”.
The input voltage, output voltage and frequency, and overall power handling depend on the
design of the specific device or circuitry. The inverter does not produce any power; the power
is provided by the DC source.

DC AC
INVERTER

1.2 MULTILEVEL INVERTER

 MULTILEVEL INVERTER is a power electronic device which is capable of providing

desired alternating voltage level at the output using multiple lower level DC voltages as an
input.
 Multilevel Inverter (MLI)has more advantages than conventional inverter because of less
switching losses, less voltage stress across switch and less Electromagnetic Interference
(EMI).
 Multilevel voltage sources inverter allows them to reach high voltages with low
harmonics without the us of Transformers or series connected synchronized switching
devices.

1
 CHAPTER 2

2.1 CLASSIFICATION OF MULTILEVEL LEVEL INVERTER

Generally there are 3 types of MLI. They are
i. Neutral clamped (NPC) or Diode Clamped MLI
ii. Flying capacitor (FC) MLI
iii. Cascaded H-Bridge (CHB) MLI .

MULTILEVEL INVERTER

DIODE CASCADED H- FLYING

CLAMPED MLI BRIDGE MLI CAPACITOR MLI

SINGLE DC SOURCE MULTIPLE DC SOURCE

Asymmetrical
Cascaded H-Bridge multilevel Cascaded H-Bridge
inverter with low frequency MLI
D transformer

Symmetrical
Cascaded H-Bridge
MLI

2
2.1.1) DIODE CLAMPED MLI

The diode-clamped inverter was also called the neutral-point clamped (NPC) inverter
when it was first used in a three-level inverter in which the mid-voltage level was defined as
the neutral point. Because the NPC inverter effectively doubles the device voltage level
without requiring precise voltage matching, the circuit topology prevailed in the 1980s.
A three-level diode-clamped inverter is shown in Fig. 2.1.1(a). In this circuit, the dc-
bus voltage is split into three levels by two series-connected bulk capacitors, C1 and C2 . The
middle point of the two capacitors ‘n’ can be defined as the neutral point. The output voltage
Van has three states: Vdc/2 ,0 and -Vdc/2. For voltage level, Vdc/2 switches S1 and S2 need
to be turned on; for -Vdc/2 , switches S1’ and S2’ need to be turned on; and for the 0 level, S2
and S2’ need to be turned on.
Fig. 2.1.1(b) shows a five-level diode-clamped converter in which the dc bus consists
of four capacitors, C1, C2, C3, and C4. For dc-bus voltage, Vdc the voltage across each
capacitor is, Vdc/4 and each device voltage stress will be limited to one capacitor voltage level
Vdc/4 through clamping diodes.

Fig:2.1.1 Diode-clamped multilevel inverter circuit topologies. (a) Three-level. (b) Five-level.

3
There are five switch combinations to synthesize five level voltages across a and n.
1) For voltage level Van=Vdc/2, turn on all upper switches S1– S4.
2) For voltage level Van=Vdc/4, turn on three upper switches S2– S4 and one lower switch
S1’.
3) For voltage level Van=0, turn on two upper switches S3 and S4 and two lower switches
S1’and S2’ .
4) For voltage level Van=-Vdc/4, turn on one upper switch S4 and three lower switches S1’–
S3’.
5) For voltage level Van=Vdc/2, turn on all lower switches S1’ – S4’.

2.1.2) FLYING CAPACITOR MULTILEVEL INVERTER

The structure of this inverter is similar to that of the diode- clamped inverter
except that instead of using clamping diodes, the inverter uses capacitors in their place.
The flying capacitor involves series connection of capacitor clamped switching cells. This
topology has a ladder structure of dc side capacitors, where the voltage on each capacitor
differs from that of the next capacitor. The voltage increment between two adjacent
capacitor legs gives the size of the voltage steps in the output waveform. Figure 2.1.2
shows the three-level and five-level capacitor clamped inverters respectively.

In the operation of flying capacitor multi-level inverter, each phase node (a, b, or c)
can be connected to any node in the capacitor bank (V3, V2, V1). Connection of the a-

phase to positive node V3 occurs when S1 and S2 are turned on and to the neutral point

voltage when S2 and S1′ are turned on. The negative node V1 is connected when S1′ and

S2′are turned on. The clamped capacitor C1is charged when S1 and S1′ are turned on and

is discharged when S2 and S2′ are turned on. The charge of the capacitor can be balanced

by proper selection of the zero states.

4
 Fig:2.1.2: Capacitor-clamped multilevel inverter circuit topologies (a) 3-level
inverter (b) 5- level inverter.

2.1.3) CASCADED H-BRIDGE MULTILEVEL INVERTER

The most popular multilevel inverter topologies are diode clamped, flying capacitor
and cascaded H-bridge multilevel inverter. The latter requires less number of power switching
components, has higher efficiency and has simple circuit layout, all these aspects make it
superior over the other topologies. Conventional single phase five level cascaded H-bridge
multilevel inverter circuit with two H-bridge module is shown in Fig.2.1.3.
The number of power switches required for a k levels inverter are N = 2(k − 1). Each
module of the H-bridge has its own DC input voltage and consists of four power switching
devices. Each module of the cascaded multilevel inverter can produce three levels of the
output voltage which are +V dc, 0 and −V dc. The resulting phase voltage is synthesized by
the addition of voltage generated by the each H-bridge.
As the demand for lower size & performance ratio of power converters increases, there
is an increasing trend of reducing the numbers and size of power components in
implementation of power converters. In cascaded H-bridge multilevel inverter implementation,

5
reducing the numbers of main switching devices reduces the switching and conduction losses
and increases the inverter efficiency.

Fig:2.1.3: 5-level single phase cascaded H-bridge multilevel inverter.

2.1.4: ADVANTAGES, DISADVANTAGES AND APPLICATION OF MUTLILEVEL

INVERTERS

TYPES ADVANTAGES DISADVANTAGES APPLICATIONS

 Capacitance is low.  Number of  Static var
 Back to back clamping diodes compensation
inverters can be increases with  Variable speed
used. motor drives
the increase of
Capacitors are pre  High voltage system
 each level. interconnections
charged.  Dc level will
Efficiency is high at  High voltage DC and
DIODE  discharge when
fundamental AC transmission
CLAMPED control and lines
MLI frequency, monitoring are
not precise.

6
  For balancing  Voltage control  Induction motor
capacitors voltage is difficult for all control.
the capacitors  Static var generation.
levels, phase
Flying
 Both AC-DC and
Capacitors redundancies are  Complex startup
MLI DC-AC Conversion
available.  Poor Switching applications.
efficiency
 We can control
reactive and real  Capacitors are  Converters with
expansive than harmonic distortion
power flow diodes capability.

 Electric vehicle
 Output voltages  Every H Bridge drives
levels are doubled needs a separate
the number of dc source  DC power source
CASCADED sources utilization.
H-BRIDGE  Easy and quick  Due to large  Power factor
MLI Manufacturing number of compensators.
 Packaging and sources,
Layout is Applications are  Back to back
modularized. Limited. frequency link
 We can control it systems.
Easily with a  Interfacing with
transformer renewable energy
 Inexpensive resources.

7
 CHAPTER 3
3.1. SYMMETRICAL &ASMMETRICAL MLI

The cascaded H-bridge MLI Two types depending upon the DC source.

1.Sigle DC source

2.Multiple DC source

In multiple DC Source the CHBMLI are connected in series. To increase the “n”
number of output voltage levels the several H-Bridge and DC source are used. To reduce the
switches in this topology the Symmetrical and Asymmetrical CHBMLI are utilized.

Fig :3.1.1 symmetrical multilevel inverter

the Symmetrical Cascaded H Bridge Inverter (SCHB-MLI) topology is show in

Fig3.1.1. In this Circuit, When MOSFET Controlled Switch is Turned On, the DC Voltage
Source and MOSFET Controlled Switch is connected in series, so that the current flows from
DC Source to MOSFET and the Diode becomes Reverse biased Condition. When MOSFET
controlled Switch is turned OFF, the Current flows via diode and the diode is forward biased.
The Circuit needs four DC voltage source,7 switches and 3 diodes. The 4 DC source are equal

8
with Voltage of 100VDC, and this circuit will generate Nine Level output voltage of 400VDC,
300VDC, 200VDC, 100VDC, 0VDC, -100VDC, -200VDC, -300VDC, -400VDC respectively.

In SCHBMLI the total Number of switches and the output voltage levels are obtained as
follows

Nlevel=2n+3 and NMOSFET=n+4

The Asymmetrical Cascaded H Bridge Inverter (ASCHB-MLI) topology is show in

Fig:3.1.2. In this Inverter the DC source magnitude are unequal. The DC source magnitude are
designed with binary form of voltage such as 25VDC, 50VDC, 100VDC respectively. Both the
inverter consists of same number of Power semiconductor switches but the voltage level varies.
In SCHBMLI the output voltage is 9level, where as in ASCHBMLI the output voltage is 15
level and they are 15Vdc, 30Vdc, 45Vdc, 60Vdc,75Vdc,90Vdc,105Vdc,0Vdc, -15Vdc, -
30Vdc, -45Vdc, -60Vdc, -75Vdc, -90Vdc, -105Vdc respectively.

In ASCHMLI the number of switches and number of levels are represented as follows

NLEVEL=2(n+1)-1
NMOSFET=n+4

Fig:3.1.2 Asymmetrical multilevel inverter

9
3.2. SWITCHING MODE OF OPERATION FOR 15 LEVEL PROPOSED
INVERTER
Mode :1 Maximum Positive output Voltage (Vdc)

When MOSFET Switch S1, S2, S3&S4 is turned ON, the maximum positive voltage
Vdc is united to the (+ve) terminal (a) of the load. When the MOSFET Switch S5 is turned ON,
the (-ve) terminal (b) of the load is connected to the ground and remaining all the switches are
in OFF condition. The current flows through the load from ‘a’ to ‘b’, so that the voltage
brought to bear across the load is +Vdc as shown in fig:3.2.1.

Fig:3.2.1. Output Voltage level Vab=Vdc to generate the Switching Sequence

10
MODE:2 :- Vout = 6Vdc/7

when MOSFET Switch S2, S3&S4 is turned ON and MOSFET Switch S1 is turned
OFF the current flows via Diode D1, So that the positive voltage 6Vdc/7 is united to the (+ve)
terminal (a) of the load. When the MOSFET Switch S5 is turned ON , the(-ve) terminal (b) of
the load is united to the ground and remaining all the switches are in OFF condition. The
current flows through the load from ‘a’ to ‘b’, so that the voltage brought to bear across the
load is + 6Vdc/7 as shown in fig:3.2.2

Fig:3.2.2: Output Voltage level Vab=6Vdc/7 to generate the Switching Sequence

11
MODE 3 :- Vout = 5Vdc/7

When MOSFET Switch S1, S3&S4 is turned ON and MOSFET Switch S2 is turned
OFF the current flows via Diode D2 So that the positive voltage 5Vdc/7 is united to the (+ve)
terminal (a) of the load. When the MOSFET S5 is turned ON, the (-ve) terminal (b) of the load
is united to the ground and remaining all the switches are in OFF condition. The current flows
through the load from ‘a’ to ‘b’, so that the voltage brought to bear across the load is +5Vdc/7
as shown in fig3.2.3.

Fig:3.2.3: Output Voltage level Vab=5Vdc/7 to generate the Switching Sequence

12
MODE 4:- Vout = 4Vdc/7

When MOSFET Switch S3 &S4 is turned ON and MOSFET Switch S1& S2 is turned
OFF the current flows via Diode D1 & D2. So that the positive voltage 4Vdc/7 is united to the
(+ve) terminal (a) of the load. When the MOSFET Switch S5 is turned ON, the (-ve) terminal
(b) of the load is united to the ground and remaining all the switches are in OFF condition. The
current flows through the load from ‘a’ to ‘b’, so that the voltage brought to bear across the
load is + 4Vdc/7 as shown in fig3.2.4.

13
 Fig:3.2.4 : Output Voltage level Vab=4Vdc/7 to generate the Switching Sequence

MODE :-5 Vout = 3Vdc/7

When MOSFET Switch S1, S2&S4 is turned ON and MOSFET Switch S3 is turned
OFF the current flows via Diode D3. So that the positive voltage 3Vdc/7 is united to the (+ve)
terminal (a) of the load. When the MOSFET Switch S5 is turned ON, the (-ve) terminal (b) of
the load is united to the ground and remaining all the switches are in OFF condition. The
current flows through the load from ‘a’ to ‘b’, so that the voltage brought to bear across the
load is +3Vdc/7 as shown in fig3.2.5.

Fig:3.2.5 : Output Voltage level Vab=3Vdc/7 to generate the Switching Sequence

14
MODE:-6 Vout = 2Vdc/7

When MOSFET switch S2 &S4 is turned ON and Switch S1& S3 is turned OFF the
current flows via Diode D1& D3. so that the positive voltage 2Vdc/7 is united to the (+ve)
terminal (a) of the load. When the MOSFET switch S5 is turned ON, the (-ve) terminal (b) of
the load is united to the ground and remaining all the switches are in OFF condition. The
current flows through the load from ‘a’ to ‘b’, so that the voltage brought to bear across the
load is + 2Vdc/7 as shown in fig3.2.6

Fig:3.2.6 : Output Voltage level Vab=2Vdc/7 to generate the Switching Sequence

15
MODE :- 7 Vout = Vdc/7

When MOSFET switch S1 & S4 is turned ON and MOSFET Switch S2 &S3 is turned
OFF the current flows via Diode D2 &D3. so that the positive voltage 1Vdc/7 is united to the
(+ve) terminal (a) of the load. When the MOSFET switch S5 is turned ON , the (-ve) terminal
(b) of the load is united to the ground and remaining all the switches are in OFF condition. The
current flows through the load from ‘a’ to ‘b’, so that the voltage brought to bear across the
load is + 1Vdc/7 as shown in fig.3.2.7

Fig:3.2.7 : Output Voltage level Vab=Vdc/7 to generate the Switching Sequence

16
MODE:- 8 Zero output voltage (0Vdc)

The Zero Output voltage level is produced by turning ON MOSFET Switch

S7&S5orS4&S6 and remaining controlled switches are in OFF condition. When MOSFET

switch S7 &S5 or S4 &S6 is turned ON, the output voltage across the load is zero as shown in

the fig3.2.8.

Fig:3.2.8 Output Voltage level Vab=0 Vdc to generate the Switching Sequence

17
MODE:-9 Vout = -1Vdc/7

When MOSFET Switch S1&S6 is turned ON and MOSFET Switch S2 & S3 is turned
OFF the Current flows via Diode D2 & D3, So that the Positive voltage Vdc/7 is united to the
(-ve) terminal (b) of the load. When the MOSFET switch S7 is turned ON, the (+ve) terminal
(a) of the load is united to the ground and remaining all the switches are in OFF condition. The
current flows through the load from ‘b’ to ‘a’, so that the voltage brought to bear across the
load is -1Vdc/7 as shown in fig3.2.9

Fig:3.2.9 Output Voltage level Vab=-1Vdc/7 to generate the Switching Sequence

18
MODE :- 10 Vout = -2Vdc/7

When MOSFET switch S2&S6 is turned ON and MOSFET Switch S1 & S3 is turned
OFF the Current flows via Diode D1 & D3, So that the Positive voltage 2Vdc/7 is united to the
(-ve) terminal (b) of the load. When the MOSFET switch S7 is turned ON , the (+ve) terminal
(a) of the load is united to the ground and remaining all the switches are in OFF condition. The
current flows through the load from ‘b’ to ‘a’, so that the voltage brought to bear across the
load is -2Vdc/7 as shown in fig3.2.10

Fig:3.2.10 Output Voltage level Vab=-2Vdc/7 to generate the Switching Sequence

19
MODE:-11 Vout = -3Vdc/7

When MOSFET Switch S1, S2&S6 is turned ON and MOSFET Switch S3 is turned
OFF the Current flows via Diode D3, So that the Positive voltage 3Vdc/7 is united to the (-ve)
terminal (b) of the load. When the MOSFET S7 is turned ON, the (+ve) terminal (a) of the
load is united to the ground and remaining all the switches are in OFF condition. The current
flows through the load from ‘b’ to ‘a’, so that the voltage brought to bear across the load is -
3Vdc/7 as shown in fig3.2.11

FIG 3.2.11 Output Voltage level Vab=-3Vdc/7 to generate the Switching Sequence

20
MODE:12 Vout = -4Vdc/7

When MOSFET Switch S3&S6 is turned ON and MOSFET Switch S1 & S2 is turned
OFF the Current flows via Diode D1 & D2 , So that the Positive voltage 4Vdc/7 is united to
the (-ve) terminal (b) of the load. When the MOSFET switch S7 is turned ON , the (+ve)
terminal (a) of the load is united to the ground and remaining all the switches are in OFF
condition. The current flows through the load from ‘b’ to ‘a’, so that the voltage brought to
bear across the load is -4Vdc/7 as shown in fig3.2.12

FIG 3.2.12 Output Voltage level Vab=-4Vdc/7 to generate the Switching Sequence

21
MODE:13 Vout = -5Vdc/7

When MOSFET switch S1, S3&S6 is turned ON and MOSFET Switch S2 is turned
OFF the Current flows via Diode D2 , So that the Positive voltage 5Vdc/7 is united to the (-ve)
terminal (b) of the load. When MOSFET switch S7 is turned ON, the (+ve) terminal (a) of the
load is united to the ground, remaining all the switches are in OFF condition. The current
flows through the load from ‘b’ to ‘a’, so that the voltage brought to bear across the load is -
5Vdc/7 as shown in FIG 3.2.13

FIG 3.2.13 Output Voltage level Vab=-5Vdc/7 to generate the Switching Sequence

22
MODE:14 Vout = -6Vdc/7

When MOSFET Switch S2, S3&S6 is turned ON and MOSFET Switch S1 is turned
OFF the Current flows via Diode D1, So that the Positive voltage 6Vdc/7 is united to the (-ve)
terminal (b) of the load. When the MOSFET switch S7 is turned ON , the (+ve) terminal (a) of
the load is united to the ground and remaining all the switches are in OFF condition. The
current flows through the load from ‘b’ to ‘a’, so that the voltage brought to bear across the
load is -6Vdc/7 as shown in FIG 3.2.14

FIG 3.2.14 Output Voltage level Vab=-6Vdc/7 to generate the Switching Sequence

23
MODE:15 Vout = -Vdc

When MOSFET Switch S1, S2, S3&S6 is turned ON, the Positive voltage Vdc/7 is
united to the (-ve) terminal (b) of the load. When the MOSFET switch S7 is turned ON , the
(+ve) terminal (a) of the load is united to the ground and remaining all the switches are in OFF
condition. The current flows through the load from ‘b’ to ‘a’, so that the voltage brought to
bear across the load is -Vdc as shown in FIG 3.2.15

FIG 3.2.15 Output Voltage level Vab= -Vdc to generate the Switching Sequence

24
 3.3. OUTPUT VOLTAGE ACCORDING TO THE SWITCHING ON-OFF
CONDITION

Vo S1 S2 S3 S4 S5 S6 S7

Vdc 1 1 1 1 1 0 0
6Vdc/7 0 1 1 1 1 0 0
5Vdc/7 1 0 1 1 1 0 0
4Vdc/7 0 0 1 1 1 0 0
3Vdc/7 1 1 0 1 1 0 0
2Vdc/7 0 1 0 1 1 0 0
Vdc/7 1 0 0 1 1 0 0
0Vdc 0 0 0 1 0 1 0
0Vdc 0 1 0 0 1 0 1
-Vdc/7 1 1 0 0 0 1 1
-2Vdc/7 0 0 0 0 0 1 1
-3Vdc/7 1 0 0 0 0 1 1
-4Vdc/7 0 1 1 0 0 1 1
-3Vdc/7 1 1 1 0 0 1 1
-2Vdc/7 0 0 1 0 0 1 1
-Vdc/7 1 0 1 0 0 1 1

Table:1. The Switching Combination That Generated The 15 Level Output Voltage
Level (0VDC, VDC/7,2VDC/7,3VDC/7, 4VDC/7,5VDC/7,6VDC/7, VDC , -VDC/7,-2VDC/7,-
3VDC/7,-4VDC/7, - 5VDC/7, -6VDC/7, -VDC)

25
 CHAPTER-4

4.1) MODULATION TECHNIQUE

Fig:4.1 modulation techniques

 Pulse width modulation (PWM), or pulse-duration modulation (PDM), is a method

of reducing the average power delivered by an electrical signal, by effectively chopping
it up into discrete parts.
 The average value of voltage (and current) fed to the load is controlled by turning the
switch between supply and load on and off at a fast rate.

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  PWM is particularly suited for running inertial loads such as motors, which are not as
easily affected by this discrete switching, because their inertia causes them to react
slowly.
 The PWM switching frequency has to be high enough not to affect the load, which is to
say that the resultant waveform perceived by the load must be as smooth as possible.
 The main aim of these modulation techniques is to enhance, the output of the inverters.
Various techniques are designed to control the PWM inverter switches in order to shape
up the PWM inverter output AC voltage or current to be very close to sine waveform.
 The quality of these, PWM techniques, depends on the amplitude of the fundamental
component, the harmonic content in the inverter output, the effect of harmonics on the
source, the switching losses, controllability and implementation.

4.2 MULTI CARRIER PWM

Number of modulation techniques is available for controlling the multilevel inverter
but multi-carrier pulse width modulation (MCPWM) techniques are frequently used due to its
simplicity and easy implementation.
These are two types
1.Phase Shifted PWM
2. Level Shifted PWM

4.2.1 PHASE SHIFTED PWM (PS-PWM)

In this technique, a suitable phase shift is introduced between the carrier signals to
improve the inverter performance. The important feature of this technique is, it provides self
even power distribution among the input dc sources, means no dc link voltage controlling is
required. The generation method of phase shifted carriers and waveforms for n level inverter
are depicted as show in Fig4.2.1

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 Fig:4.2.1 Method to generate Phase Shifted carrier signals

4.2.2 LEVEL SHIFTED PWM (LS-PWM)

In the LS-PWM methods all the carrier signals use triangular signals, cover the total
extent range of generated converter output voltage and consist same amplitude and frequency.
They are classified basically based on the placement of various carrier signals. For generation
of n level, n-1 carrier signals are required. The LS-PWM methods are used in the controlling
of inverters where power balancing is not required.
Carrier singles= N-1
N-no of levels
i) Phase Disposition PWM (PD-PWM):

The operating principle of PD-PWM is that the carriers signals are in same phase and
level shifted. Generation of one waveform of carrier signal is show in Fig.4.2.2(a) and with
the addition of constant +1 and -1 symmetrical (n-1) carrier signals can be generated for n
level inverter.

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 Fig:4.2.2(a) PD-PWM carrier signals

ii) Phase Opposition Disposition PWM (POD-PWM):

In case of POD-PWM technique, the carrier signals above the zero axes and below the
zero axes are 180˚ out of phase but the carriers above the zero axes or positive carrier
signals are in same phase and the carriers below the zero axes or negative carrier signals
are in same phase. The method to generate POD-PWM technique and generated carrier
signals are presented in Fig. 4.2.2(b). Two carrier signals- positive and negative are
generated and with the addition of constant +1 and -1 respectively, (n-1) carrier signals can
be generated for n level inverter.

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 Fig:4.2.2(b) POD PWM carrier signals

iii) ALTERNATE PHASE OPPOSITION DISPOSITION PWM (APODPWM)

In this method, the entire carrier signals are alternate 180˚ shifted with its neighbour is
demonstrated and it can be seen in Fig.4.2.2(c). Two carrier signals are generated above
and below of zero axis and alternate addition and subtraction of constant 2 in these two
signals can generate (n-1) number of pulses for n level inverter.

Fig:4.2.2(c) APOD-PWM carrier signals

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 CHAPTER-5
5.1 SIMULATION DIAGRAM OF 15-LEVEL ASCHBMLI
The ASCHBMLI consists of three DC source, seven Mosfet Controlled Switches and three
Diodes.the input dc voltages are 30v,60v,120v. For Low switching all switch are operated to
50Hz.For high switching ,s1,s2,s3 are operated to 2K Hz remaining switches are operated to
50Hz.

Fig:5.1 simulation diagram of a 15 level ASCHBMLI with PD-PWM technique.

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5.2 IN SUBSYSTEM
It consist of one Sine Wave, Repeating Sequences are 15, Relational Operators are
15.for the switches ON -OFF we are using the logical operators(NOT,AND,OR gates).

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5.3 SWTCHING PLUSES FOR LOW&HIGH FREQUENCY
The switching pulses of S1,S2 & S3 and the Switching Pulse of Cascaded H Bridge
inverter switches of S4,S5,S6 &S7 are shown in fig 5.3(a).

FIG:5.3(a) low switching frequency pulses

The switches of S1,S2 & S3 are generated with high switching frequency of
2KHz,where as in the Cascaded H bridge Inverter (CHBI), the Switches S4,S5,S6&S7 are
generated with low switching frequency of 50Hz as shown in fig 5.3(b).

Fig:5.3(b) high switching frequency pulses

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5.4 PD-PWM SWITCHING SIGNALs

The sine wave form frequency is 50Hz and triangle wave form frequency is 2K Hz.
This input is use for high switching. For low switching just change the triangles wave from
frequency is 50Hz. As show in fig 5.4

Fig:5.4 PD-PWM switching signals generate.

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 CHAPTER-6
6.1 SIMULATION RESULTS FOR LOW & HIGH SWITCHING FREQUENCY

1.FOR LOW SWITCHING

Fig :6.1.1 output voltage for 15 level ASCHBMLI for low switching

2. FOR HIGH SWITCHING

Fig: 6.1.2 output voltage for 15 level ASCHBMLI for high switching

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6.2 THD ANALYSIS OF LOW &HIGH SWITCHING FOR ASCHMLI

1.FOR LOW SWITCHING

Fig 6.2.1
2. FOR HIGH SWITCHING

Fig 6.2.2

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 CONCLUSION
A symmetrical Cascaded H bridge Multilevel inverter(SCHBMLI) and Asymmetrical
Cascaded H bridge Multilevel Inverter(ASCHBMLI) has been analysed in this report.
Generally in a 15 level number of bridges is7, Number of sources are 7 and switches present
are 28. But our work carried out on the asymmetric cascaded H-Bridge multilevel inverter uses
3 sources, 1 bridges and no of switches are 7.by using PD-PWM technique the THD values of
low and high switching are 5.57% and 8.86% respectively. This type of system is used for
high power applications for photovoltaic system because it reduce the overall cost and size of
the system.

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 REFERENCES
 15 level Asymmetrical cascaded H bridge Multilevel inverter with less number of
switches by J.gowri shankar &Dr.j .Belwin Edward.
 SBoobalan , R.Dhanasekaran ,Hybrid Topology of Asymmetric Cascaded Multilevel
Inverter with Renewable Energy Sources.
 T. V. V. S. Lakshmi, N. George, S. Umashankar, and D. P. Kothari, “Cascaded seven
level inverter with reduced number of switches using level shifting PWM technique”.
 THD analysis of cascaded h bridge multilevel inverter by Gurucharn singh ;IEEE
papers
 Mohamad fathi mohamad elias, nasrudin abd. Rahim, hew wooi ping, and mohammad
nasir uddin, asymmetrical cascaded multilevel inverter based on transistor-clamped h-
bridge power cell ieee transactions on industry applications, vol. 50, no. 6,
november/december 2014.

 Eduardo e. Espinosa, jose r. Espinoza, pedro e. Melín, roberto o. Ramírez, felipe

villarroel,javier a. Muñoz, member, and luis morán, fellow, ieeea new modulation
method for a 13-level asymmetric inverter toward minimum thd ieee transactions on
 Krishna Kumar Gupta, Shailendra Jain Comprehensive review of a recently proposed
multilevel inverter IET Power Electronics.
 Rasoul Shalchi Alishah1, Daryoosh Nazarpour1, Seyyed Hossein Hosseini2, Mehran
Sabahi2New hybrid structure for multilevel inverter with fewer number of components
for high-voltage levels in IET Power Electronics.

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