Definition

Pipelining is a technique wherein a sequential process is broken up into sub operations, with each sub
operation being executed in a special dedicated segment that operates concurrently with all other
segments. A pipeline can be visualized as a collection of processing segments. Each segment performs
partial processing. The result obtained from the computation in each segment is transferred to the next
segment in the pipeline. All the segments operated concurrently.

Sequential execution
Le t Fi and Ei refer to the fetch and execute steps for an instruction Ii. If we execute the instruction in
sequential order then processing sequence steps will be as follows

F1 E1 F2 E2 F3 E3 F4 E4

Pipeline Execution
Now consider a CPU that has two separate hardware units, one for fetching instructions and another for
executing them. The instruction fetch by the fetch unit is stored in an intermediate storage buffer B1.
The results of execution are stored in the destination location specified by the instruction. For simplicity
it is assumed that fetch and execute steps of any instruction can be completed in one clock cycle. Basic
idea of instruction pipelining with hardware organization is shown below.

Storage Buffer B1
Instruction Fetch Execution Unit
Unit

Pipeline Hazards
The ideal pipeline executes instructions during each clock cycle so that the pipeline hardware is always
doing something useful. Real pipelines with real instructions can encounter situations where an
instruction would not execute correctly because of problems with other instructions already in the
pipeline. These situations are called hazards.

There 3 types of hazard occurs in pipeline defined as below-----

1. Structural hazards - When hardware units are being used by instructions already in the pipeline,
these units will not be available for use by other instructions. Any situation where there is not enough
hardware is a structural hazard.

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 2. Data hazards - Data hazards can occur when two instructions use data from the same register.
Data hazards are divided into three categories.
 RAW (read after write) hazards - the current instruction must wait to read data until after a
previous instruction writes the correct data.
 WAR (write after read) hazards - the current instruction must wait to write data until after
a previous instruction reads the old data.
 WAW (write after write) hazards - the current instruction must wait to write data until
after a previous instruction writes to the same register. This hazard is more subtle in that
neither instruction executes incorrectly. However, subsequent instructions can be incorrect if
the writes occur out of order.

3. Control hazards - In the ideal pipeline, we fetch instructions one after another in order. As long as
location of the next instruction is known, this process can go forward. When a branch instruction is
fetched, the next instruction location is not known until the branch instruction finishes execution. Thus,
we may have to wait until the correct location of the next instruction is known before fetching more
instructions. This is a control hazard.

Solutions for Control Hazards

The following are solutions that have been proposed for mitigating aspects of control hazards:

 Pipeline stall cycles. Freeze the pipeline until the branch outcome and target are known, then proceed
with fetch. Thus, every branch instruction incurs a penalty equal to the number of stall cycles. This
solution is unsatisfactory if the instruction mix contains many branch instructions, and/or the pipeline
is very deep.

 Branch delay slots. The ISA is constructed such that one or more instructions sequentially following
a conditional branch instruction are executed whether or not the branch is taken. The compiler or
assembly language writer must fill these branch delay slots with useful instructions or NOPs (no-
operation opcodes). This solution doesn't extend well to deeper pipelines, and becomes architectural
baggage that the ISA must carry into future implementations.

 Branch prediction. The outcome and target of conditional branches are predicted using some
heuristic. Instructions are speculatively fetched and executed down the predicted path, but results are
not written back to the register file until the branch is executed and the prediction is verified. When a
branch is predicted, the processor enters a speculative mode in which results are written to another
register file that mirrors the architected register file. Another pipeline stage called the commit stage is
introduced to handle writing verified speculatively obtained results back into the "real" register file.
Branch predictors can't be 100% accurate, so there is still a penalty for branches that is based on the
branch misprediction rate.

 Indirect branch prediction. Branches such as virtual method calls, computed gotos and jumps through
tables of pointers can be predicted using various techniques.

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 Return address stack (RAS). Procedure returns are a form of indirect jump that can be perfectly
predicted with a stack as long as the call depth doesn't exceed the stack depth. Return addresses are
pushed onto the stack at a call and popped off at a return.

RISC (Reduced Instruction Set Computer)

 In RISC, an instruction executes in single clock cycle, where clock cycle is the speed of a computer
processor, or CPU in which during each cycle, a CPU can perform a basic operation such as fetching
an instruction, accessing memory, or writing data.
 An instruction set composed of a few basic steps like loading, evaluating and storing so it requires a
greater number of registers.
 Simpler fixed size instructions hence simpler instructions decoding and have simple ‘addressing
modes.
 Fixed size instructions mean, all the instructions in RISC have same length.
 In RISC, Pipelining is easy as the execution of all instructions will be done in a uniform interval of
time i.e. one click
 RISC processor is implemented using the hardwired control unit. The hardwired control unit
produces control signals which regulate the working of processors hardware.

Five Stage Pipeline for RISC Processor

1. IF – Instruction Fetch – In this stage the CPU reads instructions from the address in the memory
whose value is present in the program counter.

2. ID – Instruction Decode – In this stage, instruction is decoded and the register file is accessed to get
the values from the registers used in the instruction.

3. EX- Execute – In this stage, ALU operations are performed.

4. MEM- Memory Access – In this stage, memory operands are read and written from/to the memory
that is present in the instruction.

5. WB- Write Back – In this stage, computed/fetched value is written back to the register present in the
instructions