A High-Performance Single-Phase AC-DC Power Factor Corrected Boost Converter for plug in

Hybrid Electric Vehicle Battery Chargers

1
Fariborz Musavi Wilson Eberle
Student Member IEEE Member IEEE

2
William G. Dunford
Senior Member IEEE

Delta-Q Technologies Corp. The University of British Columbia

1
Burnaby, BC, Canada Kelowna, BC, Canada | 2 Vancouver, BC, Canada
1
fmusavi@delta-q.com wilson.eberle@ubc.ca, 2 wgd@ece.ubc.ca

Abstract -- In this paper, several conventional plug in hybrid

electric vehicle charger front end AC-DC converter topologies II. REVIEW OF EXISTING TOPOLOGIES
are investigated and a new bridgeless interleaved PFC converter
is proposed to improve the efficiency and performance. A. Conventional Boost Converter
Experimental and simulation results of a prototype boost
converter converting universal AC input voltage to 400 V DC at The conventional boost topology is the most popular
3.4 kW are given to verify the proof of concept, and analytical topology for PFC applications. It uses a dedicated diode
work reported in this paper. bridge to rectify the AC input voltage to DC, which is then
followed by the boost section, as shown in Fig. 2. In this
Index Terms—Bridgeless PFC, Interleaved PFC, PFC boost topology, the output capacitor ripple current is very high [8]
converter, PHEV charger.
and is the difference between diode current and the dc output
current. Furthermore, as the power level increases, the diode
I. INTRODUCTION
bridge losses significantly degrade the efficiency, so dealing
A plug-in hybrid electric vehicle (PHEV) is a hybrid with the heat dissipation in a limited area becomes
vehicle with a storage system that can be recharged by problematic. Due to these constraints, this topology is good
connecting the vehicle plug to an external electric power for a low to medium power range up to approximately 1kW.
source [1]. The accepted charger power architecture includes For power levels >1kW, typically, designers parallel
an AC-DC converter with power factor correction (PFC) [2] semiconductors in order to deliver greater output power. The
followed by an isolated DC-DC converter with input and inductor volume also becomes a problematic design issue at
output EMI filters [3], as shown in Fig. 1. Selecting the high power.
optimal topology and evaluating power loss in the power LB DB
semiconductors are important steps in the design and
development of these battery chargers. The front-end AC-DC
converter is a key component of the charger system, and a D1 D4
L
proper topology selection is essential to meet the regulatory O
Vin A
requirements of input current harmonics [4-6], output voltage D
QB Co
regulation and implementation of power factor correction [7]. D3
D2

Fig. 2. Conventional PFC boost converter

B. Bridgeless Boost Converter

Fig. 1. Simplified system block diagram of a universal battery charger
In the following sub-sections, three existing continuous
conduction mode (CCM) AC/DC PFC boost converters are
evaluated, and a solution is proposed for front end AC/DC
converter.
The bridgeless configuration topology avoids the need for
the rectifier input bridge yet maintains the classic boost
topology [9-16], as shown in Fig. 3. It is an attractive solution
for applications >1kW, where power density and efficiency
are important. The bridgeless boost converter solves the
problem of heat management in the input rectifier diode
bridge, but it introduces increased EMI [17, 18].
Another disadvantage of this topology is the floating input

978-1-4244-5287-3/10/$26.00 ©2010 IEEE 3588

line with respect to the PFC stage ground, which makes it
impossible to sense the input voltage without a low frequency
transformer or an optical coupler. Also in order to sense the
input current, complex circuitry is needed to sense the current
in the MOSFET and diode paths separately, since the current
path does not share the same ground during each half-line
cycle [11, 19].

Fig. 5. Proposed bridgeless interleaved (BLIL) PFC boost converter

TABLE I
REVIEW OF EXCISING TOPOLOGIES FOR BOOST CONVERTER
Conventio- Bridgeless Interleaved BLIL
Topology
nal PFC PFC PFC PFC
Power Rating < 1000 W < 2000W < 3000W > 3000W
EMI / Noise Fair Poor Best Fair

Fig. 3. Bridgeless PFC boost converter
C. Interleaved Boost Converter
The interleaved boost converter, Fig. 4, is simply two
boost converters in parallel operating 180° out of phase [20-
22]. The input current is the sum of the two inductor currents
ILB1 and ILB2. Because the inductors’ ripple currents are out of
phase, they tend to cancel each other and reduce the input
ripple current caused by the boost switching action. The
interleaved boost converter has the advantage of paralleled
semiconductors. Furthermore, by switching 180° out of
phase, it doubles the effective switching frequency and
introduces smaller input current ripples, so the input EMI
filters will be smaller [23-25]. It also reduces output capacitor
high frequency ripple, but it still has the problem of heat
management for the input diode bridge rectifiers.
In the following section, a new bridgeless interleaved
boost PFC converter is proposed in order to improve overall
efficiency of the AC-DC PFC converter, while maintaining
all the advantages of the existing solutions.
Fig. 4. Interleaved PFC boost converter
III. BRIDGELESS INTERLEAVED BOOST TOPOLOGY
The bridgeless interleaved (BLIL) PFC converter shown in
Fig. 5 is proposed to address the problems discussed in
section II. This converter introduces two more MOSFETs and
two more fast diodes in place of 4 slow diodes used in the
input bridge of the interleaved boost PFC converter.
A detailed converter description and steady state operation
analysis is given in the following section. Table 1 shows the
advantages and disadvantages of each topology.
Capacitor Ripple High High Low Low
Input Main
High High Low Low
Ripple
Magnetic Size Large Medium Small Small
Efficiency Poor Fair Fair Best
IV. CIRCUIT OPERATION AND STEADY STATE ANALYSIS
To analyze the circuit operation, the input line cycle has
been separated into the positive and negative half cycles as
explained in sub-sections A and B that follow. In addition,
the detailed circuit operation depends on the duty cycle,
therefore positive half cycle operation analysis is provided for
D > 0.5 in sub-section C and D < 0.5 in sub-section D.
A. Positive Half Cycle Operation
Referring to Fig. 5, during the positive half cycle, when
the AC input voltage is positive, Q1/Q2 turn on and current
flows through L1 and Q1 and continues through Q2 and then
L2, returning to the line while storing energy in L1 and L2.
When Q1/Q2 turn off, energy stored in L1 and L2 is released
as current flows through D1, through the load and returns
through the body diode of Q2 back to the input mains.
With interleaving, the same mode happens for Q3/Q4, but
with a 180 degree phase delay. The operation for this mode is
Q3/Q4 on storing energy in L3/L4 through the path L3-Q3-
Q4-L4 back to the input. When Q3/Q4 turn off, energy is
released through D3 to the load and returning through the
body diode of Q4 back to the input mains.
B. Negative Half Cycle Operation
Referring to Fig. 5, during the negative half cycle, when
the AC input voltage is negative, Q1/Q2 turn on and current
flows through L2 and Q2 and continues through Q1 and then
L1, returning to the line while storing energy in L2 and L1.
When Q1/Q2 turn off, energy stored in L2 and L1 is released
as current flows through D2, through the load and returns

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through the body diode of Q1 back to the input mains.
With interleaving, the same mode happens for Q3/Q4, but
with a 180 degree phase delay. The operation for this mode is
Q3/Q4 on storing energy in L3/L4 through the path L4-Q4-
Q3-L3 back to the input.

C. Detailed Positive Half Cycle Operation and Analysis for

D > 0.5
The detailed operation of the proposed BLIL PFC
converter depends on the duty cycle. During any half cycle,
the converter duty cycle is either greater than 0.5 (when the
input voltage is smaller than half of output voltage) or smaller
than 0.5 (when the input voltage is greater than half of output
voltage).
Fig. 6 shows the three unique operating interval circuits of
the proposed converter for duty cycles greater than 0.5 during
positive half cycle operation. Waveforms of the proposed
converter during these conditions are shown in Fig. 7.

a) Interval 1: Q1 and Q2 are “ON”, and body diode of Q4 conducting

Fig. 7. BLIL PFC boost converter steady-state Waveforms at D > 0.5

Since the switching frequency of proposed converter is

much higher than the frequency of input line voltage, the
input voltage is considered constant during one switching
b) Intervals 2 and 4: Q1, Q2, Q3 and Q4 are “ON”
period . The input voltage is given by:

√2 | | (1)
In a positive half cycle of the input voltage, the duty ratio
of the proposed converter determines the following voltage
relation:
(2)
The intervals of operation are explained as follows. In
addition, the ripple current components are derived, enabling
calculation of the input ripple current, which provides design
guidance to meet the required input current ripple standard.
Interval 1 [t0-t1]: At t0, Q1/ Q2 are ON, and Q3/Q4 are off,
c) Interval 3: Q3 and Q4 are “ON”, and body diode of Q2 conducting
as shown in Fig. 6-a. During this interval, the current in series
Fig. 6. BLIL PFC boost converter operating at D > 0.5

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inductances L1 and L2 increases linearly and stores the ∆ (12)
energy in these inductors. The ripple currents in Q1 and Q2
Similarly, the ripple currents Q3 and Q4 are the same as
are the same as the current in series inductances L1 and L2,
the ripple current in series inductances L3 and L4:
where the ripple current is given by:
∆ (13)
∆ 1 (3)
The input ripple current is the sum of currents in L1/L2 and
The current in series inductances L3 and L4 decreases
L3/L4:
linearly and transfers the energy to the load through D3, Co
and body diode of Q4. The ripple current in series ∆ (14)
inductances L3 and L4 is given by:
D. Detailed Positive Half Cycle Operation and Analysis for
∆ 1 (4) D < 0.5
The input ripple current is the sum of currents in L1/L2 and
Fig. 8 shows the operating interval circuits of the proposed
L3/L4: converter for duty cycles smaller than 0.5 during the positive
∆ 1 (5) half cycle. The waveforms of the proposed converter during
Interval 2 [t1-t2]: At t1, Q3/Q4 are turned on, while Q1/Q2 these conditions are shown in Fig. 9. The intervals of
remain on, as shown I Fig. 6-b. During this interval, the operation are explained as follows.
current in the four inductors each increase linearly, storing
energy in these inductors. The ripple currents in Q1 and Q2
are the same as the ripple current in series inductances L1 and
L2 as given by.

∆ (6)
Similarly, the ripple currents in Q3 and Q4 are the same as
the ripple current in series inductances L3 and L4:

∆ (7)
The input ripple current is the sum of currents in L1/L2 and a) Intervals 1 and 3: Body diodes of Q2 and Q4 conducting
L3/L4:
∆ (8)
Interval 3 [t2-t3]: At t2, Q1/Q2 are turned off, while Q3/
Q4 remain on, as shown in Fig. 6-c. During this interval, the
current in series inductances L3 and L4 increases linearly and
stores the energy in these inductors. The ripple currents in Q3
and Q4 are the same as the ripple current in series
inductances L3 and L4:

∆ 1 (9)
The current in L1 and L2 decreases linearly and transfers the b) Interval 2: Q1 and Q2 are “ON”, and body diode of Q4 conducting
energy to the load through D1, Co and body diode of Q2. The
ripple current in series inductances L1 and L2 is given by:

∆ 1 (10)
The input ripple current is the sum of currents in L1/L2 and
L3/L4:
∆ 1 (11)
Interval 4 [t3-t4]: At t3, Q3/Q4 remain on, while Q1/Q2 are
turned on, as shown I Fig. 6-b. During this interval, the
currents in the four inductors each increase linearly, storing
energy in these inductors. The ripple currents in Q1 and Q2 c) Interval 4: Q3 and Q4 are “ON”, and body diode of Q2 conducting
are the same as the ripple currents in L1 and L2:
Fig. 8. BLIL PFC boost converter operating at D < 0.5

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Fig. 9. BLIL PFC boost converter steady-state waveforms at D < 0.5
Interval 1 [t0-t1]: At t0, Q1 and Q2 turn off, while Q3 and
Q4 remain off, as shown in Fig. 8-a. During this interval, the
current in series inductances L1 and L2 decreases linearly
and transfers the energy to the load through D1, Co and body
diode of Q2. The ripple current in series inductances L1 and
L2 is:
∆ (15)
In addition, the current in the series inductances L3 and L4
also decreases linearly, transferring the energy to the load
through D3, Co and body diode of Q4. The ripple currents in
series inductances L3 and L4 is:
∆ (15)
The input current is the sum of currents in L1/L2 and L3/L4:
∆ (16)
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Interval 2 [t1-t2]: At t1, Q1/Q2 turn on, while Q3/Q4
remain off, as shown in Fig. 8-b. During this interval, the
current in series inductances L1 and L2 increases linearly,
storing energy in these inductors. The ripple currents in Q1
and Q2 are the same as the current in series inductances L1
and L2, where the ripple current is given by:
∆ (17)
The current in series inductances L3 and L4 decreases
linearly and transfers the energy to the load through D3, Co
and body diode of Q4. The ripple current in L3 and L4 is:
∆ (18)
The input ripple current is the sum of the currents in L1/L2
and L3/L4:
∆ (19)
Interval 3 [t2-t3]: At t2, Q1/Q2 are turned off, while Q3/Q4
remain off, as shown in Fig. 8-a. During this interval, the
current in series inductances L1 and L2 decreases linearly
and transfers the energy to the load through D1, Co and body
diode of Q2. The ripple current in series inductances L1 and
L2 is given by:
∆ (20)
Similarly, the current in the series inductances L3 and L4 also
decreases linearly, transferring the energy to the load through
D3, Co and body diode of Q4. The ripple current in series
inductances L3 and L4 is:
∆ (21)
The input current is the sum of currents in L1/L2 and L3/L4:
∆ (22)
Interval 4 [t3-t4]: At t3, Q3/Q4 are turned on, while Q1/Q2
remain off, as shown in Fig. 8-c. During this interval, the
current in series inductances L3 and L4 increases linearly and
stores the energy in these inductors. The ripple currents in
Q3 and Q4 are the same as the current in series inductances
L3 and L4, where the ripple current is given by:
∆ (23)
The current in series inductances L1 and L2 decreases
linearly and transfers the energy to the load through D2, Co
and body diode of Q4. The ripple current in L1 and L2 is:
∆ (24)
The input ripple current is the sum of currents in L1/L2 and
L3/L4:
∆ (25)
The operation of converter during the negative input
voltage half cycle is similar to the operation of converter
during the positive input voltage half cycle.
 V. SIMULATION RESULTTS
PSIM simulation software was used to vverify steady state
waveforms of each component. Fig. 10 sshows the PSIM
simulation circuits of the proposed BLIL PFC
C converter. As it
can be seen the power stage section of convverter consists of
four boost inductors – Ld1 to Ld4, four fasst boost diodes –
Db1 to Db4, four switches – Q1 to Q4 and ttheir body diodes
Dq1 to Dq4. Also it consists of two currennt loops and one
voltage loop. The sensed input voltage is mmultiplied by the
Fig. 10. PSIM simulation circuit for the proposed BLIL
L PFC boost converter
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compensated output voltage, and then generates a control
signal to be compared with the switching career waveforms
to generate the gating signals for maain FETs.
Fig. 11 shows the PSIM simulatiion results of a BLIL PFC
boost converter. The input current is in phase with input
voltage, and it has close to unity y power factor. Also the
output voltage is regulated at arou und 400V, with a 120 Hz
low frequency ripple. The converteer is operating at 70 kHz
switching frequency, 240 V input voltage
v and 3.4 kW output
power.
Fig. 11. Simulation waveforms for the proposed BLIL PFC boost converter
including output voltage, input voltage and in
nput current
VI. EXPERIMENTA
TAL RESULTS
An experimental prototype, illusttrated in Fig. 12, was built
to verify the operation of the proposed converter. Fig. 13
shows the input voltage, input curren nt and PFC bus voltage of
the converter under the following test
t conditions: Vin = 240
V, Iin = 15 A, Po = 3400 W, fsw = 700 kHz. The input current is
in line and phase with the input volttage, and its shape is close
to a sinusoidal waveform.
In order to verify the quality of the input current, its
harmonics up to 39th harmonic order are given and compared is available from the mains feed to charge the batteries,
with the EN 61000-3-2 standard. Fig. 14 shows the input reducing charging time and electricity costs.
current harmonics versus harmonic numbers at full load for
120 V and 240 V input voltages. It is clearly shown that the 2.5
generated harmonics are well below IEC 61000-3-2 standard
for the input line harmonics which is required for PHEV 2
EN 61000-3-2 Class D Limits (A)

Harmonic Current (A)

chargers. In Fig. 15, the input current total harmonics
distortions are given at full load and for 120 V and 240 V 1.5 Amplitude (A) Vin = 120 V
input voltages. It can be noted that mains current THD are Amplitude (A) Vin = 240 V
smaller than 5% from 50% load to full load and it is 1
compliant to IEC 6100-3-2. Another parameter to show the
quality of input current is power factor. In Fig. 16, the 0.5
converter power factor is shown at full load for different
input voltages. As it can be seen, power factor is greater than 0
0.99 from 50% load to full load.

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
3
5
7
9
Harmonics Order
Fig. 14. Input current harmonics at full load for Vin = 120 V and 240 V

45
40
35

20 cm 30
THD (%)

25
Vin=240
20
15 Vin=120
10
5
Fig. 12. Breadboard prototype of BLIL PFC boost converter 0
500

1000

1500

2000

2500

3000

3500
0

Output Power (W)

Output Voltage Fig. 15. Total harmonics distortion vs. output power at Vin = 120V and Vin
Input Voltage
= 240V

1.02
1
0.98
0.96
Power factor

0.94
Input Current Vin=240
0.92
0.9 Vin=120
0.88
Fig. 13. Proposed BLIL PFC experimental waveforms; Test Condition: Po =
3400W, Vin = 240V, Iin = 15A 0.86

The efficiency of converter versus output power for 0.84

different input voltages is provided in Fig. 17. High
0

500

1000

1500

2000

2500

3000

3500

efficiency over entire load range is achieved in this topology, Output Power (W)
enabling fewer problems with heat dissipation and cooling Fig. 16. Power Factor vs. output power at Vin = 120V and Vin = 240V
systems. Furthermore, a higher efficiency means more power

3594
 100 [7] "Guide to Energy Management - Power Factor," BC Hydro, Vancouver
2000.
99 [8] Dehong Xu; Jindong Zhang; Weiyun Chen; Jinjun Lin; Lee, F.C.;,
98 "Evaluation of output filter capacitor current ripples in single phase
PFC converters " in Proceedings of the Power Conversion Conference,
97 PCC. vol. 3 Osaka, Japan, 2002, pp. 1226 - 1231.
Efficiency (%)

96 [9] Lu, B.; Brown, R.; Soldano, M.;, "Bridgeless PFC implementation
Vin=240 V using one cycle control technique," in IEEE Applied Power Electronics
95 Conference and Exposition. vol. 2, 2005, pp. 812 - 817.
94 [10] Petrea, C.; Lucanu, M.;, "Bridgeless Power Factor Correction
Vin=220 V
Converter Working at High Load Variations," in International
93 Symposium on Signals, Circuits and Systems, ISSCS. vol. 2, 2007, pp. 1
Vin=120 V -4
92
[11] U. Moriconi;, "A Bridgeless PFC Configuration based on L4981 PFC
91 Vin=90 V Controller ": STMicroelectronics Application Note AN1606, 2002.
90 [12] J. M. Hancock;, "Bridgeless PFC Boosts Low-Line Efficiency,"
Infineon Technologies, 2008.
0

500

1000

1500

2000

2500

3000

3500
Output Power (W)
Fig. 17. Efficiency vs. output power at Vin = 90V, Vin = 120V, Vin = 220V
and Vin = 240V
VII. CONCLUSION
A high performance AC-DC boost converter topology has
been presented in this paper for the front-end AC-DC
converter in PHEV battery chargers. The proposed converter
topology has been analyzed and performance characteristics
presented. A prototype converter was built to verify the
proof-of-concept.
The theoretical waveforms were compared with the
simulation results and the results taken from prototype unit.
Also some key experimental waveforms are given. Finally
input current harmonics at each harmonic order was
compared more explicitly with the IEC 6100-3-2 standard
limits. The total harmonics distortion and power factor was
measured on prototype unit and showed great results.
The converter topology shows a high input power factor,
high efficiency over entire load range and excellent input
current harmonics. It is an excellent option for single phase
PFC solution in higher power applications.
REFERENCES
[1] K. Morrow, D. Karner, and J. Francfort;, "Plug-in Hybrid Electric
Vehicle Charging Infrastructure Review," U.S. Departent of Energy -
Vehicle Technologies Program, 2008.
[2] Singh, B.; Singh, B.N.; Chandra, A.; Al-Haddad, K.; Pandey, A.;
Kothari, D.P.;, "A review of single-phase improved power quality AC-
DC converters," Industrial Electronics, IEEE Transactions on vol. 50,
pp. 962 - 981 2003
[3] Petersen, L.; Andersen, M.;, "Two-Stage Power Factor Corrected
Power Supplies: The Low Component-Stress Approach " in IEEE
Applied Power Electronics Conference and Exposition, APEC. vol. 2,
2002, pp. 1195 - 1201.
[4] Key, T.S.; Jih-Sheng Lai;, "IEEE and International Harmonic Standards
Impact on Power Electronic Equipment Design," in International
Conference on Industrial Electronics, Control and Instrumentation,
IECON. vol. 2, 1997, pp. 430 - 436.
[5] "IEEE Std 519-1992 IEEE Recommended Practices and Requirements
for Harmonic Control in Electrical Power Systems," IEEE 1992.
[6] "Compliance testing to the IEC 1000-3-2 (EN 61000-3-2) and IEC
1000-3-3 (EN 61000-3-3) Standards ": Agilent Technology.
[13] Yungtaek Jang; Jovanovic, M.M.; Dillman, D.L.;, "Bridgeless PFC
boost rectifier with optimized magnetic utilization," in IEEE Applied
Power Electronics Conference and Exposition, 2008, pp. 1017 – 1021.
[14] Yungtaek Jang; Jovanovic, M.M.;, "A Bridgeless PFC Boost Rectifier
With Optimized Magnetic Utilization," IEEE Transactions on Power
Electronics, vol. 24, pp. 85 - 93 2009.
[15] Woo-Young Choi; Jung-Min Kwon; Eung-Ho Kim; Jong-Jae Lee;
Bong-Hwan Kwon;, "Bridgeless Boost Rectifier With Low Conduction
Losses and Reduced Diode Reverse-Recovery Problems," IEEE
Transactions on Industrial Electronics, vol. 54, pp. 769 – 780, April
2007 2007.
[16] Huber, L.; Yungtaek Jang; Jovanovic, M.M.;, "Performance Evaluation
of Bridgeless PFC Boost Rectifiers," IEEE Transactions on Power
Electronics, vol. 23, pp. 1381 - 1390 2008.
[17] Pengju Kong; Shuo Wang; Lee, F.C.;, "Common Mode EMI Noise
Suppression for Bridgeless PFC Converters," IEEE Transactions on
Power Electronics, vol. 23, pp. 291 – 297, January 2008 2008.
[18] Baur, T.; Reddig, M.; Schlenk, M.;, "Line-conducted EMI-behaviour of
a High Efficient PFC-stage without input rectification," Infineon
Technology – Application Note, 2006.
[19] Frank, W.; Reddig, M.; Schlenk, M.;, "New control methods for
rectifier-less PFC-stages," in EEE International Symposium on
Industrial Electronics. vol. 2, 2005, pp. 489 - 493
[20] M. O’Loughlin;, "An Interleaved PFC Preregulator for High-Power
Converters." vol. Topic 5: Texas Instrument Power Supply Design
Seminar, 2007, pp. 5-1, 5-14.
[21] Yungtaek Jang; Jovanovic, M.M.;, "Interleaved Boost Converter With
Intrinsic Voltage-Doubler Characteristic for Universal-Line PFC Front
End," IEEE Transactions on Power Electronics, vol. 22, pp. 1394 –
1401, July 2007 2007.
[22] Balogh, L.; Redl, R.;, "Power-factor correction with interleaved boost
converters in continuous-inductor-current mode," in IEEE Applied
Power Electronics Conference and Exposition, 1993, pp. 168 - 174
[23] Chuanyun Wang; Ming Xu; Lee, F.C.;, "Asymmetrical interleaving
strategy for multi-channel PFC," in IEEE Applied Power Electronics
Conference and Exposition, 2008, pp. 1409 - 1415.
[24] Pengju Kong; Shuo Wang; Lee, F.C.; Chuanyun Wang;, "Common-
Mode EMI Study and Reduction Technique for the Interleaved
Multichannel PFC Converter," IEEE Transactions on Power
Electronics, vol. 23, pp. 2576 - 2584 2008.
[25] Chuanyun Wang; Ming Xu; Lee, F.C.; Bing Lu;, "EMI Study for the
Interleaved Multi-Channel PFC," in IEEE Power Electronics
Specialists Conference, PESC, 2007, pp. 1336 - 1342

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