PIC24FJXXXGA0XX Flash Programming Specification

PIC24FJXXXGA0XX
PIC24FJXXXGA0XX Flash Programming Specification
1.0 DEVICE OVERVIEW The Enhanced In-Circuit Serial Programming

(Enhanced ICSP) protocol uses a faster method that
This document defines the programming specification takes advantage of the programming executive, as
for the PIC24FJXXXGA0XX family of 16-bit micro- illustrated in Figure 2-1. The programming executive
controller devices. This programming specification is provides all the necessary functionality to erase, pro-
required only for those developing programming support gram and verify the chip through a small command set.
for the PIC24FJXXXGA0XX family. Customers using The command set allows the programmer to program
only one of these devices should use development the PIC24FJXXXGA0XX devices without having to
tools that already provide support for device deal with the low-level programming protocols of the
programming. chip.
This specification includes programming specifications
for the following devices: FIGURE 2-1: PROGRAMMING SYSTEM
OVERVIEW FOR
• PIC24FJ16GA002 • PIC24FJ96GA006
ENHANCED ICSP™
PIC24FJXXXGA0XX
• PIC24FJ32GA004 • PIC24FJ128GA006 Programming
Programmer
Executive
• PIC24FJ64GA002
• PIC24FJ64GA004 On-Chip Memory
• PIC24FJ64GA006
• PIC24FJ64GA008
• PIC24FJ64GA010 This specification is divided into major sections that
describe the programming methods independently.
Section 4.0 “Device Programming – Enhanced
2.0 PROGRAMMING OVERVIEW ICSP” describes the Run-Time Self-Programming
OF THE PIC24FJXXXGA0XX (RTSP) method. Section 3.0 “Device Programming –
FAMILY ICSP” describes the In-Circuit Serial Programming
method.
There are two methods of programming the
PIC24FJXXXGA0XX family of devices discussed in 2.1 Power Requirements
this programming specification. They are:
All devices in the PIC24FJXXXGA0XX family are dual
• In-Circuit Serial Programming™ (ICSP™)
voltage supply designs: one supply for the core and
• Enhanced In-Circuit Serial Programming peripherals and another for the I/O pins. A regulator is
(Enhanced ICSP) provided on-chip to alleviate the need for two external
The ICSP programming method is the most direct voltage supplies.
method to program the device; however, it is also the All of the PIC24FJXXXGA0XX devices power their core
slower of the two methods. It provides native, low-level digital logic at a nominal 2.5V. To simplify system
programming capability to erase, program and verify design, all devices in the PIC24FJXXXGA0XX family
the chip. incorporate an on-chip regulator that allows the device
to run its core logic from VDD.
© 2008 Microchip Technology Inc. DS39768D-page 1

PIC24FJXXXGA0XX
The regulator provides power to the core from the other FIGURE 2-3: CONNECTIONS FOR THE
VDD pins. A low-ESR capacitor (such as tantalum) must ON-CHIP REGULATOR
be connected to the VDDCORE pin (Figure 2-2 and (28/44-PIN DEVICES)
Figure 2-3). This helps to maintain the stability of the
regulator. The specifications for core voltage and capac- Regulator Enabled (DISVREG tied to VSS):
itance are listed in Section 7.0 “AC/DC Characteristics
and Timing Requirements”. 3.3V
PIC24FJXXXGA0XX
FIGURE 2-2: CONNECTIONS FOR THE VDD
ON-CHIP REGULATOR DISVREG
(64/80/100-PIN DEVICES)
VDDCORE/VCAP
Regulator Enabled (ENVREG tied to VDD): CEFC
(10 μF typ) VSS
3.3V
PIC24FJXXXGA0XX
VDD Regulator Disabled (DISVREG tied to VDD):
ENVREG
2.5V(1) 3.3V(1)
VDDCORE/VCAP
PIC24FJXXXGA0XX
CEFC
VSS VDD
(10 μF typ)
DISVREG
VDDCORE/VCAP
Regulator Disabled (ENVREG tied to ground):
VSS
2.5V(1) 3.3V(1)
PIC24FJXXXGA0XX
VDD Regulator Disabled (VDD tied to VDDCORE):
ENVREG
2.5V(1)
VDDCORE/VCAP PIC24FJXXXGA0XX
VDD
VSS
DISVREG
VDDCORE/VCAP
Regulator Disabled (VDD tied to VDDCORE): VSS
2.5V(1)
PIC24FJXXXGA0XX
VDD Note 1: These are typical operating voltages. Refer
to Section 7.0 “AC/DC Characteristics and
ENVREG Timing Requirements” for the full operating
ranges of VDD and VDDCORE.
VDDCORE/VCAP
VSS
Note 1: These are typical operating voltages. Refer

to Section 7.0 “AC/DC Characteristics and
Timing Requirements” for the full operating
ranges of VDD and VDDCORE.
DS39768D-page 2 © 2008 Microchip Technology Inc.

PIC24FJXXXGA0XX
2.2 Program Memory Write/Erase 2.3 Pin Diagrams
Requirements The pin diagrams for the PIC24FJXXXGA0XX family
The Flash program memory on the PIC24FJXXXGA0XX are shown in the following figures. The pins that are
devices has a specific write/erase requirement that must required for programming are listed in Table 2-1 and
be adhered to for proper device operation. The rule is are shown in bold letters in the figures. Refer to the
that any given word in memory must not be written more appropriate device data sheet for complete pin
than twice before erasing the page in which it is located. descriptions.
Thus, the easiest way to conform to this rule is to write
all the data in a programming block within one write
cycle. The programming methods specified in this
specification comply with this requirement.
Note: Writing to a location multiple times without
erasing is not recommended.
TABLE 2-1: PIN DESCRIPTIONS (DURING PROGRAMMING)

During Programming
Pin Name
Pin Name Pin Type Pin Description
MCLR MCLR P Programming Enable

ENVREG ENVREG I Enable for On-Chip Voltage Regulator
DISVREG(1) DISVREG I Disable for On-Chip Voltage Regulator
VDD and AVDD(2) VDD P Power Supply
VSS and AVSS(2) VSS P Ground
VDDCORE VDDCORE P Regulated Power Supply for Core
PGC1 PGC I Primary Programming Pin Pair: Serial Clock
PGD1 PGD I/O Primary Programming Pin Pair: Serial Data
PGC2 PGC I Secondary Programming Pin Pair: Serial Clock
PGD2 PGD I/O Secondary Programming Pin Pair: Serial Data
Legend: I = Input, O = Output, P = Power
Note 1: Applies to 28 and 44-pin devices only.
2: All power supply and ground pins must be connected, including analog supplies (AVDD) and ground
(AVSS).

PIC24FJXXXGA0XX
Pin Diagrams
28-Pin PDIP, SSOP, SOIC
MCLR 1 28 VDD
RA0 2 27 VSS
RA1 3 26 RB15
PIC24FJXXGA002
PGD1/EMUD1/AN2/C2IN-/RP0/CN4/RB0 4 25 RB14
PGC1/EMUC1/AN3/C2IN+/RP1/CN5/RB1 5 24 RB13
RB2 6 23 RB12
RB3 7 22 PGC2/EMUC2/TMS/RP11/CN15/PMD1/RB11
VSS 8 21 PGD2/EMUD2/TDI/RP10/CN16/PMD2/RB10
RA2 9 20 VCAP/VDDCORE
RA3 10 19 DISVREG
RB4 11 18 RB9
RA4 12 17 RB8
VDD 13 16 RB7
PGD3/EMUD3/RP5/SDA1/CN27/PMD7/RB5 14 15 PGC3/EMUC3/RP6/SCL1/CN24/PMD6/RB6
28-Pin QFN(1)
MCLR
RB15
RB14
RA1
RA0
VDD
Vss
28 27 26 25 24 23 22
PGD1/EMUD1/AN2/C2IN-/RP0/CN4/RB0 1 21 RB13
PGC1/EMUC1/AN3/C2IN+/RP1/CN5/RB1 2 20 RB12
RB2 3 19 PGC2/EMUC2/TMS/RP11/CN15/PMD1/RB11
RB3 4 PIC24FJXXGA002 18 PGD2/EMUD2/TDI/RP10/CN16/PMD2/RB10
VSS 5 17 VCAP/VDDCORE
RA2 6 16 DISVREG
RA3 7 15 RB9
8 9 10 11 12 13 14
RB4
RA4
VDD
PGD3/EMUD3/RP5/SDA1/CN27/PMD7/RB5
PGC3/EMUC3/RP6/SCL1/CN24/PMD6/RB6
RB7
RB8
Legend: RPx represents remappable peripheral pins.

Note 1: The bottom pad of QFN packages should be connected to VSS.

PIC24FJXXXGA0XX
Pin Diagrams (Continued)
44-Pin QFN(1)
RC5
RC4
RC3
RB7
RA9
RA4
RB8
VDD
VSS
44
43
42
41
40
39
38
37
36
35
34
RB9 1 33 RB4
RC6 2 32 RA8
RC7 3 31 RA3
RC8 4 30 RA2
RC9 5 29 VSS
DISVREG 6 PIC24FJXXGA004 28 VDD
VCAP/VDDCORE 7 27 RC2
PGD2/EMUD2/RP10/CN16/PMD2/RB10 8 26 RC1
PGC2/EMUC2/RP11/CN15/PMD1/RB11 9 25 RC0
RB12 10 24 RB3
RB13 11 23 RB2
12
13
14
15
16
17
18
19
20
21
22
MCLR
AVSS
RA10
RA7
RB14
RB15
PGD1/EMUD1/AN2/C2IN-/RP0/CN4/RB0
PGC1/EMUC1/AN3/C2IN+/RP1/CN5/RB1
AVDD
RA0
RA1

Note 1: The bottom pad of QFN packages should be connected to VSS.

PIC24FJXXXGA0XX
44-Pin TQFP
RC5
RC4
RC3
RB7
RA9
RA4
RB8
VDD
VSS
38
44
43
42
41
40
39
37
36
35
34
RB9 1 33 RB4
RC6 2 32 RA8
RC7 3 31 RA3
RC8 4 30 RA2
RC9 5 29 VSS
DISVREG 6 PIC24FJXXGA004 28 VDD
VCAP/VDDCORE 7 27 RC2
PGD2/EMUD2/RP10/CN16/PMD2/RB10 8 26 RC1
PGC2/EMUC2/RP11/CN15/PMD1/RB11 9 25 RC0
RB12 10 24 RB3
RB13 11 23 RB2
12
13
14
15
16
17
18
19
20
21
22
RA10
RA7
RB14
RB15
AVDD
RA0
RA1
PGD1/EMUD1/AN2/C2IN-/RP0/CN4/RB0
PGC1/EMUC1/AN3/C2IN+/RP1/CN5/RB1
MCLR
AVSS

PIC24FJXXXGA0XX
64-Pin TQFP
VCAP/VDDCORE
ENVREG
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RE4
RE3
RE2
RE1
RE0
RF1
RF0
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
1 48 RC14
RE5
47 RC13
RE6 2
RE7 46 RD0
3
RG6 4 45 RD11
RG7 5 44 RD10
RG8 6 43 RD9
MCLR 7 42 RD8
RG9 8 PIC24FJXXGA006 41 Vss
VSS 9 PIC24FJXXXGA006 40 RC15
VDD 10 39 RC12
RB5 11 38 VDD
RB4 12 37 RG2
RB3 13 36 RG3
RB2 14 35 RF6
PGC1/EMUC1/VREF-/AN1/CN3/RB1 15 34 RF2
PGD1/EMUD1/PMA6/VREF+/AN0/CN2/RB0 16 33 RF3
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PGD2/EMUD2/AN7/RB7
AVDD
RB8
RB9
RB10
RB11
VDD
RB12
RB13
RB14
RB15
RF4
RF5
PGC2/EMUC2/AN6/OCFA/RB6
VSS
AVSS

PIC24FJXXXGA0XX
80-Pin TQFP
VCAP/VDDCORE
ENVREG
RD13
RD12
RG0
RG1
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RE4
RE3
RE2
RE1
RE0
RF1
RF0
65
64
63
62
61
75
74
73
72
71
70
69
68
67
66
80
79
78
77
76
RE5 1 60 RC14
RE6 59 RC13
2
RE7 58 RD0
3
RC1 4 57 RD11
RC3 5 56 RD10
RG6 6 55 RD9
RG7 7 54 RD8
RG8 8 53 RA15
MCLR 9 52 RA14
RG9 10 PIC24FJXXGA008 51 VSS
VSS 11 PIC24FJXXXGA008 50 RC15
VDD 12 49 RC12
RE8 13 48 VDD
RE9 14 47 RG2
RB5 15 46 RG3
RB4 16 45 RF6
RB3 17 44 RF7
RB2 18 43 RF8
PGC1/EMUC1/AN1/CN3/RB1 19 42 RF2
PGD1/EMUD1/AN0/CN2/RB0 20 41 RF3
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
RD15
PGD2/EMUD2/AN7/RB7
PMA7/VREF-/RA9
PMA6/VREF+/RA10
RB8
RB9
PMA13/CVREF/AN10/RB10
RB11
RB12
RB13
RB14
RB15
RD14
RF4
RF5
VSS
AVDD
VDD
AVSS

PIC24FJXXXGA0XX
100-Pin TQFP
VCAP/VDDCORE
ENVREG
RG13
RG12
RG14
RD13
RD12
RG0
RG1
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RE4
RE3
RE2
RE1
RE0
RA7
RA6
RF1
RF0
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
RG15 1 75 VSS
VDD 2 74 RC14
RE5 3 73 RC13
RE6 4 72 RD0
RE7 5 71 RD11
RC1 6 70 RD10
RC2 7 69 RD9
RC3 8 68 RD8
RC4 9 67 RF2
RG6 10 66 RA14
RG7 11 65 VSS
RG8 12 64 RC15
MCLR 13 PIC24FJXXGA010 63 RC12
PRG9 14 PIC24FJXXXGA010 62 VDD
VSS 15 61 TDO
VDD 16 60 TDI
RA0 17 59 RA3
RE8 18 58 RA2
RE9 19 57 RG2
RB5 20 56 RG3
RB4 21 55 RF6
RB3 22 54 RF7
RB2 23 53 RF8
PGC1/EMUC1/AN1/CN3/RB1 24 52 RF2
PGD1/EMUD1/AN0/CN2/RB0 25 51 RF3
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDD
VSS
PGD2/EMUD2/AN7/RB7
PMA7/VREF-/RA9
RA10
RB8
RB9
RB10
RB11
RA1
RF13
RF12
RB12
RB13
RB14
RB15
RD14
RD15
RF4
RF5
AVSS
VSS
AVDD
VDD

PIC24FJXXXGA0XX
2.4 Memory Map Locations, FF0000h and FF0002h, are reserved for the
Device ID registers. These bits can be used by the
The program memory map extends from 000000h to programmer to identify what device type is being
FFFFFEh. Code storage is located at the base of the programmed. They are described in Section 6.1
memory map and supports up to 44K instruction words “Device ID”. The Device ID registers read out
(about 128 Kbytes). Table 2-3 shows the program normally, even after code protection is applied.
memory size and number of erase and program blocks
present in each device variant. Each erase block, or Figure 2-4 shows the memory map for the
page, contains 512 instructions, and each program PIC24FJXXXGA0XX family variants.
block, or row, contains 64 instructions.
TABLE 2-3: CODE MEMORY SIZE
Locations 800000h through 8007FEh are reserved for
executive code memory. This region stores the User Memory
Write Erase
programming executive and the debugging executive. Device Address Limit
Blocks Blocks
The programming executive is used for device pro- (Instruction Words)
gramming and the debugging executive is used for PIC24FJ16GA 002BFEh (5.5K) 88 11
in-circuit debugging. This region of memory can not be PIC24FJ32GA 0057FEh (11K) 176 22
used to store user code.
PIC24FJ48GA 0083FEh (16.5K) 264 33
The last two implemented program memory locations PIC24FJ64GA 00ABFEh (22K) 344 43
are reserved for the device Configuration registers.
PIC24FJ96GA 00FFFEh (32K) 512 64
PIC24FJ128GA 0157FEh (44K) 688 86
TABLE 2-2: FLASH CONFIGURATION
WORD LOCATIONS FOR
PIC24FJXXXGA0XX DEVICES
Configuration Word
Device Addresses
1 2
PIC24FJ16GA 002BFEh 002BFCh
PIC24FJ32GA 0057FEh 0057FCh
PIC24FJ48GA 0083FEh 0083FCh
PIC24FJ64GA 00ABFEh 00ABFCh
PIC24FJ96GA 00FFFEh 00FFFCh
PIC24FJ128GAGA 0157FEh 0157FCh

PIC24FJXXXGA0XX
FIGURE 2-4: PROGRAM MEMORY MAP
000000h
User Flash
Code Memory
(44031 x 24-bit)
0157FAh(1)
Configuration Words 0157FCh(1)
(2 x 24-bit) 0157FEh(1)
015800h(1)
User Memory
Space
Reserved
7FFFFEh
800000h
Executive Code Memory
(1024 x 24-bit)
8007EEh
Diagnostic and Calibration 8007F0h
Words
(8 x 24-bit)
800800h
Configuration Memory
Space
Reserved
FEFFFEh
Device ID FF0000h
(2 x 16-bit) FF0002h
FF0004h
Reserved
FFFFFEh
Note 1: The address boundaries for user Flash code memory are device dependent (see Table 2-3).

PIC24FJXXXGA0XX
3.0 DEVICE PROGRAMMING – ICSP FIGURE 3-1: HIGH-LEVEL ICSP™
PROGRAMMING FLOW
ICSP mode is a special programming protocol that
allows you to read and write to PIC24FJXXXGA0XX Start
device family memory. The ICSP mode is the most
direct method used to program the device; note, how-
ever, that Enhanced ICSP is faster. ICSP mode also Enter ICSP™
has the ability to read the contents of executive
memory to determine if the programming executive is
present. This capability is accomplished by applying Perform Chip
control codes and instructions, serially to the device, Erase
using pins, PGCx and PGDx.
In ICSP mode, the system clock is taken from the Program Memory
PGCx pin, regardless of the device’s oscillator Config-
uration bits. All instructions are shifted serially into an
internal buffer, then loaded into the Instruction Register
Verify Program
(IR) and executed. No program fetching occurs from
internal memory. Instructions are fed in 24 bits at a
time. PGDx is used to shift data in and PGCx is used
as both the serial shift clock and the CPU execution Program Configuration Bits
clock.
Note: During ICSP operation, the operating Verify Configuration Bits
frequency of PGCx must not exceed
10 MHz.
Exit ICSP
3.1 Overview of the Programming
Process Done
Figure 3-1 shows the high-level overview of the
programming process. After entering ICSP mode, the
first action is to Chip Erase the device. Next, the code 3.2 ICSP Operation
memory is programmed, followed by the device
Upon entry into ICSP mode, the CPU is Idle. Execution
Configuration registers. Code memory (including the
of the CPU is governed by an internal state machine. A
Configuration registers) is then verified to ensure that
4-bit control code is clocked in using PGCx and PGDx,
programming was successful. Then, program the
and this control code is used to command the CPU (see
code-protect Configuration bits, if required.
Table 3-1).
The SIX control code is used to send instructions to the
CPU for execution, and the REGOUT control code is
used to read data out of the device via the VISI register.
TABLE 3-1: CPU CONTROL CODES IN

ICSP™ MODE
4-Bit
Mnemonic Description
Control Code
0000b SIX Shift in 24-bit instruction
and execute.
0001b REGOUT Shift out the VISI (0784h)
register.
0010b-1111b N/A Reserved.

PIC24FJXXXGA0XX
3.2.1 SIX SERIAL INSTRUCTION Coming out of Reset, the first 4-bit control code is
EXECUTION always forced to SIX and a forced NOP instruction is
executed by the CPU. Five additional PGCx clocks are
The SIX control code allows execution of the
needed on start-up, resulting in a 9-bit SIX command
PIC24FJXXXGA0XX family assembly instructions.
instead of the normal 4-bit SIX command.
When the SIX code is received, the CPU is suspended
for 24 clock cycles, as the instruction is then clocked into After the forced SIX is clocked in, ICSP operation
the internal buffer. Once the instruction is shifted in, the resumes as normal. That is, the next 24 clock cycles
state machine allows it to be executed over the next four load the first instruction word to the CPU.
PGC clock cycles. While the received instruction is Note: To account for this forced NOP, all example
executed, the state machine simultaneously shifts in the code in this specification begin with a NOP
next 4-bit command (see Figure 3-2). to ensure that no data is lost.
FIGURE 3-2: SIX SERIAL EXECUTION
P1
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 1 2 3 4
PGCx
P4 P4A
P3 P1A
P1B
P2
LSB X X X X X X X X X X X X X X MSB
PGDx 0 0 0 0 0 0 0 0 0 0 0 0 0
Execute PC – 1, 24-Bit Instruction Fetch Execute 24-Bit

Fetch SIX Instruction, Fetch
Control Code Only for
Program Next Control Code
Memory Entry
PGDx = Input
3.2.1.1 Differences Between Execution of During normal operation, the CPU automatically
SIX and Normal Instructions will force a NOP while the new data is read. When
using ICSP, there is no automatic stall, so any
There are some differences between executing instruc-
indirect references to a recently modified
tions normally and using the SIX ICSP command. As a
register should be preceded by a NOP.
result, the code examples in this specification may not
match those for performing the same functions during For example, the instructions, mov #0x0,W0 and
normal device operation. mov [W0],W1, must have a NOP inserted
between them.
The important differences are:
If a two-cycle instruction modifies a register that is
• Two-word instructions require two SIX operations
used indirectly, it will require two following NOPs: one
to clock in all the necessary data.
to execute the second half of the instruction and a
Examples of two-word instructions are GOTO and second to stall the CPU to correct the pipeline.
CALL.
Instructions such as tblwtl [W0++],[W1]
• Two-cycle instructions require two SIX operations. should be followed by two NOPs.
The first SIX operation shifts in the instruction and • The device Program Counter (PC) continues to
begins to execute it. A second SIX operation – which automatically increment during ICSP instruction
should shift in a NOP to avoid losing data – provides execution, even though the Flash memory is not
the CPU clocks required to finish executing the being used.
instruction.
As a result, the PC may be incremented to point to
Examples of two-cycle instructions are table read invalid memory locations. Invalid memory spaces
and table write instructions. include unimplemented Flash addresses and the
• The CPU does not automatically stall to account vector space (locations 0x0 to 0x1FF).
for pipeline changes. If the PC points to these locations, the device will
A CPU stall occurs when an instruction modifies a reset, possibly interrupting the ICSP operation. To
register that is used for Indirect Addressing by the prevent this, instructions should be periodically
following instruction. executed to reset the PC to a safe space. The
optimal method to accomplish this is to perform a
GOTO 0x200.

PIC24FJXXXGA0XX
3.2.2 REGOUT SERIAL INSTRUCTION Note 1: After the contents of VISI are shifted out,
EXECUTION the PIC24FJXXXGA0XX device
The REGOUT control code allows for data to be maintains PGDx as an output until the
extracted from the device in ICSP mode. It is used to first rising edge of the next clock is
clock the contents of the VISI register, out of the device, received.
over the PGDx pin. After the REGOUT control code is 2: Data changes on the falling edge and
received, the CPU is held Idle for 8 cycles. After these latches on the rising edge of PGCx. For
8 cycles, an additional 16 cycles are required to clock the all data transmissions, the Least
data out (see Figure 3-3). Significant bit (LSb) is transmitted first.
The REGOUT code is unique because the PGDx pin is
an input when the control code is transmitted to the
device. However, after the control code is processed,
the PGDx pin becomes an output as the VISI register is
shifted out.
FIGURE 3-3: REGOUT SERIAL EXECUTION

1 2 3 4 1 2 7 8 1 2 3 4 5 6 11 12 13 14 15 16 1 2 3 4
PGCx
P4 P4A
P5
PGDx 1 0 0 0 LSb 1 2 3 4 ... 10 11 12 13 14 MSb 0 0 0 0
Execute Previous Instruction, CPU Held in Idle Shift Out VISI Register<15:0> No Execution Takes Place,
Fetch REGOUT Control Code Fetch Next Control Code
PGDx = Input PGDx = Output PGDx = Input

PIC24FJXXXGA0XX
3.3 Entering ICSP Mode The key sequence is a specific 32-bit pattern:
‘0100 1101 0100 0011 0100 1000 0101 0001’
As shown in Figure 3-4, entering ICSP Program/Verify (more easily remembered as 4D434851h in hexa-
mode requires three steps: decimal). The device will enter Program/Verify mode only
1. MCLR is briefly driven high, then low. if the sequence is valid. The Most Significant bit (MSb) of
2. A 32-bit key sequence is clocked into PGDx. the most significant nibble must be shifted in first.
3. MCLR is then driven high within a specified Once the key sequence is complete, VIH must be
period of time and held. applied to MCLR and held at that level for as long as
Program/Verify mode is to be maintained. An interval of
The programming voltage applied to MCLR is VIH,
at least time, P19 and P7, must elapse before present-
which is essentially VDD in the case of
ing data on PGDx. Signals appearing on PGCx before
PIC24FJXXXGA0XX devices. There is no minimum
P7 has elapsed will not be interpreted as valid.
time requirement for holding at VIH. After VIH is
removed, an interval of at least P18 must elapse before On successful entry, the program memory can be
presenting the key sequence on PGDx. accessed and programmed in serial fashion. While in
ICSP mode, all unused I/Os are placed in the
high-impedance state.
FIGURE 3-4: ENTERING ICSP™ MODE
P6
P14 P19 P7
VIH VIH
MCLR
VDD
Program/Verify Entry Code = 4D434851h
PGDx 0 1 0 0 1 ... 0 0 0 1
b31 b30 b29 b28 b27 b3 b2 b1 b0
PGCx
P18 P1A
P1B

PIC24FJXXXGA0XX
3.4 Flash Memory Programming in 3.5 Erasing Program Memory
ICSP Mode The procedure for erasing program memory (all of code
memory, data memory, executive memory and
3.4.1 PROGRAMMING OPERATIONS
code-protect bits) consists of setting NVMCON to
Flash memory write and erase operations are controlled 404Fh and executing the programming cycle.
by the NVMCON register. Programming is performed by
A Chip Erase can erase all of user memory or all of both
setting NVMCON to select the type of erase operation
the user and configuration memory. A table write
(Table 3-2) or write operation (Table 3-3) and initiating
instruction should be executed prior to performing the
the programming by setting the WR control bit
Chip Erase to select which sections are erased.
(NVMCON<15>).
When this table write instruction is executed:
In ICSP mode, all programming operations are
self-timed. There is an internal delay between the user • If the TBLPAG register points to user space (is
setting the WR control bit and the automatic clearing of less than 0x80), the Chip Erase will erase only
the WR control bit when the programming operation user memory.
is complete. Please refer to Section 7.0 “AC/DC • If TBLPAG points to configuration space (is
Characteristics and Timing Requirements” for greater than or equal to 0x80), the Chip Erase will
information about the delays associated with various erase both user and configuration memory.
programming operations. If configuration memory is erased, the internal
oscillator Calibration Word, located at 0x807FE,
TABLE 3-2: NVMCON ERASE will be erased. This location should be stored prior
OPERATIONS to performing a whole Chip Erase and restored
NVMCON afterward to prevent internal oscillators from
Erase Operation becoming uncalibrated.
Value
Figure 3-5 shows the ICSP programming process for
404Fh Erase all code memory, executive
performing a Chip Erase. This process includes the
memory and Configuration registers
ICSP command code, which must be transmitted (for
(does not erase Unit ID or Device ID
each instruction), Least Significant bit first, using the
registers).
PGCx and PGDx pins (see Figure 3-2).
4042h Erase a page of code memory or
executive memory. Note: Program memory must be erased before
writing any data to program memory.
TABLE 3-3: NVMCON WRITE
FIGURE 3-5: CHIP ERASE FLOW
OPERATIONS
NVMCON
Write Operation Start
Value
4003h Write a Configuration Word register.
4001h Program 1 row (64 instruction words) of Write 404Fh to NVMCON SFR
code memory or executive memory.
3.4.2 STARTING AND STOPPING A Set the WR bit to Initiate Erase

PROGRAMMING CYCLE
The WR bit (NVMCON<15>) is used to start an erase or
write cycle. Setting the WR bit initiates the programming Delay P11 + P10 Time
cycle.
All erase and write cycles are self-timed. The WR bit
should be polled to determine if the erase or write cycle
has been completed. Starting a programming cycle is Done
performed as follows:
BSET NVMCON, #WR

PIC24FJXXXGA0XX
TABLE 3-4: SERIAL INSTRUCTION EXECUTION FOR CHIP ERASE
Command Data
Description
(Binary) (Hex)
Step 1: Exit the Reset vector.
0000 000000 NOP
0000 040200 GOTO 0x200
0000 000000 NOP
Step 2: Set the NVMCON to erase all program memory.
0000 2404FA MOV #0x404F, W10
0000 883B0A MOV W10, NVMCON
Step 3: Set TBLPAG and perform dummy table write to select what portions of memory are erased.
0000 200000 MOV #<PAGEVAL>, W0
0000 880190 MOV W0, TBLPAG
0000 200000 MOV #0x0000, W0
0000 BB0800 TBLWTL W0,[W0]
0000 000000 NOP
0000 000000 NOP
Step 4: Initiate the erase cycle.
0000 A8E761 BSET NVMCON, #WR
0000 000000 NOP
0000 000000 NOP
Step 5: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware.
0000 040200 GOTO 0x200
0000 000000 NOP
0000 803B02 MOV NVMCON, W2
0000 883C22 MOV W2, VISI
0000 000000 NOP
0001 <VISI> Clock out contents of the VISI register.
0000 000000 NOP

PIC24FJXXXGA0XX
3.6 Writing Code Memory In Step 5, eight TBLWT instructions are used to copy
the data from W0:W5 to the write latches of code mem-
The procedure for writing code memory is the same as ory. Since code memory is programmed 64 instruction
the procedure for writing the Configuration registers, words at a time, Steps 4 and 5 are repeated 16 times to
except that 64 instruction words are programmed at a load all the write latches (Step 6).
time. To facilitate this operation, working registers,
W0:W5, are used as temporary holding registers for the After the write latches are loaded, programming is
data to be programmed. initiated by writing to the NVMCON register in Steps 7
and 8. In Step 9, the internal PC is reset to 200h. This
Table 3-5 shows the ICSP programming details, includ- is a precautionary measure to prevent the PC from
ing the serial pattern with the ICSP command code incrementing into unimplemented memory when large
which must be transmitted, Least Significant bit first, devices are being programmed. Lastly, in Step 10,
using the PGCx and PGDx pins (see Figure 3-2). Steps 3-9 are repeated until all of code memory is
In Step 1, the Reset vector is exited. In Step 2, the programmed.
NVMCON register is initialized for programming a full
row of code memory. In Step 3, the 24-bit starting des- FIGURE 3-6: PACKED INSTRUCTION
tination address for programming is loaded into the WORDS IN W<0:5>
TBLPAG register and W7 register. (The upper byte of
the starting destination address is stored in TBLPAG
15 8 7 0
and the lower 16 bits of the destination address are
stored in W7.) W0 LSW0
To minimize the programming time, A packed instruction W1 MSB1 MSB0
format is used (Figure 3-6). W2 LSW1
In Step 4, four packed instruction words are stored in W3 LSW2
working registers, W0:W5, using the MOV instruction, W4 MSB3 MSB2
and the Read Pointer, W6, is initialized. The contents of
W5 LSW3
W0:W5 (holding the packed instruction word data) are
shown in Figure 3-6.
TABLE 3-5: SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORY

Command Data
Description
(Binary) (Hex)
0000 000000 NOP
0000 040200 GOTO 0x200
0000 000000 NOP
Step 2: Set the NVMCON to program 64 instruction words.
0000 24001A MOV #0x4001, W10
Step 3: Initialize the Write Pointer (W7) for TBLWT instruction.
0000 200xx0 MOV #<DestinationAddress23:16>, W0
0000 880190 MOV W0, TBLPAG
0000 2xxxx7 MOV #<DestinationAddress15:0>, W7
Step 4: Load W0:W5 with the next 4 instruction words to program.
0000 2xxxx0 MOV #<LSW0>, W0
0000 2xxxx1 MOV #<MSB1:MSB0>, W1
0000 2xxxx4 MOV #<MSB3:MSB2>, W4

PIC24FJXXXGA0XX
TABLE 3-5: SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORY (CONTINUED)
Command Data
Description
(Binary) (Hex)
Step 5: Set the Read Pointer (W6) and load the (next set of) write latches.
0000 EB0300 CLR W6
0000 000000 NOP
0000 BB0BB6 TBLWTL [W6++], [W7]
0000 000000 NOP
0000 000000 NOP
0000 BBDBB6 TBLWTH.B [W6++], [W7++]
0000 000000 NOP
0000 000000 NOP
0000 BBEBB6 TBLWTH.B [W6++], [++W7]
0000 000000 NOP
0000 000000 NOP
0000 BB1BB6 TBLWTL [W6++], [W7++]
0000 000000 NOP
0000 000000 NOP
0000 BB0BB6 TBLWTL [W6++], [W7]
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 BB1BB6 TBLWTL [W6++], [W7++]
0000 000000 NOP
0000 000000 NOP
Step 6: Repeat Steps 4 and 5, sixteen times, to load the write latches for 64 instructions.
Step 7: Initiate the write cycle.
0000 000000 NOP
0000 000000 NOP
0000 040200 GOTO 0x200
0000 000000 NOP
0000 883C22 MOV W2, VISI
0000 000000 NOP
0000 000000 NOP
Step 9: Reset device internal PC.
0000 040200 GOTO 0x200
0000 000000 NOP
Step 10: Repeat Steps 3-9 until all code memory is programmed.

PIC24FJXXXGA0XX
FIGURE 3-7: PROGRAM CODE MEMORY FLOW
Start
N=1
LoopCount = 0
Configure
Device for
Writes
Load 2 Bytes
N=N+1 to Write
Buffer at <Addr>
All
No bytes
written?
N=1 Yes
LoopCount = Start Write Sequence
LoopCount + 1 and Poll for WR bit
to be Cleared
No All
locations
done?
Yes
Done

PIC24FJXXXGA0XX
3.7 Writing Configuration Words In Step 1, the Reset vector is exited. In Step 2, the
NVMCON register is initialized for programming of
The PIC24FJXXXGA0XX family configuration is stored code memory. In Step 3, the 24-bit starting destination
in Flash Configuration Words at the end of the user address for programming is loaded into the TBLPAG
space program memory and in multiple register register and W7 register.
Configuration Words located in the test space.
The TBLPAG register must be loaded with the
These registers reflect values read at any Reset from following:
program memory locations. The values can be changed
only by programming the content of the corresponding • 96 and 64 Kbyte devices – 00h
Flash Configuration Word and resetting the device. The • 128 Kbyte devices – 01h
Reset forces an automatic reload of the Flash stored To verify the data by reading the Configuration Words
configuration values by sequencing through the after performing the write in order, the code protection
dedicated Flash Configuration Words and transferring bits initially should be programmed to a ‘1’ to ensure
the data into the Configuration registers. To change the that the verification can be performed properly. After
values of the Flash Configuration Word once it has been verification is finished, the code protection bit can be
programmed, the device must be Chip Erased, as programmed to a ‘0’ by using a word write to the
described in Section 3.5 “Erasing Program Memory”, appropriate Configuration Word.
and reprogrammed to the desired value. It is not
possible to program a ‘0’ to ‘1’, but they may be TABLE 3-6: DEFAULT CONFIGURATION
programmed from a ‘1’ to ‘0’ to enable code protection. REGISTER VALUES
Table 3-7 shows the ICSP programming details for pro- Address Name Default Value
gramming the Configuration Word locations, including
the serial pattern with the ICSP command code which Last Word CW1 7FFFh(1)
must be transmitted, Least Significant bit first, using the Last Word – 2 CW2 FFFFh
PGCx and PGDx pins (see Figure 3-2).
Note 1: CW1<15> is reserved and must be
programmed to ‘0’.

PIC24FJXXXGA0XX
TABLE 3-7: SERIAL INSTRUCTION EXECUTION FOR WRITING CONFIGURATION REGISTERS
Command Data
Description
(Binary) (Hex)
0000 000000 NOP
0000 040200 GOTO 0x200
0000 000000 NOP
Step 2: Initialize the Write Pointer (W7) for the TBLWT instruction.
0000 2xxxx7 MOV <CW2Address15:0>, W7
Step 3: Set the NVMCON register to program CW2.
0000 24003A MOV #0x4003, W10
Step 4: Initialize the TBLPAG register.
0000 200xx0 MOV <CW2Address23:16>, W0
0000 880190 MOV W0, TBLPAG
Step 5: Load the Configuration register data to W6.
0000 2xxxx6 MOV #<CW2_VALUE>, W6
Step 6: Write the Configuration register data to the write latch and increment the Write Pointer.
0000 000000 NOP
0000 BB1B86 TBLWTL W6, [W7++]
0000 000000 NOP
0000 000000 NOP
Step 7: Initiate the write cycle.
0000 000000 NOP
0000 000000 NOP
0000 040200 GOTO 0x200
0000 000000 NOP
0000 883C22 MOV W2, VISI
0000 000000 NOP
0000 000000 NOP
0000 040200 GOTO 0x200
0000 000000 NOP
Step 10: Repeat Steps 5-9 to write CW1.

PIC24FJXXXGA0XX
3.8 Reading Code Memory To minimize the reading time, the packed instruction
word format that was utilized for writing is also used for
Reading from code memory is performed by executing reading (see Figure 3-6). In Step 3, the Write Pointer,
a series of TBLRD instructions and clocking out the data W7, is initialized. In Step 4, two instruction words are
using the REGOUT command. read from code memory and clocked out of the device,
Table 3-8 shows the ICSP programming details for through the VISI register, using the REGOUT
reading code memory. In Step 1, the Reset vector is command. Step 4 is repeated until the desired amount
exited. In Step 2, the 24-bit starting source address for of code memory is read.
reading is loaded into the TBLPAG register and W6
register. The upper byte of the starting source address
is stored in TBLPAG and the lower 16 bits of the source
address are stored in W6.
TABLE 3-8: SERIAL INSTRUCTION EXECUTION FOR READING CODE MEMORY

Command Data
Description
(Binary) (Hex)
Step 1: Exit Reset vector.
0000 000000 NOP
0000 040200 GOTO 0x200
0000 000000 NOP
Step 2: Initialize TBLPAG and the Read Pointer (W6) for TBLRD instruction.
0000 200xx0 MOV #<SourceAddress23:16>, W0
0000 880190 MOV W0, TBLPAG
0000 2xxxx6 MOV #<SourceAddress15:0>, W6
Step 3: Initialize the Write Pointer (W7) to point to the VISI register.
0000 207847 MOV #VISI, W7
0000 000000 NOP
Step 4: Read and clock out the contents of the next two locations of code memory, through the VISI register, using
the REGOUT command.
0000 BA0B96 TBLRDL [W6], [W7]
0000 000000 NOP
0000 000000 NOP
0001 <VISI> Clock out contents of VISI register
0000 000000 NOP
0000 BADBB6 TBLRDH.B [W6++], [W7++]
0000 000000 NOP
0000 000000 NOP
0000 BAD3D6 TBLRDH.B [++W6], [W7--]
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 BA0BB6 TBLRDL [W6++], [W7]
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 040200 GOTO 0x200
0000 000000 NOP
Step 6: Repeat Steps 4 and 5 until all desired code memory is read.

PIC24FJXXXGA0XX
3.9 Reading Configuration Words Table 3-9 shows the ICSP programming details for
reading the Configuration Words. Note that the
The procedure for reading configuration memory is TBLPAG register must be loaded with 00h for 96 Kbyte
similar to the procedure for reading code memory, and below devices and 01h for 128 Kbyte devices (the
except that 16-bit data words are read (with the upper upper byte address of configuration memory), and the
byte read being all ‘0’s) instead of 24-bit words. Since Read Pointer, W6, is initialized to the lower 16 bits of
there are two Configuration registers, they are read one the Configuration Word location.
register at a time.
TABLE 3-9: SERIAL INSTRUCTION EXECUTION FOR READING ALL CONFIGURATION MEMORY
Command Data
Description
(Binary) (Hex)
0000 000000 NOP
0000 040200 GOTO 0x200
0000 000000 NOP
Step 2: Initialize TBLPAG, the Read Pointer (W6) and the Write Pointer (W7) for TBLRD instruction.
0000 200xx0 MOV <CW2Address23:16>, W0
0000 880190 MOV W0, TBLPAG
0000 2xxxx7 MOV <CW2Address15:0>, W6
0000 207847 MOV #VISI, W7
0000 000000 NOP
Step 3: Read the Configuration register and write it to the VISI register (located at 784h), and clock out the
VISI register using the REGOUT command.
0000 BA0BB6 TBLRDL [W6++], [W7]
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
Step 4: Repeat Step 3 again to read Configuration Word 1.
0000 040200 GOTO 0x200
0000 000000 NOP

PIC24FJXXXGA0XX
3.10 Verify Code Memory and 3.11 Reading the Application ID Word
Configuration Word The Application ID Word is stored at address 8005BEh
The verify step involves reading back the code memory in executive code memory. To read this memory
space and comparing it against the copy held in the location, you must use the SIX control code to move
programmer’s buffer. The Configuration registers are this program memory location to the VISI register.
verified with the rest of the code. Then, the REGOUT control code must be used to clock
the contents of the VISI register out of the device. The
The verify process is shown in the flowchart in
corresponding control and instruction codes that must
Figure 3-8. Memory reads occur a single byte at a time,
be serially transmitted to the device to perform this
so two bytes must be read to compare against the word
operation are shown in Table 3-10.
in the programmer’s buffer. Refer to Section 3.8
“Reading Code Memory” for implementation details After the programmer has clocked out the Application
of reading code memory. ID Word, it must be inspected. If the Application ID has
the value, BBh, the programming executive is resident
Note: Because the Configuration registers in memory and the device can be programmed using
include the device code protection bit, the mechanism described in Section 4.0 “Device
code memory should be verified immedi- Programming – Enhanced ICSP”. However, if the
ately after writing if code protection is Application ID has any other value, the programming
enabled. This is because the device will executive is not resident in memory; it must be loaded
not be readable or verifiable if a device to memory before the device can be programmed. The
Reset occurs after the code-protect bit in procedure for loading the programming executive to
CW1 has been cleared. memory is described in Section 5.4 “Programming
the Programming Executive to Memory”.
FIGURE 3-8: VERIFY CODE
MEMORY FLOW 3.12 Exiting ICSP Mode
Start Exiting Program/Verify mode is done by removing VIH
from MCLR, as shown in Figure 3-9. The only require-
ment for exit is that an interval, P16, should elapse
Set TBLPTR = 0 between the last clock and program signals on PGCx
and PGDx before removing VIH.
FIGURE 3-9: EXITING ICSP™ MODE
Read Low Byte P16 P17

with Post-Increment VIH
MCLR
Read High Byte VDD

with Post-Increment
VIH
PGDx
Does Failure,
No
Word = Expect Report PGCx
Data? Error
Yes PGD = Input
All
No code memory
verified?
Yes
Done

PIC24FJXXXGA0XX
TABLE 3-10: SERIAL INSTRUCTION EXECUTION FOR READING THE APPLICATION ID WORD
Command Data
Description
(Binary) (Hex)
0000 000000 NOP
0000 040200 GOTO 0x200
0000 000000 NOP
0000 200800 MOV #0x80, W0
0000 880190 MOV W0, TBLPAG
0000 205BE0 MOV #0x5BE, W0
0000 207841 MOV #VISI, W1
0000 000000 NOP
0000 BA0890 TBLRDL [W0], [W1]
0000 000000 NOP
0000 000000 NOP
Step 3: Output the VISI register using the REGOUT command.
0001 <VISI> Clock out contents of the VISI register
0000 000000 NOP

PIC24FJXXXGA0XX
4.0 DEVICE PROGRAMMING – After the programming executive has been verified
in memory (or loaded if not present), the
ENHANCED ICSP
PIC24FJXXXGA0XX family can be programmed using
This section discusses programming the device the command set shown in Table 4-1.
through Enhanced ICSP and the programming execu-
tive. The programming executive resides in executive FIGURE 4-1: HIGH-LEVEL ENHANCED
memory (separate from code memory) and is executed ICSP™ PROGRAMMING FLOW
when Enhanced ICSP Programming mode is entered.
The programming executive provides the mechanism Start
for the programmer (host device) to program and verify
the PIC24FJXXXGA0XX devices using a simple
command set and communication protocol. There are Enter Enhanced ICSP™
several basic functions provided by the programming
executive:
Perform Chip
• Read Memory
Erase
• Erase Memory
• Program Memory
• Blank Check Program Memory
• Read Executive Firmware Revision
The programming executive performs the low-level Verify Program
tasks required for erasing, programming and verifying
a device. This allows the programmer to program the
device by issuing the appropriate commands and data.
Program Configuration Bits
Table 4-1 summarizes the commands. A detailed
description for each command is provided in
Section 5.2 “Programming Executive Commands”.
Verify Configuration Bits
TABLE 4-1: COMMAND SET SUMMARY

Command Description Exit Enhanced ICSP
SCHECK Sanity Check
READC Read Device ID Registers
Done
READP Read Code Memory
Program One Row of Code Memory
PROGP
and Verify
4.2 Confirming the Presence of the
Program One Word of Code Memory Programming Executive
PROGW
and Verify
QBLANK Query if the Code Memory is Blank Before programming can begin, the programmer must
confirm that the programming executive is stored in
QVER Query the Software Version executive memory. The procedure for this task is
The programming executive uses the device’s data shown in Figure 4-2.
RAM for variable storage and program execution. After First, In-Circuit Serial Programming mode (ICSP) is
the programming executive has run, no assumptions entered. Then, the unique Application ID Word stored in
should be made about the contents of data RAM. executive memory is read. If the programming executive
is resident, the Application ID Word is BBh, which means
4.1 Overview of the Programming programming can resume as normal. However, if the
Process Application ID Word is not BBh, the programming
executive must be programmed to executive code
Figure 4-1 shows the high-level overview of the memory using the method described in Section 5.4
programming process. After entering Enhanced ICSP “Programming the Programming Executive to
mode, the programming executive is verified. Next, the Memory”.
device is erased. Then, the code memory is Section 3.0 “Device Programming – ICSP” describes
programmed, followed by the configuration locations. the ICSP programming method. Section 3.11 “Reading
Code memory (including the Configuration registers) is the Application ID Word” describes the procedure for
then verified to ensure that programming was successful. reading the Application ID Word in ICSP mode.

PIC24FJXXXGA0XX
FIGURE 4-2: CONFIRMING PRESENCE 4.3 Entering Enhanced ICSP Mode
OF PROGRAMMING
As shown in Figure 4-3, entering Enhanced ICSP
EXECUTIVE
Program/Verify mode requires three steps:
1. The MCLR pin is briefly driven high, then low.
Start 2. A 32-bit key sequence is clocked into PGDx.
3. MCLR is then driven high within a specified
Enter ICSP™ Mode period of time and held.
The programming voltage applied to MCLR is VIH,
which is essentially VDD in the case of
Read the
Application ID
PIC24FJXXXGA0XX devices. There is no minimum
from Address time requirement for holding at VIH. After VIH is
807F0h removed, an interval of at least P18 must elapse before
presenting the key sequence on PGDx.
The key sequence is a specific 32-bit pattern:
Is
No ‘0100 1101 0100 0011 0100 1000 0101 0000’
Application ID
BBh? (more easily remembered as 4D434850h in hexa-
decimal format). The device will enter Program/Verify
Yes mode only if the key sequence is valid. The Most
Significant bit (MSb) of the most significant nibble must
Prog. Executive is Prog. Executive must be shifted in first.
Resident in Memory be Programmed
Once the key sequence is complete, VIH must be
applied to MCLR and held at that level for as long as
Finish Program/Verify mode is to be maintained. An interval of
at least time P19 and P7 must elapse before presenting
data on PGDx. Signals appearing on PGDx before P7
has elapsed will not be interpreted as valid.
On successful entry, the program memory can be
accessed and programmed in serial fashion. While in
the Program/Verify mode, all unused I/Os are placed in
the high-impedance state.
FIGURE 4-3: ENTERING ENHANCED ICSP™ MODE
P6
P19 P7
P14
VIH VIH
MCLR
VDD
Program/Verify Entry Code = 4D434850h
PGDx 0 1 0 0 1 ... 0 0 0 0
b31 b30 b29 b28 b27 b3 b2 b1 b0
PGCx
P18 P1A
P1B

PIC24FJXXXGA0XX
4.4 Blank Check FIGURE 4-4: FLOWCHART FOR
PROGRAMMING CODE
The term “Blank Check” implies verifying that the
MEMORY
device has been successfully erased and has no
programmed memory locations. A blank or erased
Start
memory location is always read as ‘1’.
The Device ID registers (FF0002h:FF0000h) can be
ignored by the Blank Check since this region stores BaseAddress = 00h
device information that cannot be erased. The device RemainingCmds = 688
Configuration registers are also ignored by the Blank
Check. Additionally, all unimplemented memory space
should be ignored by the Blank Check. Send PROGP
Command to Program
The QBLANK command is used for the Blank Check. It BaseAddress
determines if the code memory is erased by testing
these memory regions. A ‘BLANK’ or ‘NOT BLANK’
response is returned. If it is determined that the device
Is
is not blank, it must be erased before attempting to No
PROGP response
program the chip. PASS?
4.5 Code Memory Programming Yes
4.5.1 PROGRAMMING METHODOLOGY RemainingCmds =

Code memory is programmed with the PROGP RemainingCmds – 1
command. PROGP programs one row of code memory
BaseAddress =
starting from the memory address specified in the
BaseAddress + 80h
command. The number of PROGP commands
required to program a device depends on the number Are
No
of write blocks that must be programmed in the device. RemainingCmds
‘0’?
A flowchart for programming code memory is shown in
Figure 4-4. In this example, all 44K instruction words of Yes
a PIC24FJ128GA device are programmed. First, the
number of commands to send (called Failure
Finish Report Error
‘RemainingCmds’ in the flowchart) is set to 688 and the
destination address (called ‘BaseAddress’) is set to ‘0’.
Next, one write block in the device is programmed with
a PROGP command. Each PROGP command
contains data for one row of code memory of the
PIC24FJXXXGA0XX device. After the first command is
processed successfully, ‘RemainingCmds’ is decre-
mented by 1 and compared with 0. Since there are
more PROGP commands to send, ‘BaseAddress’ is
incremented by 80h to point to the next row of memory.
On the second PROGP command, the second row is
programmed. This process is repeated until the entire
device is programmed. No special handling must be
performed when a panel boundary is crossed.

PIC24FJXXXGA0XX
4.5.2 PROGRAMMING VERIFICATION 4.6 Configuration Bits Programming
After code memory is programmed, the contents of
memory can be verified to ensure that programming 4.6.1 OVERVIEW
was successful. Verification requires code memory to The PIC24FJXXXGA0XX family has Configuration bits
be read back and compared against the copy held in stored in the last two locations of implemented program
the programmer’s buffer. memory (see Table 2-2 for locations). These bits can
The READP command can be used to read back all of be set or cleared to select various device configura-
the programmed code memory. tions. There are three types of Configuration bits:
system operation bits, code-protect bits and unit ID bits.
Alternatively, you can have the programmer perform The system operation bits determine the power-on
the verification after the entire device is programmed settings for system level components, such as
using a checksum computation. oscillator and Watchdog Timer. The code-protect bits
prevent program memory from being read and written.
The register descriptions for the CW1 and CW2
Configuration registers are shown in Table 4-2.
TABLE 4-2: PIC24FJXXXGA0XX FAMILY CONFIGURATION BITS DESCRIPTION

Bit Field Register Description
(1)
I2C1SEL CW2<2> I2C1 Pin Mapping bit
1 = Default location for SCL1/SDA1 pins
0 = Alternate location for SCL1/SDA1 pins
DEBUG CW1<11> Background Debug Enable bit
1 = Device will reset in User mode
0 = Device will reset in Debug mode
FCKSM1:FCKSM0 CW2<7:6> Clock Switching Mode bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
FNOSC2:FNOSC0 CW2<10:8> Initial Oscillator Source Selection bits
111 = Internal Fast RC (FRCDIV) oscillator with postscaler
110 = Reserved
101 = Low-Power RC (LPRC) oscillator
100 = Secondary (SOSC) oscillator
011 = Primary (XTPLL, HSPLL, ECPLL) oscillator with PLL
010 = Primary (XT, HS, EC) oscillator
001 = Internal Fast RC (FRCPLL) oscillator with postscaler and PLL
000 = Fast RC (FRC) oscillator
FWDTEN CW1<7> Watchdog Timer Enable bit
1 = Watchdog Timer always enabled (LPRC oscillator cannot be disabled;
clearing the SWDTEN bit in the RCON register will have no effect)
0 = Watchdog Timer enabled/disabled by user software (LPRC can be
disabled by clearing the SWDTEN bit in the RCON register)
GCP CW1<13> General Segment Code-Protect bit
1 = User program memory is not code-protected
0 = User program memory is code-protected
GWRP CW1<12> General Segment Write-Protect bit
1 = User program memory is not write-protected
0 = User program memory is write-protected
ICS CW1<8> ICD Communication Channel Select bit
1 = Communicate on PGC2/EMUC2 and PGD2/EMUD2
0 = Communicate on PGC1/EMUC1 and PGD1/EMUD1
Note 1: Available on 28 and 44-pin packages only.
2: Available only on 28 and 44-pin devices with a silicon revision of 3042h or higher.

PIC24FJXXXGA0XX
TABLE 4-2: PIC24FJXXXGA0XX FAMILY CONFIGURATION BITS DESCRIPTION (CONTINUED)
(1)
ICS CW1<8> ICD Pin Placement Select bit
11 = ICD EMUC/EMUD pins are shared with PGC1/PGD1
00 = Reserved; do not use
IESO CW2<15> Internal External Switchover bit
1 = Two-Speed Start-up enabled
0 = Two-Speed Start-up disabled
IOL1WAY(1) CW2<4> IOLOCK Bit One-Way Set Enable bit
0 = The OSCCON<IOLOCK> bit can be set and cleared as needed (provided
an unlocking sequence is executed)
1 = The OSCCON<IOLOCK> bit can only be set once (provided an unlocking
sequence is executed). Once IOLOCK is set, this prevents any possible
future RP register changes
JTAGEN CW1<14> JTAG Enable bit
1 = JTAG enabled
0 = JTAG disabled
OSCIOFNC CW2<5> OSC2 Pin Function bit (except in XT and HS modes)
1 = OSC2 is clock output
0 = OSC2 is general purpose digital I/O pin
SOSCSEL1: CW2<12:11> Secondary Oscillator Power Mode Select bits
SOSCSEL0(2) 11 = Default (high drive strength) mode
01 = Low-Power (low drive strength) mode
x0 = Reserved; do not use
POSCMD1: CW2<1:0> Primary Oscillator Mode Select bits
POSCMD0 11 = Primary oscillator disabled
10 = HS Crystal Oscillator mode
01 = XT Crystal Oscillator mode
00 = EC (External Clock) mode
WDTPOST3: CW1<3:0> Watchdog Timer Prescaler bit
WDTPOST0 1111 = 1:32,768
1110 = 1:16,384
.
.
.
0001 = 1:2
0000 = 1:1
WDTPRE CW1<4> Watchdog Timer Postscaler bit
1 = 1:128
0 = 1:32
WINDIS CW1<6> Windowed WDT bit
1 = Watchdog Timer in Non-Window mode
0 = Watchdog Timer in Window mode; FWDTEN must be ‘1’
WUTSEL1: CW2<14:13> Voltage Regulator Standby Mode Wake-up Time Select bits
WUTSEL0(2) 11 = Default regulator wake time used
01 = Fast regulator wake time used
x0 = Reserved; do not use
Note 1: Available on 28 and 44-pin packages only.
2: Available only on 28 and 44-pin devices with a silicon revision of 3042h or higher.

PIC24FJXXXGA0XX
4.6.2 PROGRAMMING METHODOLOGY 4.6.4 CODE-PROTECT
Configuration bits may be programmed a single byte at CONFIGURATION BITS
a time using the PROGW command. This command CW1 Configuration register controls code protection for
specifies the configuration data and Configuration the PIC24FJXXXGA0XX family. Two forms of code pro-
register address. When Configuration bits are tection are provided. One form prevents code memory
programmed, any unimplemented or reserved bits from being written (write protection) and the other
must be programmed with a ‘1’. prevents code memory from being read (read protection).
Two PROGW commands are required to program the GWRP (CW1<12>) controls write protection and GCP
Configuration bits. A flowchart for Configuration bit (CW1<13>) controls read protection. Protection is
programming is shown in Figure 4-5. enabled when the respective bit is ‘0’.
Note: If the General Segment Code-Protect bit Erasing sets GWRP and GCP to ‘1’, which allows the
(GCP) is programmed to ‘0’, code memory device to be programmed.
is code-protected and can not be read. When write protection is enabled (GWRP = 0), any
Code memory must be verified before programming operation to code memory will fail.
enabling read protection. See Section 4.6.4
“Code-Protect Configuration Bits” for When read protection is enabled (GCP = 0), any read
more information about code-protect from code memory will cause a 0h to be read, regard-
Configuration bits. less of the actual contents of code memory. Since the
programming executive always verifies what it
4.6.3 PROGRAMMING VERIFICATION programs, attempting to program code memory with
read protection enabled also will result in failure.
After the Configuration bits are programmed, the
contents of memory should be verified to ensure that It is imperative that both GWRP and GCP are ‘1’ while
the programming was successful. Verification requires the device is being programmed and verified. Only after
the Configuration bits to be read back and compared the device is programmed and verified should either
against the copy held in the programmer’s buffer. The GWRP or GCP be programmed to ‘0’ (see Section 4.6
READP command reads back the programmed “Configuration Bits Programming”).
Configuration bits and verifies that the programming Note: Bulk Erasing in ICSP mode is the only way
was successful. to reprogram code-protect bits from an ON
state (‘0’) to an Off state (‘1’).

PIC24FJXXXGA0XX
FIGURE 4-5: CONFIGURATION BIT PROGRAMMING FLOW
Start
ConfigAddress = 0157FCh(1)
Send PROGW
Command
Is No
PROGW response
PASS?
Yes
Is
ConfigAddress = No
ConfigAddress
ConfigAddress + 2
0157FEh?(1)
Yes
Finish Failure
Report Error
Note 1: Configuration Word addresses for PIC24FJ128GA devices are shown. Refer to Table 2-2 for others.
4.7 Exiting Enhanced ICSP Mode FIGURE 4-6: EXITING ENHANCED

ICSP™ MODE
Exiting Program/Verify mode is done by removing VIH
from MCLR, as shown in Figure 4-6. The only require- P16 P17
ment for exit is that an interval, P16, should elapse
VIH
between the last clock and program signals on PGCx
MCLR
and PGDx before removing VIH.
VDD
VIH
PGDx
PGCx
PGDx = Input

PIC24FJXXXGA0XX
5.0 THE PROGRAMMING FIGURE 5-2: PROGRAMMING
EXECUTIVE EXECUTIVE SERIAL TIMING
FOR DATA TRANSMITTED
5.1 Programming Executive TO DEVICE
P1
Communication
1 2 3 4 5 6 11 12 13 14 15 16
The programmer and programming executive have a PGCx
master-slave relationship, where the programmer is P1A
the master programming device and the programming P3
P1B
executive is the slave. P2
All communication is initiated by the programmer in the PGDx
MSb 14 13 12 11 ... 5 4 3 2 1 LSb
form of a command. Only one command at a time can
be sent to the programming executive. In turn, the
Since a 2-wire SPI is used, and data transmissions are
programming executive only sends one response to
half duplex, a simple protocol is used to control the
the programmer after receiving and processing a
direction of PGDx. When the programmer completes a
command. The programming executive command set
command transmission, it releases the PGDx line and
is described in Section 5.2 “Programming Executive
allows the programming executive to drive this line
Commands”. The response set is described in
high. The programming executive keeps the PGDx line
Section 5.3 “Programming Executive Responses”.
high to indicate that it is processing the command.
5.1.1 COMMUNICATION INTERFACE After the programming executive has processed the
AND PROTOCOL command, it brings PGDx low for 15 μsec to indicate to
the programmer that the response is available to be
The Enhanced ICSP interface is a 2-wire SPI,
clocked out. The programmer can begin to clock out the
implemented using the PGCx and PGDx pins. The
response 23 μsec after PGDx is brought low, and it must
PGCx pin is used as a clock input pin and the clock
provide the necessary amount of clock pulses to receive
source must be provided by the programmer. The
the entire response from the programming executive.
PGDx pin is used for sending command data to, and
receiving response data from, the programming After the entire response is clocked out, the program-
executive. mer should terminate the clock on PGCx until it is time
to send another command to the programming
Data transmits to the device must change on the rising
executive. This protocol is shown in Figure 5-3.
edge and hold on the falling edge. Data receives from
the device must change on the falling edge and hold on 5.1.2 SPI RATE
the rising edge.
In Enhanced ICSP mode, the PIC24FJXXXGA0XX
All data transmissions are sent to the Most Significant family devices operate from the internal Fast RC oscil-
bit (MSb) first, using 16-bit mode (see Figure 5-1). lator (FRCDIV), which has a nominal frequency of
8 MHz. This oscillator frequency yields an effective
FIGURE 5-1: PROGRAMMING system clock frequency of 4 MHz. To ensure that the
EXECUTIVE SERIAL programmer does not clock too fast, it is recommended
TIMING FOR DATA that a 4 MHz clock be provided by the programmer.
RECEIVED FROM DEVICE
5.1.3 TIME-OUTS
P1
The programming executive uses no Watchdog Timer
1 2 3 4 5 6 11 12 13 14 15 16 or time-out for transmitting responses to the program-
PGCx mer. If the programmer does not follow the flow control
P1A mechanism using PGCx, as described in Section 5.1.1
P3
P1B “Communication Interface and Protocol”, it is
P2 possible that the programming executive will behave
PGDx
...
unexpectedly while trying to send a response to the
MSb 14 13 12 11 5 4 3 2 1 LSb
programmer. Since the programming executive has no
time-out, it is imperative that the programmer correctly
follow the described communication protocol.
As a safety measure, the programmer should use the
command time-outs identified in Table 5-1. If the
command time-out expires, the programmer should
reset the programming executive and start
programming the device again.

PIC24FJXXXGA0XX
FIGURE 5-3: PROGRAMMING EXECUTIVE – PROGRAMMER COMMUNICATION PROTOCOL
Host Transmits Programming Executive

Host Clocks Out Response
Last Command Word Processes Command
1 2 15 16 1 2 15 16 1 2 15 16
PGCx
PGDx MSB X X X LSB 1 0 MSB X X X LSB MSB X X X LSB
P8 P9 P20 P21
PGCx = Input PGCx = Input (Idle) PGCx = Input

PGDx = Input PGDx = Output PGDx = Output
5.2 Programming Executive 5.2.2 PACKED DATA FORMAT

Commands When 24-bit instruction words are transferred across
the 16-bit SPI interface, they are packed to conserve
The programming executive command set is shown in
space using the format shown in Figure 5-5. This
Table 5-1. This table contains the opcode, mnemonic,
format minimizes traffic over the SPI and provides the
length, time-out and description for each command.
programming executive with data that is properly
Functional details on each command are provided in
aligned for performing table write operations.
Section 5.2.4 “Command Descriptions”.
5.2.1 COMMAND FORMAT FIGURE 5-5: PACKED INSTRUCTION

WORD FORMAT
All programming executive commands have a general
format consisting of a 16-bit header and any required
15 8 7 0
data for the command (see Figure 5-4). The 16-bit
header consists of a 4-bit opcode field, which is used to LSW1
identify the command, followed by a 12-bit command MSB2 MSB1
length field. LSW2
LSWx: Least Significant 16 bits of instruction word
FIGURE 5-4: COMMAND FORMAT MSBx: Most Significant Bytes of instruction word
15 12 11 0
Opcode Length Note: When the number of instruction words
Command Data First Word (if required) transferred is odd, MSB2 is zero and
• LSW2 can not be transmitted.
•
5.2.3 PROGRAMMING EXECUTIVE
Command Data Last Word (if required)
ERROR HANDLING
The command opcode must match one of those in the The programming executive will “NACK” all
command set. Any command that is received which unsupported commands. Additionally, due to the
does not match the list in Table 5-1 will return a “NACK” memory constraints of the programming executive, no
response (see Section 5.3.1.1 “Opcode Field”). checking is performed on the data contained in the
programmer command. It is the responsibility of the
The command length is represented in 16-bit words
programmer to command the programming executive
since the SPI operates in 16-bit mode. The program-
with valid command arguments or the programming
ming executive uses the command length field to
operation may fail. Additional information on error
determine the number of words to read from the SPI
handling is provided in Section 5.3.1.3 “QE_Code
port. If the value of this field is incorrect, the command
Field”.
will not be properly received by the programming
executive.

PIC24FJXXXGA0XX
TABLE 5-1: PROGRAMMING EXECUTIVE COMMAND SET
Length
Opcode Mnemonic Time-out Description
(16-bit words)
0h SCHECK 1 1 ms Sanity check.
1h READC 3 1 ms Read an 8-bit word from the specified Device ID register.
2h READP 4 1 ms/row Read N 24-bit instruction words of code memory starting from
the specified address.
3h RESERVED N/A N/A This command is reserved. It will return a NACK.
4h PROGC 4 5 ms Write an 8-bit word to the specified Device ID registers.
5h PROGP 99 5 ms Program one row of code memory at the specified address,
then verify.(1)
Ah QBLANK 3 TBD Query if the code memory is blank.
Bh QVER 1 1 ms Query the programming executive software version.
Dh PROGW 4 5 ms Program one instruction word of code memory at the specified
address, then verify.
Legend: TBD = To Be Determined
Note 1: One row of code memory consists of (64) 24-bit words. Refer to Table 2-3 for device-specific information.
5.2.4 COMMAND DESCRIPTIONS The SCHECK command instructs the programming

executive to do nothing but generate a response. This
All commands supported by the programming executive
command is used as a “Sanity Check” to verify that the
are described in Section 5.2.5 “SCHECK Command”
programming executive is operational.
through Section 5.2.12 “QVER Command”.
Expected Response (2 words):
5.2.5 SCHECK COMMAND 1000h
15 12 11 0 0002h
Opcode Length Note: This instruction is not required for
programming but is provided for
development purposes only.
Field Description
Opcode 0h
Length 1h

PIC24FJXXXGA0XX
5.2.6 READC COMMAND 5.2.7 READP COMMAND
15 12 11 8 7 0 15 12 11 8 7 0
Opcode Length Opcode Length
N Addr_MSB N
Addr_LS Reserved Addr_MSB
Addr_LS
Field Description
Opcode 1h Field Description
Length 3h Opcode 2h
N Number of 8-bit Device ID registers to Length 4h
read (max. of 256) N Number of 24-bit instructions to read
Addr_MSB MSB of 24-bit source address (max. of 32768)
Addr_LS Least Significant 16 bits of 24-bit Reserved 0h
source address Addr_MSB MSB of 24-bit source address
The READC command instructs the programming Addr_LS Least Significant 16 bits of 24-bit
executive to read N or Device ID registers, starting from source address
the 24-bit address specified by Addr_MSB and
The READP command instructs the programming
Addr_LS. This command can only be used to read 8-bit
executive to read N 24-bit words of code memory,
or 16-bit data.
including Configuration Words, starting from the 24-bit
When this command is used to read Device ID address specified by Addr_MSB and Addr_LS. This
registers, the upper byte in every data word returned by command can only be used to read 24-bit data. All data
the programming executive is 00h and the lower byte returned in response to this command uses the packed
contains the Device ID register value. data format described in Section 5.2.2 “Packed Data
Expected Response (4 + 3 * (N – 1)/2 words for N odd): Format”.
1100h Expected Response (2 + 3 * N/2 words for N even):
2+N 1200h
Device ID Register 1 2 + 3 * N/2
... Least significant program memory word 1
Device ID Register N ...
Note: Reading unimplemented memory will Least significant data word N
cause the programming executive to Expected Response (4 + 3 * (N – 1)/2 words for N odd):
reset. Please ensure that only memory 1200h
locations present on a particular device
are accessed. 4 + 3 * (N – 1)/2
Least significant program memory word 1
...
MSB of program memory word N (zero padded)
Note: Reading unimplemented memory will
cause the programming executive to
reset. Please ensure that only memory
locations present on a particular device
are accessed.

PIC24FJXXXGA0XX
5.2.8 PROGC COMMAND 5.2.9 PROGP COMMAND
15 12 11 8 7 0 15 12 11 8 7 0
Reserved Addr_MSB Reserved Addr_MSB
Addr_LS Addr_LS
Data D_1
D_2
Field Description ...
Opcode 4h D_96
Length 4h
Reserved 0h Field Description
Addr_MSB MSB of 24-bit destination address Opcode 5h
Addr_LS Least Significant 16 bits of 24-bit Length 63h
destination address Reserved 0h
Data 8-bit data word Addr_MSB MSB of 24-bit destination address
The PROGC command instructs the programming Addr_LS Least Significant 16 bits of 24-bit
executive to program a single Device ID register destination address
located at the specified memory address.
D_1 16-bit data word 1
After the specified data word has been programmed to D_2 16-bit data word 2
code memory, the programming executive verifies the
programmed data against the data in the command. ... 16-bit data word 3 through 95
D_96 16-bit data word 96
The PROGP command instructs the programming
1400h
executive to program one row of code memory, includ-
0002h ing Configuration Words (64 instruction words), to the
specified memory address. Programming begins with
the row address specified in the command. The
destination address should be a multiple of 80h.
The data to program to memory, located in command
words, D_1 through D_96, must be arranged using the
packed instruction word format shown in Figure 5-5.
After all data has been programmed to code memory,
the programming executive verifies the programmed
data against the data in the command.
1500h
0002h
Note: Refer to Table 2-3 for code memory size
information.

PIC24FJXXXGA0XX
5.2.10 PROGW COMMAND 5.2.11 QBLANK COMMAND
15 12 11 8 7 0 15 12 11 0
Data_MSB Addr_MSB PSize_MSW
Addr_LS PSize_LSW
Data_LS
Field Description
Field Description Opcode Ah
Opcode Dh Length 3h
Length 4h PSize Length of program memory to check
Reserved 0h in 24-bit words plus one (max. of
49152)
Addr_MSB MSB of 24-bit destination address
The QBLANK command queries the programming
Addr_LS Least Significant 16 bits of 24-bit
executive to determine if the contents of code memory
destination address
and code-protect Configuration bits (GCP and GWRP)
Data_MSB MSB of 24-bit data are blank (contain all ‘1’s). The size of code memory to
Data_LS Least Significant 16 bits of 24-bit data check must be specified in the command.
The PROGW command instructs the programming The Blank Check for code memory begins at 0h and
executive to program one word of code memory advances toward larger addresses for the specified
(3 bytes) to the specific memory address. number of instruction words.
After the word has been programmed to code memory, QBLANK returns a QE_Code of F0h if the specified
the programming executive verifies the programmed code memory and code-protect bits are blank;
data against the data in the command. otherwise, QBLANK returns a QE_Code of 0Fh.
Expected Response (2 words): Expected Response (2 words for blank device):
1600h 1AF0h
0002h 0002h
Expected Response (2 words for non-blank device):
1A0Fh
0002h
Note: QBLANK does not check the system
operation Configuration bits, since these
bits are not set to ‘1’ when a Chip Erase is
performed.

PIC24FJXXXGA0XX
5.2.12 QVER COMMAND 5.3.1 RESPONSE FORMAT
15 12 11 0 All programming executive responses have a general
format consisting of a two-word header and any
Opcode Length
required data for the command.
Field Description
15 12 11 8 7 0
Opcode Bh
Opcode Last_Cmd QE_Code
Length 1h
The QVER command queries the version of the Length
programming executive software stored in test
memory. The “version.revision” information is returned D_1 (if applicable)
in the response’s QE_Code using a single byte with the ...
following format: main version in upper nibble and
revision in the lower nibble (i.e., 23h means version 2.3 D_N (if applicable)
of programming executive software).
Field Description
1BMNh (where “MN” stands for version M.N)
0002h Opcode Response opcode
Last_Cmd Programmer command that
5.3 Programming Executive generated the response
Responses QE_Code Query code or error code.
Length Response length in 16-bit words
The programming executive sends a response to the
(includes 2 header words)
programmer for each command that it receives. The
response indicates if the command was processed D_1 First 16-bit data word (if applicable)
correctly. It includes any required response data or D_N Last 16-bit data word (if applicable)
error data.
The programming executive response set is shown in 5.3.1.1 Opcode Field
Table 5-2. This table contains the opcode, mnemonic The opcode is a 4-bit field in the first word of the
and description for each response. The response format response. The opcode indicates how the command
is described in Section 5.3.1 “Response Format”. was processed (see Table 5-2). If the command was
processed successfully, the response opcode is PASS.
TABLE 5-2: PROGRAMMING EXECUTIVE If there was an error in processing the command, the
RESPONSE OP CODES response opcode is FAIL and the QE_Code indicates
the reason for the failure. If the command sent to
Opcode Mnemonic Description the programming executive is not identified, the
1h PASS Command successfully programming executive returns a NACK response.
processed
5.3.1.2 Last_Cmd Field
2h FAIL Command unsuccessfully
processed The Last_Cmd is a 4-bit field in the first word of
the response and indicates the command that the
3h NACK Command not known
programming executive processed. Since the program-
ming executive can only process one command at a
time, this field is technically not required. However, it
can be used to verify that the programming executive
correctly received the command that the programmer
transmitted.

PIC24FJXXXGA0XX
5.3.1.3 QE_Code Field TABLE 5-4: QE_Code FOR NON-QUERY
The QE_Code is a byte in the first word of the COMMANDS
response. This byte is used to return data for query QE_Code Description
commands and error codes for all other commands.
0h No error
When the programming executive processes one of the
two query commands (QBLANK or QVER), the 1h Verify failed
returned opcode is always PASS and the QE_Code 2h Other error
holds the query response data. The format of the
QE_Code for both queries is shown in Table 5-3. 5.3.1.4 Response Length
The response length indicates the length of the
TABLE 5-3: QE_Code FOR QUERIES programming executive’s response in 16-bit words.
Query QE_Code This field includes the 2 words of the response header.
With the exception of the response for the READP
QBLANK 0Fh = Code memory is NOT blank
command, the length of each response is only 2 words.
F0h = Code memory is blank
The response to the READP command uses the
QVER 0xMN, where programming executive
packed instruction word format described in
software version = M.N (i.e., 32h means
Section 5.2.2 “Packed Data Format”. When reading
software version 3.2)
an odd number of program memory words (N odd), the
When the programming executive processes any response to the READP command is (3 * (N + 1)/2 + 2)
command other than a query, the QE_Code represents words. When reading an even number of program
an error code. Supported error codes are shown in memory words (N even), the response to the READP
Table 5-4. If a command is successfully processed, the command is (3 * N/2 + 2) words.
returned QE_Code is set to 0h, which indicates that
there was no error in the command processing. If the
verify of the programming for the PROGP or PROGC
command fails, the QE_Code is set to 1h. For all other
programming executive errors, the QE_Code is 2h.

PIC24FJXXXGA0XX
5.4 Programming the Programming Storing the programming executive to executive
Executive to Memory memory is similar to normal programming of code
memory. Namely, the executive memory must be
5.4.1 OVERVIEW erased, and then the programming executive must be
programmed 64 words at a time. Erasing the last page
If it is determined that the programming executive is of executive memory will cause the FRC oscillator
not present in executive memory (as described calibration settings and device diagnostic data in the
in Section 4.2 “Confirming the Presence of the Diagnostic and Calibration Words, at addresses
Programming Executive”), it must be programmed 8007F0h to 8007FEh, to be erased. In order to retain
into executive memory using ICSP, as described in this calibration, these memory locations should be read
Section 3.0 “Device Programming – ICSP”. and stored prior to erasing executive memory. They
should then be reprogrammed in the last words of pro-
gram memory. This control flow is summarized in
Table 5-5.
TABLE 5-5: PROGRAMMING THE PROGRAMMING EXECUTIVE

Command Data
Description
(Binary) (Hex)
Step 1: Exit Reset vector and erase executive memory.
0000 000000 NOP
0000 040200 GOTO 0x200
0000 000000 NOP
Step 2: Initialize pointers to read Diagnostic and Calibration Words for storage in W6-W13.
0000 200800 MOV #0x80, W0
0000 880190 MOV W0, TBLPAG
0000 207F00 MOV #0x07F0, W1
0000 2000C2 MOV #0xC, W2
0000 000000 NOP
Step 3: Repeat this step 8 times to read Diagnostic and Calibration Words, storing them in W registers, W6-W13.
0000 BA1931 TBLRDL [W1++].[W2++]
0000 000000 NOP
0000 000000 NOP
Step 4: Initialize the NVMCON to erase executive memory.
0000 240420 MOV #0x4042, W0
0000 883B00 MOV W0, NVMCON
Step 5: Initialize Erase Pointers to first page of executive and then initiate the erase cycle.
0000 200800 MOV #0x80, W0
0000 880190 MOV W0, TBLPAG
0000 200001 MOV #0x0, W1
0000 000000 NOP
0000 BB0881 TBLWTL W1, [W1]
0000 000000 NOP
0000 000000 NOP
0000 A8E761 BSET NVMCON, #15
00000 000000 NOP
0000 000000 NOP
0000 040200 GOTO 0x200
0000 000000 NOP
0000 883C22 MOV W2, VISI
0001 000000 NOP
<VISI> Clock out contents of the VISI register.
0000 000000 NOP

PIC24FJXXXGA0XX
TABLE 5-5: PROGRAMMING THE PROGRAMMING EXECUTIVE (CONTINUED)
Command Data
Description
(Binary) (Hex)
Step 7: Repeat Steps 5 and 6 to erase the second page of executive memory. The W1 Pointer should be
incremented by 400h to point to the second page.
Step 8: Initialize TBLPAG and NVMCON to write stored diagnostic and calibration as single words. Initialize W1
and W2 as Write and Read Pointers to rewrite stored Diagnostic and Calibration Words.
0000 200800 MOV #0x80, W0
0000 880190 MOV W0, TBLPAG
0000 240031 MOV #0x4003, W1
0000 207F00 MOV #0x07F0, W1
0000 2000C2 MOV #0xC, W2
0000 000000 NOP
Step 9: Perform write of a single word of calibration data and initiate single-word write cycle.
0000 BB18B2 TBLWTL [W2++], [W1++]
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 040200 GOTO 0x200
0000 000000 NOP
0000 883C20 MOV W0, VISI
0000 000000 NOP
0001 <VISI> Clock out contents of VISI register.
0000 000000 NOP
Step 11: Repeat steps 9-10 seven more times to program the remainder of the Diagnostic and Calibration Words
back into program memory.
Step 12: Initialize the NVMCON to program 64 instruction words.
0000 240010 MOV #0x4001, W0
Step 13: Initialize TBLPAG and the Write Pointer (W7).
0000 200800 MOV #0x80, W0
0000 880190 MOV W0, TBLPAG
0000 EB0380 CLR W7
0000 000000 NOP
Step 14: Load W0:W5 with the next four words of packed programming executive code and initialize W6 for
programming. Programming starts from the base of executive memory (800000h) using W6 as a Read
Pointer and W7 as a Write Pointer.
0000 2<LSW0>0 MOV #<LSW0>, W0
0000 2<MSB1:MSB0>1 MOV #<MSB1:MSB0>, W1
0000 2<LSW1>2 MOV #<LSW1>, W2
0000 2<LSW2>3 MOV #<LSW2>, W3
0000 2<MSB3:MSB2>4 MOV #<MSB3:MSB2>, W4
0000 2<LSW3>5 MOV #<LSW3>, W5

PIC24FJXXXGA0XX
TABLE 5-5: PROGRAMMING THE PROGRAMMING EXECUTIVE (CONTINUED)
Command Data
Description
(Binary) (Hex)
Step 15: Set the Read Pointer (W6) and load the (next four write) latches.
0000 EB0300 CLR W6
0000 000000 NOP
0000 BB0BB6 TBLWTL [W6++], [W7]
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 BB1BB6 TBLWTL [W6++], [W7++]
0000 000000 NOP
0000 000000 NOP
0000 BB0BB6 TBLWTL [W6++], [W7]
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 BB1BB6 TBLWTL [W6++], [W7++]
0000 000000 NOP
0000 000000 NOP
Step 16: Repeat Steps 14-15, sixteen times, to load the write latches for the 64 instructions.
Step 17: Initiate the programming cycle.
0000 000000 NOP
0000 000000 NOP
0000 040200 GOTO 0x200
0000 000000 NOP
0000 883C22 MOV W2, VISI
0000 000000 NOP
0000 000000 NOP
Step 19: Reset the device internal PC.
0000 040200 GOTO 0x200
0000 000000 NOP
Step 20: Repeat Steps 14-19 until all 16 rows of executive memory have been programmed. On the final row, make
sure to initialize the write latches at the Diagnostic and Calibration Words locations with 0xFFFFFF to
ensure that the calibration is not overwritten.

PIC24FJXXXGA0XX
5.4.2 PROGRAMMING VERIFICATION Reading the contents of executive memory can be
performed using the same technique described in
After the programming executive has been
Section 3.8 “Reading Code Memory”. A procedure
programmed to executive memory using ICSP, it must
for reading executive memory is shown in Table 5-6.
be verified. Verification is performed by reading out the
Note that in Step 2, the TBLPAG register is set to 80h,
contents of executive memory and comparing it with
such that executive memory may be read. The last
the image of the programming executive stored in the
eight words of executive memory should be verified
programmer.
with stored values of the Diagnostic and Calibration
Words to ensure accuracy.
TABLE 5-6: READING EXECUTIVE MEMORY

Command Data
Description
(Binary) (Hex)
0000 000000 NOP
0000 040200 GOTO 0x200
0000 000000 NOP
0000 200800 MOV #0x80, W0
0000 880190 MOV W0, TBLPAG
0000 EB0300 CLR W6
Step 3: Initialize the Write Pointer (W7) to point to the VISI register.
0000 207847 MOV #VISI, W7
0000 000000 NOP
Step 4: Read and clock out the contents of the next two locations of executive memory through the VISI register
using the REGOUT command.
0000 BA0B96 TBLRDL [W6], [W7]
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 BADBB6 TBLRDH.B [W6++], [W7++]
0000 000000 NOP
0000 000000 NOP
0000 BAD3D6 TBLRDH.B [++W6], [W7--]
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 BA0BB6 TBLRDL [W6++], [W7]
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
Step 5: Reset the device internal PC.
0000 040200 GOTO 0x200
0000 000000 NOP
Step 6: Repeat Steps 4 and 5 until all desired code memory is read.

PIC24FJXXXGA0XX
6.0 DEVICE DETAILS TABLE 6-1: DEVICE IDs
Device DEVID
6.1 Device ID
PIC24FJ16GA002 0444h
The Device ID region of memory can be used to PIC24FJ16GA004 044Ch
determine mask, variant and manufacturing
information about the chip. The Device ID region is
2 x 16 bits and it can be read using the READC PIC24FJ32GA004 044Dh
command. This region of memory is read-only and can PIC24FJ48GA002 0446h
also be read when code protection is enabled. PIC24FJ48GA004 044Eh
Table 6-1 shows the Device ID for each device, Table 6-2 PIC24FJ64GA002 0447h
shows the Device ID registers and Table 6-3 describes
PIC24FJ64GA004 044Fh
the bit field of each register.
PIC24FJ64GA010 040Bh
PIC24FJ96GA010 040Ch
PIC24FJ128GAGA006 0407h
PIC24FJ128GAGA008 040Ah
PIC24FJ128GAGA010 040Dh
TABLE 6-2: PIC24FJXXXGA0XX DEVICE ID REGISTERS

Bit
Address Name
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FF0000h DEVID — FAMID<7:0> DEV<5:0>
FF0002h DEVREV — MAJRV<2:0> — DOT<2:0>
TABLE 6-3: DEVICE ID BIT DESCRIPTIONS

FAMID<7:0> DEVID Encodes the family ID of the device
DEV<5:0> DEVID Encodes the individual ID of the device
MAJRV<2:0> DEVREV Encodes the major revision number of the device
DOT<2:0> DEVREV Encodes the minor revision number of the device

PIC24FJXXXGA0XX
6.2 Checksum Computation Table 6-4 describes how to calculate the checksum for
each device. All memory locations are summed, one
Checksums for the PIC24FJXXXGA0XX family are byte at a time, using only their native data size. More
16 bits in size. The checksum is calculated by summing specifically, Configuration registers are summed by
the following: adding the lower two bytes of these locations (the
• Contents of code memory locations upper byte is ignored), while code memory is summed
• Contents of Configuration registers by adding all three bytes of code memory.
TABLE 6-4: CHECKSUM COMPUTATION

Erased Checksum with
Read Code
Device Checksum Computation Checksum 0xAAAAAA at 0x0 and Last
Protection
Value Code Address
Disabled CFGB + SUM(0:02BFB) 0xBB5A 0xB95C
PIC24FJ16GA002
Enabled 0 0x0000 0x0000
Disabled CFGB + SUM(0:02BFB) 0xBB5A 0xB95C
PIC24FJ16GA004
Enabled 0 0x0000 0x0000
Disabled CFGB + SUM(0:057FB) 0x795A 0x775C
PIC24FJ32GA002
Enabled 0 0x0000 0x0000
PIC24FJ32GA004
Enabled 0 0x0000 0x0000
PIC24FJ48GA002
Enabled 0 0x0000 0x0000
PIC24FJ48GA004
Enabled 0 0x0000 0x0000
Disabled CFGB + SUM(0:0ABFB) 0xFB5A 0xF95C
PIC24FJ64GA002
Enabled 0 0x0000 0x0000
Disabled CFGB + SUM(0:0ABFB) 0xFB5A 0xF95C
PIC24FJ64GA004
Enabled 0 0x0000 0x0000
Disabled CFGB + SUM(0:0ABFB) 0xFACC 0xF8CE
PIC24FJ64GA006
Enabled 0 0x0000 0x0000
PIC24FJ64GA008
Enabled 0 0x0000 0x0000
PIC24FJ64GA010
Enabled 0 0x0000 0x0000
Disabled CFGB + SUM(0:0FFFB) 0x7CCC 0x7ACE
PIC24FJ96GA006
Enabled 0 0x0000 0x0000
PIC24FJ96GA008
Enabled 0 0x0000 0x0000
PIC24FJ96GA010
Enabled 0 0x0000 0x0000
Legend: Item Description
SUM[a:b] = Byte sum of locations, a to b inclusive (all 3 bytes of code memory)
CFGB = Configuration Block (masked),
64/80/100-Pin Devices = Byte sum of (CW1 & 0x7DDF + CW2 & 0x87E3)
28/44-Pin Devices = Byte sum of (CW1 & 0x7FDF + CW2 & 0xFFF7)
Note: CW1 address is last location of implemented program memory; CW2 is (last location – 2).

PIC24FJXXXGA0XX
TABLE 6-4: CHECKSUM COMPUTATION (CONTINUED)
Erased Checksum with
Read Code
Device Checksum Computation Checksum 0xAAAAAA at 0x0 and Last
Protection
Value Code Address
Disabled CFGB + SUM(0:0157FB) 0xF8CC 0xF6CE
PIC24FJ128GAGA006
Enabled 0 0x0000 0x0000
PIC24FJ128GAGA008
Enabled 0 0x0000 0x0000
PIC24FJ128GAGA010
Enabled 0 0x0000 0x0000
Legend: Item Description
SUM[a:b] = Byte sum of locations, a to b inclusive (all 3 bytes of code memory)
CFGB = Configuration Block (masked),
64/80/100-Pin Devices = Byte sum of (CW1 & 0x7DDF + CW2 & 0x87E3)
28/44-Pin Devices = Byte sum of (CW1 & 0x7FDF + CW2 & 0xFFF7)
Note: CW1 address is last location of implemented program memory; CW2 is (last location – 2).

PIC24FJXXXGA0XX
7.0 AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS
Standard Operating Conditions
Operating Temperature: 0°C to +70°C. Programming at +25°C is recommended.
Param
Symbol Characteristic Min Max Units Conditions
No.
D111 VDD Supply Voltage During Programming VDDCORE + 0.1 3.60 V Normal programming(1,2)
D112 IPP Programming Current on MCLR — 5 μA
D113 IDDP Supply Current During Programming — 2 mA
D031 VIL Input Low Voltage VSS 0.2 VDD V
D041 VIH Input High Voltage 0.8 VDD VDD V
D080 VOL Output Low Voltage — 0.4 V IOL = 8.5 mA @ 3.6V
D090 VOH Output High Voltage 3.0 — V IOH = -3.0 mA @ 3.6V
D012 CIO Capacitive Loading on I/O pin (PGDx) — 50 pF To meet AC specifications
D013 CF Filter Capacitor Value on VCAP 4.7 10 μF Required for controller core
P1 TPGC Serial Clock (PGCx) Period 100 — ns
P1A TPGCL Serial Clock (PGCx) Low Time 40 — ns
P1B TPGCH Serial Clock (PGCx) High Time 40 — ns
P2 TSET1 Input Data Setup Time to Serial Clock ↑ 15 — ns
P3 THLD1 Input Data Hold Time from PGCx ↑ 15 — ns
P4 TDLY1 Delay Between 4-Bit Command and 40 — ns
Command Operand
P4A TDLY1A Delay Between 4-Bit Command Operand 40 — ns
and Next 4-Bit Command
P5 TDLY2 Delay Between Last PGCx ↓ of Command 20 — ns
Byte to First PGCx ↑ of Read of Data Word
P6 TSET2 VDD ↑ Setup Time to MCLR ↑ 100 — ns
P7 THLD2 Input Data Hold Time from MCLR ↑ 25 — ms
P8 TDLY3 Delay Between Last PGCx ↓ of Command 12 — μs
Byte to PGDx ↑ by Programming Executive
P9 TDLY4 Programming Executive Command 40 — μs
Processing Time
P10 TDLY6 PGCx Low Time After Programming 400 — ns
P11 TDLY7 Chip Erase Time 400 — ms
P12 TDLY8 Page Erase Time 40 — ms
P13 TDLY9 Row Programming Time 2 — ms
P14 TR MCLR Rise Time to Enter ICSP™ mode — 1.0 μs
P15 TVALID Data Out Valid from PGCx ↑ 10 — ns
P16 TDLY10 Delay Between Last PGCx ↓ and MCLR ↓ 0 — s
P17 THLD3 MCLR ↓ to VDD ↓ 100 — ns
P18 TKEY1 Delay from First MCLR ↓ to First PGCx ↑ 40 — ns
for Key Sequence on PGDx
P19 TKEY2 Delay from Last PGCx ↓ for Key 1 — ms
Sequence on PGDx to Second MCLR ↑
P20 TDLY11 Delay Between PGDx ↓ by Programming 23 — µs
Executive to PGDx Driven by Host
P21 TDLY12 Delay Between Programming Executive 8 — ns
Command Response Words
Note 1: VDDCORE must be supplied to the VDDCORE/VCAP pin if the on-chip voltage regulator is disabled. See Section 2.1
“Power Requirements” for more information. (Minimum VDDCORE allowing Flash programming is 2.25V.)
2: VDD must also be supplied to the AVDD pins during programming. AVDD and AVSS should always be within ±0.3V
of VDD and VSS, respectively.

PIC24FJXXXGA0XX
NOTES:

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience
The Microchip name and logo, the Microchip logo, Accuron,
and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
ensure that your application meets with your specifications. PICSTART, rfPIC, SmartShunt and UNI/O are registered
MICROCHIP MAKES NO REPRESENTATIONS OR
trademarks of Microchip Technology Incorporated in the
WARRANTIES OF ANY KIND WHETHER EXPRESS OR U.S.A. and other countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, SEEVAL, SmartSensor and The Embedded Control Solutions
QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology
FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A.
arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard,
devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, In-Circuit Serial
hold harmless Microchip from any and all damages, claims, Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
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SQTP is a service mark of Microchip Technology Incorporated
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All other trademarks mentioned herein are property of their
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© 2008, Microchip Technology Incorporated, Printed in the
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Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and
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and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

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DS39768C-page 52 © 2008 Microchip Technology Inc.

PIC24FJXXXGA0XX Flash Programming Specification

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PIC24FJXXXGA0XX

PIC24FJXXXGA0XX Flash Programming Specification

1.0 DEVICE OVERVIEW The Enhanced In-Circuit Serial Programming

© 2008 Microchip Technology Inc. DS39768D-page 1

Note 1: These are typical operating voltages. Refer

DS39768D-page 2 © 2008 Microchip Technology Inc.

TABLE 2-1: PIN DESCRIPTIONS (DURING PROGRAMMING)

MCLR MCLR P Programming Enable

© 2008 Microchip Technology Inc. DS39768D-page 3

28-Pin PDIP, SSOP, SOIC

Legend: RPx represents remappable peripheral pins.

DS39768D-page 4 © 2008 Microchip Technology Inc.

Legend: RPx represents remappable peripheral pins.

© 2008 Microchip Technology Inc. DS39768D-page 5

Legend: RPx represents remappable peripheral pins.

DS39768D-page 6 © 2008 Microchip Technology Inc.

© 2008 Microchip Technology Inc. DS39768D-page 7

DS39768D-page 8 © 2008 Microchip Technology Inc.

© 2008 Microchip Technology Inc. DS39768D-page 9

DS39768D-page 10 © 2008 Microchip Technology Inc.

© 2008 Microchip Technology Inc. DS39768D-page 11

TABLE 3-1: CPU CONTROL CODES IN

DS39768D-page 12 © 2008 Microchip Technology Inc.

FIGURE 3-2: SIX SERIAL EXECUTION

Execute PC – 1, 24-Bit Instruction Fetch Execute 24-Bit

© 2008 Microchip Technology Inc. DS39768D-page 13

FIGURE 3-3: REGOUT SERIAL EXECUTION

PGDx 1 0 0 0 LSb 1 2 3 4 ... 10 11 12 13 14 MSb 0 0 0 0

PGDx = Input PGDx = Output PGDx = Input

DS39768D-page 14 © 2008 Microchip Technology Inc.

FIGURE 3-4: ENTERING ICSP™ MODE

© 2008 Microchip Technology Inc. DS39768D-page 15

3.4.2 STARTING AND STOPPING A Set the WR bit to Initiate Erase

DS39768D-page 16 © 2008 Microchip Technology Inc.

© 2008 Microchip Technology Inc. DS39768D-page 17

TABLE 3-5: SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORY

DS39768D-page 18 © 2008 Microchip Technology Inc.

© 2008 Microchip Technology Inc. DS39768D-page 19

DS39768D-page 20 © 2008 Microchip Technology Inc.

© 2008 Microchip Technology Inc. DS39768D-page 21

DS39768D-page 22 © 2008 Microchip Technology Inc.

TABLE 3-8: SERIAL INSTRUCTION EXECUTION FOR READING CODE MEMORY

© 2008 Microchip Technology Inc. DS39768D-page 23

DS39768D-page 24 © 2008 Microchip Technology Inc.

FIGURE 3-9: EXITING ICSP™ MODE

Read Low Byte P16 P17

Read High Byte VDD

Yes PGD = Input

© 2008 Microchip Technology Inc. DS39768D-page 25

DS39768D-page 26 © 2008 Microchip Technology Inc.

TABLE 4-1: COMMAND SET SUMMARY

© 2008 Microchip Technology Inc. DS39768D-page 27

FIGURE 4-3: ENTERING ENHANCED ICSP™ MODE

DS39768D-page 28 © 2008 Microchip Technology Inc.

4.5 Code Memory Programming Yes

4.5.1 PROGRAMMING METHODOLOGY RemainingCmds =

© 2008 Microchip Technology Inc. DS39768D-page 29

TABLE 4-2: PIC24FJXXXGA0XX FAMILY CONFIGURATION BITS DESCRIPTION

DS39768D-page 30 © 2008 Microchip Technology Inc.

© 2008 Microchip Technology Inc. DS39768D-page 31

DS39768D-page 32 © 2008 Microchip Technology Inc.

4.7 Exiting Enhanced ICSP Mode FIGURE 4-6: EXITING ENHANCED

© 2008 Microchip Technology Inc. DS39768D-page 33