Synchronous Sequential

Circuits
 Synchronous Sequential Circuits

• Goals (Things to keep in mind):

• To understand the difference between
e y andd Moore
Mealy oo e type
ype seque
sequential circuits.
c cu s.
• To understand the concept of states.
• To understand
nderstand the design procedure
proced re for
implementing sequential circuits.
 Synchronous Sequential Circuits

• As was previously stated, sequential circuits extend the

capabilities of our systems by including the past behavior
of the circuit with its present behavior.
• Sequential circuits consist of a combinational circuit
(present behavior) to which memory elements (past
behavior) are connected via a feedback path.

W Combinational Combinational
Flip-flops
p p circuit Z
circuit
i i Q

Cl k
Clock

The general form of a sequential circuit.

Sequential circuits have a set of inputs, W; a state, Q; and a
set of outputs, Z.
 Synchronous Sequential Circuits

• When discussing sequential circuits, the operation of the

circuit
i it can be b controlled
t ll d by
b a clock
l k signal
i l andd suchh a
circuit is called a synchronous sequential circuit.
• Alternatively,y, circuits where there is no clock signal
g used,,
are called asynchronous sequential circuits.
• The link between the input W and the output combinational
l i in
logic i the
th above
b figure
fi mayor may nott be
b present.
t
• This difference is indicated by referring to the circuit either
as a:
– Moore Type - where the outputs depend only on the state of the
circuit, Q;
– Mealy Type - where the outputs depend on both the state Q,
Q and
the primary inputs, W.
• Sequential circuits are also called finite state machines
(FSM ) which
(FSMs) hi h iis a more fformall name that
h iis often
f found
f d in
i
technical literature.
 Synchronous Sequential Circuits
Basic Design Steps
• Suppose that we wish to design a circuit that meets the
following specification:
• 1. The circuit has one input w, and one output z.
• 2. All changes occur on the positive edge of the clock.
• 3. The output z is equal to 1 if during the two immediately
preceding
di clock
l k cycles
l theth input
i t w was equall to t 1.
1
Otherwise, z is equal to 0.
• State Diagram
• The first step in designing a finite state machine is to
determine how many states are needed, and what
transitions
ii are possible
ibl from
f one state to another.
h
• One can arbitrarily select one particular state as a starting
state; generally, this is the state that the circuit should enter
when power is first turned on or when a reset signal is
applied.
• For our example (on the right): 1. The circuit has one input w, and one
output z.
• We can call the first state A. 2. All changes occur on the positive edge of
the clock.
• State A occurs when the input w w=0 0. 3 Th
3. The output
t t z is
i equall to
t 1 if during
d i theth
two immediately preceding clock cycles the
• In state A, the circuit need not do anything, input w was equal to 1. Otherwise, z is
and so each active clock edge should result in equal to 0.
the circuit remaining in state A.
A
• While in state A, the machine should Reset
recognize w=1 and move to a different state,
which we can call B. B w = 1
• In state B we are 'remembering' the w = 0 A z = 0 B z = 0
occurance of w=1 and waiting for the
w = 0
following ww=1 1
• In state B, like state A, the circuit should not w = 1
generate an output, z=0.
• When in state B,B if w=0,
w=0 at the next active
edge of the clock, the circuit should move C z = 1
back to state A.
• If w=1 when in state B (ie the second w=1),
w=1)
the circuit should change to a third state,
called C, and generate an output, z= 1.
• The circuit should remain in state C, as long 1. The circuit has one input w, and one
output z.
as w= 1 and continue to maintain z=1. 2. All changes occur on the positive edge of
the clock.
• When w=0,, the machine should move back 3 Th
3. The output
t t z is
i equall to
t 1 if during
d i theth
to state A. two immediately preceding clock cycles the
input w was equal to 1. Otherwise, z is
• Thus three states are needed to implement the equal to 0.
desired machine.
• The simplest representation of this Reset
nformation is in a pictorial form called a state
diagram.
g w = 1
• A state diagram depicts states w = 0 A z = 0 B z = 0
of the circuit as nodes (circles) and
w = 0
transitions between states as directed arcs.
arcs
w = 0 w = 1

Clockcycle: t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
w: 0 1 0 1 1 0 1 1 1 0 1
C z = 1
z: 0 0 0 0 0 1 0 0 1 1 0

w = 1
 Synchronous Sequential Circuits

State Table
• Rather than having the circuit description in the graphical
form of a state diagram, we can translate the diagram into a
tabular form known as a state table.
• A state table contains all the information of the state
diagram: transitions, input signal, and output signals; but
places
l them
th in i a form
f from
f which
hi h it is
i easier
i tot simplify
i lif
and implement a circuit.
w=1
w=0 A z = 0 B z = 0
w=0
Present Next state Output w=0 w=1
state w = 0 w = 1 z

A A B 0 C z = 1

B A C 0
C A C 1
w=1
 Synchronous Sequential Circuits

State Assignment
• When implementing a sequential circuit, each state is
represented by a particular valuation (combination of values) of
state variables.
• With each state variable implemented in the form of a flip-flop.
w= 1
• We have three states, and can w= 0 Az=0 Bz=0
w= 0
represent this using two state variables. w= 0 w= 1
• Since the output z is a function of only the
Cz=1
current state, our design is a Moore type.
• Once we have determined how many flip-flops
flip flops we w= 1
need to implement our circuit, we need to be able to map the
information contained in the state table to the information
which will be stored in the flip-flops
 Synchronous Sequential Circuits

• The mapping of state table information produces an assigned

state
t t table
t bl which,
hi h like
lik a standard
t d d truth
t th table,
t bl is
i usedd for
f the
th
design of a combinational circuit which will generates the
correct output signal z and drive the inputs for the flip-flops.
• To produce an assigned state table, we assign specific valuation
to each state, and determine what input are required to produce
that state.
state w= 1
w= 0 Az=0 Bz=0
Present Next state Output w= 0
state w = 0 w = 1 z
w= 0 w= 1
A A B 0
B A C 0 Cz=1
C A C 1

w= 1
• We have two state variables, and therefore two flip-flops.
• For an assigned state table, we can label their present states as
y1 and y2, and the next-state variables as Y1 and Y2.
 As can be seen
seen, the below assigned state table is
basically a variation on a truth table and can be used
to generate the necessary combinational logic using
techniques such as Karnaugh maps, etc.

Next state w= 1
Present w= 0 Az=0 Bz=0
w = 0 w = 1 Output
state w= 0
z w= 0 w= 1
y y Y Y Y Y
2 1 2 1 2 1
Cz=1
A 00 00 01 0
B 01 00 10 0
w= 1
C 10 00 10 1
11 dd dd d
 Y1 y1
w
Combinational Combinational z
circuit circuit

Y2 y2

Clock

A general sequential circuit with input w,

w output z,
z and
two state flip-flops.
 Synchronous Sequential Circuits
Choice of Flip-Flops
• As the ability to maintain "state" is exhibited by all the flip-
flip
flops types we have seen, it is therefore necessary to decide
which type will be used in any implementation.
• The most straightforward choice is to use D-type flip-flops,
since the values for the next state are simply clocked into the
flip-flops to become the new current state values.
values
• For other types of flip-flops, such as the JK type, the
relationship between the next-state variables and inputs to a
flip-flop is not as straightforward; we will consider this later.
• Regardless of the type of flip-flop selected to be used, the next
state columns of the assigned state table represent what needs
to be stored in the flip-flops and thus each individual column
can be thought of as an individual function.
• If the inputs to the two flip-flops are called D1 and D2, then
these signals are the same as Y1 and Y2.
 D1
Y1 y1
w
Combinational Combinational z
circuit circuit

Y2 y2
D2

Clock
 y y
2 1 Next state
w 00 01 11 10 Ignoring don't cares
Present
w = 0 w = 1 Output
0 0 0 d 0 Y = wy y
state
1 1 2 z
1 1 0 d 0
Using don't cares y 2y 1 Y 2 Y1 Y 2 Y1
Y = wy y
1 1 2
A 00 00 01 0
B 01 00 10 0
y y
2 1 C 10 00 10 1
w
00 01 11 10 Ignoring don't cares 11 dd dd d
0 0 0 d 0 Y = wy y + wy y
2 1 2 1 2

1 Using don't cares

0 1 d 1
Y = wy + wy
2 1 2 D1
= w(y + y ) w Y1 y1
1 2
y2 z
y
1
Y2
y D2
2 0 1
Ignoring don't
don t cares
0 0 0 z = y y
1 2
Using don't cares
1 1 d Clock
z = y
2
 Y2 y2
D Q z

Y1 y1
w D Q

Clock
Resetn

Final implementation of the sequential circuit

 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
1
Clock
0

1
w
0

1
y1
0

1
y2
0

1
z
0

Timing diagram for the circuit

 Synchronous Sequential Circuits

Summary of Design Steps

• 1) Obtain the specification of the desired circuit.
• 2) Derive the states for the machine by first selecting a
starting state.
state
• Then, consider all valuations of the inputs to the circuit and
create new states as needed for the machine to respond to
these inputs.
• To keep track of the states, create a state diagram.
• 3) Create
C t a state t t table
t bl from
f the
th state
t t diagram.
di
• 4) When dealing with circuits that have large number of
states,, it is likelyy that the first attempt
p will have more states
than is really necessary.
• This can be corrected by minimizing the number of states.
• 5) Determine the number of state variables needed to
represent all the states and perform a state assignment.
 Synchronous Sequential Circuits

Summaryy of Design g Stepsp ((continuation))

• There are many different state assignments possible for a
given circuit.
• 6) Choose the type of the flip-flops to be used in the
• circuit.
• Derive the next-state
next state logic expressions to control the inputs
to all flip-flops and then derive logic expressions for the
outputs of the circuit.
• 7) Implement the circuit as indicated by logic expressions
 Synchronous Sequential Circuits

Consider a new assignment for the previous problem:

Next state Next state

Present Present
Output w = 0 w = 1 Output
state w = 0 w = 1 state
z z
y 2y 1 Y 2 Y1 Y 2 Y1 y 2y 1 Y 2 Y1 Y 2 Y1

A 00 00 01 0 A 00 00 01 0
B 01 00 10 0 B 01 00 11 0
C 10 00 10 1 C 11 00 11 1
11 dd dd d 10 dd dd d

y y y y y
2 1 2 1 1
y
w 00 01 11 10 w 00 01 11 10 2 0 1

0 0 0 0 0 d 0 0 0
0 0 0 d

1 1 1 1 d 1 0 1 1 d 1 d 1
 Y2 y2
D Q z
Y2 y2
D Q z
Q
Q

Y1 y1
Y1 y1 w D Q
w D Q

Q Clock Q

Resetn
Clock
Resetn

Final circuit for the original (left) and improved (right) state
g
assignments
 Synchronous Sequential Circuits
Bus Structure
• Digital systems such as microprocessor contain a set of
registers.
• Each register Ri (i=1,2,..k) is connected to a set of n wires.
 Synchronous Sequential Circuits
• It is essential to ensure that only one circuit block attempts
to place data onto the bus
• A control circuit will ensure that the bus is used by only
one register as well as the transfer of the data signals.

R1out
R1in
w
R2out
Control
circuit R2in

Tri-state Clock
R3out
R3in
buffers Done
 Synchronous Sequential Circuits
• In the starting state A, no transfer is indicated, and all
output signals are 0.
w= 0
• The circuit remains in this state until a request to swap
arrives in the form of w =1. Reset
A No transfer
• In state B the signals required to transfer the contents of
R2 into R3 are asserted. w= 1
• Th nextt active
The ti clock
l k edge
d places
l the
th contents
t t into
i t R3
B R2out= 1R3in = 1
• It also causes the circuit to change to state C , regardless
of the value of w w= 0
w= 1
• In this state the signals
g for transferringg R1 into R2 are w= 0
w= 1 C R1out= 1R
R1 R2
2in = 1
asserted.
w= 0
• The transfer takes place at the next active clock edge the w= 1
ckt changes to state D regardless of the value w
D R3out= 1R1in = 1Done = 1
• The final transfer from R3 to R1 is performed on the
clock edge that leaves state D which causes the ckt to go
to state A

Present Next
N t state
t t O t t
Outputs
state w = 0 w = 1
A A B 0 0 0 0 0 0 0
B C C 0 0 1 0 0 1 0
C D D 1 0 0 1 0 0 0
D A A 0 1 0 0 1 0 1
State-assigned table

Present Next state

state Outputs

A 00 00 01 0 0 0 0 0 0 0
B 01 10 10 0 0 1 0 0 1 0
C 10 11 11 1 0 0 1 0 0 0
D 11 00 00 0 1 0 0 1 0 1
y2 y1
w
00 01 11 10

0 1
Y 1 = wy 1 + y 1 y 2
1 1 1

y2 y1
w
00 01 11 10

0 1 1
Y 2 = y1 y2 + y1 y2
1 1 1
 w R 1 in
Y1 y1
D Q
R 3 out
y1
Clock Q Done

R 1 out

R 2 in

Y2 y2
D Q

y2
Q

R 2 out

R 3 in

Final implementation of the sequential circuit

 Present Next state
state Outputs

A 00 00 01 0 0 0 0 0 0 0
B 01 10 10 0 0 1 0 0 1 0
C 10 11 11 1 0 0 1 0 0 0
D 11 00 00 0 1 0 0 1 0 1

Present Nextstate
state Outputs

A 00 00 01 0 0 0 0 0 0 0
B 01 11 11 0 0 1 0 0 1 0
C 11 10 10 1 0 0 1 0 0 0
D 10 00 00 0 1 0 0 1 0 1
 Present
Present
Nextstate
Next state
state Outputs
Outputs
state

AA 00
00 000
0 01
01 00 00 0 00 00 00 00
BB 01
01 110
1 10
11 00 00 11 00 00 11 00
CC 10
11 111
0 11
10 11 00 00 11 00 00 00
DD 11
10 000
0 00
00 00 11 00 00 11 00 11

y2y1 y2y1
w
w 00 01 11 10 00 01 11 10

0 1 0 1 1

1 1 1 1 1 1

Y1 = wy2 + y1y2 Y2 = y1
 Synchronous Sequential Circuits
One-Hot Encoding
• Another approach to the state assignment questions is to use as many
state variables as there are states in a sequential circuit.
• In this method, for each state all but one of the state variables are equal
to 0, and is referred to as one-hot encoding.
• The following table shows how one-hot state can be applied to the
example sequential circuit.
w= 1
w= 0 Az=0 Bz=0 Present NextNextstate
Present
state
w= 0 state = 1 Output
state w =w0= w0 = 1 w Output
w= 0 w= 1 z z
y 32 12 y 1 2Y31Y2 Y12 1 Y3 Y2 Y1
y y Y Y Y Y
A 00 00 01 0
Cz=1 A
B
001
01 00
001 10
010 0
0
B
C 010
10 00001 10 1001 0
w= 1 C 100
11 dd001 dd 100d 1

• Because there are three states, it is Y1  w

necessary to use three state variables. Y2  wy1
• The remaining five valuations are not Y3  w y1
used and they can be treated as don't cares. z  y3
 w= 0

A No transfer
Present Next state
w= 1 state Outputs
B R2out= 1R3in = 1

w= 0
w= 1 A 00 00 01 0 0 0 0
w= 0 B 01 10 10 0 0 1 0
w= 1 C R1out= 1R2in = 1
C 10 11 11 1 0 0 1
w= 0
w= 1
D 11 00 00 0 1 0 0
D R3out= 1R1in = 1Done = 1

Present Nextstate
state Outputs

A 0 001 0001 0010 0 0 0 0 0 0 0

B 0 010 0100 0100 0 0 1 0 0 1 0
C 0 100 1000 1000 1 0 0 1 0 0 0
D 1 000 0001 0001 0 1 0 0 1 0 1
 Present Nextstate
state Outputs

A 0 001 0001 0010 0 0 0 0 0 0 0

B 0 010 0100 0100 0 0 1 0 0 1 0
C 0 100 1000 1000 1 0 0 1 0 0 0
D 1 000 0001 0001 0 1 0 0 1 0 1

Y1  wy1  y4
Y2  wy1 R1out  R 2in  y3
Y3  y2 R1in  R3out  Done  y4
Y4  y3 R 2out  R3in  y2

Easier to implement than before!

 Synchronous Sequential Circuits

Mealy State Model

• So far we have looked at sequential circuits in which the output
signals were a function of only the state of the system i.e.
Moore type
yp FSMs.
• As was previously mentioned, we can also have FSMs where
the output values are based on both the state of the circuit and
th presentt values
the l off its
it inputs,
i t i.e.
i Mealy
M l typet FSMs.
FSM
• The use of Mealy implementations provides additional options
in the design of the FSM.
• The actual steps required in the implementation are identical to
the Moore implementation.
• A key difference in the Mealy implementation is that during
the present clock cycle the output value corresponds to the
label on the arc emanating from the present
present-state
state node.
 Synchronous Sequential Circuits

Example:
Design a circuit which monitors an input for two consecutive 1s
with the output z equal to 1 in the same clock cycle when the
second occurrence of w=1 is detected.

Clock cycle: t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10

w::
w 0 1 0 1 1 0 1 1 1 0 1
z: 0 0 0 0 1 0 0 1 1 0 0

• The greater flexibility of Mealy-type FSMs often leads to

simpler circuit realizations.
• It is important to note that the two circuits are different in terms
of their output behavior.
• This can be seen in the differences in timing of the output.
 Reset
State diagram
w = 1 z = 0

w = 0 z = 0 A B w = 1 z = 1

w = 0 z = 0

Present Next state p z

Output
state w= 0 w= 1 w= 0 w= 1
State table
A A B 0 0
B A B 0 1

Present Next state Output

State-assigned
St t i d state w= 0 w= 1 w= 0 w= 1
table
y Y Y z z
A 0 0 1 0 0
B 1 0 1 0 1
 z

w D Q
y

Clock Q

Resetn

Circuit

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t 10
1
Clock
0
1
w
0
1
y
0
1
z
0

Timing diagram
 z
D Q Z

w D Q Q
y

Cl k
Clock
Resetn
Mealy
l → Moore
(a) Circuit

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t 10
1
Clock
0
1
w
0
1
y
0
1
z
0
1
Z
0

(b) Timing diagram

Clk

Mealy
State
Mealy
Out
More
State
Moore
State
Moore
Out

In the Moore FSM,

FSM the output is synchronized to the
state of the machine, whereas the Mealy FSM
synchronization is lost.
Example Bus controller

w= 0 w = 0

A No transfer A Reset

w= 1
w = 1  R2out = 1 R3in = 1
B R2out= 1R3in = 1

w= 0 B
w= 1
w= 0
w= 1 C R1out= 1R2in = 1 w = 0 R1 = 1 R2 = 1
w = 1 out in
w= 0
w= 1

D R3out= 1R1in = 1Done = 1

C

w = 0 R3 = 1 R1 = 1 Done = 1
w = 1 out in

The most important difference is the timing

 Synchronous Sequential Circuits

Serial Adder Example

• Addition of two n-bit number can be performed in a serial
manner adding one pair of bits at a time.
• The serial adder,
adder though slower than a parallel addition,
addition
requires less complexity and is easily expanded.
• The only complex part of a serial adder is keeping track of
whether a "carry-out" is generated for each step in the addition
process.
• Since memory of the carry is required,
required this circuit is simple to
implement as an FSM.
• A serial full adder can be designed as either a Mealy or a
Moore type FSM.
• For a Mealy implementation, different actions will have to be
taken depending on the value of the carry from the previous bit
position.
 Synchronous Sequential Circuits

• With the output value depending on both the state and the
present value of the inputs
• For a Moore-type FSM, the output must depend only on the
state off the
h machine hi andd will
ill therefore
h f require
i additional
ddi i l states.
• A key difference between the two types of FSMs is that in the
Mealy a change in the inputs reflects itself immediately in the
outputs,
• while in the Moore the outputs do not change until the change
i inputs
in i forces
f the
h machine
hi into
i a new state, which
hi h takes
k place
l
one clock cycle later. a1 b1 a0 b0

• Solution:
• Let A = an-1,an-2, … a0 c1
c2 FA FA
• Let B = bnn-11,bnn-22, … b0

s1 s0
 Synchronous Sequential Circuits

• With the output value depending on both the state and the
present value of the inputs
• The process starts by adding a0 and b0
• In the next clock cycle, a1 and b1 bits are added including a
possible carry
A

a
Shift register
Parallel load s
Adder
dd
FSM Shift register
Shift register
Parallel load
b
S
Sum = A+ B
B
Clock

Block diagram for the serial adder

 Synchronous Sequential Circuits

• With the output value depending on both the state and the
present value of the inputs
• The addition starts by loading the values of A and B
• Then in each clock cycle, a pair of bits is added by the Adder
FSM and at the end of the cycle the resulting sum is shifted to
the Sum register A
a
Shift register
Parallel load s
Adder
dd
FSM Shift register
Shift register
Parallel load
b
S
Sum = A+ B
B
Clock

Block diagram for the serial adder

Mealy State diagram for the serial adder FSM.
State G: carry-in = 0
State H: carry-in = 1
Reset
11/0
(ab/s)
01/0
00/0
G H 10/0
01/1
11/1
10/1
00/1

State table for the serial adder FSM.

Presentt
P Next state Output s
state ab =00 01 10 11 00 01 10 11
G G G G H 0 1 1 0
H G H H H 1 0 0 1
 State-assigned table.
Next state Output
Present
state ab =00 01 10 11 00 01 10 11
y Y s
0 0 0 0 1 0 1 1 0
1 0 1 1 1 1 0 0 1

Circuit for the adder FSM.

a s
Full
b
adder Y y
D Q
carry-outt

Clock Q

Reset
 Synchronous Sequential Circuits
Moore-type FSM serial adder
Instead of G,, we will use G0 and G1 to denote the fact that the carry
y is 0 and
that the sum is either 0 or 1
We will use H0 and H1 the same way

State diagram for the Moore-type serial adder FSM.

Reset

11 01
00 G0 s = 0 H0 s = 0
10

00
01 00 11 01
10 11 10

01 G1 s = 1 H1 s = 1 11
10 00
State table for the Moore-type serial adder FSM.

Present Nextstate Output

state ab =00 01 10 11 s
G0 G0 G1 G1 H0 0
G1 G0 G1 G1 H0 1
H0 G1 H0 H0 H1 0
H1 G1 H0 H0 H1 1

State-assigned table.
Nextstate
Present
state ab =00 01 10 11 Output
y2 y1 s
Y2 Y1
00 00 01 01 10 0
01 00 01 01 10 1
10 01 10 10 11 0
11 01 10 10 11 1
 Y1  a  b  y2
Y2  ab  ay2  by2
s  y1
Sum bit Y1 y1
a D Q s
Full
b
adder Carry-out
Q

Y2 y2
D Q

Clock Q

Reset

Circuit for the Moore-type serial adder FSM.

 Synchronous Sequential Circuits
State Minimization
• When designing
g g a complex
p FSM,, it is likelyy that the initial attempt
p will
result in a machine that has more states than is actually required.
• Minimizing the number of states is of interest because fewer flip-flops may
be needed to represent
p the states and the complexity
p y of the combinational
circuit needed in the FSM may be reduced.
• Definition 1: Two states Si and Sj are said to be equivalent if and only if for
everyy ppossible input
p sequence,
q the same outputp sequence
q will be produced
p
regardless of whether Si orSj is the initial state.
• This procedure is tedious to perform manually, but it is automated for use in
CAD tools.
• Instead of trying to show that some states are equivalent, it is often easier to
show that some states are definitely not equivalent.
Partitioning Minimization Procedure
• As indicated earlier, the first step in designing an FSM requires the
determination of the number of states which will be needed to implement
the desired machine.
• When dealing with a complex FSM, often redundant states are introduced
which should be eliminated.
 Synchronous Sequential Circuits

• Ideally, to minimize the complexity of the FSM, a machine should use the
minimum number of states.states
• Therefore it becomes important to be able to identify redundant or duplicate
states.
• T define
To d fi what h constitutes
i a duplicate
d li state, if we have
h two states, Si and
d Sj
they are considered to be equivalent if and only if for every possible input
sequence, the same output sequence will be produced regardless of whether
Si orSj is the initial state,
state i.e.
ie
• The two state produce the same k successors.
• If an input signal w=0 is applied to a machine in state Si and the result is
th t the
that th machine
hi moves to t state
t t Su we will
ill say that
th t Su is
i a 0-successor
0 off Si .
• Similarly, if w=1 is applied in the state Si and it causes the machine to move
to state Sv we will say that Sv is a 1-successor of Si.
• In general, we will refer to the successors of Si as its k-successors.
• Using the concept of equivalency and k-successors, we are able to define a
method to minimize the number of states known as the partitioning
• minimization method.
 Synchronous Sequential Circuits

• A partition consists of one or more blocks, where each block comprises a

subset of states that may be equivalent,
equivalent but the states in a given block are
definitely not equivalent to the states in the other blocks.
• The partitioning method initially assumes that all states are equivalent and
then proceeds to determine those state which are not equivalent by
analyzing each states k-successors.
• Example:

Present Next state Output

state z First partition consider
w= 0 w= 1
all
ll states:
A B C 1
B D F 1
C F E 0
P1=(ABCDEFG)
( )
D B G 1
E F C 0
F E D 0
G F G 0
• Second partition consider states that have different outputs (Moore type)
• P2=(ABD)(CEFG)
• We must consider all 0-
0 and 1-1 successors of the states in each block
• For (ABD) the 0- successors are (BDB)
• Since all these successors are in the same block in P2 we should still assume that the
states A,B,
A B and D may be equivalent.
equivalent
• The 1- successors for these states are (CFG)
• Since these successors are also in the same block in P2, we conclude that that (ABD)
should remain in one block of P3
• Let consider the block (CEFG)
Present Next state Output • Its 0- successors are (FFEF)
state z • They are in the same block in P2
w= 0 w= 1
• The 1- successors are (ECDG)
A B C 1 • They are not in the same block in P2,
B D F 1 • It means that at least one of the states in
C F E 0 (CEFG) is not equivalent to the others
D B G 1 • In particular F must be different from the
E F C 0 states C, E, and G because its 1-successors
F E D 0 is D which is in a different block than C,
C E
G F G 0 and G
• Hence P3=(ABD)(CEG) (F)
• P3=(ABD)(CEG) (F)
• For (ABD) the 0- successors are (BDB) which are in the same block in P3
• The 1-
1 successors are (CFG) , which are not in the same block
• Since F is in a different block than C and G, it follows that the state B cannot be
equivalent to states A and D
• The 0- and 1- successors of (CEG) are (FFF) and (ECG)
• Both of these are accomodated in the blocks of P3
• Hence P4=(AD)(B)(CEG) (F)

Present Next state Output

state w= 0 w= 1 z

A B C 1
B D F 1
C F E 0
D B G 1
E F C 0
F E D 0
G F G 0
• P3=(ABD)(CEG) (F)
• For (ABD) the 0- successors are (BDB) which are in the same block in P3
• The 1-
1 successors are (CFG) , which are not in the same block
• Since F is in a different block than C and G, it follows that the state B cannot be
equivalent to states A and D
• The 0- and 1- successors of (CEG) are (FFF) and (ECG)
• Both of these are accomodated in the blocks of P3
• Hence P4=(AD)(B)(CEG) (F)

• Following the same approach we find that

Present Next state Output • P5=(AD)(B)(CEG) (F)
state z • Since P5= P4 , it follows that the states in
w= 0 w= 1
each block are equivalent
A B C 1 • Since each block can be represented by a
B D F 1 single state, only four states are needed
C F E 0 • A A and
A→ dD
D B G 1 • C→ C, E and G
E F C 0 • We will only need two flip-flops
F E D 0
G F G 0
Present Next state Output Present Nextstate Output
state w= 0 w= 1 z state w= 0 w= 1 z

A B C 1 A B C 1
B D F 1 B A F 1
C F E 0 C F C 0
D B G 1 F C A 0
E F C 0
F E D 0 A→ A and D
G F G 0
C→ C, E and G
P4=(AD)(B)(CEG) (F)
 Synchronous Sequential Circuits
Example vending machine
• Suppose that a coin
coin-operated
operated vending machine dispenses candy
under the following conditions:
– The machine accepts nickels and dimes.
– It takes 15 cents for a piece of candy to be released from the
machine.
– If 20 cents is deposited
deposited, the machine will not return the
change, but will credit the buyer with 5 cents and wait for
the buyer to make a second purchase
• Assume a 100 ns clock period and positive edge trigger flip-
flops.
• The coin receptor generates two signals senseD and senseN
which are asserted when a dime or a nickel is detected.
• The coin receptor also generates signal D and is set to 1 for one
clock cycle after senseD becomes 1
• Same for signal N and senseN
 Clock

sense N

senseD

Timing diagram

N
senseN D Q D Q

Clock Q Q

Circuit that generates N

 DN

Reset
DN
DN S1 0 DN

DN DN
D N

S3 0 D
S4 1 S2 0 S7 1
N

D N
DN
S5 1 S6 0 DN DN

N D

S8 1 S9 1

State diagram.
 State table

DN Present Next state Output

Reset state DN =00 01 10 11 z
DN
DN S10 DN
DN DN S1 S1 S3 S2 – 0
D N
S2 S2 S4 S5 – 0
S20 S30 D S71
S41
N S3 S3 S6 S7 – 0
D
DN
N
DN S4 S1 – – – 1
S51 S60 DN S5 S3 – – – 1
S6 S6 S8 S9 – 0
N D
S7 S1 – – – 1
S81 S91
S8 S1 – – – 1
S9 S3 – – – 1
 State table

Present Next state Output

state DN =00 01 10 11 z
P1=(S1,S2,S3,S4,S5,S6 ,S7,S8,S9)
S1 S1 S3 S2 – 0
P2=(S1,S2,S3,S6)(S4,S5,S7,S8,S9)
P3=(S1)(S3)(S2,S6)(S4,S5,S7,S8,S9) S2 S2 S4 S5 – 0
P4=(S
(S1)(S3)(S2,S
S6)(S4, S7,SS8)(S5,S
S9) S3 S3 S6 S7 – 0
P5=(S1)(S3)(S2,S6)(S4, S7,S8)(S5,S9) S4 S1 – – – 1
S5 S3 – – – 1
S6 S6 S8 S9 – 0
S7 S1 – – – 1
S8 S1 – – – 1
S9 S3 – – – 1
Present Next state Output
state DN =00 01 10 11 z
S1 S1 S3 S2 – 0
S2 S2 S4 S5 – 0
S3 S3 S6 S7 – 0
S4 S1 – – – 1
S5 S3 – – – 1
S6 S6 S8 S9 – 0
S7 S1 – – – 1
S8 S1 – – – 1
S9 S3 – – – 1
P5=(S1)(S3)(S2,S6)(S4, S7,S8)(S5,S9)
Present Next state Output
state DN =00 01 10 11 z

S1 S1 S3 S2 – 0
S2 S2 S4 S5 – 0
S3 S3 S2 S4 – 0
S4 S1 – – – 1
S5 S3 – – – 1
Minimized state table
Present Next state Output DN
state DN =00
00 01 10 11 z

S1 S1 S3 S2 – 0 S1 0
S2 S2 S4 S5 – 0
S3 S3 S2 S4 – 0 N
S4 S1 – – – 1 DN
S5 S3 – – – 1
S3 0
D

DN N DN

D
Minimized state diagram. DN S2 0 S5 1

N
D
S4 1
 DN 0 DN

S1 0
S1

N
N 0 D 1 DN

DN 0 S3 0
D
N 1 S3 D 0
DN N DN

N 0 D 1 D
DN S2 0 S5 1

S2 N
D
S4 1

DN 0

Mealy-type FSM
 Synchronous Sequential Circuits
Incompletely Specified FSMs
• If all the k-successors for each state are defined,, a state table is said to be
completely specified.
• However, it is possible that some successors may not be specified or
represent
p input
p conditions which will never occur.
• These unspecified successors correspond to don't care conditions, and the
state table containing them is said to be incompletely specified.
• The partitioning minimization procedure which was applied to completely
specified state tables can also be applied to incompletely specified state
tables.
• To perform the partitioning process, we can assume that the unspecified
outputs have a specific value.
• The partitioning method is equally applicable to Mealy type FSMs in the
same way as for Moore
Moore-type
type FSMs.
 Example of incompletely specified FSM.

Present Next state Output z

state w= 0 w= 1 w= 0 w= 1
A B C 0 0
B D – 0 –
C F E 0 1
D B G 0 0
E F C 0 1
F E D 0 1
G F – 0 –

Let consider both unspecified Let consider both unspecified

outputs = 0 outputs = 1
P1=(ABCDEFG) P1=(ABCDEFG)
(ABCDEFG)
P2=(ABDG)(CEF) P2=(AD)(BCEFG)
P3=(AB)(D)(G)(CEF) P3=(AD)(B)(CEG)(F)
P4=(A)(B)(D)(G)(CE)(F) P4=(AD)(B)(CEG)(F)
P5= P4
 Synchronous Sequential Circuits

Design of a Counter Using The Sequential Circuit Approach

• Counters
C can be
b realized
li d as cascaded
d d stages off flip-flops
fli fl plus
l some
additional standard logic gates.
• As a result, counters can be designed as synchronous sequential circuits
using
i the
h design
d i techniques
h i introduced
i d d ini the
h previousi sections.
i
• Example:
• Design a mod-8 counter
• The counting sequence is 0,1,2,…,6,7,0,1,…
• There is an input signal w
• The value of this signal is considered during each clock cycle.
cycle
• If w=0, the present counter remains the same
• If w =1, the count is incremented.
 w = 0 w= 0 w= 0 w= 0

w= 1 w= 1 w= 1
A/0 B/1 C/2 D/3

w= 1 w= 1

H/7 G/6 F/5 E/4

w= 1 w= 1 w= 1

w= 0 w= 0 w= 0 w= 0

State diagram for the counter.

counter
 w=0 w=0 w=0 w=0

w=1 w=1 w=1

A/0 B/1 C/2 D/3

w=1 w=1

H/7 G/6 F/5 E/4

w=1 w=1 w=1

w=0 w=0 w=0 w=0

Present Next state

Output
state w= 0 w= 1
A A B 0
B B C 1
C C D 2
D D E 3
E E F 4
F F G 5
G G H 6
H H A 7
 Next state
Present
Count
state w= 0 w= 1
y2 y1 y0 z2z1z0
Y2 Y1 Y0 Y2 Y 1 Y0
A 000 000 001 000
B 001 001 010 001
C 010 010 011 010
D 011 011 100 011
E 100 100 101 100
F 101 101 110 101
G 110 110 111 110
H 111 111 000 111

St t
State-assigned
i d table
t bl for
f the
th counter.
t
 y1y0
wy2
Next state 00 01 11 10
Present
Count
state w= 0 w= 1 00 0 0

y2 y1 y0 z2z1z0 01 0 0
Y0 Y0
11 1 0 0 1
A 000 0 1 000
B 001 1 0 001 10 1 0 0 1

C 010 0 1 010 Y0 = wy0 + wy0

D 011 1 0 011
E 100 0 1 100
F 101 1 0 101
G 110 0 1 110
H 111 1 0 111

St t
State-assigned
i d table
t bl for
f the
th counter.
t
 y1y0
wy2
00 01 11 10
00 0 0 1 1

Next state 01 0 0 1 1
Present
Count 11 0 1 0 1
state
t t w= 0 w= 1
y2 y1 y0 z2z1z0 10 0 1 0 1
Y2 Y1 Y0 Y2 Y 1 Y0
Y1 = wy1 + y1y0 + wy0y1
A 000 000 001 000
y1y0
B 001 001 010 001 wy2
C 010 010 011 010 00 01 11 10

D 011 011 100 011 00 0 0 0 0

E 100 100 101 100 01 1 1 1 1
F 101 101 110 101
11 1 1 0 1
G 110 110 111 110
H 111 111 000 111 10 0 0 1 0

Y2 = wy2 + y0y2 + y1y2 + wy0y1y2

St t
State-assigned
i d table
t bl for
f the
th counter.
t
 w Y0
D Q y0

Y1
D Q y1

Y2
D Q y2

Clock
Resetn
 Synchronous Sequential Circuits

Implementation Using JK-Type Flip-Flops

• Implementing
I l i an FSM using i JK flip-flops
fli fl is
i marginally
i ll more difficult
diffi l than
h
using D-type flip-flops.
• Rather than the direct mapping of the single input of the D-type to the next
state, the
h Yi must be
b mappedd on to the h two inputs
i J andd K off the
h JK
JK-type
flip-flop.
• To change the state of the JK to the desired value:
• A JK flip-flop in state 0, and to remain in state 0,
– J=0 and K=d (K can be equal to either 0 or 1)
• A JK flip-flop
p p in state 0,, and to changeg to state 1,,
– J=1 and K=d
• A JK flip-flop in state 1, and to remain in state 1,
– J=d and K= 0
• A JK flip-flop in state 1, and to change to state 0,
– J=d and K=1.
 A JK flip-flop in state 0, and to remain in state 0,
J=0 and K=d (K can be equal to either 0 or 1)
A JK flip-flop
flip flop in state 0, and to change to state 1,
J=1 and K=d
A JK flip-flop in state 1, and to remain in state 1,
J=d and K= 0
A JK fli
flip-flop
fl ini state 1,
1 andd to change
h to state 0,
0
J=d and K=1.

Flip-flop
p p inputs
p
Present
Count
state w= 0 w= 1
y2 y1 y0 z2z1z0
Y2 Y1 Y0 J2K 2 J1K 1 J0K 0 Y2 Y1 Y0 J2K 2 J1K 1 J0K 0
A 000 000 0d 0d 0d 001 0d 0d 1d 000
B 001 001 0d 0d d0 010 0d 1d d1 001
C 010 010 0d d0 0d 011 0d d0 1d 010
D 011 011 0d d0 d0 100 1d d1 d1 0011
E 100 100 d0 0d 0d 101 d0 0d 1d 100
F 101 101 d0 0d d0 110 d0 1d d1 101
G 110 110 d0 d0 0d 111 d0 d0 1d 110
H 111 111 d0 d0 d0 000 d1 d1 d1 111

Excitation table for the counter with JK flip-flops.

 y1 y0 y1 y0
wy2 wy2
00 01 11 10 00 01 11 10
00 0 d d 0 00 d 0 0 d

01 0 d d 0 01 d 0 0 d

11 1 d d 1 11 d 1 1 d

10 1 d d 1 10 d 1 1 d

J0 = w K0 = w

Flip-flop
p p inputs
p
Present
Count
state w= 0 w= 1
y2 y1 y0 z2z1z0
Y2 Y1 Y0 J2K 2 J1K 1 J0K 0 Y2 Y1 Y0 J2K 2 J1K 1 J0K 0
A 000 000 0d 0d 0d 001 0d 0d 1d 000
B 001 001 0d 0d d0 010 0d 1d d1 001
C 010 010 0d d0 0d 011 0d d0 1d 010
D 011 011 0d d0 d0 100 1d d1 d1 0011
E 100 100 d0 0d 0d 101 d0 0d 1d 100
F 101 101 d0 0d d0 110 d0 1d d1 101
G 110 110 d0 d0 0d 111 d0 d0 1d 110
H 111 111 d0 d0 d0 000 d1 d1 d1 111

Excitation table for the counter with JK flip-flops.

 y1 y0 y1 y0
wy2 wy2
00 01 11 10 00 01 11 10
00 0 0 d d 00 d d 0 0

01 0 0 d d 01 d d 0 0

11 0 1 d d 11 d d 1 0

10 0 1 d d 10 d d 1 0

J1 = wy0 K 1 = wy0

y1 y0 y1 y0
wy2 wy2
00 01 11 10 00 01 11 10
00 0 0 0 0 00 d d d d

01 d d d d 01 0 0 0 0

11 d d d d 11 0 0 1 0

10 0 0 1 0 10 d d d d

J2 = wy0 y1 K 2 = wy0 y1
 w J Q y0

K Q

J Q y1

K Q

J Q y2

K Q

Clock
Resetn

Circuit diagram using JK flip-flops.

 Synchronous Sequential Circuits
Example
• Design a three-bit counter that counts the pulses on an input line, w.
• This counter must display the count in sequence 0, 4, 2, 6, 1, 5, 0, 4, and so
on.
• The count is to be represented directly by the flip-flop values themselves,
without using any external gates. (Count = Q2Q1Q0)
• Solution
• Inputp line w should be the clock signal
g
P
Present t N t
Next O t t
Output
Present Next Output state state
state state z 2 z 1 z 0 D flipflops : y 2 y 1 y 0 Y2 Y 1 Y 0 z 2 z 1 z 0

A B 000 D2  Y2  y2 000 1 00 0 00
B C 100 D1  Y1  y1  y2 100 0 10 1 00
C D 010 D0  Y0  y0  y1 y2 010 1 10 0 10
D E 110 110 0 01 1 10
E F 001 001 1 01 0 01
F G 101
0 101 0 11 1 01
G H 011 011 1 11 0 11
H A 111 111 0 00 1 11
 D Q z2

D Q z1

D Q z0

w Q
 Synchronous Sequential Circuits
FSM As An Arbiter Circuit
• The purpose of the arbiter FSM is to control access to a shared resource
where only one device can use the resource at a time.
• Arbiter FSMs are practical circuits which are useful in many types of
systems.
• An example is a computer system in which various devices are connected to
a bus.
• Example
• Design a 3 input priority arbiter circuit, where 3 devices (device 1, device 2,
device 3) provide requests (r1, r2, and r3) to the machine, and the FSM
produces separate output grants (g1, g2, and g3).
• A device indicates its need to use the resource by asserting its request
signal.
• The devices are assigned
g a priority:
p y device 1> device 2 > device 3
• Thus if more than one request signal is asserted, the grant is given to the
highest priority device.
• All signals can change values only on the positive edge of the clock.
clock
 r 1r 2 r 3
Reset 000 Reset

Idle Idle

0xx 1xx r1 r1

gnt1 g1 = 1 gnt1 g1 = 1

x0x 1xx 01x r2 r1 r 1r 2

gnt2 g2 = 1 gnt2 g2 = 1

xx0 x1x 001 r3 r2 r 1r 2 r 3

gnt3 g3 = 1 gnt3 g3 = 1

xx1 r3

State diagram for the arbiter. Alternative style of state diagram

Practical Considerations When Designing FSMs Synchronous Sequential Circuits
• As was the case for our combinational circuits, practical considerations limit
the pperformance of our sequential
q circuits.
• It was previously noted that when dealing with our standard gates,
parameters such as propagation delay, fan-out, etc. limited performance.
• The flip
flip-flops
flops used in our sequential circuits are also constructed from
standard gates, however they have added the complexity of feedback.
• When you consider that for many types of flip-flops the inputs travel
through more layers of gates than the clock,
clock it is necessary to allow time for
the inputs to propagate prior to applying the clock.
• The period of time the input data must be supplied before applying the
clock is referred to as the setup time (tsu.))
• Likewise, since it takes time for the outputs of the latch to feedback to the
inputs, it is important not to be changing the latch inputs while waiting for
the feedback to arrive.
arrive
• Therefore the inputs need to be held constant for a period of time after the
active edge of the clock.
• This is referred to as the hold time (th.))
• The combination of tsu and th affect how quickly the data can be changed
and therefore the maximum frequency at which the FSM can operate.
 Output delays in the arbiter circuit.

Delay

Output delay when using one-hot encoding.

 Synchronous Sequential Circuits

Analysis of Synchronous Sequential Circuits

• As was the case with combinational circuits, rather than synthesizing an
FSM, it is useful to be able to analyze an existing FSM.
• For the analysis
y of an FSM we reverse the steps p of the synthesis
y process.
p
• Knowing that the outputs of the flip-flops represent the present-state
variables, and their inputs determine the next state that the circuit will
• enter,
enter we can construct the state
state-assigned
assigned table for the circuit
circuit.
• Once the assigned state table is determined, the state table and the
corresponding state diagram can be generated by giving a name to each
state.
Example
Y1 y1
D Q
z

Q
w

Y2 y2
D Q

Clock Q

Resetn

Next State
Present
Output
state w= 0 w= 1
Y1 = y2 y1 z
Y2 Y1 Y2 Y1
Y2 = 00 00 01 0
01 00 10 0
z= 10 00 11 0
11 00 11 1
 Next State
Present
Output
p
state w= 0 w= 1 Present Next state Output
y2 y1 z state z
Y2 Y1 Y2 Y1 w= 0 w= 1
00 00 01 0 A A B 0
01 00 10 0 B A C 0
10 00 11 0 C A D 0
11 00 11 1 D A D 1

State-assigned table State table

From the tables we can see that z = 1 when

there are three consecutive ones in w
Example
J y
1 1
w J Q
z

K Q
K
1

J y
2 2
J Q
Clock
K Q
K
2
Resetn

Present Flip-flop inputs

J1  w state w= 0 w= 1 Output
K1  w  y2 y2 y1 z
J 2K 2 J 1K 1 J 2K 2 J 1K 1
J 2  wy1
00 01 01 00 11 0
K2  w 01 01 01 10 11 0
10 01 01 00 10 0
11 01 01 10 10 1

z = 1 when there are three consecutive ones in w

 Synchronous Sequential Circuits

Algorithmic
Al ith i StState
t MMachine
hi (ASM) Ch Chartst
• For large FSMs, rather than using the state diagram, designers often use a
different representation called an Algorithmic State Machine (ASM) chart.
• The ASM chart is a type of flow chart and is used since it provides more
information than is normally indicated on a state diagram
• Three types of elements are used in an ASM chart:
• i) state boxes; ii) decision boxes; and iii) conditional output boxes.
• State box: equivalent to a node in the state diagram or a row in the state table.
• The name of the state is indicated outside the box in the top p left corner.
• The Moore outputs are listed inside the box.
• It is customary to write only the name of the signal that has to be asserted, i.e.
it is sufficient to write z rather than z = 1.
1
• Also, it may be useful to indicate an action that has to be taken, e.g. Count
Count+1.
 Synchronous Sequential Circuits

Algorithmic
g State Machine (ASM)
( ) Charts ((continue))

State name

Output signals
or actions State box
(Moore type)

• For the analysis

y of an FSM we reverse the steps p of the synthesis
y process.
p
• Knowing that the outputs of the flip-flops represent the present-state
variables, and their inputs determine the next state that the circuit will enter,
we can construct the state-assigned
g table for the circuit.
• Once the assigned state table is determined, the state table and the
corresponding state diagram can be generated by giving a name to each
state.
• Decision Box: This indicates that the stated condition expression is to be
tested and the exit path is to be chosen accordingly.
• Conditional Output Box: denotes the output signals that are of Mealy type.
 Synchronous Sequential Circuits

Algorithmic
g State Machine (ASM)
( ) Charts ((continue))
• For the analysis of an FSM we reverse the steps of the synthesis process.
• Knowing that the outputs of the flip-flops represent the present-state
variables, and their inputs determine the next state that the circuit will enter,
we can construct the state-assigned table for the circuit.
• Once the assigned state table is determined, the state table and the
corresponding state diagram can be generated by giving a name to each
state.
• Decision Box: This indicates that the stated condition expression is to be
tested and the exit path is to be chosen accordingly.

0 (False) Condition 1 (True) Decision box

expression
 Synchronous Sequential Circuits

Algorithmic
g State Machine (ASM)
( ) Charts ((continue))
• Conditional Output Box: denotes the output signals that are of Mealy type.
• The condition that determines whether such outputs are generated is
specified in a decision box.

Conditional outputs Conditional output box

or actions (Mealy type)

• NOTE: ASM charts are similar to traditional flowcharts, but includes timing
information because it implicitly specifies that the FSM changes from one
state to another only after each active clock edge.
 Reset

Two consecutive ones

detector A

Reset
w = 1 z = 0 0
w
A B 1
w = 0 z = 0 w = 1 z = 1
w = 0 z = 0
B z

1
w

ASM chart for the FSM on the left

 Synchronous Sequential Circuits

Summary:
• Throughg the use of a state diagram,
g state table, and assigned
g
state table, a formal method for designing FSMs was
introduced.
• Mealy
Meal FSMs can be designed using sing the same methods as a
Moore FSM with the understanding that the output timing will
differ.
• By using a portioning procedure, the number of states in an
FSM can be optimized.