CD 1814146

STi5189
Low-cost QPSK demodulator and MPEG2 decoder

for set-top box applications
Datasheet − production data
Features ■ Active and passive low power modes

■ Integrated voltage regulator
■ DVB-S compliant
■ Two package options: PBGA 23 x 23
■ QPSK demodulation and DiSEqC™ controller
and LFBGA 15 x 15
■ MPEG2 MP@ML video decoding
Information classified Confidential - Do not copy (See last page for obligations)
■ Audio decoding (MPEG1, 2, MP3, Dolby® Description
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Digital 5.1)
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The STi5189 uses state-of-the-art process
■ Linux and OS21 compatible ST40 applications
technology to provide an ultra low-cost, fully
CPU (350 MHz)
featured, SD set-top box SoC. It is a highly
■ 16-bit SDR/DDR1 compatible local memory integrated solution combining QPSK (quadrature
en
interface phase shift keying) demodulation, audio/video
■ Multi-stream, DVR capable transport stream decoding and applications processing into a
Confidential
processing single chip, suitable for MPEG2-based satellite

networks worldwide.
■ Extensive connectivity (USB 2.0 host/ULPI,
fid
Ethernet MAC MII/RMII, DVB-CI) The STi5189 provides a solution for operators to
■ Flash and peripheral memory interface specify a range of low-cost SD STBs including
supporting NOR, NAND and Serial Flash low-cost Zappers, interactive STBs and DVR-
capable STBs, with content delivery using
■ Advanced security features, compatible with broadcast or broadband networks, or both (Hybrid
on
the latest CA requirements STBs).

■ Satellite STBs can be produced with very small
BOM and two-layer PCBs
Resets Analog out
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clocks PCM I/O STB peripherals I/O

JTAG modes S/PDIF out external interrupts
CPU/FPU Audio I/O Peripherals System Flash, SFlash

Clock Gen interfaces
ST40 350 MHz NOR, NAND
System serv
PCM players
MMU SSC
S/PDIF player FMI
Interrupts UART
DACs
I cache FDMA GPIO SFlash Serial Flash
D cache PWM LMI
Timer Infrared
Debug Smartcard
Blitter display ILC SDRAM/DDR
Audio decoder
Memory
STBus
Transport Video decoder Display Video I/O

Security
Video planes DVOs USB
LCMPEG Graphic planes Denc
Cursor plane Teletext
PTI
Deinterlacer DACs Connectivity
TS merger
VTG
Ethernet
Demodulator
DVB-S
Transport streams IQ in Digital video SD in/out

Parallel/serial In/Out Analog video SD out
April 2012 Doc ID 8141465 Rev 5 1/294

This is information on a product in full production. www.st.com 1
Contents STi5189
Contents
1 Related documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1 STi5189 programming manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2 CPU documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 STi5189 features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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3.1 IQ to MPEG2 TS block conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Transport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
en
3.4 Audio/video decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Confidential
3.5 Graphics and display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.6 Audio/video outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
fid
3.7 Processor and memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.8 DVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.9 STB peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
on
3.10 Clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.11 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.12 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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3.13 Package options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.14 Target applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4 Audio and video summary specification . . . . . . . . . . . . . . . . . . . . . . . 21
5 Architecture features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1 Satellite receiver subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.1 Embedded QPSK demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2 Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2.1 STBus interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2.2 Processor core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2.3 Memory subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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STi5189 Contents
5.2.4 Transport stream processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.2.5 MPEG graphics and display processing . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2.6 Graphics and display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2.7 Digital encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2.8 Audio subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.2.9 Central DMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2.10 Internal peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2.11 Clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6 Dataflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.1 Video decode flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.1 15 mm x 15 mm package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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7.2 23 mm x 23 mm package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.3 Environmentally friendly packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Confidential
8 BGA footprint and ball list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

fid
8.1 Ball grid array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8.2 15 x 15 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
on
8.3 23 x 23 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.4 Ball list sorted by ball number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
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9.1 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

9.2 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.4 Demodulator IF interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.5 QPSK AGC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.6 QPSK DAC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.7 QPSK tuner interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.8 Transport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.9 DMA and FDMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.10 Flexible memory interface (FMI) (23 mm x 23 mm package) . . . . . . . . . . 64
9.11 Local memory interface (LMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Doc ID 8141465 Rev 5 3/294

Contents STi5189
9.12 Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.13 Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.14 Video mapping with DENC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.15 CEC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
9.16 Serial Flash interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
9.17 Infrared interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
9.18 USB 2.0 ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
9.19 Ethernet and TS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
9.20 Smartcard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
9.21 Asynchronous serial controller (ASC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
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9.22 Synchronous serial controller (SSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
9.23 Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
9.24 Programmable I/O ports (GPIO and PIO) . . . . . . . . . . . . . . . . . . . . . . . . 76
en
9.25 Alternative functions (mapped to PIO pins) . . . . . . . . . . . . . . . . . . . . . . . 78
Confidential
10 Mode pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
fid
11 Register base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

11.1 Decoder base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
on
12 QPSK demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
12.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
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12.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
12.3 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
12.3.1 I2C chip addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
12.3.2 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
12.3.3 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
12.3.4 I2C interface in standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
12.3.5 Identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
12.3.6 I2C bus repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
12.4 Clock distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.4.1 Clock inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.4.2 Internal clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.4.3 Clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.5 Signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
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STi5189 Contents
12.5.1 Demodulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.5.2 Timing recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
12.5.3 Carrier recovery and derotator loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
12.5.4 Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
12.5.5 Noise indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12.5.6 Forward error correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12.6 DiSEqC 2.x interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
12.6.1 Transmit DiSEqC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
12.6.2 DiSEqC receive interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
12.7 Fast channel acquisition and blind search . . . . . . . . . . . . . . . . . . . . . . . 105
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12.7.1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
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13 QPSK interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
13.1 DiSEqC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
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13.2 DVB-S and DIRECTV registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Confidential
13.3 General-purpose registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

13.4 Fast channel acquisition and blind search registers . . . . . . . . . . . . . . . . 151
fid
14 Configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

14.1 Configuration monitor registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
on
14.1.1 High-speed configuration monitor registers . . . . . . . . . . . . . . . . . . . . . 159

14.1.2 High-density configuration monitor registers . . . . . . . . . . . . . . . . . . . . 160
14.2 Configuration control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
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14.2.1 High-speed configuration control registers . . . . . . . . . . . . . . . . . . . . . 167

14.2.2 High-density configuration control registers . . . . . . . . . . . . . . . . . . . . . 169
15 System services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

15.1 Brief overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
15.2 States of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
15.2.1 Programming the registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
15.3 Clock generation and distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
15.3.1 Subsystem clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
15.3.2 PLL clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
15.3.3 Frequency synthesizer clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
15.4 Reduced power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
15.5 Dynamic power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
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Contents STi5189
15.6 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

15.6.1 Low power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
15.7 Real-time counter (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
15.7.1 RTC_LP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
15.7.2 RTC_27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
15.8 Integrated clock recovery (VCXO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
15.8.1 Clock recovery command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
15.8.2 Clock recovery interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
15.9 Smartcard power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
15.10 Reset control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
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15.10.1 Combining resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
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15.10.2 Power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
15.10.3 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
15.10.4 Long time-out reset timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
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15.10.5 Smartcard reset detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Confidential
15.10.6 SDRAM interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

15.11 CPU programmable interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
fid
16 System services registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

16.1 System services control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
on
16.2 PLL clock generation registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

16.3 Frequency synthesizer clock generation registers . . . . . . . . . . . . . . . . . 212
16.4 Reduced power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
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16.5 Low power control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

16.6 Real-time counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
16.6.1 CLK_LP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
16.6.2 CLK_27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
16.7 Integrated clock recovery (DCO) registers . . . . . . . . . . . . . . . . . . . . . . . 226
16.8 Smartcard power control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
16.9 Reset control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
16.10 CPU programmable interrupt timer register . . . . . . . . . . . . . . . . . . . . . . 233
16.11 Dynamic power control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
17 Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

17.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
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17.2 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

17.2.1 Internal and external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
17.3 Interrupt handlers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
17.3.1 Nested interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
17.4 Interrupt level controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
17.5 Interrupt assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
18 Interrupt system registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

18.1 Interrupt control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
18.2 Interrupt level controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
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19 Memory system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
19.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
19.2 ST40-300 CPU memory management . . . . . . . . . . . . . . . . . . . . . . . . . . 257
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19.2.1 External memories and on-chip peripherals address map . . . . . . . . . 257
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20 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

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20.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

20.2 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
20.3 System: oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
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20.4 Standard digital 3.3V pad DC specifications . . . . . . . . . . . . . . . . . . . . . 261

20.5 LMI pads DC/AC specifications for DDR-based systems . . . . . . . . . . . . 262
20.6 LMI pads DC/AC specifications for SDR-based systems . . . . . . . . . . . . 263
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20.7 Audio DAC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

20.7.1 Audio DAC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
20.8 Video DAC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
20.8.1 Mono video DAC performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
20.8.2 Triple video DAC performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
20.9 Front-end interface: ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
21 Timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

21.1 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
21.1.1 System AC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
21.1.2 Reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
21.1.3 Watchdog reset out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
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Contents STi5189
21.1.4 System clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

21.2 LMI interface specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
21.3 Flexible memory interface (FMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
21.3.1 Synchronous devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
21.4 Transport stream timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
21.5 Transport - output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
21.6 TAP timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
21.7 Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
21.7.1 S/PDIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
21.7.2 PCM decoder output interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
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21.7.3 External audio DAC interface timing requirements . . . . . . . . . . . . . . . 275
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21.8 General PIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
21.9 Digital I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
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21.9.1 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
21.9.2 External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
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21.9.3 ASC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

21.9.4 SSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
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21.9.5 IRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

21.10 Video interface output: YUV dataout (DENC output) . . . . . . . . . . . . . . . 278
21.11 DVO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
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21.12 USB ULPI 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

21.13 Ethernet interface AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
21.13.1 MII interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
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21.13.2 RMII interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

21.14 SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
21.15 QPSK output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
22 Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
23 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
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STi5189 Related documents
1 Related documents
This datasheet is a part of the STi5189 documentation suite, which forms a complete
system description and programming guide. This datasheet is intended for hardware
engineers, and describes the pins, package, electrical characteristics and timing information
for the STi5189 device.
To obtain an up-to-date specification of this product, this datasheet should be read in
conjunction with the latest product errata sheet (bug list) obtainable from
STMicroelectronics.
The documents related to this datasheet are described in the following sections.
1.1 STi5189 programming manual
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The programming manual describes programming of the interfaces and peripherals of the
STi5197 device. It is intended for software and system engineers.
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1.2 CPU documentation
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The ST40 core and its instruction set are documented in the ST40 32-bit CPU Core
Architecture Manual.
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Introduction STi5189
2 Introduction
The STi5189 is optimized for secure Pay-TV applications with integrated DVB, DES, Multi2
and ICAM descramblers and smartcard interfaces. It also has advanced security features
normally found in mid-to-high end devices to further safeguard operator and content
investment.
The STi5189 offers enhancements in performance, features and integration to current users
of ST’s MPEG2 SD family of audio/video decoders and QPSK demodulators, whilst
reducing cost and time-to-market for the next generation of deployments. Few external
components are required to realize a complete STB solution, resulting in very low BOM
cost.
The STi5189 proposes a very small package version allowing unrivaled small applications
and cost reduction.
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STi5189 features summary
The STi5189 integrates in a single IC, QPSK demodulation, FEC, Multi-stream transport
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demultiplexer, applications CPU, audio/video decode, video processing, graphics and
display, advanced security, STB peripherals, audio/video DACs, digital audio/video outputs,
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USB 2.0 host controller/ULPI and Ethernet MAC MII/RMII interface.

The STi5189 has the following features:
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● Embedded QPSK demodulator:

– Fast channel acquisition
– Compatible with direct conversion tuners
– Digital carrier and timing recovery loops
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– DVB-S decoding
– Up to 60 MSPS operation
– Automatic spectral inversion ambiguity resolution
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– Digital cancellation of A/D offset

– Digital Nyquist root filter
● High-performance CPU for applications, middleware, drivers, audio decoding and
network protocols:
– ST40-300, dual-issue, applications CPU
– FPU, MMU, 32 K instruction, 32 K data, two-way, set-associative caches
– Supports OS21 and Linux operating systems
– Target speed at 350 MHz delivering > 630 DMIPs
● Single, 16-bit wide, unified local memory interface:
– Supports both SDR SDRAM up to 166 MHz and DDR1 SDRAM up to 200 MHz
● MPEG2 MP@ML video decoder, dual SD decoding/PIP capable
● Audio subsystem:
– MPEG-1 layers I/II decoding
– MP3 decoding
– Dolby® Digital 5.1 decoding and down mix to Stereo/Pro-logic
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STi5189 Introduction
– Concurrent decoding of audio description

– Optional feature: BTSC stereo encoding
– PCM mixing with sample rate conversion
– Simultaneous audio decode and output of Dolby streams on S/PDIF
IEC60958/IEC61937 digital audio output interface
– Integrated stereo audio DAC system
● Programmable external memory interface:
– Four separately configurable banks, 8-/16-bit wide
– SRAM, peripheral, NOR Flash, NAND Flash, burst mode Flash support
– Boot from NOR or NAND Flash
– Support for DVB-CI module host interface
● Interface to and boot from Serial Flash through high-speed SPI interface:
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– Dual output read support
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● Graphics/Display processing:
– High-performance 2-D graphics blitter accelerator and display compositor, Link-list
control
– Multi-plane video/graphics composition with alpha blending, typical four-plane use
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case (background color + still plane + video plane + OSD plane) and integrated
Tile RAM bandwidth saver for enhanced performance
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– High-quality horizontal and vertical reformatting and resizing, with sample rate
conversion/filtering for video and graphics
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– 8 bpp CLUT and 16 bpp/32 bpp true color graphics formats supported
– Advanced anti-flicker filtering
– De-interlacing SD to 480p/576p for HDMI output
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● Display output:
– PAL/NTSC/SECAM encoder
– Encoding of CGMS, Teletext, WSS, VPS, closed caption
– RoviTM 7.1D and DCS copy protection
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– Four 10-bit video DACs, outputting RGB/CVBS/YC analog video signals

– High drive-capability on one of the video DACs for CVBS output without buffering
– 8-bit digital video output (DVO), compliant with ITU-R BT 601/656 formats
– 54 MHz output data rate on DVO supporting 480p/576p output over 8 bits
● DVR capable transport subsystem:
– TS reception from internal QPSK demodulator
– External TS interface for a second stream input from external tuner/demodulator
– Dual internal TS from memory for network/IP stream input and DVR playback
– TS output for routing to DVB-CI module
– DVB-compliant, triple-stream transport de-multiplexing
● DVB, DES, Multi2 descrambling
● ICAM2.2 NDS Conditional Access
● DVR supported with HDD attachment through EIDE (PIO mode) or USB 2.0
● Multi-channel flexible DMA Controller
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Introduction STi5189
● Connectivity:
– 10/100 Ethernet MAC with MII/RMII interface to external PHY
– USB 2.0 host controller with ULPI interface to external PHY
● On-chip STB peripherals:
– Two smartcard interfaces with integrated clock generation
– Four UARTs with Tx and Rx FIFOs
– Three SSCs for I²C/SPI master/slave interfaces, one of which can be dedicated for
tuner control with minimum tuner disturbance
– Five 8-bit GPIO banks with alternate functions
– Infrared transmitter/receiver
– PWM
– CEC line controller
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● System services:
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– All clocks generated from a single external crystal
– Integrated DCO for clock recovery
– Low power/RTC/watchdog controller
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– JTAG/TAP interface
● Advanced security:
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– Secure control words

– Code authentication
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– JTAG interface locking

– DVR copy protection
● On chip 1 V (nominal) voltage regulator
● Two package options:
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– 23 mm x 23 mm
– 15 mm x 15 mm full specification
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STi5189 Functional overview
3 Functional overview
The STi5189 will be available in two packages, LFBGA 15 mm x 15 mm and PBGA

23 mm x 23 mm, with application options dependent upon the package size. Details of the
options can be found in Section 3.13: Package options.
3.1 IQ to MPEG2 TS block conversion

The device contains two 8-bit analog to digital converters for I-input and Q-input, a QPSK
demodulator and a forward error correction (FEC) unit with both an inner (Viterbi) and a
outer (Reed-Solomon) decoder.
It also provides a DiSEqC™ bi-directional interface for flexible control of the outdoor unit.
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The device accepts baseband differential signals as I and Q inputs. Analog to digital
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conversion is performed by two 8-bit ADCs. The signal is then demodulated by the QPSK
demodulator to recover a byte stream. The FEC block then performs convolutional
de-interleaving, Reed–Solomon decoding and de-randomizing to provide an MPEG2
transport stream.
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The QPSK demodulator and FEC unit is compliant with the DVB-S specification. The high
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sampling rate facilitates the implementation of low-cost, direct conversion tuners.

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3.2 Transport
The STi5189 is able to receive and process transport streams from different sources
including the internal QPSK demodulator, an external parallel/serial transport stream input
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and from a network or HDD source through two internal transport streams from memory
paths. A transport stream output is also available to route TS streams to an external DVB-CI
module which is then returned through the external TS input, eliminating the need for
external buffers. The external TS input can also be used to attach a second
tuner/demodulator front end to support dual tuner DVR applications.
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Transport streams are processed by the integrated Programmable Transport Stream engine
(PTI). This performs PID filtering, packet demultiplexing, descrambling and section filtering
on multiple transport streams received from the broadcast, IP and HDD sources.
DES, DVB and Multi2 ciphers are supported for descrambling. The STi5189 integrates the
latest version of NDS’s ICAM CA (v2.2), and is compatible with the advanced security
requirements of all the mainstream CA vendors including Conax, Irdeto, Nagra, NDS and
Viaccess.
3.3 Connectivity
The STi5189 has a range of options for connecting to external peripherals or IP network
devices, such as wired Ethernet, xDSL, Wi-Fi, and so on. These interfaces enable the
delivery of IP streams received over broadband networks and support streaming over home
networks. These interfaces include a USB 2.0 host controller with a digital ULPI interface
(PHY attached externally) and a 10/100 Ethernet MAC with MII/RMII interface (PHY
attached externally).
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Functional overview STi5189
3.4 Audio/video decoding

The STi5189 incorporates the latest MPEG2 decoding technology. It can decode up to two
MPEG2 MP@ML SD streams concurrently, for watching a main program with an optional
PIP program and for supporting smooth trick modes in DVR applications.
Audio decoding is performed in firmware running on the high-performance ST40-300 host
CPU. The host CPU has been greatly enhanced, compared with previous generation
devices, to make this possible without affecting the overall performance for the applications.
MPEG1 Layers I/II, MP3, Dolby Digital 5.1 with down-mix are supported. Concurrent
decoding of an MPEG-1 audio description channel is also possible.
3.5 Graphics and display
The STi5189 integrates a graphics and display subsystem that can deliver a high-quality
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visual experience for applications. The heart of this subsystem is a high-performance
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multi-operator 2D graphics blitter/compositor. This is a link-list-based module that also
supports a high-priority composition thread to perform the main display composition of video
and graphics planes. The CPU can also intervene to generate graphics and subtitle.
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Paced interleaving of application tasks within the composition thread ensures the most
efficient use of the blitter/compositor for enhanced graphics performance. Both 8 bpp CLUT
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(32-bit entries) and 16 bpp/32 bpp true color graphics formats are supported. True color
formats include ARGB1555, ARGB4444, ARGB8888, RGB565 and YCbCr422.
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Graphics can be independently rendered on each plane of an application requiring typically

two graphic planes (for example, still and OSD planes). These are then combined, using
alpha blending and color keying, with video by the blitter/compositor for the main video
output. High-quality video post-processing can be applied to resize, reformat and
de-interlace video between the encoded and intended display formats during composition.
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The STi5189 graphics sub-system benefits further from a tile RAM to reduce latency and
bandwidth of blitter/compositor operations, resulting in significant increases in display
rendering and overall system performance. Further enhancements include an advanced
anti-flicker filter engine, capable of frame-to-field or frame-to-frame operations, filter strength
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adaptation and optimum handling of transparent pixels.

The above feature set guarantees a smooth user interface and high performance for
demanding middlewares such as MHP™.
A graphics DMA (GDMA) reads the final composed display fields/frame and sends it to the
digital encoder and digital video output. Teletext data is also read by the GDMA and sent to
a buffer for insertion in the VBI through the digital encoder.
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3.6 Audio/video outputs

The STi5189 has both digital and analog interfaces for outputting video to the TV, and
supports the standard 480i/576i SD timings. An integrated digital encoder (DENC) supports
output of PAL/NTSC and SECAM formats. The DENC inserts synchronization and VBI
signals, with support for CGMS-A, Rovi and DCS copy protection, Teletext, closed caption,
WSS and VPS. The Analog interface comprises four video DACs for outputting RGB+CVBS
or YC+CVBS signals. A high drive DAC is used for CVBS, eliminating the need for an
external buffer.
The digital video output (DVO) provides a digital version of the display composition
compliant to ITU-T R BT601 or BT656 standards. Both SD and ED (480p/576p) output
timings can be supported on this interface. This interface may be used to connect to an
external HDMI transmitter to provide an HDMI interface in the application.
Audio is output over an S/PDIF interface, stereo analog DACs (DAC is high drive and does
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not require buffers) and a digital PCM output interface. It is possible to output both
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compressed and decoded audio streams, at the same time, over different interfaces (for
example, Dolby Digital 5.1 over S/PDIF with decoded MPEG1 audio through the analog
output).
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3.7 Processor and memory
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The STi5189 embeds the latest ST40 applications processor, the ST40-300, with two-way
set associative caches, a 32 K instruction cache, 32 K data cache, FPU and MMU. At an
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operating frequency of 350 MHz it can deliver > 580 DMIPs performance.
The STi5189 supports both SDR and DDR1 memory technology on its 16-bit Local Memory
Interface (LMI), providing a high bandwidth, unified memory for code, data, audio and video
buffers, graphics, and so on. Up to 64 Mbytes capacity can be supported with a single
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512 Mbit device and 128 Mbytes capacity can be supported by two 512 Mbit devices.
A 16-bit Flexible Memory Interface (FMI) is used for connecting to Flash and
RAM/peripherals supporting a standard 8- or 16-bit asynchronous read/write protocol.
Synchronous or burst mode Flash can also be supported. Both NOR and NAND Flash can
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be used, with the ability to boot from either. The STi5189 integrates a NAND controller for
accessing NAND Flash and to perform ECC generation.
Interfacing and booting from Serial Flash devices attached through high-speed SPI is also
supported.
3.8 DVR
The STi5189 supports the attachment of an HDD through USB 2.0 or EIDE (PIO mode),
allowing DVR STBs to be developed. The STi5189 can support recording of up to two SD
streams, with local playback of a third SD stream with trick modes. Streams can be
encrypted to/from the HDD using the T-DES cipher. Basic DVR time-shift capability, without
HDD attachment, can also be supported, either over USB 2.0 with attached Flash drive or
with NAND Flash attached directly on the FMI.
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3.9 STB peripherals

The STi5189 integrates a range of peripherals and interfaces to minimize or eliminate the
external cost of implementing basic STB functions. These include four UARTs and two
SSCs used for serial interfaces and I2C control busses. An additional dedicated I2C port is
available for the tuner. There are two smartcard controllers, an IR transmitter/receiver, PWM
module, five general-purpose programmable I/O banks and three external interrupt inputs.
3.10 Clock generation

All internal clocks and output clocks are generated on chip, using PLL/frequency
synthesizers from a single externally attached crystal. An integrated DCO performs encoder
clock recovery.
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3.11 Low power modes
Two low power modes are supported by the STi5189, passive and active standby modes.
Passive standby mode reduces the power consumption to a minimum. Almost all the device
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is powered down (clocks reduced/stopped and interfaces disabled) and the ST40 CPU can
remain running at the minimum frequency possible. The LMI puts the SDRAM into
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self-refresh mode before powering down. The device context is fully maintained. The device
can be quickly powered up without re-booting by an IR remote control event, an internal
timer event or an external interrupt.
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Active standby mode is a user-defined configuration where selected features and interfaces
can be powered down (clocks reduced/stopped and interfaces disabled) while required
features can remain clocked at full speed. In a typical configuration, the STB may not be
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decoding or displaying a program (that is, decoders and DACs are powered down), but is
required to respond to data or messages arriving through the broadcast or broadband
connection (transport or Ethernet subsystems remain active).
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3.12 Power supplies

The STi5189 requires three supply voltages. Nominally these are 1 V, 2.5 V and 3.3 V. The
STi5189 incorporates a nominal 1 V voltage regulator to generate all the on chip 1 V
requirements from the 2.5 V supply without a separate voltage regulator.
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3.13 Package options

The STi5189 will be available in two package options, 15 mm x 15 mm LFBGA, 0.8 mm
pitch and 23 mm x 23 mm PBGA, 0.8 mm pitch. Both package types are compatible with the
design of two-layer PCBs.
15 mm x 15 mm LFBGA, 0.8 mm pitch

This is the main stream, low-cost option that does not include the FMI interface. Both
Ethernet and USB 2.0 interfaces are still available. For this option, the Flash used must be
Serial NOR Flash attached to the high-speed SPI interface.
23 mm x 23 mm PBGA, 0.8 mm pitch

This option should be selected if a full specification device is required, which includes the
FMI. Any Flash type (Serial NOR, parallel NOR, NAND) can be used with this package. The
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following features are available with this package option:
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● All the features as in the BGA15 mm x 15 mm package
● DVB-CI support
● NAND Flash storage
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● FMI interfaces available, secure boot from any Flash (Serial, NAND or NOR)
● HDD attachment through EIDE
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With this package, DVB-CI and Ethernet are mutually exclusive options.
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Doc ID 8141465 Rev 5 17/294

3.14 Target applications

The following diagrams show typical applications of the STi5189. The Figure 1 and Figure 2
use the 15 mm x 15 mm package version and Figure 3 uses the 23 mm x 23 mm package
version.
Figure 1. MPEG2 broadcast satellite STB (basic zapper)
Smartcard 0
RF IN
AGC
2
Satellite I C ST8024
tuner
IQ+/-
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SC0
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DDR LMI
SSC/I2C
SDRAM E2 PROM
STi5189
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HS_SPI 15 mm x 15 mm Analog audio,
Flash L/R
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CVBS
CVBS
fid
Display driver
UART
or FP micro
4 digit, 7 segment 30 MHz
PIOs
display
Left
IR Rx
Front panel display Right
and controls S/PDIF
on
S/PDIF
JTAG
Reset DCU
Power supply
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IDC (20)
18/294 Doc ID 8141465 Rev 5

Figure 2. MPEG2 dual tuner/hybrid DVR satellite STB with HDD
Ethernet USB 2.0

host
RJ45 RS232 Smartcard 0
HDD
RF IN
Ethernet USB
PHY PHY
LNA, splitters
ST3232 ST8024
RMII ULPI
AGC
Satellite Satellite I2C
tuner tuner IQ+/- UART
IF
AGC
UART/SC
Serial TSin
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STV289 I2C
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SSC/I2C
E2 PROM
STi5189
DDR LMI
15 mm x 15 mm
SDRAM TV
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CVBS
SCART
HS_SPI
Flash RGB STv
AUX/
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641x
loop-through
30 MHz SCART
Display driver UART
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4 digit, 7 segment or FP micro Analog audio,

PIOs
display L/R
Left
IR Rx
Right
Front panel display S/PDIF
S/PDIF
and controls
on
JTAG
Reset DCU
Power supply
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IDC (20)
Doc ID 8141465 Rev 5 19/294

Figure 3. MPEG2 broadcast satellite STB (common interface zapper)
Smartcard 1 Smartcard 0
RF IN
AGC
Satellite I2C ST8024
ST8024
tuner IQ+/-
TS OUT
SC1
DVB-CI TS IN
UART/SC
SSC/I2C
FMI E2 PROM
I STi5189
Buffers
23 mm x 23 mm Analog audio,
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L/R
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DDR LMI
SDRAM
CVBS
HS_SPI CVBS
Flash
30 MHz
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Display driver UART
4 digit, 7 segment Left
or FP micro
display
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PIOs Right
S/PDIF
Front panel display IR Rx S/PDIF
and controls
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JTAG
Reset DCU
Power supply
on
IDC (20)
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20/294 Doc ID 8141465 Rev 5

STi5189 Audio and video summary specification
4 Audio and video summary specification
Table 1. Summary specification

Feature Description
Video decoder
Based on the Omega2, provides a memory to memory decode into YC 4:2:0

Video decode display
macroblock format
MPEG-1 video (ISO/IEC 11172-2), MPEG-2 video (ISO/IEC 13818-2)
Bit streams accepted MPEG-2 packetized elementary stream (PES) format as defined by ISO/IEC 13818-1
MPEG-1 ISO/IEC 11172-1 packets
MPEG-2 profiles/levels Main profile at main level (MP@ML), main profile at low level (MP@LL)
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supported Simple profile at main level (SP@ML)
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Width: 720 x 576 pixels = 45 x 36
Maximum picture size
Number of macroblocks: 45 x 36 = 1620
MPEG-1: -1024 to 1023 (full pel), -512 to 511.5 (half pel) horizontal and vertical
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Motion vector range
MPEG-2: -1024 to 1023.5 horizontal and -128 to 127.5 vertical
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PTI compressed data

Serial peak input rate: 100 Mbit/s
input
16-bit wide SDRAM interface (DDR or SDR). Theoretical peak bandwidth 800 Mbyte/s
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(200 MHz DDR). Supports 64 Mbit, 128 Mbit, 256 Mbit or 512 Mbit SDRAM (DDR or
SDRAM LMI interface
SDR). Fully cacheable address space for data and instructions, with data cacheability
controlled in 512 Kbyte blocks for up to 8 Mbytes.
Automatic detection of start codes (of picture layer and above) to enable the
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Start code detection microcontroller to access header data

Counters provided for time-stamp tracking
Instruction register sets up each picture and defines pipeline operation
Decoding pipeline Double-buffered quantization matrices enable loading of new tables concurrently with
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decoding
Automatic concealment of errors detected by VLD and decoding pipeline by macroblock
Error concealment
copy
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Audio and video summary specification STi5189
Table 1. Summary specification (continued)

Feature Description
Display
Video clock 27 MHz nominal

External pel clock
Horizontal/vertical synchronization provided by internal digital encoder or external
source
Video output Interlaced output
3:2 pull-down operation supported
On-chip up-/down-sampling with anti-aliasing filter
Vertical chroma reconstruction or luma filtering up to 5-tap filter
Horizontal: maximum vector size: 2047 pels, resolution: 1/8 pel
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Pan and scan vectors
Vertical: maximum vector size: 1022 lines, resolution: 1 line
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Blitter-based composition
The OSD plane is managed as a set of horizontal bands with a specification comprising
configuration, bitmap and, for CLUT formats, palette information for each region. The
OSD operates in one of two modes, palette mode or true color mode.
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Palette mode: Each region can be independently specified with a resolution of 8 bpp.
Regions are frame based. Each region palette can support up to 256 colors with up to
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On-screen display (OSD)

24-bit resolution per color entry.
True color mode: Each region can be independently specified with a 16 bpp/32 bpp
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resolution in one of the following direct color formats: RGB565, ARGB1555, ARGB4444
or ARGB8888.
A vertical interfield, anti-flicker filter is provided to reduce flicker on interlace displays. It
is available for both palette and true color modes.
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Audio decoder
Bit streams accepted MPEG-1 layers I, II and III (MP3), Dolby digital 5.1
ISO/IEC 11172-3 layers I and II
All MPEG input bit rates supported with sampling rates of 32 kHz, 44.1 kHz and
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Performance
48 kHz, free format at 32 kHz and 48 kHz sampling rates.
Decodes in single channel, dual channel, stereo or joint stereo modes
Error concealment Automatic error concealment on CRC or synchronization error detection
General
Support for A/V sync PTS/DTS extraction from MPEG packet layers with automatic association
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STi5189 Architecture features
5 Architecture features
The major components of the STi5189 are described in the following sections.
5.1 Satellite receiver subsystem

The satellite receiver subsystem incorporates an AD converter, QPSK demodulator and a
dedicated PLL. The QPSK demodulator creates the transport stream from the satellite input
and passes it through a multiplexer to the programmable transport stream interface (PTI).
The PTI provides the functions of transport stream parsing, demultiplexing and interfaces to
descramblers.
On the side of the transport stream received from the QPSK demodulator, the STi5189 can
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also support an external transport stream input.
5.1.1
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Embedded QPSK demodulator
The embedded QPSK demodulator has the following features:
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● Fast channel acquisition:
– Rapid scanning in seconds for satellite transponders
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– High-speed scanning mode for blind symbol rate acquisition

● Compatible with direct conversion tuners:
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– Dual 8-bit analog to digital converters

– Wide range carrier tracking loop for frequency offset recovery
– Flexible clock generation to operate with 30 MHz external reference
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● Digital carrier and timing recovery loops:

– Full digital timing and phase recovery loops
– 0.20, 0.25, 0.35 roll-off factors
● DVB-S decoding:
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– VITERBI soft decoder rate 1/2

– Puncture rates are 1/2, 2/3, 3/4, 5/6, 6/7, 7/8
– Outer Reed-Solomon decoder as per DVB-S specification
– Energy dispersal descrambler
● Up to 60 MSPS operation
● Automatic spectral inversion ambiguity resolution
● Digital cancellation of A/D offset
● Digital Nyquist root filter
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Architecture features STi5189
5.2 Decoder
5.2.1 STBus interconnect

The Omega2 multi-path unified interconnect provides high on-chip bandwidth and low
latency accesses between modules. The interconnect operates hierarchically with latency-
critical modules placed at the top level. The multipath router allows simultaneous access
paths between modules and simultaneous read and write phases from different transactions
to and from the modules.
5.2.2 Processor core

The STi5189 integrates a 350 MHz ST40-300 processor core that features a 32-bit
superscalar RISC CPU and IEEE-754 compliant floating point unit (FPU). The ST40-300
includes two-way, set-associative caches and an interrupt controller with 15 user interrupt
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sources and an interrupt expansion port.
5.2.3 Memory subsystem

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The STi5189 has a local memory interface (LMI) and a Serial Flash interface. The
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23 mm x 23 mm package option additionally supports a parallel peripheral/Flash memory
interface (FMI).
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Local memory interface

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The LMI is used for all code/data requirements in unified memory applications, including
graphics, video and audio buffers. It is a 16-bit wide SDR/DDR SDRAM interface with a peak
bandwidth of 800 Mbytes (DDR running @ 200 MHz). It supports 64-Mbit, 128-Mbit,
256-Mbit or 512-Mbit devices. The LMI provides a fully cacheable address space for data
and instructions, with data cacheability controllable at block level.
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Serial Flash interface

The Serial Flash interface is a dedicated four-wire synchronous serial peripheral interface
(SPI) for attaching Serial Flash devices. The STi5189 also supports dual output read mode.
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The STi5189 is capable of booting directly from Serial Flash. Code can then be copied into
LMI memory and executed from there. Secure boot from Serial NOR Flash is supported.
Flash memory interface

The FMI (23 mm x 23 mm package option) provides a glueless interface to SRAM, parallel
NOR Flash, NAND Flash and peripherals, in up to four configurable banks over a 16-bit wide
interface. Bus cycle strobe timings can be programmed from 0 to 15 phases for slower
peripherals.
The FMI interface provides the support for DVB-CI and ATAPI connections. With the
23 mm x 23 mm package, the STi5189 can boot from either NOR Flash (parallel or serial) or
NAND Flash.
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5.2.4 Transport stream processing

The STi5189 has a TSmerger and programmable transport stream interface for processing
the transport stream from the demodulator and a second transport stream coming from the
transport stream input.
When the STi5189 is used to implement a DVB-CI application (23 mm x 23 mm package
only), the transport stream coming from the demodulator can be output from the chip to go
to the conditional access module, and reinserted in the chip through the transport stream
input.
Programmable transport interface (PTI)

The PTI hardware performs the following functions:
● descrambling, demultiplexing and data filtering
● DMA transfers the PES data to audio and video decoders through circular buffers
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● DMA transfers the section data to separate buffers for further processing by the CPU
● DVB transport streams with data rates up to 100 Mbit/s
● PID filtering to select the audio, video and data packets to be processed
● can support 48 PID slots
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● Descramble streams using the following ciphers:
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– DVB-CSA
– DES-ECB
– NDS specific streams that are supported by the integrated ICAM functionality
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● has a section filter core that filters DVB standard sections using 48 x 8 byte filters
5.2.5 MPEG graphics and display processing

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The MPEG graphics and display architecture shown in the following figure provides the
graphics, video-stream processing and display capabilities of the STi5189:
Figure 4. Graphics and display sub-system

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DDR
16
Blitter
LMI
Omega2 interconnect
Omega2 Digital video

GDMA
video
decoder
VDAC Analog video

DENC output
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Video decode and display

Video decoding is performed by the STi5189's MPEG2 MP@ML video decoder. The
decoded 4:2:0 macroblock formatted video is then resized and composited with graphics by
the blitter-based display as described in the next section.
The GDMA then retrieves the final composition from memory and delivers it to the DENC,
which in turn drives the output video DACs.
5.2.6 Graphics and display

Display
The STi5189 uses blitter-based display architecture that allows the user to build a complex
user interface with background color, still picture, video plane and on-screen display (OSD)
as illustrated in the following figure:
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Figure 5. Example of composition
Background
color
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Decompressed
video
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Replay
On-screen
Score Stats
display
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Replay Score Stats
OSD plane
The OSD plane is managed as a set of horizontal bands with a specification comprising
configuration, bitmap and, for CLUT formats, palette information for each region. The OSD
operates in one of two modes, palette mode or true color mode.
Palette mode: Each region can be independently specified with a resolution of 8 bpp.
Regions are frame based. Each region palette can support up to 256 colors with up to 24-bit
resolution per color entry.
True color mode: Each region can be independently specified with a 16 bpp/32 bpp
resolution in one of the following direct color formats: RGB565, ARGB1555, ARGB4444 or
ARGB8888.
A vertical inter-field, anti-flicker filter is provided to reduce flicker on interlace displays. It is
available for both palette and true color modes.
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Display mixing
Display planes are mixed by the blitter using alpha blending between the planes. Mixing of
the OSD plane with the lower layers is achieved using one of the following on a per region
basis:
● a 4-bit alpha blending component per region (true color mode and palette mode without
anti-aliasing enabled)
● an individual 6-bit alpha component per color (palette mode with anti-aliasing enabled)
● alpha with pixel (ARGB1555, ARGB4444 or ARGB8888, true color mode only)
Digital video output

The STi5189 provides a digital video output (DVO). This is an 8-bit interface that outputs the
display composition digitally over 8-bit in accordance with ITU-R BT601 and BT656
standards. 480i/576i is output with a 27 MHz pixel clock and de-interlaced 480p/576p can
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also be output with a 54 MHz pixel clock. Both formats can be used to interface to an
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external HDMI transmitter if the application requires an HDMI interface.
CEC controller
The STi5189 integrates a hardware CEC controller to support HDMI applications with a
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low-cost external HDMI transmitter. The CEC controller offloads the CPU from the low-level
bit timing, bit shaping and arbitration needs of the CEC protocol.
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Genlocking
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Genlocking locks the STi5189 OSD to an incoming analog signal. The RGB signals contain
OSD that can be overlaid on top of analog CVBS, allowing single OSD for both digital and
analog reception. The OSD active signal can be used as a fast blanking signal to switch
between CVBS and RGB, as illustrated in the following figure.
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The STi5189 does not require any external PLL to lock its own pixel clock. It uses its own
internal PLL, which reduces the overall BOM.
Figure 6. Genlock support

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CVBS
from analog
tuner Sync HSync
Extractor VSync RGB
27 MHz STi5189
OSD
Xtal active
Genlocked to incoming CVBS
5.2.7 Digital encoder

The digital converter process YCbCr 4:4:4/4:2:2 from main memory, which the blitter has
generated and produces standard analog baseband PAL/SECAM/NTSC signal and
component (YUV/RGB).
The digital encoder can handle interlaced mode in all standards. ITU-T 601 aspect ratio
displays can be supported in all standards. The digital encoder performs closed-caption,
CGMS, WSS, Teletext and VPS encoding, and allows Rovi 7.01/6.1 and DCS copy
protection.
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One integrated quad-DAC provides four analog TV outputs, on which it is possible to output
either (CVBS + RGB) or (CVBS + YUV) or (S - VHS (Y/C) + CVBS1 + CVBS2).
5.2.8 Audio subsystem

The audio subsystem supports audio decoding of MPEG-1 layers I, II, III (MP3) and Dolby
Digital 5.1 with down-mixing.
Simultaneous audio decoding and compressed output of Dolby streams on the S/PDIF is
supported.
Audio sample rates of 32 kHz, 44.1 kHz and 48 kHz are supported.
The audio subsystem is illustrated in the following figure:
Figure 7. Audio subsystem
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DMA request
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DMA request
Memory
FS
Stereo
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analog
Audio outputs
decoder
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LMI FDMA PCM player ADAC

(ST40)
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System interconnect
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S/PDIF output
S/PDIF
player
CPU Interrupts
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The audio subsystem consists of the following units:

● audio decoder (audio decoding is performed by firmware running on the ST40
applications CPU)
● S/PDIF player
● PCM player
● integrated 24-bit stereo audio DAC system
● audio/digital frequency synthesizer: generates the PCM and sample rate clocks
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5.2.9 Central DMA controller

The STi5189 has a multi-channel, burst-capable direct memory access controller that
supports the following:
● Fast 2D unaligned memory to memory transfers of graphics and stills.
● Real time stream transfers to and from memory with or without pacing. These channels
are suitable for transfers with external peripherals, for audio and video stream transfers
within the STi5189.
5.2.10 Internal peripherals

The STi5189 has many dedicated internal peripherals for digital TV receiver applications,
including:
● two smartcard controllers
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● four ASCs (UARTs) which are generally used by the smartcard controllers or for
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modem application
● three SSCs for I²C master/slave interfaces, with SPI support
● five GPIO ports
● infrared blaster/decoder interface module
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● DVB common interface support
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● a fully integrated digital VCXO

● an interrupt level controller
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● a low-power/RTC/watchdog controller
● DCU toolset support
● a JTAG/TAP interface
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5.2.11 Clock generation

All system clocks are generated using the clock generator block. This contains two
high-frequency PLLs (800 MHz/700 MHz) that are divided down to produce a series of
phase-related programmable clock channels.
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The STi5189 has a clock master. The Flash clock output may be phase aligned to optimize
the external bus performance of the FMI.
VCXO functionality has been integrated using a special purpose frequency synthesizer, thus
removing the need for an external varactor diode or VCXO module.
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Dataflow STi5189
6 Dataflow
This chapter describes the system dataflow for audio/video reproduction from the front-end
compressed stream through the audio/video decoders and various buffers to the final
audio / video presentation.
In the following dataflow, the programmable transport interface (PTI) performs the transport
stream demultiplexing. The channel 0 DMA generates audio and video circular buffers in the
main memory.
6.1 Video decode flow
Figure 8. Video decode flow
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Transport In (from demodulator section)
LMI
Memory buffer Association
table of
TSIS PTI Ch0 PTI Vid address
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FDMA PES/SCD and SC
PES buff
by FDMA
FDMA
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Vid
ES VidDMA
fid
Vid VidDMA
Video
TMP
VidDMA
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Vid420
out
BlitDMA
OSD
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BlitDMA BLIT
Video + Display
background buffers
(444)
GDMA DENC TVOut
The PTI channel 0 circular video buffer is accessed by the FDMA, which is a linear linked-list
machine. The synchronization is described in the following paragraph:
The host CPU is interrupted by a programmed timer event from system services, for
example, every 10 ms. The interrupt routine reads the Ch0 write pointer from the PTI; using
this and the previous write pointer, a single pass linear access is activated using a dedicated
process (PPSCD) running on the FDMA (with hardware assist) to perform PES parsing and
start code detect.
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STi5189 Dataflow
The FDMA PPSCD process generates an elementary stream (ES) buffer in the main
memory and an association table, which can be placed in the external memory or local
SRAM.
Each entry of the PPSCD table contains the following information:
● start code value
● PTS if present
● start code offset in the PES buffer
● start code address in the ES buffer
This table is accessed by the video driver running on the host CPU. The ES video buffer is
accessed directly using the linear DMA engine inside the video decoder. This block
generates several intermediate buffers during the prediction and reconstruction phases of
decode, before generating a final video buffer in YCbCr 4:2:0 format.
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The video buffer is read directly by the blitter, which performs multiple passes to format
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convert and blend the video buffer with a background and OSD overlay, before rendering a
final display buffer in YCbCr 4:2:2 format.
The picture composed by the blitter is always frame based. The final presentation buffer is
read by the GDMA, which drives the digital encoder to produce composite video output. The
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GDMA should be programmed to access the presentation buffer field based.
Standard audio decode flow: The elementary stream, corresponding to the bypass (Dolby
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stream), is moved to the S/PDIF player by the FDMA. The FDMA performs appropriate
formatting for the S/PDIF player. The S/PDIF player outputs the data on the S/PDIF output.
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The audio elementary stream is read from buffers in memory by the ST40 CPU executing
the decoding firmware. The decoded audio is then written back to decoded audio buffers in
memory. The CPU can also perform some post-processing.
The FDMA can also move the decoded audio, which is buffered external to the audio
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decoder, to the S/PDIF player after appropriate formatting. The formatting consists of the
addition of channel status, user data and validity flag.
The CPU generates a PCM buffer that can be used to generate the beep tones or sync
noise. The contents of the buffer are moved to the PCM player by the FDMA. The quad
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frequency synthesizer provides the PCM and the S/PDIF clocks.
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Package mechanical data STi5189
7 Package mechanical data
7.1 15 mm x 15 mm package
The following table gives the values of the dimensions marked in Figure 9:
Table 2. LFBGA 15 mm x 15 mm package dimensions

Millimeters Inches
Dimensions Notes
Minimum Typical Maximum Minimum Typical Maximum
(1)
A 1.70 0.06698
A1 0.21 0.00827399
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A2 1.085 0.0428
A3 0.30 0.0118
A4 0.80 0.0315
(2)
b 0.35 0.40 0.45 0.0137899 0.0158 0.0177
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D 14.85 15.00 15.15 0.58509 0.591 0.5969
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D1 13.60 0.5358
E 14.85 15.00 15.15 0.58509 0.591 0.5969
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E1 13.60 0.5358
e 0.80 0.0315
F 0.70 0.0276
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ddd 0.10 0.0039

(3)
eee 0.15 0.0059
(4)
fff 0.08 0.0032
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1. LFBGA stands for Low profile Fine Pitch Ball Grid Array.
- Low profile: 1.20 mm < A = 1.70 mm/Fine pitch: e < 1.00 mm pitch.
-The total profile height (Dim A) is measured from the seating plane to the top of the component
-The maximum total package height is calculated by the following methodology:
A Max = A2 Typ+A1 Typ + V (A1²+A3²+A4² tolerance values)
2. The typical ball diameter before mounting is 0.40 mm.
3. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B. For each ball,
there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position with respect to datums A
and B as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone.
4. The tolerance of position that controls the location of the balls within the matrix with respect to each other. For each ball,
there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position as defined by e. The axis
perpendicular to datum C of each ball must lie within this tolerance zone. Each tolerance zone fff in the array is contained
entirely in the respective zone eee above. The axis of each ball must lie simultaneously in both tolerance zones.
5. The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metalized markings, or other
feature of package body or integral heatslug.
A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1 corner. Exact shape of
each corner is optional.
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STi5189 Package mechanical data
Figure 9. LFBGA 15 mm x 15 mm pitch 0.8 (bottom view)
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Package mechanical data STi5189
7.2 23 mm x 23 mm package
The following table gives the values of the dimensions marked in Figure 10:
Table 3. PBGA 23 mm x 23 mm package dimensions

Millimeters Inches
Dimensions Notes
Minimum Typical Maximum Minimum Typical Maximum
(1)
A 1.70 0.06698
A1 0.20 0.00788
A2 1.305 0.05138
A3 0.52 0.02047
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A4 0.785 0.030905
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b 0.40 0.50 0.60 0.01576 0.0197 0.0237
D 22.80 23.00 23.20 0.89764 0.905509 0.913383
D1 20.80 0.818895
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D2 19.30 19.50 19.70 0.7598401 0.7677141 0.775588
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E 22.80 23.00 23.20 0.89764 0.905509 0.913383

E1 20.80 0.818895
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E2 19.30 19.50 19.70 0.7598401 0.7677141 0.775588

e 0.80 0.03152
F 1.10 0.043340
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ddd 0.20 0.00788

(2)
eee 0.25 0.00985
(3) (4)
fff 0.10 0.00394
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1. PBGA stands for Low Plastic Ball Grid Array.

2. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B. For each ball,
there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position with respect to datums A
and B as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone.
3. The tolerance of position that controls the location of the balls within the matrix with respect to each other. For each ball,
there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position as defined by e. The axis
perpendicular to datum C of each ball must lie within this tolerance zone. Each tolerance zone fff in the array is contained
entirely in the respective zone eee above. The axis of each ball must lie simultaneously in both tolerance zones.
4. The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metalized markings, or other
feature of package body or integral heatslug.
A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1 corner. Exact shape of
each corner is optional.
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STi5189 Package mechanical data
Figure 10. PBGA 23x23 pitch 0.8 (bottom view)
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7.3 Environmentally friendly packages

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Doc ID 8141465 Rev 5 35/294

BGA footprint and ball list STi5189
8 BGA footprint and ball list
8.1 Ball grid array

The ball grid array (BGA) diagrams give the allocation of pins to the package, shown from
the top looking down using the PCB footprint.
Signal names are prefixed by NOT if they are active low; otherwise they are active high.
In the ball grid array (BGA) diagram, grey indicates that the ball is reserved and must not be
used.
Table 4. Key to BGA diagram
Function Type Key
l
Transport and Demodulator SIG
tia
PIO/peripheral SIG
Video SIG
Audio SIG
en
System (JTAG, interrupts) SIG
Confidential
Memory (FMI, LMI) SIG

Power VCC/VDD
fid
Ground VSS/GND
Do not connect(1) DNC
No ball -
on
1. DNC: There is no internal connection to these balls. Routing is NOT allowed over these balls.
C
36/294 Doc ID 8141465 Rev 5

STi5189 BGA footprint and ball list
8.2 15 x 15 package
Table 5. Ballout - Left-half

1 2 3 4 5 6 7 8 9
A PIO1[7] LMIADDR[4] LMIADDR[5] LMIDATA[13]
NOT_LMICLK
B PIO3[1] PIO1[6] LMIADDR[6] LMIADDR[7]
OUT
LMIDATA[14]
C VDD33_25 VDD33_25 VDD33_25 VDD33_25 LMIADDR[9] LMIADDR[12] LMICLKOUT LMIDATA[15] LMIDATA[11]
D VDD33 VDD33 VDD33 VDD33 LMIADDR[8] LMIADDR[11] GND GND LMIDATA[12]
l
VCCA2V5_DA VCCA2V5_DA
E
tia
VDD33 VDD33 LMICLKEN GND GND GND
CS CS
MASS_QUIET[
F REXT[35]
35]
IDUMPX
en
G VOUT XOUT UOUT GND GND GND
Confidential
MASS_QUIET[
H REXT[10] WOUT
10]
IDUMPUVW GND GND GND
fid
GNDA2V5_DA
J ADAC_AOL ADAC_VBG ADAC_AOR ADAC_VSSAH
CS
GND GND GND
GNDA2V5_DA
K ADAC_VCCAH PIO2[3]
CS
GND GND GND
on
TS0OUTERR
L OR
TS0INDATA[3] PIO2[4] PIO3[5] PIO3[6] GND GND GND
TS0OUTDATA[ TS0OUTDATA[
M 7] 6]
TS0INDATA[2] GND GND GND GND
C
TS0OUTBITO
TS0OUTDATA[ TS0OUTDATA[
N 4] 5]
RBYTECLKVA
LID
TS0OUTDATA[
P TS0INDATA[1] TS0INDATA[4]
2]
USB_DATA[3] VDD1V0 VDD1V0
TS0OUTDATA[
R 3]
TS0INDATA[5] TS0INDATA[0] USB_DIR USB_DATA[1] USB_DATA[4] USB_DATA[7] SPI_NOTCS
TS0OUTBITO TS0INBITORB
T TS0INDATA[6]
RBYTECLK
TS0INDATA[7]
YTECLK
USB_DATA[0] USB_DATA[2] USB_CLK USB_DATA[5] SPI_CLK
TS0OUTPACK TS0OUTDATA[ TS0INBITORB

U ETCLK 1] YTECLKVALID
USB_STP USB_NXT USB_DATA[6] SPI_DATAIN
TS0OUTDATA[ TS0INPACKET RESETEXTOU

V 0]
TS0INERROR
CLK T
SPI_DATAOUT
1 2 3 4 5 6 7 8 9
Doc ID 8141465 Rev 5 37/294

Table 6. Ballout - Right-half

10 11 12 13 14 15 16 17 18
LMIDATA[8] LMIDATA[0] NOT_LMICAS NOT_LMICS LMIBA[1] A
LMIDQS[1] LMIVREF LMIDATA[3] LMIDATA[1] NOT_LMIRAS LMIBA[0] LMIADDR[10] B
LMIRDNOTW
LMIDATA[9] LMIDQM[1] LMIDQS[0] LMIDATA[6] LMIDATA[4]
R
LMIADDR[0] LMIADDR[2] LMIADDR[1] C
LMIDATA[10] REXT_LMI LMIDQM[0] LMIDATA[7] LMIDATA[2] LMIADDR[3] PIO4[6] PIO4[7] D
GND GND GND LMIDATA[5] PIO4[3] PIO4[5] PIO4[4] E
l
CEC PIO4[1] PIO4[2] F
tia
GND GND GND PIO3[2] PIO3[3] PIO4[0] PIO3[7] G
en
GND GND GND PIO3[4] SPDIF PIO0[4] PIO0[6] PIO0[5] H
Confidential
GND GND GND PIO0[3] PIO0[7] J

fid
GND GND GND PIO1[1] PIO1[2] PIO0[1] PIO0[0] PIO0[2] K
GND GND GND GNDA2V5_BE PIO1[4] PIO1[5] PIO1[3] L

on
GND GND GNDA1V0_FE NOTASEBRK NOT_RESET AUXCLKOUT M
GNDA2V5_FE PIO2[1] PIO2[0] N

C
VDD1V0 VDD1V0 VDDA2V5_BE QPSK_AGC PIO1[0] PIO2[5] PIO2[2] P
VDD1V0 VDD1V0 VBASE DISEQCOUT VCCA2V5_FE QPSK_DAC PIO3[0] PIO2[6] PIO2[7] R
VDD1V0 VDD1V0 QPSK_SCLT DISEQCIN VCCA2V5_FE QP TMS NOT_TRST TCK T
VDD10REG QPSK_SDAT QM IM XTALI TDI U
VDDA1V0_FE IP XTALO TDO V
10 11 12 13 14 15 16 17 18
38/294 Doc ID 8141465 Rev 5

Confidential
8.3 23 x 23 package
39/294
BGA footprint and ball list

Table 7. Ballout - Top-left
1 2 3 4 5 6 7 8 9 10 11 12 13 14
VCCA2V5_ VCCA2V5_ MASS_QUI LMIADDR[6 LMIADDR[8

A DACS DACS ET[10] ] ]
B
VCCA2V5_
DACS
VCCA2V5_
DACS
REXT[10]
IDUMPUV
W
C VDD33_25
LMIADDR[5 LMIADDR[9 LMIADDR[1
] ] 2]
C VOUT XOUT
VCCA2V5_
DACS
IDUMPX REXT[35]
on VDD33 VDD33_25
LMIADDR[4 LMIADDR[1
] 1]
LMICLKEN
NOT_LMIC
LKOUT
D WOUT ADAC_VBG UOUT

VCCA2V5_
DACS
MASS_QUI
ET[35]
fid
PIO1[6] VDD33 VDD33 VDD33_25
LMIADDR[7
]
LMICLKOU
T
LMIDATA[1
5]
LMIDATA[1
4]
Doc ID 8141465 Rev 5
ADAC_VSS LMIDATA[1
en
E ADAC_AOR ADAC_AOL PIO3[1] PIO1[7] VDD33 VDD33 VDD33_25 GND
AH 3]
ADAC_VCC
F PIO2[4] PIO2[3] GND VDD33 VDD33 VDD33_25 GND
AH
G PIO3[5] PIO3[6] GND

tia VDD33 VDD33 VDD33_25 GND
J
TS0INDATA TS0OUTER
[3]
TS0OUTDA TS0OUTDA
ROR
TS0INDATA
GND
GNDA2V5_
l
GNDA2V5_
DACS
GNDA2V5_
VDD33
GND GND
GND
GND
GND
GND GND
TA[6] TA[7] [2] DACS DACS
TS0OUTBI
TS0OUTDA TS0OUTDA GNDA2V5_
K TORBYTEC GND GND GND GND GND GND GND
TA[4] TA[5] DACS
LKVALID
TS0INDATA TS0INDATA TS0OUTDA TS0INDATA

L GND GND GND GND GND GND GND GND
[4] [5] TA[3] [1]
TS0OUTBI
TS0OUTDA TS0INDATA
M TORBYTEC GND GND GND GND GND GND GND
TA[2] [6]
LK
TS0INDATA TS0OUTPA
STi5189
N GND GND GND GND GND GND GND GND
[7] CKETCLK
Confidential
STi5189
Table 8. Ballout - Top-right
15 16 17 18 19 20 21 22 23 24 25 26 27
LMIVREF LMIDQM[0] LMIADDR[0] LMIADDR[2] GND GND A
LMIADDR[1
LMIDATA[8] REXT_LMI LMIDQS[0] LMIDATA[6] LMIBA[0] LMIADDR[3] GND GND B
0]
LMIDATA[11] LMIDATA[9] LMIDQS[1] LMIDATA[7]

C
LMIDATA[5] LMIDATA[3]
NOT_LMICA
S
NOT_LMICS LMIADDR[1] PIO4[7] PIO4[5] PIO4[6] C
LMIDATA[12] LMIDATA[10] LMIDQM[1] LMIDATA[4] on

LMIDATA[2] LMIDATA[0]
LMIRDNOT
WR
LMIBA[1] PIO4[4] PIO4[2] PIO4[3] D
GND GND
fid
GND LMIDATA[1]
NOT_LMIRA
S
PIO4[1] PIO3[7] PIO4[0] E
en
GND GND GND GND GND CEC PIO3[2] F
GND GND GND GND PIO3[3] PIO3[4] G
GND GND GND tia GND SPDIF PIO0[6] PIO0[5] H
GND
GND GND
GND
GND
GND
GND
GND
GND
GND
l GND
GND
GND
PIO0[4] PIO0[7]
PIO0[1]
PIO0[3]
PIO0[2] PIO0[0]
J

GND GND GND GND GND GND GND PIO1[1] PIO1[4] PIO1[3] PIO1[2] L
AUXCLKOU NOT_RESE
GND GND GND GND GND PIO1[5] M
T T
NOTASEBR
GND GND GND GND GND GND GND PIO2[0] N
K
40/294
Confidential
41/294

Table 9. Ballout - Bottom-left
TS0OUTDA TS0OUTDA
P GND GND GND GND GND GND GND
TA[0] TA[1]
TS0INERR TS0INDATA
R GND GND GND GND GND GND GND GND
OR [0]
TS0INBITO
TS0INBITO TS0INPAC
C
T RBYTECLK GND GND GND GND GND GND GND
RBYTECLK KETCLK
VALID
V
CSn[3]
RBn[2]
CSn[2]
RBn[3]
CSn[1]
NOT_FMIC
RBn[1]
GND
on GND
GND
GND GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
fid
SB
NOT_FMIC NOT_FMIC FMIADDR[

W GND GND GND GND GND GND GND
SC SD 23]
Y
FMIADDR[
21]
FMIADDR[
22]
FMIADDR[
5] en GND GND GND GND
AA
FMIADDR[
3]
FMIADDR[
FMIADDR[
7]
FMIADDR[
GND
tia GND GND GND GND
l
AB GND GND GND GND GND
20] 17]
FMIADDR[ FMIADDR[ NOT_FMIC NOT_FMIB NOT_FMIO NAND_WAI

AC GND GND GND
8] 6] SA E[1] E T
FMIADDR[ FMIADDR[ FMIADDR[ FMIADDR[ FMIADDR[ NOT_FMIB FMIDATA[1 FMIFLASH NOT_FMIB

AD FMIDATA[3] FMIDATA[9] FMIDATA[8]
4] 18] 19] 2] 1] E[0] 4] CLK AA
NOT_FMIL FMIRDNOT FMIADDR[ FMIADDR[ FMIADDR[ FMIDATA[1 FMIDATA[1 FMIDATA[1 FMIDATA[1

AE FMIWAIT FMIDATA[7] FMIDATA[0]
BA WR 14] 12] 16] 5] 2] 1] 0]
FMIADDR[ FMIADDR[ FMIADDR[ FMIDATA[1

AF VDD33 VDD33 FMIDATA[6] FMIDATA[4] FMIDATA[1]
10] 13] 15] 3]
FMIADDR[ FMIADDR[
AG VDD33 VDD33 FMIDATA[5] FMIDATA[2]
9] 11]
STi5189
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Confidential
STi5189
Table 10. Ballout - Bottom-right
GND GND GND GND GND GND PIO2[5] PIO2[1] P
GND GND GND GND GND GND GND PIO2[2] PIO1[0] R
GNDA2V5_
GND GND GND GND GND PIO2[6] PIO2[7] PIO3[0] T
C
PLL_FS_BE
GNDA2V5_ GNDA2V5_
on
GND GND GND GND GND TMS TCK NOT_TRST TDI U
PLL_FS_BE PLL_FS_BE
GNDA2V5_ VCCA2V5_P VCCA2V5_P VCCA2V5_P

GND GND GND GND GND TDO V
PLL_FS_BE LL_FS_BE LL_FS_BE LL_FS_BE
GND GND GND GND fid

VDD1V0 VDD1V0 VDD1V0 VDD1V0 VDD1V0 W
GND GND VDD10REG

en VDD1V0 VDD1V0 VDD1V0 VDD1V0 Y
tia
GNDA1V0_F GNDA1V0_F VDDA1V0_F
GND GND VBASE AA
E E E
GNDA1V0_F GNDA1V0_F VCCA2V5_F VCCA2V5_F

GND GND GND GND AB
l
E E E E
QPSK_SDA VCCA2V5_F GNDA2V5_F GNDA2V5_F

GND GND GND QPSK_AGC AC
T E E E
RESETEXT SPI_DATAO DISEQCOU GNDA2V5_F GNDA2V5_F

USB_DIR USB_CLK SPI_NOTCS QPSK_SCLT QPSK_DAC XTALO AD
OUT UT T E E

USB_DATA[ USB_DATA[
USB_STP USB_NXT SPI_DATAIN SPI_CLK QM DISEQCIN GND XTALI AE
1] 6]
USB_DATA[ USB_DATA[ USB_DATA[ USB_DATA[

QP IM GND GND AF
0] 2] 5] 7]
USB_DATA[ USB_DATA[
IP GND GND AG
3] 4]
15 16 17 18 19 20 21 22 23 24 25 26 27
42/294
8.4 Ball list sorted by ball number
Table 11. Ball list

Ball Signal name (15 x 15 mm package) Signal name (23 x 23 mm package)
A1 PIO1[7] VCCA2V5_DACS
A2 LMIADDR[4] VCCA2V5_DACS
A3 LMIADDR[5] MASS_QUIET[10]
A8 LMIDATA[13] -
A10 LMIDATA[8] LMIADDR[6]
A11 - LMIADDR[8]
A15 LMIDATA[0] -
l
tia
A16 NOT_LMICAS -
A17 NOT_LMICS LMIVREF
A18 LMIBA[1] LMIDQM[0]
en
A24 - LMIADDR[0]
A25 - LMIADDR[2]
Confidential
A26 - GND
A27 - GND
fid
B1 PIO3[1] VCCA2V5_DACS
B2 PIO1[6] VCCA2V5_DACS
B3 LMIADDR[6] REXT[10]
on
B4 LMIADDR[7] IDUMPUVW
B7 NOT_LMICLKOUT -
B8 LMIDATA[14] -
C
B9 - VDD33_25
B10 LMIDQS[1] LMIADDR[5]
B11 LMIVREF LMIADDR[9]
B12 - LMIADDR[12]
B14 LMIDATA[3] -
B15 LMIDATA[1] -
B16 NOT_LMIRAS LMIDATA[8]
B17 LMIBA[0] REXT_LMI
B18 LMIADDR[10] LMIDQS[0]
B19 - LMIDATA[6]
B23 - LMIBA[0]
B24 - LMIADDR[10]
B25 - LMIADDR[3]
Doc ID 8141465 Rev 5 43/294

Table 11. Ball list (continued)

B26 - GND
B27 - GND
C1 VDD33_25 VOUT
C2 VDD33_25 XOUT
C3 VDD33_25 VCCA2V5_DACS
C4 VDD33_25 IDUMPX
C5 LMIADDR[9] REXT[35]
C6 LMIADDR[12] -
C7 LMICLKOUT -
l
tia
C8 LMIDATA[15] VDD33
C9 LMIDATA[11] VDD33_25
C10 LMIDATA[9] LMIADDR[4]
en
C11 LMIDQM[1] LMIADDR[11]
C12 LMIDQS[0] LMICLKEN
Confidential
C13 LMIDATA[6] NOT_LMICLKOUT

fid
C14 LMIDATA[4] -
C15 LMIRDNOTWR LMIDATA[11]
C16 LMIADDR[0] LMIDATA[9]
C17 LMIADDR[2] LMIDQS[1]
on
C18 LMIADDR[1] LMIDATA[7]

C19 - LMIDATA[5]
C20 - LMIDATA[3]
C
C22 - NOT_LMICAS
C23 - NOT_LMICS
C24 - LMIADDR[1]
C25 - PIO4[7]
C26 - PIO4[5]
C27 - PIO4[6]
D1 VDD33 WOUT
D2 VDD33 ADAC_VBG
D3 VDD33 UOUT
D4 VDD33 VCCA2V5_DACS
D5 LMIADDR[8] MASS_QUIET[35]
D6 LMIADDR[11] PIO1[6]
D7 GND VDD33
44/294 Doc ID 8141465 Rev 5


D8 GND VDD33
D9 LMIDATA[12] VDD33_25
D10 LMIDATA[10] -
D11 REXT_LMI LMIADDR[7]
D12 LMIDQM[0] LMICLKOUT
D13 LMIDATA[7] LMIDATA[15]
D14 LMIDATA[2] LMIDATA[14]
D15 LMIADDR[3] LMIDATA[12]
D16 PIO4[6] LMIDATA[10]
l
tia
D17 PIO4[7] LMIDQM[1]
D19 - LMIDATA[4]
D20 - LMIDATA[2]
en
D21 - LMIDATA[0]
D22 - LMIRDNOTWR
Confidential
D23 - LMIBA[1]
fid
D24 - PIO4[4]
D25 - PIO4[2]
D26 - PIO4[3]
E2 VCCA2V5_DACS ADAC_VSSAH
on
E3 VCCA2V5_DACS ADAC_AOR
E4 VDD33 ADAC_AOL
E5 VDD33 PIO3[1]
C
E6 LMICLKEN PIO1[7]
E7 GND VDD33
E8 GND VDD33
E9 GND -
E10 GND VDD33_25
E11 GND -
E12 GND GND
E13 LMIDATA[5] -
E14 PIO4[3] LMIDATA[13]
E15 PIO4[5] -
E16 PIO4[4] GND
E18 - GND
E20 - GND
Doc ID 8141465 Rev 5 45/294


E21 - LMIDATA[1]
E22 - NOT_LMIRAS
E23 - PIO4[1]
E24 - PIO3[7]
E25 - PIO4[0]
F3 REXT[35] PIO2[4]
F4 MASS_QUIET[35] PIO2[3]
F5 IDUMPX ADAC_VCCAH
F6 - GND
l
tia
F7 - VDD33
F9 - VDD33
F11 - VDD33_25
en
F13 - GND
F14 CEC -
Confidential
F15 PIO4[1] GND

fid
F16 PIO4[2] -
F17 - GND
F19 - GND
F21 - GND
on
F22 - GND
F23 - CEC
F24 - PIO3[2]
C
G3 VOUT -
G4 XOUT PIO3[5]
G5 UOUT PIO3[6]
G6 - GND
G7 GND -
G8 GND VDD33
G9 GND -
G10 GND VDD33
G11 GND -
G12 GND VDD33_25
G14 PIO3[2] GND
G15 PIO3[3] -
G16 PIO4[0] GND
46/294 Doc ID 8141465 Rev 5


G17 PIO3[7] -
G18 - GND
G20 - GND
G22 - GND
G23 - PIO3[3]
G24 - PIO3[4]
H2 REXT[10] -
H3 WOUT TS0INDATA[3]
H4 MASS_QUIET[10] TS0OUTERROR
l
tia
H5 IDUMPUVW GND
H7 GND GNDA2V5_DACS
H8 GND -
en
H9 GND VDD33
H10 GND -
Confidential
H11 GND GND

fid
H12 GND -
H13 - GND
H14 PIO3[4] -
H15 SPDIF GND
on
H16 PIO0[4] -
H17 PIO0[6] GND
H18 PIO0[5] -
C
H19 - GND
H21 - GND
H23 - SPDIF
H24 - PIO0[6]
H25 - PIO0[5]
J1 ADAC_AOL -
J2 ADAC_VBG TS0OUTDATA[6]
J3 ADAC_AOR TS0OUTDATA[7]
J4 ADAC_VSSAH TS0INDATA[2]
J5 GNDA2V5_DACS -
J6 - GNDA2V5_DACS
J7 GND -
J8 GND GNDA2V5_DACS
Doc ID 8141465 Rev 5 47/294


J9 GND GND
J10 GND GND
J11 GND GND
J12 GND -
J13 - GND
J14 DNC GND
J15 PIO0[3] GND
J16 PIO0[7] -
J17 - GND
l
tia
J18 - GND
J19 - GND
J20 - GND
en
J22 - GND
J24 - PIO0[4]
Confidential
J25 - PIO0[7]
fid
J26 - PIO0[3]
K1 - TS0OUTBITORBYTECLKVALID
K2 - TS0OUTDATA[4]
K3 ADAC_VCCAH TS0OUTDATA[5]
on
K4 PIO2[3] -
K5 GNDA2V5_DACS GND
K7 GND GNDA2V5_DACS
C
K8 GND -
K9 GND GND
K10 GND GND
K11 GND GND
K12 GND GND
K13 - GND
K14 PIO1[1] GND
K15 PIO1[2] GND
K16 PIO0[1] GND
K17 PIO0[0] GND
K18 PIO0[2] GND
K19 - GND
K21 - GND
48/294 Doc ID 8141465 Rev 5


K23 - GND
K25 - PIO0[1]
K26 - PIO0[2]
K27 - PIO0[0]
L1 TS0OUTERROR TS0INDATA[4]
L2 TS0INDATA[3] TS0INDATA[5]
L3 PIO2[4] TS0OUTDATA[3]
L4 PIO3[5] TS0INDATA[1]
L5 PIO3[6] -
l
tia
L6 - GND
L7 GND -
L8 GND GND
en
L9 GND GND
L10 GND GND
Confidential
L11 GND GND

fid
L12 GND GND

L13 - GND
L14 GNDA2V5_BE GND
L15 PIO1[4] GND
on
L16 PIO1[5] GND

L17 PIO1[3] GND
L18 - GND
C
L19 - GND
L20 - GND
L22 - GND
L24 - PIO1[1]
L25 - PIO1[4]
L26 - PIO1[3]
L27 - PIO1[2]
M2 TS0OUTDATA[7] TS0OUTDATA[2]
M3 TS0OUTDATA[6] TS0OUTBITORBYTECLK
M4 TS0INDATA[2] TS0INDATA[6]
M5 GND GND
M7 GND GND
M8 GND -
Doc ID 8141465 Rev 5 49/294


M9 GND -
M10 GND GND
M11 GND GND
M12 GNDA1V0_FE GND
M13 - GND
M14 NOTASEBRK GND
M15 NOT_RESET GND
M16 AUXCLKOUT GND
M17 - GND
l
tia
M18 - GND
M19 - -
M21 - GND
en
M23 - DNC
M24 - AUXCLKOUT
Confidential
M25 - NOT_RESET
fid
M26 - PIO1[5]
N3 TS0OUTDATA[4] TS0INDATA[7]
N4 TS0OUTDATA[5] TS0OUTPACKETCLK
N5 TS0OUTBITORBYTECLKVALID -
on
N6 - GND
N8 - GND
N9 - GND
C
N10 - GND
N11 - GND
N12 - GND
N13 - GND
N14 GNDA2V5_FE GND
N15 PIO2[1] GND
N16 PIO2[0] GND
N17 - GND
N18 - GND
N19 - GND
N20 - GND
N22 - GND
N24 - PIO2[0]
50/294 Doc ID 8141465 Rev 5


N25 - NOTASEBRK
P3 TS0INDATA[1] -
P4 TS0INDATA[4] TS0OUTDATA[0]
P5 TS0OUTDATA[2] TS0OUTDATA[1]
P6 DNC -
P7 USB_DATA[3] GND
P8 VDD1V0 -
P9 VDD1V0 GND
P10 VDD1V0 GND
l
tia
P11 VDD1V0 GND
P12 DNC GND
P13 VDDA2V5_BE GND
en
P14 QPSK_AGC GND
P15 PIO1[0] GND
Confidential
P16 PIO2[5] GND

fid
P17 PIO2[2] GND

P18 - GND
P19 - GND
P21 - GND
on
P23 - PIO2[5]
P24 - PIO2[1]
R2 TS0OUTDATA[3] -
C
R3 TS0INDATA[5] TS0INERROR
R4 TS0INDATA[0] TS0INDATA[0]
R5 USB_DIR -
R6 USB_DATA[1] GND
R7 USB_DATA[4] -
R8 USB_DATA[7] GND
R9 SPI_NOTCS GND
R10 VDD1V0 GND
R11 VDD1V0 GND
R12 VBASE GND
R13 DISEQCOUT GND
R14 VCCA2V5_FE GND
R15 QPSK_DAC GND
Doc ID 8141465 Rev 5 51/294


R16 PIO3[0] GND

R17 PIO2[6] GND
R18 PIO2[7] GND
R19 - GND
R20 - GND
R22 - GND
R24 - PIO2[2]
R25 - PIO1[0]
T1 TS0INDATA[6] -
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T2 TS0OUTBITORBYTECLK TS0INBITORBYTECLK
T3 TS0INDATA[7] TS0INPACKETCLK
T4 TS0INBITORBYTECLK TS0INBITORBYTECLKVALID
en
T5 USB_DATA[0] GND
T6 USB_DATA[2] -
Confidential
T7 USB_CLK GND
fid
T8 USB_DATA[5] -
T9 SPI_CLK -
T10 VDD1V0 GND
T11 VDD1V0 GND
on
T12 QPSK_SCLT GND

T13 DISEQCIN GND
T14 VCCA2V5_FE GND
C
T15 QP GND
T16 TMS GND
T17 NOT_TRST GND
T18 TCK GND
T19 - -
T21 - GNDA2V5_PLL_FS_BE
T23 - GND
T24 - PIO2[6]
T25 - PIO2[7]
T26 - PIO3[0]
U1 TS0OUTPACKETCLK CSn[3]
U2 TS0OUTDATA[1] CSn[2]
U3 TS0INBITORBYTECLKVALID CSn[1]
52/294 Doc ID 8141465 Rev 5


U4 USB_STP RBn[1]
U5 USB_NXT -
U6 - GND
U8 USB_DATA[6] GND
U9 SPI_DATAIN GND
U10 - GND
U11 VDD10REG GND
U12 QPSK_SDAT GND
U13 - GND
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U14 - GND
U15 QM GND
U16 IM GND
en
U17 XTALI GND
U18 TDI GND
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U19 - GND
fid
U20 - GNDA2V5_PLL_FS_BE
U22 - GNDA2V5_PLL_FS_BE
U24 - TMS
U25 - TCK
on
U26 - NOT_TRST
U27 - TDI
V1 TS0OUTDATA[0] RBn[2]
C
V2 TS0INERROR RBn[3]
V3 TS0INPACKETCLK NOT_FMICSB
V4 RESETEXTOUT -
V5 - GND
V7 - GND
V9 SPI_DATAOUT GND
V10 - GND
V11 VDDA1V0_FE GND
V12 - GND
V13 - GND
V14 - GND
V15 - GND
V16 IP GND
Doc ID 8141465 Rev 5 53/294


V17 XTALO GND

V18 TDO GND
V19 - GND
V21 - GNDA2V5_PLL_FS_BE
V23 - VCCA2V5_PLL_FS_BE
V27 - TDO
W2 - NOT_FMICSC
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W3 NOT_FMICSD
W4 - FMIADDR[23]
W6 - GND
en
W8 - GND
W9 - GND
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W10 - GND
fid
W11 - GND
W12 - -
W13 - GND
W14 - GND
on
W15 - GND
W16 - -
W17 - GND
C
W18 - GND
W19 - GND
W20 - VDD1V0
W22 - VDD1V0
W24 - VDD1V0
W25 - VDD1V0
W26 - VDD1V0
Y3 - FMIADDR[21]
Y4 - FMIADDR[22]
Y5 - FMIADDR[5]
Y7 - GND
Y9 - GND
Y11 - GND
54/294 Doc ID 8141465 Rev 5


Y13 - GND
Y15 - GND
Y17 - GND
Y19 - VDD10REG
Y21 - VDD1V0
Y23 - VDD1V0
Y24 - VDD1V0
Y25 - VDD1V0
AA4 - FMIADDR[3]
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AA5 - FMIADDR[7]
AA6 - GND
AA8 - GND
en
AA10 - GND
AA12 - GND
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AA14 - GND
fid
AA16 - GND
AA18 - GND
AA20 - VBASE
AA22 - GNDA1V0_FE
on
AA23 - GNDA1V0_FE
AA24 - VDDA1V0_FE
AB4 - FMIADDR[20]
C
AB5 - FMIADDR[17]
AB6 - GND
AB7 - GND
AB9 - GND
AB11 - GND
AB13 - GND
AB15 - GND
AB17 - GND
AB19 - GND
AB21 - GND
AB22 - GNDA1V0_FE
AB23 - GNDA1V0_FE
AB24 - VCCA2V5_FE
Doc ID 8141465 Rev 5 55/294


AB25 - VCCA2V5_FE
AC3 - FMIADDR[8]
AC4 - FMIADDR[6]
AC5 - NOT_FMICSA
AC6 - NOT_FMIBE[1]
AC7 - NOT_FMIOE
AC8 - GND
AC10 - GND
AC12 - GND
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AC14 - NAND_WAIT
AC16 - GND
AC18 - GND
en
AC20 - DNC
AC21 - QPSK_SDAT
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AC22 - GND
fid
AC23 - QPSK_AGC
AC24 - VCCA2V5_FE
AC25 - GNDA2V5_FE
AC26 - GNDA2V5_FE
on
AD2 - FMIADDR[4]
AD3 - FMIADDR[18]
AD4 - FMIADDR[19]
C
AD5 - FMIADDR[2]
AD6 - FMIADDR[1]
AD7 - NOT_FMIBE[0]
AD8 - FMIDATA[14]
AD9 - FMIFLASHCLK
AD11 - FMIDATA[3]
AD12 - FMIDATA[9]
AD13 - FMIDATA[8]
AD14 - NOT_FMIBAA
AD15 - RESETEXTOUT
AD16 - USB_DIR
AD17 - USB_CLK
AD19 - SPI_DATAOUT
56/294 Doc ID 8141465 Rev 5


AD20 - SPI_NOTCS
AD21 - DISEQCOUT
AD22 - QPSK_SCLT
AD23 - QPSK_DAC
AD24 - DNC
AD25 - GNDA2V5_FE
AD26 - GNDA2V5_FE
AD27 - XTALO
AE1 - NOT_FMILBA
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AE2 - FMIWAIT
AE3 - FMIRDNOTWR
AE4 - FMIADDR[14]
en
AE5 - FMIADDR[12]
AE6 - FMIADDR[16]
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AE8 - FMIDATA[7]
fid
AE9 - FMIDATA[15]
AE10 - FMIDATA[12]
AE11 - FMIDATA[11]
AE12 - FMIDATA[10]
on
AE13 - FMIDATA[0]
AE15 - USB_STP
AE16 - USB_NXT
C
AE17 - USB_DATA[1]
AE18 - USB_DATA[6]
AE19 - SPI_DATAIN
AE20 - SPI_CLK
AE23 - DNC
AE24 - QM
AE25 - DISEQCIN
AE26 - GND
AE27 - XTALI
AF1 - VDD33
AF2 - VDD33
AF3 - FMIADDR[10]
AF4 - FMIADDR[13]
Doc ID 8141465 Rev 5 57/294


AF5 - FMIADDR[15]
AF9 - FMIDATA[6]
AF10 - FMIDATA[13]
AF11 - FMIDATA[4]
AF12 - FMIDATA[1]
AF16 - USB_DATA[0]
AF17 - USB_DATA[2]
AF18 - USB_DATA[5]
AF19 - USB_DATA[7]
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AF24 - QP
AF25 - IM
AF26 - GND
en
AF27 - GND
AG1 - VDD33
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AG2 - VDD33
fid
AG3 - FMIADDR[9]
AG4 - FMIADDR[11]
AG10 - FMIDATA[5]
AG11 - FMIDATA[2]
on
AG17 - USB_DATA[3]
AG18 - USB_DATA[4]
AG25 - IP
C
AG26 - GND
AG27 - GND
58/294 Doc ID 8141465 Rev 5

STi5189 Connections
9 Connections
9.1 Power supply

Table 12. Power supply
Ball (15 mm x 15 mm Ball (23 mm x 23 mm
Signal name Description
package) package)
VDD33_25 LMI supply, 2V5/3V3 C1, C2, C3, C4 B9, C9, D9, E10, F11, G12
AF1, AF2, AG1, AG2, C8, D7,
VDD33 3V3 I/O supply D1, D2, D3, D4, E4, E5 D8, E7, E8, F7, F9, G8, G10,
H9
A26, A27, B26, B27, E12, E16,
l
E18, E20, F6, F13, F15, F17,
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F19, F21, F22, G6, G14, G16,
G18, G20, G22, H5, H11, H13,
H15, H17, H19, H21, J9, J10,
J11, J13, J14, J15, J17, J18,
en
J19, J20, J22, K5, K9, K10,
K11, K12, K13, K14, K15, K16,
K17, K18, K19, K21, K23, L6,
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L8, L9, L10, L11, L12, L13, L14,

L15, L16, L17, L18, L19, L20,
fid
L22, M5, M7, M10, M11, M12,

M13, M14, M15, M16, M17,
M18, M21, N6, N8, N9, N10,
N11, N12, N13, N14, N15, N16,
D7, D8, E7, E8, E9, E10,
N17, N18, N19, N20, N22, P7,
E11, E12, G7, G8, G9, G10,
on
P9, P10, P11, P12, P13, P14,

G11, G12, H7, H8, H9, H10,
P15, P16, P17, P18, P19, P21,
Ground (GND and H11, H12, J7, J8, J9, J10,
GND R6, R8, R9, R10, R11, R12,
GNDE) J11, J12, K7, K8, K9, K10,
R13, R14, R15, R16, R17, R18,
K11, K12, L7, L8, L9, L10,
R19, R20, R22, T5, T7, T10,
L11, L12, M5, M7, M8, M9,
C
T11, T12, T13, T14, T15, T16,

M10, M11
T17, T18, T23, U6, U8, U9,
U10, U11, U12, U13, U14, U15,
U16, U17, U18, U19, V5, V7,
V9, V10, V11, V12, V13, V14,
V15, V16, V17, V18, V19, W6,
W8, W9, W10, W11, W13,
W14, W15, W17, W18, W19,
Y7, Y9, Y11, Y13, Y15, Y17,
AA6, AA8, AA10, AA12, AA14,
AA16, AA18, AB6, AB7, AB9,
AB11, AB13, AB15, AB17,
AB19, AB21, AC8, AC10,
AC12, AC16, AC18, AC22,
AE26, AF26, AF27, AG26,
AG27
Common ground for
GNDA1V0_FE AD12, FEOSC, M12 AA22, AA23, AB22, AB23
FEPLL
Doc ID 8141465 Rev 5 59/294

Connections STi5189
Table 12. Power supply (continued)

Signal name Description
package) package)
Common supply for

VCCA2V5_DACS audio and video E2, E3 A1, A2, B1, B2, C3, D4
DACs
2V5 ANA supply of
VCCA2V5_FE R14, T14 AB24, AB25, AC24
the front-end
Common ground for
GNDA2V5_DACS two video DACs and J5, K5 H7, J6, J8, K7
one audio DAC
1V0 supply for core P8, P9, P10, P11, R10, R11, W20, W22, W24, W25, W26,
VDD1V0
and analog T10, T11 Y21, Y23, Y24, Y25
l
Common supply for
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VDDA1V0_FE AD12, FEOSC, V11 AA24
FEPLL
On-chip voltage
VDD10REG U11 Y19
regulator
en
Ground for the 2.5 V
GNDA2V5_FE supply of the N14 AC25, AC26, AD25, AD26
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front-end
Common supply for
fid
VCCA2V5_PLL_FS_BE AD12, FEOSC, - V25, V26, V23

FEPLL
Common ground for
GNDA2V5_PLL_FS_BE - T21, U20, U22, V21
FS, PLL
on
9.2 System
Some system functions use GPIO pins, which are shared with other functions. For further
C
details, see Table 41.
Table 13. System functions

Ball Ball
Signal name Description I/O Mapping (15 mm x 15 mm (23 mm x 23 mm
package) package)
XTALI 30 MHz crystal oscillator circuit I - U17 AE27

XTALO 30 MHz crystal oscillator circuit O - V17 AD27
AUXCLKOUT Auxiliary clock for general use O - M16 M24
FPRESET Timeout reset I PIO2[7] R18 T25
NOT_RESET Decoder reset input I - M15 M25
VBASE On-chip voltage regulator O - R12 AA20
RESETEXTOUT Chip/watchdog reset output O V4 AD15
DNC Do not connect - - J14 M23
60/294 Doc ID 8141465 Rev 5

STi5189 Connections
9.3 Interrupts
Some interrupt functions use GPIO pins, which are shared with other functions. For further
Table 14. Interrupt functions

Ball Ball
Signal
Description I/O Mapping (15 mm x 15 mm (23 mm x 23 mm
name
package) package)
EXTINT[0] Interrupt from/to external device I/O PIO3[0] (Alt 1) R16 T26
EXTINT[1] Interrupt from/to external device I/O PIO3[4] (Alt 1) H14 G24
EXTINT[2] Interrupt from external device I PIO3[1] B1 E5
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9.4 Demodulator IF interface
Table 15. Demodulator functions
Signal Ball (15 mm x 15 mm Ball (23 mm x 23 mm
en
Description I/O Type
name package) package)
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IM Differential input signal (-) I track I Analog U16 AF25

IP Differential input signal (+) I track I Analog V16 AG25
fid
QM Differential input signal (-) Q track I Analog U15 AE24

QP Differential input signal (+) Q track I Analog T15 AF24
on
9.5 QPSK AGC interface
Table 16. QPSK AGC functions

C

Signal name Description I/O Type
package) package)
QPSK_AGC RF PWM output O Digital P14 AC23

DISEQCIN DiSEqC in I Analog T13 AE25
DISEQCOUT DiSEqC out O Analog R13 AD21
9.6 QPSK DAC interface
Table 17. QPSK tuner functions

package) package)
QPSK_DAC QPSK DAC O Digital R15 AD23
Doc ID 8141465 Rev 5 61/294

Connections STi5189
9.7 QPSK tuner interface
Table 18. QPSK tuner functions

package) package)
QPSK_SCLT QPSK tuner clock output O Digital T12 AD22

QPSK_SDAT QPSK tuner data I/O Digital U12 AC21
9.8 Transport
Some transport functions use GPIO pins, which are shared with other functions. For further
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Table 19. Transport functions
Ball Ball
(15 mm x 15 (23 mm x 23
Signal name Description Dir Type
en
mm mm
package) package)
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TS0INBITORBYTECLK Bit/byte clock I Digital Schmitt T4 T2

TS0INBITORBYTECLKVALID Bit/byte clock valid I Digital Schmitt U3 T4
fid
TS0INERROR Error I Digital Schmitt V2 R3

TS0INPACKETCLK Packet clock I Digital Schmitt V3 T3
Serial data or parallel
on
TS0INDATA[0] I Digital Schmitt R4 R4

data[0]
Parallel interface input data
TS0INDATA[1] I Digital Schmitt P3 L4
bit for TS0
C
TS0INDATA[2] I Digital Schmitt M4 J4

bit for TS0
TS0INDATA[3] I Digital Schmitt L2 H3
bit for TS0
TS0INDATA[4] I Digital Schmitt P4 L1
bit for TS0
TS0INDATA[5] I Digital Schmitt R3 L2
bit for TS0
TS0INDATA[6] I Digital Schmitt T1 M4
bit for TS0
TS0INDATA[7] I Digital T3 N3
bit for TS0
TS0OUTBITORBYTECLK Bit/byte clock O Digital Schmitt T2 M3
TS0OUTBITORBYTECLKVALID Bit/byte clock valid O Digital Schmitt N5 K1
TS0OUTERROR Error O Digital Schmitt L1 H4
TS0OUTPACKETCLK Packet clock O Digital Schmitt U1 N4
62/294 Doc ID 8141465 Rev 5

STi5189 Connections
Table 19. Transport functions (continued)

Ball Ball
(15 mm x 15 (23 mm x 23
Signal name Description Dir Type
mm mm
package) package)
Parallel interface output

TS0OUTDATA[0] O Digital Schmitt V1 P4
data bit for TS0
TS0OUTDATA[1] O Digital Schmitt U2 P5
data bit for TS0
TS0OUTDATA[2] O Digital Schmitt P5 M2
data bit for TS0
TS0OUTDATA[3] O Digital Schmitt R2 L3
data bit for TS0
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TS0OUTDATA[4] O Digital Schmitt N3 K2
data bit for TS0
TS0OUTDATA[5] O Digital Schmitt N4 K3
data bit for TS0
en
TS0OUTDATA[6] O Digital Schmitt M3 J2
data bit for TS0
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Serial data or parallel

TS0OUTDATA[7] O Digital M2 J3
data[7]
fid
9.9 DMA and FDMA requests

All DMA and FDMA request functions use GPIO pins, which are shared with other functions.
on
For further details, see Table 41.
Table 20. DMA and FDMA request functions

Ball Ball
C

package) package)
DMAREQ[0] DMA request O PIO3[1] (Alt 2) B1 E5

DMAREQ[1] DMA request O PIO3[2] (Alt 2) G14 F24
FDMA_REQ[0] FDMA request I PIO1[0] P15 R25
FDMA_REQ[1] FDMA request I PIO1[1] K14 L24
Doc ID 8141465 Rev 5 63/294

Connections STi5189
9.10 Flexible memory interface (FMI) (23 mm x 23 mm package)

FMI is not available in the 15 mm x 15 mm package version. It is only available in the
23 mm x 23 mm package version.
Table 21. FMI functions

Ball
Signal name Description I/O Drive Type (23 mm x 23 mm
package)
FMIADDR[1] O 4 mA Digital AD6

FMIADDR[3] O 4 mA Digital AA4
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FMIADDR[5] O 4 mA Digital Y5
FMIADDR[6] O 4 mA Digital AC4
FMIADDR[7] O 4 mA Digital AA5
en
FMIADDR[8] O 4 mA Digital AC3
FMIADDR[9] O 4 mA Digital AG3
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FMIADDR[10] O 4 mA Digital AF3

fid
FMIADDR[11] O 4 mA Digital AG4

FMIADDR[12] Address O 4 mA Digital AE5
FMIADDR[14] O 4 mA Digital AE4
on

FMIADDR[16] O 4 mA Digital AE6
FMIADDR[17] O 4 mA Digital AB5
C

FMIADDR[20] O 4 mA Digital AB4
FMIADDR[23] O 4 mA Digital W4
64/294 Doc ID 8141465 Rev 5

STi5189 Connections
Table 21. FMI functions (continued)

Ball
package)
FMIDATA[0] IO 4 mA Digital AE13

FMIDATA[1] IO 4 mA Digital AF12
FMIDATA[2] IO 4 mA Digital AG11
FMIDATA[3] IO 4 mA Digital AD11
FMIDATA[5] IO 4 mA Digital AG10
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Data
en
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fid

FMIFLASHCLK Flash/peripheral clock O 4 mA Digital AD9
on
FMIRDNOTWR Write enable O 4 mA Digital AE3

FMIWAIT Wait (extend read/write I 4 mA Digital AE2
cycle)
NAND_WAIT Ready not busy for first I 4 mA Digital AC14
C
device in the flex mode

NOT_FMIBE[0] Byte enables O 4 mA Digital AD7
NOT_FMIBE[1] Byte enables O 4 mA Digital AC6
NOT_FMICSA Chip select A O 4 mA Digital AC5
NOT_FMICSB Chip select B O 4 mA Digital V3
NOT_FMICSC Chip select C O 4 mA Digital W2
NOT_FMICSD Chip select D O 4 mA Digital W3
NOT_FMILBA Flash device load burst O Digital AE1
4 mA
address
NOT_FMIOE Output enable O 4 mA Digital AC7
NOT_FMIBAA FMI burst address I/O 4 mA Digital AD14
advance
CSn[1] Chip enable for second O 4 mA Digital U3
Doc ID 8141465 Rev 5 65/294

Connections STi5189
Table 21. FMI functions (continued)

Ball
package)
CSn[2] Chip enable for third O 4 mA Digital U2

CSn[3] Chip enable for fourth O 4 mA Digital U1
RBn[1] Ready not busy for second I 4 mA Digital U4
RBn[2] Ready not busy for third I 4 mA Digital V1
RBn[3] Ready not busy for fourth I 4 mA Digital V2
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9.11 tia
Local memory interface (LMI)
en
The LMI supports four memory configurations, 64 Mbits, 128 Mbits, 256 Mbits or 512 Mbits,
organized as 2 Mbytes x 4 banks x 16 bits. The 128 Mbit configuration uses all signals on
Confidential
the interface, with the LMI’s LMIADDR[11:0] pins being directly connected to DDR SDRAM’s
A[11:0]. For 256 Mbits and 512 Mbits configurations, LMIADDR12 is also connected to the
DDR SDRAM’s A12 bit. Only one device can be connected to a board, operating in SSTL
fid
weak mode.
Table 22. LMI functions

on
Ball Ball
(15 mm x 15 (23 mm x 23
Signal name Description I/O Drive Type
mm mm
package) package)
LMIADDR[0] O Programmable Digital C16 A24

C
LMIADDR[1] O Programmable Digital C18 C24

LMIADDR[2] O Programmable Digital C17 A25
LMIADDR[3] O Programmable Digital D15 B25
LMIADDR[4] O Programmable Digital A2 C10
LMIADDR[5] O Programmable Digital A3 B10
LMIADDR[6] Address O Programmable Digital B3 A10
LMIADDR[7] O Programmable Digital B4 D11
LMIADDR[8] O Programmable Digital D5 A11
LMIADDR[9] O Programmable Digital C5 B11
LMIADDR[10] O Programmable Digital B18 B24
LMIADDR[11] O Programmable Digital D6 C11
LMIADDR[12] O Programmable Digital C6 B12
LMIBA[0] LMI bank select O Programmable Digital B17 B23
66/294 Doc ID 8141465 Rev 5

STi5189 Connections
Table 22. LMI functions (continued)

Ball Ball
(15 mm x 15 (23 mm x 23
Signal name Description I/O Drive Type
mm mm
package) package)
LMIBA[1] LMI bank select O Programmable Digital A18 D23

LMICLKEN LMI clock enable O Programmable Digital E6 C12
LMICLKOUT LMI clock O Programmable Digital C7 D12
LMIDQM[0] Data IO mask O Programmable Digital D12 A18
LMIDQM[1] Data IO mask O Programmable Digital C11 D17
LMIDQS[0] Data strobe O Programmable Digital C12 B18
LMIDQS[1] Data strobe O Programmable Digital B10 C17
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ReadNotWrite
LMIRDNOTWR O Programmable Digital C15 D22
enable
Input reference
LMIVREF I - Analog B11 A17
voltage
en
NOT_LMICAS Col address strobe O Programmable Digital A16 C22
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NOT_LMICLKOUT Inverted clock O Programmable Digital B7 C13

NOT_LMICS Chip select O Programmable Digital A17 C23
fid
NOT_LMIRAS Row address strobe O Programmable Digital B16 E22

REXT_LMI I/O - Digital D11 B17
LMIDATA[0] I/O Programmable Digital A15 D21
on
LMIDATA[1] I/O Programmable Digital B15 E21

LMIDATA[2] I/O Programmable Digital D14 D20
LMIDATA[3] I/O Programmable Digital B14 C20
LMIDATA[4] I/O Programmable Digital C14 D19
C
LMIDATA[5] I/O Programmable Digital E13 C19

LMIDATA[6] I/O Programmable Digital C13 B19
LMIDATA[7] I/O Programmable Digital D13 C18
Data
LMIDATA[8] I/O Programmable Digital A10 B16
LMIDATA[9] I/O Programmable Digital C10 C16
LMIDATA[11] I/O Programmable Digital C9 C15
LMIDATA[13] I/O Programmable Digital A8 E14
LMIDATA[14] I/O Programmable Digital B8 D14
LMIDATA[15] I/O Programmable Digital C8 D13
Doc ID 8141465 Rev 5 67/294

Connections STi5189
9.12 Audio
Table 23. Audio functions
Ball Ball
Signal name Description I/O Type (15 mm x 15 mm (23 mm x 23 mm
package) package)
ADAC_AOL Left channel DAC O Analog J1 E4

ADAC_AOR Right channel DAC O Analog J3 E3
ADAC_VBG Audio DAC bandgap output voltage O Analog J2 D2
ADAC_VCCAH 8 V audio DAC O Analog K3 F5
ADAC_VSSAH 8 V audio DAC O Analog J4 E2
SPDIF IEC60958/61937 digital audio output O Digital H15 H23
l
9.13
Table 24.
Video
Video functions
tia
en
Ball Ball
Confidential

package) package)
fid
VOUT Video DAC output O Analog G3 C1

XOUT High drive video DAC output O Analog G4 C2
UOUT Video DAC output O Analog G5 D3
on
WOUT Video DAC output O Analog H3 D1

REXT[35] Video DAC output O Analog F3 C5
REXT[10] Video DAC output O Analog H2 B3
MASS_QUIET[35] Video DAC input I Analog F4 D5
C
IDUMPX Video DAC output O Analog F5 C4

MASS_QUIET[10] Video DAC input I Analog H4 A3
IDUMPUVW Video DAC output O Analog H5 B4
9.14 Video mapping with DENC

Table 25. Video mapping with DENC functions
Signal name Description I/O Type DENC connection
VOUT Video DAC output O Analog G

XOUT Video DAC output O Analog CVBS
UOUT Video DAC output O Analog R
WOUT Video DAC output O Analog B
68/294 Doc ID 8141465 Rev 5

STi5189 Connections
9.15 CEC interface

Table 26. CEC functions
Signal Ball (15 mm x 15 mm Ball (23 mm x 23 mm
Description I/O Type
name package) package)
CEC Consumer electronic control I/O Digital F14 F23
9.16 Serial Flash interface

Table 27. Serial Flash interface functions
Ball Ball
l
package) package)
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SPI_CLK SPI clock output to Serial Flash O Digital T9 AE20
SPI_DATAIN SPI data input from Serial Flash I Digital U9 AE19
SPI_DATAOUT SPI data output to Serial Flash O Digital V9 AD19
en
SPI_NOTCS SPI chip select output to Serial Flash O Digital R9 AD20
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9.17 Infrared interface

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All infrared interface functions use GPIO pins, which are shared with other functions. For
further details, see Table 41.
on
Table 28. Infrared interface functions

Ball Ball
package) package)
C
IRB_PPM_IN PPM input of IRB I PIO2[5] P16 P23

IRB_PPM_OUT PPM output of IRB O PIO2[7] (Alt 1) R18 T25
IRB_UHF_IN UHF channel input for IRB I PIO2[6] R17 T24
Doc ID 8141465 Rev 5 69/294

Connections STi5189
9.18 USB 2.0 ULPI
Table 29. USB 2.0 ULPI functions

Ball Ball
Signal name Pins Range Description I/O (15 mm x 15 mm (23 mm x 23 mm
package) package)
USB_CLK 1 1 Interface clock I/O T7 AD17

USB_DATA[0] 8 [‘7:0] I/O T5 AF16
USB_DATA[1] - - I/O R6 AE17
USB_DATA[2] - - I/O T6 AF17
USB_DATA[3] - - I/O P7 AG17
Data bus
l
USB_DATA[4] - - I/O R7 AG18
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USB_DATA[5] - - I/O T8 AF18
USB_DATA[6] - - I/O U8 AE18
USB_DATA[7] - - I/O R8 AF19
en
USB_NXT 1 1 Next data I/O U5 AE16
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Direction of the data

USB_DIR 1 1 I/O R5 AD16
bus
fid
USB_STP 1 1 Stop data I/O U4 AE15

on
C
70/294 Doc ID 8141465 Rev 5

STi5189 Connections
9.19 Ethernet and TS

The STi5189 integrates a 10/100 Ethernet MAC with MII and RMII interfaces available.
These interfaces share the same balls as some of the transport interface balls. The following
table shows which Ethernet and transport interfaces may be used together in an application:
Table 30. Ethernet/TS modes

Mode Ethernet TS In TS Out
Mode 1 Not available Parallel Parallel

Mode 2 RMII Parallel Not available
Mode 3 MII Serial Not available
l
The details of the pins and the proposed sharing are given in the following table:
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Table 31. Ethernet functions
Ball
Ethernet Ball
Ethernet function (23 mm x 23
en
function TS function Range RMII Pins I/O (15 mm x 15
description mm
(MII) mm package)
package)
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Timing reference for

MDC TS0OUTPACKETCLK 1 Y 1 O U1 N4
transfer information
fid
TS0OUTBITORBYTE AC presenting
TX_EN 1 Y 1 O N5 K1
CLKVALID nibbles on MII for Tx
Data signals driven M2, M3, N4, J3, J2, K3,
TXD[3:0] TS0OUTDATA [7:4] [1:0] 4 O
by the mac N3 K2
on
Data signals that

TS0OUTBITORBYTE transition
RXD[1] 1 Y 1 I T2 M3
CLK synchronously with
respect to RX_CLK
C
RX_DV TS0OUTDATA [3] Y 1 Receive data valid I R2 L3

Data signals that
transition
RXD[0] TS0OUTDATA [2] Y 1 I P5 M2
synchronously with
respect to RX_CLK
Data input/output
MDIO TS0OUTDATA [1] Y 1 O U2 P5
signal
Management data
MDINT TS0OUTDATA [0] Y 1 I V1 P4
interrupt from PHY
PHYCLK TS0OUTERROR 1 Y 1 PHY clock O L1 H4
RXCLK TS0INDATA [5] - 1 RX_DV, RX_ER, I R3 L2
RXD
RX_ER TS0INDATA [4] - 1 Receive error I P4 L1
Doc ID 8141465 Rev 5 71/294

Connections STi5189
Table 31. Ethernet functions (continued)

Ball
Ethernet Ball
Ethernet function (23 mm x 23
function TS function Range RMII Pins I/O (15 mm x 15
description mm
(MII) mm package)
package)
Data signals that

transition
RXD[3:2] TS0INDATA [7:6] - 2 I T3, T1 N3, M4
synchronously with
respect to RX_CLK
Asserted when
CRS TS0INDATA [3] - 1 either Tx or Rx I L2 H3
medium not idle
Asserted on
COL TS0INDATA [2] - 1 detection of a I M4 J4
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collision
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TXCLK TS0INDATA [1] - 1 I P3 L4
TX_EN and TXD
en
9.20 Smartcard
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All smartcard functions use GPIO pins, which are shared with other functions. For further
fid
Table 32. Smartcard interface functions

Ball Ball
Signal name Description I/O Mapping (15 mm x 15 (23 mm x 23 mm
on
mm package) package)
SC0_CG_CLK Smartcard0 clockout O PIO0[3] J15 J26

SC0_CG_EXTCLK Smartcard0 external clock I PIO0[2] K18 K26
SC0_COMD_VCC Smartcard0 power O PIO0[5] H18 H25
C
SC0_DATAIN/ ASC0_RXD ASC0 receive data I PIO0[1] K16 K25

SC0_DATAINOUT ASC0 receive/transmit data I/O PIO0[0] K17 K27
SC0_DETECT Smartcard0 detect I PIO0[7] J16 J25
SC0_DIR Smartcard0 direction O PIO0[6] H17 H24
PIO0[3]
SC0_FSCLK0 Smartcard0 FS clockout O J15 J26
(Alt 1)
PIO0[4]
SC0_RESET Smartcard0 reset O H16 J24
(Alt 0)
PIO4[3]
SC1_CG_CLK Smartcard1 clockout O E14 D26
(Alt 2)
PIO4[2]
SC1_CG_EXTCLK Smartcard1 external clock I F16 D25
(Alt 2)
PIO4[5]
SC1_COMD_VCC Smartcard1 power O E15 C26
(Alt 2)
72/294 Doc ID 8141465 Rev 5

STi5189 Connections
Table 32. Smartcard interface functions (continued)

Ball Ball
Signal name Description I/O Mapping (15 mm x 15 (23 mm x 23 mm
mm package) package)
PIO4[0]
SC1_DATAINOUT/ASC1_TXD ASC1 receive/transmit data I/O G16 E25
(Alt 2)
PIO4[1](
SC1_DATAIN/ ASC1_RXD ASC1 receive data I F15 E23
Alt 2)
PIO4[7]
SC1_DETECT Smartcard1 detect I D17 C25
(Alt 2)
PIO4[6](
SC1_DIR Smartcard1 direction O D16 C27
Alt 2)
PIO4[4]
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SC1_RESET Smartcard1 reset O E16 D24
(Alt 2)
9.21 tia
Asynchronous serial controller (ASC)
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There are four ASCs available. The ASC0 and ASC1 are smartcard capable.
All ASC functions use GPIO pins, which are shared with other functions. For further details,
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see Table 41.

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Table 33. Asynchronous serial controller functions

Ball Ball
package) package)
on
ASC0_RXD ASC0 receive data signal I PIO0[1] K16 K25

ASC0_TXD ASC0 transmit data O PIO0[0] (Alt 0) K17 K27
ASC0_CTS ASC0 clear to send signal I PIO0[5] H18 H25
C
ASC0_RTS ASC0 request to send signal O PIO0[4] (Alt 2) H16 J24

ASC1_RXD ASC1 receive data signal I PIO4[1] F15 E23
ASC1_TXD ASC1 transmit data O PIO4[0] (Alt 2) G16 E25
ASC1_CTS ASC1 clear to send signal I PIO4[3] E14 D26
ASC1_RTS ASC1 request to send signal O PIO4[2] (Alt 2) F16 D25
ASC2_RXD ASC2 receive data signal I PIO1[3] L17 L26
ASC2_TXD ASC2 transmit data O PIO1[2] (Alt 1) K15 L27
ASC2_CTS ASC2 clear to send signal I PIO1[5] L16 M26
ASC2_RTS ASC2 request to send signal O PIO1[4] (Alt 1) L15 L25
ASC3_RXD ASC3 receive data signal I PIO2[1] N15 P24
ASC3_TXD ASC3 transmit data O PIO2[0] (Alt 1) N16 N24
ASC3_CTS ASC3 clear to send signal I PIO2[2] P17 R24
ASC3_RTS ASC3 request to send signal O PIO2[5] (Alt 1) P16 P23
Doc ID 8141465 Rev 5 73/294

Connections STi5189
9.22 Synchronous serial controller (SSC)

There are three synchronous serial controllers: SSC0, SSC1 and SSC2.
For I2C operation, only two wires are required for half duplex operation. The SSC can be an
I2C master or slave because the pin MTSR_DINOUT is connected internally to the MTSR or
MRST data in and data out ports of the SSC under software configuration control.
For SPI operation, three wires are required for full duplex operation. Hence, MTSR data and
MRST data signals are on separate pins. The functionality of different SSCs is:
● SSC0 interface is shared with SPI interface for SPI write functionality. This is also
available at PIO1[7:6]. The configuration bit CFG_CTRL_M[14] is used for this sharing.
If CFG_CTRL_M[14] is programmed to 1, SSC0 interface will be used for SPI
transactions. If CFG_CTRL_M[14] is programmed to 0, SSC0 interface will be available
at PIO1[7:6].
● SSC1 interface is proposed for the connection to the tuner. The configuration bit
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CFG_CTRL_K[27] has to be set to 1, allowing the SSC1 interface to be routed to
QPSK_SCLT and QPSK_SDAT pads. While it could be possible to connect any other
I2C controlled device to the same line, this is not recommendable due to the possible
tuner sensibility to noises.
● SSC2 interface is available at PIO3[3:2] pads.
en
The SSC0 and SSC2 functions use GPIO pins, which are shared with other functions. For
Confidential
further details, see Table 41.

The SSC1 is available through the SDAT and SCLT pins.
fid
Table 34. Synchronous serial controller functions

Ball Ball
Signal name Description Dir Mapping (15 mm x 15 m (23 mm x 23 mm
on
m package) package)
SSC0 serial data;

SSC0_MTSR_DINOUT master transmit, serial B PIO1[7] (Alt 2) A1 E6
received
C
SSC0_SCLKINOUT SSC0 serial clock B PIO1[6] (Alt 2) B2 D6

SSC1 serial data;
SSC1_MTSR_DINOUT master transmit, serial B QPSK_SDAT U12 AC21
received
SSC1_SCLKINOUT SSC1 serial clock B QPSK_SCLT T12 AD22
SSC2 serial data;
SSC2_MTSR_DINOUT master transmit, serial B PIO3[2] (Alt 1) G14 F24
received
SSC2_SCLKINOUT SSC2 serial clock B PIO3[3] (Alt 1) G15 G23
74/294 Doc ID 8141465 Rev 5

STi5189 Connections
9.23 Debug
Table 35. Debug functions
Ball Ball
package) package)
TAP boundary scan - test logic

NOT_TRST I Digital T17 U26
reset - decoder
TAP boundary scan - test clock - Digital
TCK I T18 U25
decoder Schmitt
TAP boundary scan - test data
TDI I Digital U18 U27
input - decoder
TAP boundary scan - test data
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TDO O Digital V18 V27
output - decoder
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TAP boundary scan - test mode
TMS I Digital T16 U24
select - decoder
NOTASEBRK ST40 debug I/O Digital M14 N25
en
Figure 11. Recommended connections
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VCC 3.3 V
10kΩ
fid
Host device 22 Ω STi5189

TDI TDO
TDO TDI
TMS TMS
TCK TCK
NOT_TRST
on
NOT_TRST
TRIGOUT0 TRIGGERIN
TRIGIN TRIGGEROUT
NOT_RST NOTRESETIN
C
Board 10kΩ
power-on reset
Target board
Note: If there is a lot of noise on the clock line, a capacitor in the range from 10 pF to 100 pF can
be fitted between TCK and ground near the target STi5189.
Doc ID 8141465 Rev 5 75/294

Connections STi5189
9.24 Programmable I/O ports (GPIO and PIO)

The programmable I/O ports are available for general use, but many are shared with other
functions. The demodulator ports are identified as GPIO and the decoder ports identified as
PIO. For further details on decoder, see Table 41.
Table 36. PIO functions

Ball Ball
Signal name Description Dir Drive Type (15 mm x 15 mm (23 mm x 23 mm
package) package)
PIO0[0] IO 4 mA Digital K17 K27

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PIO0[3] Programmable I/O IO 4 mA Digital J15 J26
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bank 0 decoder
PIO0[4] section IO 4 mA Digital H16 J24
PIO0[5] IO 4 mA Digital H18 H25
PIO0[6] IO 4 mA Digital H17 H24
en
PIO0[7] IO 4 mA Digital J16 J25
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PIO1[0] IO 4 mA Digital P15 R25

PIO1[1] IO 4 mA Digital K14 L24
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PIO1[2] IO 4 mA Digital K15 L27

PIO1[3] Programmable I/O IO 4 mA Digital L17 L26
bank 1 decoder
PIO1[4] section IO 4 mA Digital L15 L25
on
PIO1[5] IO 4 mA Digital L16 M26

PIO1[6] IO 4 mA Digital B2 D6
PIO1[7] IO 4 mA Digital A1 E6
C
PIO2[0] IO 4 mA Digital N16 N24

PIO2[1] IO 4 mA Digital N15 P24
PIO2[2] IO 4 mA Digital P17 R24
PIO2[3] Programmable I/O IO 4 mA Digital K4 F4
bank 2 decoder
PIO2[4] section IO 4 mA Digital L3 F3
PIO2[5] IO 4 mA Digital P16 P23
PIO2[6] IO 4 mA Digital R17 T24
PIO2[7] IO 4 mA Digital R18 T25
76/294 Doc ID 8141465 Rev 5

STi5189 Connections
Table 36. PIO functions (continued)

Ball Ball
Signal name Description Dir Drive Type (15 mm x 15 mm (23 mm x 23 mm
package) package)
Digital -
PIO3[0] IO 4 mA R16 T26
I2C
Digital -
PIO3[1] IO 4 mA B1 E5
I2C
Digital -
PIO3[2] IO 4 mA G14 F24
Programmable I/O I2C
bank 3 decoder Digital -
PIO3[3] section IO 4 mA G15 G23
I2C
PIO3[4] IO 4 mA Digital H14 G24
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PIO3[5] IO 4 mA Digital L4 G4
PIO3[6] IO 4 mA Digital L5 G5
PIO3[7] IO 4 mA Digital G17 E24
en
Digital -
PIO4[0] IO 4 mA G16 E25
I2C
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Digital -
PIO4[1] IO 4 mA F15 E23
I2C
fid
Digital -
PIO4[2] IO 4 mA F16 D25
Programmable I/O I2C
bank 4 decoder Digital -
PIO4[3] section IO 4 mA E14 D26
I2C
on
PIO4[4] IO 4 mA Digital E16 D24

PIO4[5] IO 4 mA Digital E15 C26
PIO4[6] IO 4 mA Digital D16 C27
C
PIO4[7] IO 4 mA Digital D17 C25
Doc ID 8141465 Rev 5 77/294

Connections STi5189
9.25 Alternative functions (mapped to PIO pins)

To improve flexibility and to allow the STi5189 to fit into different set-top box application
architectures, the input and output signals from some of the peripherals and functions are
not directly connected to the pins of the device. Instead, they are assigned to the alternative
function inputs and outputs of a PIO port bit. This scheme allows the pins to be configured
with their default function, if the associated input or output is not required in that particular
application.
Inputs connected to the alternative function input are permanently connected to the input
pin. The output signal from a peripheral is connected when the PIO bit is configured to
push-pull function mode.
Figure 12. I/O port pins
Pin
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Push-pull
tri-state
weak pull-up
en
Alternative function Alternative function input
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1 0
Alternative function output
fid
Output latch Input latch

on
Table 37 to Table 41 show the mapping of the alternative functions. Unless otherwise stated,
the default after reset for alternative functions is the PIO port or pin function.
The alternative configurations are set using the PIOn_ALTFOP_MUX_SEL_BUS [7:0] bits in
C
the CFG_CTRL_F (PIO0 and PIO1), CFG_CTRL_G (PIO2 and PIO3) and CFG_CTRL_O
(PIO4) top-level configuration registers.
78/294 Doc ID 8141465 Rev 5

STi5189 Connections
Table 37. PIO0 alternative functions

Pins Pins
(15 mm x (23 mm x
No. Alt 0 (Default) Dir Alt1 Dir Alt2 Dir Alt 3 Dir
15 mm 23 mm
package) package)
Configured by
pio0_altfop_mux_sel_bus1<7:0>
00 = Alt0, 01 = Alt1, 10 = Alt2, 11= Alt3
K17 K27 0 SC0_DATAOUT/ASC0_TXD O - - - -
K16 K25 1 SC0_DATAIN/ASC0_RXD I General- - - - -
I/O
K18 K26 2 SC0_CG_EXTCLK I purpose I/O - - - -
J15 J26 3 SC0_CG_CLK O CLK_SC O - -
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H16 J24 4 SYSRV_SC_RESET_0 O - - ASC0_RTS O - -
H18 H25 5 SYSRV_SC_POWER_0 O - - ASC0_CTS I - -
H17 H24 6 SC0_DIR/ASC0_NOTOE - - - - - - -
en
J16 J25 7 SYSRV_SC_DETECT_0 I - - - - - -
Confidential

Pins Pins
fid
(15 mm x (23 mm x Alt 0 Alt

No. Dir Alt 1 Dir Alt 2 Dir Dir
15 mm 23 mm (Default) 3
package) package)
Configured by
on
00 = Alt0, 01 = Alt1, 10 = Alt2, 11= Alt3
General-
P15 R25 0 - - I/O FDMA_REQ_0 I - -
purpose I/O(1)
C
General-
K14 L24 1 - B I/O FDMA_REQ_1 I - -
purpose I/O(1)
General-
K15 L27 2 I/O ASC2_TXD O TVO_DENC_CFC I - -
purpose I/O
General-
L17 L26 3 I/O ASC2_RXD I PIXCLK_FROM_PAD I - -
purpose I/O
General-
L15 L25 4 I/O ASC2_RTS O HSYNC_FROM_PAD I - -
purpose I/O
General- VSYNC_FROM_PAD/
L16 M26 5 I/O ASC2_CTS I I/O - -
purpose I/O CLK_27_FROM_PAD
General- SSC0_SERIAL_CLOC
B2 D6 6 - I I/O B - -
purpose I/O(1) KINOUT(1)
General- SSC0_SERIAL_DATAI
A1 E6 7 - B I/O B - -
purpose I/O(1) NOUT_MTSR
1. If CFG_CTRL_M[14] = 1, SSC0 will be used for SPI transactions.
Doc ID 8141465 Rev 5 79/294

Connections STi5189

Pins Pins
(15 mm x (23 mm x Alt
No. Alt 0 (Default) Dir Alt1 Dir Alt 2 Dir Dir
15 mm 23 mm 3
package) package)
Configured by
00 = Alt0, 01 = Alt1, 10 = Alt2, 11= Alt3
General- PCM_DATAOU
N16 N24 0 I/O ASC3_TXD O - - -
purpose I/O T
General- PCM_LRCLKO
N15 P24 1 I/O ASC3_RXD I - - -
purpose I/O UT
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General- PCM_SCLKOU
P17 R24 2 I/O ASC3_CTS I - - -
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purpose I/O T
General-
purpose I/O/
K4 F4 3 PWM_CAPTURE[0] I PCM_MCLK - - -
I/O/DVBCI_RE O
en
SET
General-
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purpose
L3 F3 4 I/O/I PWM_OUT[0] O PCM_SCLK - - -
I/O/DVBCI_CD
1
fid
General-
P16 P23 5 I/O ASC3_RTS O IRB_PPM_IN I - -
purpose I/O
General-
R17 T24 6 I/O IRB_UHF_IN I PCM_DATAIN - - -
on
purpose I/O
General- IRB_PPM_OUT/FP
R18 T25 7 I/O O/I PCM_LRCLKIN - - -
purpose I/O RESET (long time)
C
80/294 Doc ID 8141465 Rev 5

STi5189 Connections

Pins Pins
(15 mm x (23 mm x
No. Alt 0 (Default) Dir Alt 1 Dir Alt 2 Dir Alt 3 Dir
15 mm 23 mm
package) package)
Configured by
00 = Alt0, 01 = Alt1, 10 = Alt2, 11= Alt3
General-
R16 T26 0 I/O EXTINT0 I/O PAD_VSYNC O - -
purpose I/O
General- FDMA_REQ_TOP
B1 E5 1 I/O EXTINT2 I O - -
purpose I/O AD[0]
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General- SSC2_MTSR_ FDMA_REQ_TOP
G14 F24 2 I/O B O - -
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purpose I/O DINOUT AD[1]
General- SSC2_SCLKI
G15 G23 3 I/O B PAD_VSYNC_EN O - -
purpose I/O NOUT
General-
en
H14 G24 4 I/O EXTINT1 I/O PAD_HSYNC O - -
purpose I/O
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General-
purpose
L4 G4 5 I/O - - PAD_HSYNC_EN O - -
I/O/DVBCI_BU
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S_REQ
General-
purpose
L5 G5 6 I/O - - - - - -
I/O/DVBCI_BU
on
S_GNT
General-
G17 E24 7 I/O DVO CLK O - O - -
purpose I/O
C
Doc ID 8141465 Rev 5 81/294

Connections STi5189

Pins Pins
(15 mm x (23 mm x
No. Alt 0 (Default) Dir Alt1 Dir Alt 2 Dir Alt 3 Dir
15 mm 23 mm
package) package)
Configured by
00 = alt0, 01 = alt1, 10 = alt2, 11= alt3
SC1_DATAINOUT/
G16 E25 0 DVO_DATA[0] O - - B - -
ASC1_TXD
General-
F15 E23 1 DVO_DATA[1] O I/O ASC1_RXD I - -
purpose I/O
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SC1_CG_EXTCL
F16 D25 2 DVO_DATA[2] O - - I/O - -
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K/ASC1_RTS
E14 D26 3 DVO_DATA[3] O ASC1_CTS I/O SC1_CG_CLK O - B
E16 D24 4 DVO_DATA[4] O - - SC1_RESET O - -
en
General- SC1_COMD_VCC
E15 C26 5 DVO_DATA[5] O I/O O - -
purpose I/O (SC1_POWER)
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General- SC1_DIR/ASC1N
D16 C27 6 DVO_DATA[6] O I/O O - -
purpose I/O OTOE
fid
General-
D17 C25 7 DVO_DATA[7] O I/O SC1_DETECT I - -
purpose I/O
on
C
82/294 Doc ID 8141465 Rev 5

STi5189 Mode pins
10 Mode pins
The mode pins are a group of signals configured in the input mode, and are dedicated to
capture values during the power-on-reset sequence that are used to configure certain
defined functionalities.
The mode pins are captured at the rising-edge of the RST_N signal during the reset phase,
and are made available to the system to define operating modes, mainly boot mode
configuration. The mapping of the mode pins is given in Table 42.
The mode pins are applicable for the 23 mm x 23 mm package (since they use FMI balls)
and mainly affect how and from where the device boots. The mode pins must be pulled high
or low externally to define the correct functionality even if there is only one valid setting. For
the 15 mm x 15 mm package there are no mode pins and the reset behavior of the STi5189
is fixed to boot from Serial Flash without stretch mode reset. Other settings are not relevant
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for the 15 mm x 15 mm package.
Table 42.
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Mode pins - value latched at reset
Ball (23 mm x 23 mm 15 mm x 15 mm package
en
Description
package) internal fixed setting
Confidential
Reset period
FMIADDR23 0: 200 ms stretch mode reset 1: Normal reset period
1: Normal reset period
fid
Boot mode
00: Parallel NOR Flash
01: NAND Flash
10: Serial Flash
FMIADDR[22:21] 10: Serial Flash
on
11: Reserved
The boot mode can be forced to NAND Flash or Serial
Flash regardless of the mode pins settings by software
anti-fuse configuration.
NAND Flash address type
C
Boot from Serial Flash only;

FMIADDR20 0: Long addressing mode
not applicable
1: Short addressing mode
NAND Flash page type
FMIADDR19 0: Small page size
not applicable
1: Large page size
Serial Flash type
1: All other Serial Flash types
0: Older ATMEL Flash types, non-standard opcodes
FMIADDR18 including latest ATMEL Serial
1: All other Serial Flash types including latest ATMEL
Flash types
Serial Flash types
NAND Flash boot offset remapping
0: Reserved
FMIADDR3 1: Contiguous blocks from the first error correctable block
not applicable
(marked block) are remapped to contiguous area at the
boot address (block 0)
Doc ID 8141465 Rev 5 83/294

Mode pins STi5189
Table 42. Mode pins - value latched at reset (continued)

Ball (23 mm x 23 mm 15 mm x 15 mm package
Description
package) internal fixed setting
Boot bank port size for parallel NOR Flash and NAND Boot from Serial Flash only;
FMIADDR2
Flash; must be pulled high (='1') not applicable
Boot bank port size for parallel NOR FLASH and NAND
Flash
0: 16 bits
1: 8 bits Boot from Serial Flash only;
FMIADDR1
not applicable.
Note that for NAND Flash, if 2 x 8 bit mode is used, the
boot mode should be configured for 8 bits. If 16-bit mode is
used, the boot mode should be configured for 16 bits
Note: The 15 mm x 15 mm variant only supports the Serial Flash, which is activated by default.
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There is no need to control the mode pins in this version.
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en
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on
C
84/294 Doc ID 8141465 Rev 5

STi5189 Register base addresses
11 Register base addresses
11.1 Decoder base addresses

The following table lists the base addresses for each block in the decoder, in alphabetical
order:
Table 43. Register base addresses of decoder

Module Base address
Asynchronous serial controller: UART0 0xFD13 0000

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Consumer electronics control (CEC) 0xFDE4 0000
Digital encoder 0xFD70 0000
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DVO 0xFD70 0600
Ethernet 0xFDE0 0000
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FMI configuration 0xFDF0 0000

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FMI buffer 0x0000 0000

FMI Bank 0 0x0000 0000
FMI Bank 1 0x0200 0000
FMI Bank 2 0x0400 0000
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FMI Bank 3 0x0600 0000

FMI NAND Flash 0xFDF0 1000
Flexible DMA 0xFDB0 0000
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Graphics DMA: GDMA 1 0xFD70 0C00

Infrared transmitter/receiver 0xFD11 8000
Interconnect high-speed monitor and control 0xFD00 2000
Interconnect high-density monitor and control 0xFD90 1000
Interrupt controller 0xFFD0 0000
Interrupt level controller 0xFD10 0000
Local memory interface 0xFE00 0000
MPEG video decoder 0xFD60 0000
PCM player 0xFD48 0000
PIO: PIO0 0xFD12 0000
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Register base addresses STi5189
Table 43. Register base addresses of decoder (continued)

Module Base address

PTI 0xFDA0 0000
Smartcard interface: SC0 0xFD14 8000
Smartcard interface: SC1 0xFD14 9000
S/PDIF player 0xFD40 0000
SPI Boot 0xFDF0 2000
Synchronous serial controller: SSC0 0xFD14 0000
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System services 0xFDC0 0000
Transport stream merger and router registers 0xFDE2 0000
2-D blitter display engine 0xFD80 0000
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TVOut Teletext 0xFD70 0700
USB 0xFDD0 0000
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Video timing generator 0xFD70 0400

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STi5189 QPSK demodulator
12 QPSK demodulator
12.1 Overview
The QPSK demodulator is a channel receiver for satellite television reception. It also
contains a forward error correction (FEC) unit with both an inner (Viterbi) and a outer (Reed-
Solomon) decoder and DiSEqC interface for flexible control of the outdoor unit.
The QPSK demodulator accepts 8-bit I and Q input signals. The FEC unit is compliant with
the DIRECTV® and DVB-S specifications. All processing is digital. The Reed–Solomon
decoder corrects up to eight erroneous bytes per packet.
A derotator, located before the Nyquist root filter, allows a wide range of offset tracking. The
high sampling rate facilitates the implementation of low-cost, direct conversion tuners.
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The QPSK demodulator is controlled through an internal I2C interface, allowing easy control
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of its functionalities. The I2C is also available outside the chip, through an internal repeater,
to control the tuner. This IP operates with a recommended 100 MHz and can process
variable modulation rates up to 50 Mbauds. The MPEG transport streams is internally
routed to the packet demultiplexer and MPEG decoder or it can be output to implement
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applications like the common interface.
The multi-standard capability associated with a broad range of input frequency operations
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makes it easy to use. Its low power consumption and low external component count makes
it perfect for all satellite applications.
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QPSK demodulator STi5189
12.2 Architecture
Figure 13. QPSK subsystem main functions with needed analog IPs
diseqc_out
DiSEqC
diseqc_in 2.0 QPSK subsystem
DiSEqC manager
(agc)
QPSK
AGC1
demodulator
[Im, Ip] Nyquist and
Cancellation
Dual
[Qm, Qp] ADC Derotator interpolation AGC2
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Offset
filter
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Analog
Timing
recovery
loop
PLL Timing
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DCO
loop
Clock
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manager
SSC1 from comms
Slave
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I 2C LOCK
sdat manager
To tuner indicator and monitoring
sclt
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ERROR
Transport stream
monitoring
manager
FEC
Energy Reed- Inner VITERBI
Solomon soft
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descrambler decoder deinterleaver decoder
Transport stream SS
12.3 I2C interface

The I2C interface uses the standard I2C protocol, where the first byte is 0xD0 (or 0xD2) for a
write operation or 0xD1 (or 0xD3) for a read operation. The I2C interface supports I2C fast
mode (I2C 400 kHz).
This interface is controlled internally through the SSC1 bus coming from the comms block;
the two signals used for this connection are referred as SDA and SCL.
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12.3.1 I2C chip addresses

The two I2C (device master) addresses are programmable by the software through the
register CFG_CTRL_C [7].
12.3.2 Write operation

The following is the byte sequence:
1. The first byte gives the device address plus the direction bit (R/W = 0).
2. The second byte contains the internal address of the first register to be accessed.
3. The next byte is written in the internal register. Following bytes (if any) are written in
successive internal registers.
4. The transfer lasts until stop conditions are encountered (SDA and SCL high).
5. The STi5189 acknowledges every byte transfer. The I2C controller puts the SDA line
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into high impedance after each byte transmitted and the STi5189 drives the line low to
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acknowledge reception.
12.3.3 Read operation

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The address of the first register to be read is programmed in a write operation without data.
This positions the internal pointer.
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1. The first byte gives the device master address plus the direction bit (R/W = 0).
2. The second byte contains the internal address of the first register to be accessed.
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3. A STOP is then sent.

A new start is then followed by the device master address and R/W = 1. All following
bytes are now data read at successive positions starting from the last write internal
address.
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4. The first byte gives the device master address plus the direction bit (R/W = 1).
5. The second byte is the first byte of data read out (The I2C controller is in high
impedance state and the STi5189 drives the SDA line).
6. Subsequent bytes are then read out until a STOP is reached.
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The I2C read and write modes are shown in the following figure:
Figure 14. Example of I2C read and write operations
Write registers 0 to 3 with AA, BB, CC, DD and I2C chip address D0
Device address Register Data Data Data Data

Start write D0 ACK address 00 ACK AA ACK BB ACK CC ACK DD ACK Stop
Read registers 2 and 3
Start Device address, write D0 ACK Register address 02 ACK Stop
Start Device address, read D1 ACK Data read CC ACK Data read DD ACK Stop
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12.3.4 I2C interface in standby mode

The standby mode bit is at address 0x41 (bit SYNTCTRL.STANDBY).
12.3.5 Identification register

The ID register (at address 0x00) gives the release number of the circuit. The content of this
register at reset (currently 0x10) will be modified for any new release. In this case, the
register at reset will become 0x11.
The register is first read and then the value obtained is compared with the value required by
the software, for example:
● Release 1: read address 0x00: value = 0x10
● Release 2: read address 0x00: value = 0x11
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12.3.6 I2C bus repeater
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In some applications, signal interference generated by the SDA/SCL lines of the I2C bus
may significantly degrade the tuner performance. To avoid this problem, the STi5189 offers
an I2C bus repeater so the SDAT and SCLT lines are activated only when necessary and
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muted otherwise.
Both SDAT and SCLT pins are set to high impedance at reset. When the microprocessor
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writes 1 into register bit I2CRPT.I2CT_ON, the next I2C message on SDA and SCL is
repeated on the SDAT and SCLT pins, respectively. There are two options for controlling I2C
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bus transactions (selectable through I2CRPT.STOP_ENABLE). The first (STOP_ENABLE

high) causes the I2C repeater to turn off automatically as soon as the next stop bit is
encountered. Any size of byte transfer is allowed, regardless of the address, until the stop
conditions are detected. If STOP_ENABLE is low the exchanges on the main I2C bus
continue to be forwarded on to the I2C repeater bus until the I2CRPT.I2CT_ON bit is set low.
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To write to the tuner, the external microprocessor must perform the following sequence for
each tuner message:
1. Program 1 in I2CRPT.I2CT_ON to enable messages to be transferred from the main
I2C bus to the repeater.
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2. Send the message to the tuner.

3. If STOP_ENABLE was set high then I2CT_ON will automatically be set to zero on the
first stop signal encountered (turning off the I2C repeater); no further action is
necessary. If I2CT_ON was low then I2CT_ON must be programmed to zero to disable
the repeater line.
Transfers are fully bidirectional.
I2C bus repeater stability

The I2C bus repeater is a bidirectional bus. As such, conditions for oscillation on the SDAT
line exist. In order to overcome this, a sophisticated circuit requiring some tuning has been
implemented to allow fast I2C bus transactions without oscillation.
The stability of the I2C repeater depends strongly on residual capacitance and thus on
BOARD LAYOUT and may vary from tuner to tuner. Consult the tuner datasheet for
maximum allowable rise times on I2C bus lines. R, C values may need to be adjusted
accordingly.
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The stability is obtained by introducing a programmable delay in the SDA line. The delay
may also be introduced in the SCL line if necessary (though not for reasons of stability).
The delay function is controlled through register I2CRPT fields ENARPTLEVEL and
SCLTDELAY. ENARPTLEVEL sets the division ratio which controls the delay inserted on the
SDAT line. SCLTDELAY activates the same delay on the SCLT line; this makes the delay
equal on SDAT and SCLT but implements the delay with respect to the main I2C bus.
The condition for SDA line stability is:
Delay >= R x C x FMCLK/1613
C may be measured by a capacitance meter on the SDA I2C line (pF).
R is the total value of the pull up resistance (kOhms).
FMCLK is the master clock rate (100 MHz).
Delay is defined in the ENARPTLEVEL field of the I2CRPT register (periods of FMCLK).
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Example R = 3 kOhms, C = 47 pF, FMCLK = 100 MHz.
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Delay >= 3 x 47 x 100/1613 = 8.74
Choose a delay close to 8.74 in this case 8, corresponding to ENARPT_LEVEL = 0b100
The maximum rate on the I2C bus is also fixed by ENARPTLEVEL, R, C and FMCLK.
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I2C max speed <= 1613/(4 x R x C) = 1613/(4 x 3 x 47) = 2.8 MHz, and
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I2C max speed <= FMCLK/(4 x Division_ratio value) = 100/(4 x 8) = 3.1 MHz
Thus the maximum speed allowed on the repeater bus is 2.8 MHz (the minimum of the two
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above equations).
In addition to the above, the START, ACK and STOP conditions must be respected.
START condition: SDA must fall 1/2 clock period prior to SCL falling.
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Data: 8-bit data are presented on SCL falling edge and read in (to the tuner) on SCL rising
edge.
ACK condition: A ninth SCL pulse with SDA set high Z is sent. The master then senses that
the line has been pulled low by the tuner to complete the acknowledge.
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STOP condition: SCL must rise 1/2 clock period prior to SDA rising.
Figure 15. I2C protocol

1 2 3 4 5 6 7 8 ACK
SCLT etc.
START STOP
SDAT
Hi-Z etc.
If for any reason the master detects the SDA rising, whilst SCL is high, the transaction will
be aborted.
If not used for the I2C repeater, both SDAT and SCLT can be used as general-purpose
input / output ports.
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12.4 Clock distribution
12.4.1 Clock inputs

The bandwidth of the demodulator is directly linked to the clock frequency. In case of
baudrate up to 45 Mbyte/s, a clock frequency of 100 MHz is needed. 60 Mbyte/s should be
reachable with a 125 MHz clock frequency.
The PLL takes its reference from either an internal oscillator or an external reference clock.
The STi5189 gives controls that may be used to select which clock to use. See register
SYNTCTRL for more details. The master clock frequency is programmed using the register
PLLCTRL.
12.4.2 Internal clock generation
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Two lower frequencies, F22FR and F22RX, from 22 kHz to 100 kHz, are needed for LNB
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control or DiSEqC control transmission and reception.
Figure 16. Clock signal generation

FMCLK
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1/16 ³ 1/2
(F22FR) DiSEqC/tone
DiSEqC_out
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burst modulator
(DiSEqC[1:0]) 1/0
1/0
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12.4.3 Clock registers

The auxiliary clock and F22 frequency registers are at addresses 0x02 (ACR), 0x03
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(F22FR) and 0x04 (F22RX).
12.5 Signal processing

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In general the STi5189 is programmed using scripts and low level application (LLA) drivers
supplied by STMicroelectronics. The following description provides an aid to understanding
the register settings but does not replace the need to reference the application notes, LLA
drivers and scripts.
12.5.1 Demodulation
The demodulator block performs QPSK demodulation according to DIRECTV and DVB-S
specifications. This implementation is based on the STv0289B demodulator core and has
the following functions:
● automatic gain correction (AGC1)
● IQ DC offset corrections
● carrier frequency and phase acquisition and tracking
● symbol timing acquisition and tracking
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● Nyquist filtering (alpha = 0.2, 0.35)

● equalization
● symbol demapping and soft bit decisions
The demodulator has been designed to support channel symbol rates up to 50 MSPS:
maximum QPSK 50 MSPS at 100 MHz sampling rate.
The following sections provide a description of each block within the DVB-S and DIRECTV
demodulator.
AGC1
The input signal (from analog-to-digital converter) is initially conditioned by the RF AGC
stage.
The modulus of the I and Q input is compared to a programmable threshold,
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m1 = 4.AGC1REF and the difference is integrated, the integrated value may be read in
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register AGC1IN.
This signal is converted into a pulse density modulation signal by a first order ΣΔ DAC which
drives the AGCRF output pin, it must be externally low pass filtered.
This controls the gain command of any amplifier preceding the signal path analog-to-digital
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converter. The AGC output stage is filtered by a simple analog filter.
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Figure 17. AGC signal generation

Integrator FMCLK/8
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m1 value
-
Sqroot(I^2+Q^2) + ΣΔ DAC
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The output is a 3.3 V tolerant open drain or push pull stage, configurable through the bit
AGC_OPDRAIN.
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The time constant of the AGC is given by:

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2 – β agc
T agc = -------------------------- T mclk
m1
The coefficient βagc is programmable through the AGC1C register (AGCIQ_BETA field). The
reset value of AGCIQ_BETA allows an initial settling time of less than 100 k master clock
periods. TMCLK represents the period of the master clock (FMCLK).
Offset cancellation
This device suppresses the residual DC component on I and Q (bit ENA_ADJ in AGC1C
register). The compensation may be frozen to its last value by resetting the DC offset
compensation bit in AGC control register AGC1C at address 0x0E (bit AVERAGE_ON).
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Nyquist root and interpolation filters

Two roll off values are available: 0.35 and 0.20. They are selected using the
EQUA.MODE_COEF bit.
After Nyquist filtering, the signal amplitude is adjusted using a second AGC (AGC2). This
AGC is controlled using the AGC2REF register. Through the action of the AGC, the modulus
of the output IQ signals is constant and equal to AGC2REF.
The RMS value of I and Q is measured after the Nyquist filter and compared to a
programmable value, x = 4. AGC2REF, as for the analog AGCs. The integrated error signal
is applied to a multiplier on each I and Q path.
The AGC2 control register AGC2COEF is at address 0x12. Bits[2:0] give the AGC2
coefficient and this sets BETA_AGC2, the gain of the integrator. The Table 44 shows how
BETA_AGC2 is programmed with the AGC2 coefficient (which is related to the time constant
of the AGC).
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Table 44. AGC2 coefficients
AGC2 coefficient BETA_AGC2
000 0
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001 1
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010 4
011 16
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100 64
101 256
110 NA
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111 NA
If the AGC2 coefficient = 0, the gain remains unchanged from its last value.
The time constant is independent of the symbol frequency; however it does depend on the
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modulus, m1, of the input signal programmed in the AGC1REF register with the following
approximate relationship:
TAGC2 = {60 x 103 x TMCLK} / {AGC1REF x BETA_AGC2}
12.5.2 Timing recovery

Timing control
The loop is parameterized by two coefficients: ALPHA_TMG and BETA_TMG (register RTC
at 0x11). ALPHA_TMG can take values from 0 to 8 and BETA_TMG from 0 to 12. When the
parameter is 0, the coefficient value is zero.
The symbol frequency registers (MSB, middle bits and LSB) are at addresses 0x28 (SFRH),
0x29 (SFRM) and 0x2A (SFRL). These must be programmed with the expected symbol
frequency. The units are:
FMCLK / 220
The value of the timing frequency register RTFM and RTFL (at 0x22 and 0x23), when the
system is locked, is an image of the frequency offset. The unit is FS / 219 (about 2 ppm). It
should be as close as possible to 0 (by adjusting symbol frequency register value) in order
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to have a symmetrical capture range. Reading RTFM and RTFL allows optimal trimming of
the timing range.
The actual symbol frequency is:
F M_CLK
F S_REG ⎛ 1 + T MG_REG --------⎞
1
F S = ------------------
20 ⎝ 19⎠
2 2
where FS_REG is the content of the symbol frequency register and TMG_REG the content of
the timing frequency registers (RTFM and RTFL).
Loop equation
The timing loop may be considered as a second order loop. The natural frequency and the
damping factor may be calculated using the following formula:
FN = 1.849 x 10-6 x FS √(AGC2REF x β)
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where, FS is the symbol frequency, AGC2REF is the AGC2 reference level and β is
programmed by the timing control register: (RTC)
β = 2BETA_TMG
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The damping factor is:
ξ = {47.6 x10-3 x √AGC2REF x 2ALPHA_TMG} / √2BETA_TMG
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Table 45 shows the natural frequency in DVB-S, with nominal reference level
AGC2REF = 72, for different values of BETA_TMG and ALPHA_TMG without noise.
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Table 45. Natural frequency for different values of BETA_TMG and ALPHA_TMG
ALPHA_TMG 1 2 3 4 5
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Natural frequency for

BETA_TMG Damping factor
FS = 20 Msymbols/s
0001 0.32 kHz 0.57 1.14 2.28 4.57 9.14

0010 0.44 kHz 0.4 0.81 1.62 3.23 6.46
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0011 0.54 kHz 0.29 0.57 1.14 2.28 4.57

0100 0.63 kHz 0.2 0.4 0.81 1.62 3.23
0101 0.70 kHz 0.14 0.29 0.57 1.14 2.28
0110 0.77 kHz 0.1 0.2 0.4 0.81 1.62
0111 0.89 kHz 0.07 0.14 0.29 0.57 1.14
1000 0.94 kHz 0.04 0.1 0.2 0.4 0.81
1001 0.99 kHz 0.03 0.07 0.14 0.29 0.57
1010 1.04 kHz 0.02 0.05 0.1 0.2 0.4
Timing lock indicator

The timing lock indicator reports a value dependent upon the signal-to-noise ratio and on
the signal lock state. The timing lock registers are STEP1 (at 0x14) and STEP2 (at 0x58)
(step increments for indicator 1 and 2), TLIRM, TLIRL (timing lock indicator and final
indicator), TH1, TH2 and THH (indicator 1, 2 and hysteresis thresholds) and IND1MAX
(second level threshold apply on indicator 1).
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The timing lock indicator is a function of the lock condition, but also of the current signal to
noise ratio. The timing lock parameters must be programmed as a function of the AGC2
reference level (rounded to the closest value):
● TH1 = 8.6 x AGC2REF
● TH2 = 29.8 x AGC2REF
● IND1MAX = 1.6 x AGC2REF
When the timing is locked, the indicator is positive; otherwise it is negative. The value needs
10 to 20 Ksymbols to stabilize.
In order to avoid wrong information, some hysteresis is provided by register THH:
● lock flag is set if timing lock indicator goes above THH
● lock flag is reset if timing lock indicator goes under -THH
Recommended value is THH = 8.
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12.5.3 Carrier recovery and derotator loop
The tracking range of the derotator is ± FMCLK / 2 (± FSAMPLING/2). The initial frequency
search may therefore be performed on several MHz ranges without reprogramming the
tuner.
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Three phase detectors are selectable using software as follows:
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● Phase detector algorithm 1: this algorithm is used with QPSK reception, for initial
capture or for tracking with CNR > 6 dB.
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● Phase detector algorithm 2: for QPSK reception, it is used after locking, to minimize the
bit error rate in low channel noise conditions. Algorithm 2 is recommended in tracking
for most applications.
The loop is controlled through α and β parameters.
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The carrier loop control registers are at addresses 0x16 (ACLC alpha carrier), 0x17 (BCLC
beta carrier), 0x2B and 0x2C (CFRM and CFRL respectively, MSB and LSB carrier
frequency).
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Loop parameters
As for the timing loop, the carrier loop is a 2nd-order system where two parameters, α and
β, may be programmed with ALPHA and BETA, respectively. In QPSK, with high CNR the
natural frequency (FN) is:
FN = 2.485 x 10-6 x FMCLK √{(AGC2REF x β) x (FS / FMCLK)}
The damping factor is:
ξ = 7.807 x 10-6 x α √{(AGC2REF / β) x (FS / FMCLK)}
where α = (2 + a) x 211+alpha with 1 ≥ a ≥0 and β = (4 + c + d) x 2beta-1 with 1 ≥ d ≥ 0 and
1 ≥ c ≥ 0.
Carrier lock detector

The carrier lock detector provides an indicator CLI with a high value when the carrier is
locked, dependent on the channel noise. When the carrier is not locked, the indicator value
is low.
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The indicator value is compared to two programmable 8-bit thresholds:

LOCK_THRESHOLD (LDT) and LOCK_THRESHOLD2 (LDT2), with LOCK_THRESHOLD2
≤LOCK_THRESHOLD, to give some hysteresis to the system. If CLI > LDT, the carrier found
flag CF is set. IF CLI < LDT2, CF is reset. CF may be read in VSTATUS.
The lock detector threshold registers LDT and LDT2, and the lock detector value register
LDI are at addresses 0x19, 0x1A and 0x25, respectively.
Derotator frequency
The derotator frequency can be either measured (read operation) or forced (write
operation).
(freq)kHz = Derot_freq / 216) x (FMCLK) kHz
The derotator frequency is a 16-bit signed value in registers CFRM (MSB at 0x2B) and
CFRL (LSB at 0x2C).
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Carrier frequency offset detector
The carrier recovery loop features a carrier frequency offset detector. When the carrier
frequency offset detector is enabled, the central loop frequency is modified proportionally to
the carrier offset. The gain and time constants of the detector are set by register CFD bits
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BETA_FC and FDCT respectively. When the carrier loop is about to phase lock with the
carrier, the frequency detector stops automatically and the phase lock is ensured by the
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selected phase detector. This switchover point is determined by the threshold (CFD).
For stability reasons, the gain BETA_FC should not exceed the coefficient e of BCLC[5:2].
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The carrier frequency offset detector register CFD is at address 0x15.
I, Q symbol monitoring
The IQ symbol values presented to the FEC can be read out through registers ISYMB and
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QSYMB. This allows a symbol diagram of the IQ symbols entering the FEC to be displayed
during debug.
The observation points are the following (see register SYMBCTRL):
● after offset cancellation
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● after derotation and before Nyquist filter

● after Nyquist filter
● after all demodulator stages (normal operation)
12.5.4 Equalization
The DVB-S and DIRECTV modes benefit from an equalizer that compensates for reflections
in the co-axial cable between the LNB and the tuner. The equalizer employed may correct
for reflections over a maximum of five symbols and up to a return loss of 10 dB on the
antenna connectors. No adjustment or control is required by the user.
The equalizer can be enabled or disabled from register EQUA. The equalizer may reset from
that register. The equalizer tap values can be read from registers EQUAI1[5] and
EQUAQ1[5].
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12.5.5 Noise indicator

The noise indicator may be used to facilitate antenna pointing or to give an idea about RF
signal quality and about the front-end installation (dish, LNB, cable, tuner or ADC).
A simple C/N estimator can be easily implemented by comparing the current indications with
a primarily-recorded look-up table.
The time constant ranges from 4 K to 256 Ksymbols as described in register ACLC (0x16).
The 16 MSBs of the result may be read by the microprocessor in NIRM (0x2D) and NIRL
(0x2E). The noise indicator takes equalization into account.
12.5.6 Forward error correction

FEC modes
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The Viterbi decoder is controlled through the FECM register. Using this register, the Viterbi
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decoder can be switched between DVB-S and DIRECTV modes (bit FECMODE in register
FECM), a sync byte search can be de-activated and IQ swap can be enforced.
The FEC mode register FECM is at address 0x30.
In DVB-S and DIRECTV system modes, data is fed to the Viterbi decoder. Other parts of the
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decoding may be bypassed.
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Viterbi decoder and synchronization

The convolutive codes are generated by the polynomial Gx = 171 octets and
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Gy = 133 octets in modes DVB-S or DIRECTV modes.

The Viterbi decoder computes the metrics of the four possible paths for each symbol,
proportional to the square of the Euclidian distance between the received I and Q and the
theoretical symbol value.
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At the input of the Viterbi decoder, a Kdiv gain, programmable in register VITPROG, may be
applied on I and Q for the calculation of the metrics.
The puncture rate and phase are estimated on the error rate basis. Several rates are
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allowed and may be enabled or disabled through register programming: the rates are 1/2,
2/3, 3/4, 5/6, 6/7, 7/8 in DIRECTV system or DVB-S.
For each enabled rate, the current error rate is compared to a programmable threshold. If it
is greater than this threshold, another phase (or another rate) is tried until the right rate is
obtained.
A programmable hysteresis is added to avoid losing the phase during short term
perturbations.
The rate may also be imposed by external software and the phase is incremented only upon
request by the microprocessor. The error rate may be read at any time.
The decoder is controlled through several Viterbi threshold registers: VTH12 (0x31), VTH23
(0x32), VTH34 (0x33), VTH56 (0x34), VTH67 (0x35) and VTH78 (0x36). For each Viterbi
threshold register, bits[6:0] represent an error rate threshold, the average number of errors
occurring during 256-bit periods.
The maximum programmable value is 127/256 (higher error rates are of no practical use).
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The puncture rate register PR is at address 0x37. Synchronization is controlled through the
FECM (0x30) register. The automatic rate research is only performed through the enabled
rates (see the corresponding bit set in PR).
Note: In order to minimize the Viterbi search time, the puncture rates 3/4, 5/6, 7/8 may be disabled
in DIRECTV system. In DVB-S, the puncture rate 6/7 may be disabled.
Register VSEARCH is at address 0x38. Bits AM and F program the automatic/manual
(or computer aided) search mode as follows:
● If AM = 0 and F = 0, automatic mode is set. Successive enabled punctured rates are
tried with all possible phases until the system is locked and the block sync is found.
This is the default (reset) mode.
● If AM = 0 and F = 1, the current puncture rate is frozen. If no sync is found, the phase is
incremented, but not the rate number. This mode shortens recovery time under noisy
conditions. The puncture rate is not supposed to change in a given channel. In a typical
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computer-aided implementation, the search begins in automatic mode. The
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microprocessor reads the error rate (VERROR) or flag PRF (VSTATUS) to detect the
capture of a signal, then it switches F to 1 until a new channel is requested by the
remote control.
● If AM = 1, manual mode is set. In this case, only one puncture rate should be validated.
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The system is forced to this rate on the current phase, ignoring bit TO (time-out in
VSEARCH) and the error rate. In this mode, each 0 to 1 transition of bit F leads to a
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phase incrementation, allowing full control of the operation by an external

microprocessor by choosing the lowest error rate.
The reset values are AM = 0 and F = 0 (automatic search mode).
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The IQ symmetry may also be swapped either manually (in register FECM) or automatically
(SWAP_EN in register VITPROG). In that case the bit SYM of register FECM is a status of
the symmetry found.
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Register VERROR (read only) is at address 0x2F. The last value of the error rate may be
read at any time in the register. Unlike the Viterbi threshold, the possible range is from 0 to
255/256.
Register VSTATUS (read only) is at address 0x24.
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Error monitoring
A 16-bit counter, ERRCNT, counts errors at different levels. ERRCNT is fed by one of the
following:
● the input QPSK bit errors (that are corrected by the Viterbi decoder)
● the bit
● the byte errors (that are corrected by the Reed–Solomon decoder)
● the packet error (not correctable, leading to a pulse at the ERROR output)
The content of ERRCNT may be transferred to the read only error-count registers ECNTM
(MSB at 0x26) and ECNTL (LSB at 0x27).
Doc ID 8141465 Rev 5 99/294

Two functional modes are proposed, depending on control register ERRCTRL (0x3B) bit[7]:
● ERRMODE = 0: error rate measurement. This provides the number of errors occurring
within a specified number of output bytes, NB. NB has four possible values defined by
bits NOE. Every NB bytes, the state of the error counter is transferred to the 16-bit
error-count registers and then the error counter is reset. The error-count registers may
be read by the microprocessor through the I2C bus. Two ways of reading may be used:
16-bit reading, starting with the MSB or 8-bit reading (LSB only or MSB only).
● ERRMODE = 1: the error counter just counts the errors and directly transfers the
content of the error counter. When the MSB byte is read, the error counter is reset.
In both modes, the 16-bit counter is saturated to its maximum value.
A second error monitor is added, with an identical control register ERRCTRL2 at address
0x3D, and the contents of ERRCNT2 may be transferred to ECNTM2 (0x3E) and ECNTL2
(0x3F). With this second error monitor, two error rates may be simultaneously monitored, for
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example, QPSK bit error and packet error rate.
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Convolutive de-interleaver
In DVB-S, the convolutive de-interleaver is 17 x 12. The periodicity of 204 bytes per sync
byte is retained. In DIRECTV system, the convolutive de-interleaver is 146 x 13 and there is
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also a periodicity of 147 bytes per sync byte. The de-interleaver may be bypassed (RS 0x39
bit DEINT).
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Reed–Solomon decoder and descrambler

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The input blocks are 204 bytes long with 16 parity bytes in DVB-S. The sync byte is the first
byte of the block. Up to 8 byte errors may be fixed.
The code generator polynomial is:
g(x) = (x - ω0)(x - ω1)...(x - ω15)
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over the Galois Field generated by:

x8 + x4 + x3 + x2 + 1 = 0
Energy dispersal descrambler and output energy dispersal descrambler generator:
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x15 + x14 + 1
The polynomial is initialized every eight blocks with the sequence 100 1010 1000 0000.
The sync words are unscrambled and the scrambler is reset every eight packets.
Synchronization
In DVB-S, the packet length after inner decoding is 204. The sync word is the first byte of
each packet. Its value is 0x47, but this value is complemented every eight packets. In
DIRECTV system, the packet length is 147 and the sync word is 0x1D.
An up/down sync counter counts whenever a sync word is recognized with the correct timing
and counts down during each missing sync word. This counter is bounded by a
programmable maximum (bit H in VSEARCH register). When this value is reached, bit LK
(locked) is set in register VSTATUS. When the event counter counts down to 0, this flag is
reset.
The time-out period for this sync word search is selectable through register VSEARCH (bit
TO).
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12.6 DiSEqC 2.x interface
12.6.1 Transmit DiSEqC interface

The transmit DiSEqC interface simplifies the real-time dialog between the microprocessor
and the LNB. Using the I2C bus, the microprocessor fills a 16-byte FIFO and then transmits
the data by modulating the DiSEqC transmit clock.
The following status signals are available on the I2C bus (DISEQCSTA1 register):
● TX_IDLE: transmitter is waiting
● FIFOFULL: FIFO full
● TXFIFO_BYTES (5 bits): remaining bytes in the TX FIFO
● TX_FAIL
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Typical byte transfer loop
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1. DIS_PRECHARGE is set to 1 (DISEQC register) to put the transmitter into a waiting
state.
2. One to 16 bytes can be transferred by writing to the FIFO.
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3. DIS_PRECHARGE is set to 0 and the transmitter begins sending data.
4. To transfer more than 16 bytes, the FIFO must not be full: FIFOFULL = 0. Use the
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equation
number of bytes = 16 - TXFIFO_BYTES
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to calculate the number of bytes that can be stored.

Note: Before starting the FIFO is empty (TX_IDLE = 1, TXFIFO_BYTES = 0, FIFOFULL = 0) and
is in an idle state.
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If DIS_PRECHARGE is set to 0, transfer begins as soon as a byte is written to the FIFO.

TX_IDLE = 0 during the transmission.
After the last transmitted byte, the interface returns to an idle state (TX_IDLE = 1).
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Transmit format
There are two modes for DiSEqC output; modulated and envelope. The mode is selectable
from register bit DISEQC.CMD_ENV. In the modulated mode the output is a gated 22 kHz
square wave signal. In the envelope mode, the tone is replaced by logic high, a logic low
replaces ‘no tone’.
When the modulation is active, the DiSEqC output is forced alternately to VDD and VSS
levels.
Byte format
● Idle state, no modulation is present at the output
● Byte transmission, the byte is sent (MSB first) and is followed by an odd parity bit.
A byte transmission is therefore a 9-bit serial transmission with an odd number of ones.
Each bit lasts 33 F22 periods and the transmission is PWM-modulated.
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Transmission of ones
During transmission of ones, modulation is active for 11 pulses, then inactive for 22 pulses
(1/3 PWM).
Transmission of zeros
There are two submodes controlled by bits DISEQC.DISEQC_MODE.
● DISEQC_MODE = 10: modulation is active for 22 pulses, then inactive for 11 pulses
(2/3 PWM). This is the normal mode
● DISEQC_MODE = 11: modulation is active for 33 pulses (3/3 PWM). This is used for
SA, SB modes
Figure 18. Schematic showing bit transmission
Idle 11 periods 11 periods 11 periods Next bit
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Transmission of ones
Transmission of zeros:
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a) DISEQC_MODE = 10
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b) DISEQC_MODE = 11
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DiSEqC modes SA, SB and continuous

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Some extra commands have been designed to be detected by a cheaper analog circuit in
the case of a simple two-state switch. In this type of application where the slave IC would not
be used to provide any additional functionality (such as 13/17 V detection or continuous
22 kHz detection), tone burst commands are alternatives to the DiSEqC commands for the
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satellite position switch.

SA: (Satellite A) Unmodulated tone burst. Set DISEQC_MODE = 11 and write one byte of
value 0x00 to the Tx FIFO. The parity bit is automatically set to 1. The resulting signal is a
continuous tone of 12.5 ms.
SB: (Satellite B) Modulated tone burst. Set DISEQC_MODE = 10 and write one byte of
value 0xFFto the Tx FIFO. The parity bit is automatically set to 1. As a result, the output
signal is nine 0.5 ms bursts, separated by eight 1 ms intervals.
Continuous: Continuous tone burst. Set DISEQC_MODE to 00.
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Figure 19. Timing diagram for tone burst control signal

Unmodulated tone burst (Satellite A)
Modulated tone burst (Satellite B)
> 15 ms 12.5 ms > 15 ms
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Envelope mode
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An envelope mode is available for all the previously described transmissions. For that, the
bit CMD_ENV must be activated in the DISEQC register. In the envelope mode, a 22 kHz
envelope output is generated instead of a modulated signal output. It may control the on/off
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switch of an external 22 kHz oscillator.
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Transmit burst gap control

The backward compatibility of DiSEqC requires a 15 ms gap after a tone burst sequence.
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This information is delivered by a flag in a status register. This flag is set at the beginning of
the transmission and is reset after a time that includes both the transmission and a period
defined by the I2C bus.
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Figure 20. Gap between bursts
Possible
Tone burst new tone burst
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Flag (DISEQC_STATUS) Gap between bursts > 15 ms

defined by TIM_CMD
The length of the gap between bursts is defined by DISEQCSTA2:TIM_CMD

TIM_CMD (DISEQCSTA2[3:1]):
000, number of 22 kHz periods = 330 001, number of 22 kHz periods = 440
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12.6.2 DiSEqC receive interface

The DiSEqC receive interface receives the signal coming from the DiSEqC analog IP. It is
composed of:
● digital filtering: envelope detection
● digital processing: received byte extraction and stacking in FIFO, status management
Figure 21. DiSEqC receive analog part, normal mode

2.5 V (VDD2v5_DISRX)
Functional mode Up current

R source control
0: active
1: Hi-Z
To digital core + DISEQC_IN
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Vdd/2
- Down current 200 mV to 1 V
source control
5A
R 0: Hi-Z
1: Active
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GND_DISRX
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Figure 22. DiSEqC receive analog part, bypassed mode

2.5 V (VDD2v5_DISRX)
Stop mode
Digital in mode
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To digital core + DISEQC_IN

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R
Hi-Z mode
Up current source control = 1
Down current source control = 0
GND_DISRX
The DiSEqC receiver is switched on by setting the DISEQC2.RECEIVER_ON bit to 1.

An external filter conditions the analog input signal, which is sampled through a 1 bit DAC.
The signal is then filtered digitally. The digital filter frequency is set in the F22RX register.
The DISEQC2.EXT_ENVEL bit enables the analog bypass (invoking the envelope mode)
depicted in Figure 22 (default) otherwise the configuration of Figure 21 is used.
The digitized bits are then assembled into bytes, checked for parity and stacked in the FIFO.
The FIFO is 16 bytes deep.
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The DiSEqC input may be selected through the PINSELECT (DISEQC2) bits to be the
DISEQC_IN pin or the GPIO0 pin (default). The input may be inverted (should the envelope
mode require it).
A test mode allows the DiSEqC Tx to be looped back into the Rx (accessible though bit
DISEQC2.ONECHIPTRX).
The received bytes are stacked in the receiver FIFO and can be read by access to the
DISEQCFIFO register. The status registers (DISRX_ST0, DISRX_ST1) provide information
concerning the state of the receiver:
● reception ended
● receiver active
● continuous tone detected
● 4 bytes ready for reading
● FIFO empty
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● reception failed
● parity error detected
● wrong number of bits to make a byte detected
● FIFO overflow
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● number of bytes in FIFO
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In addition to the above, status registers are interrupt flags (in register DISEQC2):
● generate interrupt at end of receive block
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● generate interrupt if there are 8 or more bytes in the FIFO ready for reading
12.7 Fast channel acquisition and blind search

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Automatic symbol rate search, signal acquisition and signal tracking are built into the
STi5189 using a simple state machine, controlled by I2C commands. This state machine
significantly reduces the required software and also decreases the duration of the
transponder acquisition. The result is simplified scanning software routines, full satellite
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band scanning in seconds and fast channel acquisition.
12.7.1 Control
The fast channel acquisition is performed in two steps. The first step, coarse autosearch,
enables the rough estimation of the QPSK carrier within a given RF bandwidth. The second
step, fine scan enables automatic lock to the previously estimated QPSK carrier. The timing
lock indicator indicates success, see Figure 23.
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Figure 23. Example channel scan algorithm

Set tuner
Adjust timing loop parameters

Launch coarse
Hard
Coarse autoscan
Soft
Nothing found
Wait timeout (max. 15 ms)
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Adjust timing loop parameters
Adjust carrier loop parameters
Adjust fine parameters
Launch fine scan
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Fine scan
Center
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Wait lock indicator status Channel OK

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First step: coarse autosearch

This mode is only valid for symbol frequencies lower than half the ADC frequency. The IC is
set in this mode by I2C bit COARSE in the ASCTRL register.
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In this mode, the symbol frequency registers (SFRH, SFRM and SFRL) and carrier
frequency registers (CFRM and CFRL) are updated by a loop in order to reach the
approximate input baud rate and carrier position.
The coarse carrier frequency loop is controlled by the KC field in the COARP2 register as
follows:
● KC = 0: the carrier frequency is frozen
● KC = 1 to 4: the loop is active; the value KC = 4 gives the minimum time constant to
recover any carrier frequency up to +/- to Fadc / 2
Decreasing KC by one unit doubles the time constant and halves the variance on the carrier
frequency.
The coarse baud rate loop is controlled by the KS field in register COARP2 as follows:
● KS = 0: the symbol frequency is frozen
● KS = 1 to 4: the loop is active; the value KS = 4 gives the minimum time constant to
recover any symbol frequency up to Fadc / 2
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Decreasing KS by one unit doubles the time constant and decreases the variance on the
symbol frequency rate.
The baud rate loop converges to a value close to the symbol frequency, depending on the
signal to noise ratio and on the roll off of the transmitter. It may be altered by changing the
value of the field KT in register COARP1.
KI in the ASCTRL register must be set to 2.
Second step: fine scan

In this mode, the normal timing and carrier loops are enabled and the symbol frequency
register is incremented with a programmable value at each symbol period.
Two 16-bit registers, FMIN (FMINM and FMINL) and FMAX (FMAXM and FMAXL), contain
the 15 MSB’s of the boundaries of the scanning. A mode bit (STOP_ON_FMIN,
STOP_ON_FMAX) selects the system behavior when a boundary is reached as follows:
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● If the bit is set, the scanning stops.
● If reset, the scanning is automatically reversed with the same step.
The scanning is automatically and definitively stopped when the timing lock flag,
TMG_LOCK in the TLIRM register is set.
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Channel centering
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After decoding a lock condition, which stops the symbol frequency scanning, the current
symbol frequency is obtained by a combination of the symbol frequency register and the
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timing register.
When the CENTER bit is set in the ASCTRL register and the timing lock indicator is set (see
Section : Timing lock indicator), an automatic process allows pulling the timing register close
to 0 by adjusting the symbol frequency register accordingly.
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The adjusting speed is controlled by the scan step and the action stops when the residual
timing offset is under 61 ppm.
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QPSK interface registers STi5189
13 QPSK interface registers
Register addresses are accessed through the I2C bus, controlled by the SSC, provided as
QPSKBaseAddress + offset
The QPSKBaseAddress is:
0xFD14 0000
It is in fact SSCBaseAddress.
.
Table 46. QPSK registers

Address offset Register Description Page
0x00 ID Identification register page 111
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0x01 I2CRPT Serial bus repeater control register page 141
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0x02 ACR Auxiliary clock register page 142
0x03 F22FR F22 transmit frequency register page 115
0x04 F22RX F22 receive frequency register page 116
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0x05 DISEQC DiSEqC control register 1 page 111
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0x06 DISEQCFIFO DiSEqC FIFO register page 113

0x07 DISEQCSTA1 DiSEqC status register 1 page 113
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0x08 DISEQCSTA2 DISEqC status register 2 page 114

0x09 DISEQC2 DISEQC control register 2 page 112
0x0A DISRX_ST0 DISEqC receiver control register 1 page 114
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0x0B DISRX_ST1 DISEqC receiver control register 2 page 115

0x0D TSREG Transport Stream control register page 117
0x0E AGC1C AGC1 control register page 116
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0x0F AGC1REF AGC1 reference control register page 117

0x10 AGC1IN AGC1 accumulator status register page 117
0x11 RTC Timing loop control register page 118
0x12 AGC2COEF Post-Nyquist AGC coefficient control register page 121
0x13 AGC2REF Post-Nyquist AGC reference control register page 121
0x14 STEP1 Timing lock control register page 120
0x15 CFD Carrier frequency offset detect register page 122
0x16 ACLC Alpha carrier loop control register page 124
0x17 BCLC Beta carrier loop control register page 124
0x18 EQUA Roll off control register page 126
0x19 LDT Carrier lock threshold1 register page 123
0x1A LDT2 Carrier lock threshold2 register page 123
0x1B DACR1 DAC register (MSB) page 143
108/294 Doc ID 8141465 Rev 5

STi5189 QPSK interface registers
Table 46. QPSK registers (continued)

0x1C DACR2 DAC register (LSB) page 143

0x1E TLIRM Timing lock indicator register (MSB) page 120
0x1F TLIRL Timing lock indicator register (LSB) page 120
0x20 AGC2IM AGC2 and offset control register (MSB) page 121
0x21 AGC2IL AGC2 and offset control register (LSB) page 122
0x22 RTFM Timing recovery control register (MSB) page 118
0x23 RTFL Timing recovery control register (LSB) page 118
0x24 VSTATUS Viterbi status register page 130
0x25 LDI Carrier lock detect register page 123
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0x26 ECNTM Error 1 count register (MSB) page 138
0x27 ECNTL Error 1 count register (LSB) page 139
0x28 SFRH symbol frequency register (HSB) page 119
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0x29 SFRM symbol frequency register (MSB) page 119
0x2A SFRL symbol frequency register (LSB) page 119
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0x2B CFRM Carrier recovery frequency (MSBs) register page 125

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0x2C CFRL Carrier recovery frequency (LSBs) register page 125

0x2D NIRM Noise indicator (MSBs) register page 125
0x2E NIRL Noise indicator (LSBs) register page 126
0x2F VERROR Viterbi error register page 131
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0x30 FECM FEC mode register page 131

0x31 VTH12 Viterbi 1/2 threshold register page 132
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0x37 PR Puncture rate and sync register page 134
0x38 VSEARCH Viterbi and sync search register page 135
0x39 RS Reed-Solomon control register page 136
0x3A RSOUT Reed-Solomon and output control register page 137
0x3B ERRCTRL Error 1 control register page 138
0x3C VITPROG Viterbi metric control register page 132
0x3D ERRCTRL2 Error 2 control register page 139
0x3E ECNTM2 Error 2 count register (MSBs) page 140
0x3F ECNTL2 Error 2 count register (LSBs) page 140
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0x40 PLLCTRL Analog PLL divider control register page 143

0x41 SYNTCTRL Frequency synthesizer control register page 144
0x42 TSTTNR1 Analog IPs control register page 145
0x43 - 0x44 IRQMSKx Enable interrupt lines page 150
0x45 - 0x46 IRQSTATx Interrupt request status registers 1 to 0 page 149
0x4A SYMBCTRL Constellation sources control register page 146
0x4B ISYMB I symbol register page 146
0x4C QSYMB Q symbol register page 146
0x50 ASCTRL Autoscan control register page 151
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0x51 COARP1 Coarse1 control register page 151
0x52 COARP2 Coarse2 control register page 152
0x53 FMINM FMIN register (MSB) page 152
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0x54 FMINL FMIN register (LSB) page 152
0x55 FMAXM FMAX register (MSB) page 153
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0x56 FMAXL FMAX register (LSB) page 153

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0x57 FINEINC Fine increment register page 153

0x58 STEP2 STEP2 register page 154
0x59 TH2 Threshold2 (MSB) register page 154
0x5A TH2ATH1 Threshold 2 (LSB) and 1 (MSB) register page 154
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0x5B TH1 Threshold 1 (LSB) register page 155

0x5C THH Threshold H register page 155
0x5D IND1MAX Indicator 1 limit register page 155
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0x5E ACCU1VAL Accu1 status register page 156

0x5F ACCU2VAL Accu2 status register page 156
0x77 EQUAI1 Equalizer TAP 1 I value page 127
0x78 EQUAQ1 Equalizer TAP 1 Q value page 127
0x79 EQUAI2 Equalizer TAP 2 I value page 127
0x7A EQUAQ2 Equalizer TAP 2 Q value page 128
0x7B EQUAI3 Equalizer TAP 3 I value page 128
0x7C EQUAQ3 Equalizer TAP 3 Q value page 128
0x7D EQUAI4 Equalizer TAP 4 I value page 129
0x7E EQUAQ4 Equalizer TAP 4 Q value page 129
0x7F EQUAI5 Equalizer TAP 5 I value page 129
0x80 EQUAQ5 Equalizer TAP 5 Q value page 130
0xB0 SDATCFG SDAT input/output control register page 147
110/294 Doc ID 8141465 Rev 5


0xB1 SCLTCFG SCLT input/output control register page 148

0xB2 AGCCFG AGC input/output control register page 148
0xB4 AUXCKCFG AUXCK input/output control register page 148
0xB8 DISEQCCFG DISEQC transmitter output control register page 148
ID Identification register
7 6 5 4 3 2 1 0
CHIP_IDENT RELEASE
Address: QPSKBaseAddress + 0x00
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Type: R
Reset: 0x10
Description: Identification register. This register is accessible in standby mode. See also
Section 12.3.5: Identification register.
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[7:4] CHIP_IDENT: Provides the identity of the circuit.

[3:0] RELEASE: Provides the release number of the circuit to ensure software compatibility.
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13.1 DiSEqC registers

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DISEQC DiSEqC control register 1

7 6 5 4 3 2 1 0
DIS_PRECHARGE
DISEQCMODE
DIS_RESET
CMD_ENV
TIM_OFF
LOW_Z
PORT0

Type: R/W
Reset: 0x06
Description: DiSEqC control register 1. See also Section 12.6: DiSEqC 2.x interface.
[7] TIM_OFF: Control.

1: Gap timer is on.
[6] DIS_RESET: Control.
1: FIFO content is reset.
[5] PORT0: Control, when high and low_Z = 1, during inactive modulation DISEQC_OUT is at
level 0.
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[4] LOW_Z: Control, when high there is low impedance on DISEQC_OUT.

During inactive modulation DISEQC_OUT is at level 1.
[3] CMD_ENV: Control.
1: Envelope mode is selected.
[2] DiS_PRECHARGE: Control.
0: FIFO contents are transmitted.
1: Tx is in wait state.
[1:0] DiSEqCMODE[1:0]: Control mode.
00: Enable continuous (22 kHz) tone
01: Reserved
10: DiSEqC 2/3
11: DiSEqC 3/3
DISEQC2 DiSEqC control register 2
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7 6 5 4 3 2 1 0
IRQ_HALF_FIFO
RECEIVER_ON
ONESHIP_TRX
IRQ_RXEND
EXT_ENVEL
PINSELECT
RESERVED
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Type: R/W
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Reset: 0x00
Description: DiSEqC control register 2. See also Section 12.6: DiSEqC 2.x interface.
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[7] RECEIVER_ON: Control.

1: Receiver is enabled.
[6] RESERVED: Must be programmed to zero.
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[5] ONESHIP_TRX: Control, DiSEqC Rx connected to Tx (loopback mode for test).

0: Rx is off when Tx is transmitting.
[4] EXT_ENVEL: Control.
0: Receives the 22 kHz tone from the pin selected using the PINSELECT bits.
1: DiSEqC Rx expects a digital 1 or 0 representing the envelope of the tone of the selected
GPIO through the PINSELECT bits (the DISEQC_IN pin is disabled).
[3:2] PINSELECT[1:0]: Control. Select DiSEqC input pin and polarity.
00: Analog DISEQC_IN pin t
01: GPIO1 digital input
10: Inverted analog, DISEQC_IN pin
11: GPIO1 inverted
[1] IRQ_RXEND: Control.
1: DiSEqC controller sends interrupt at end of receive block (no signal after 3 pulses).
[0] IRQ_HALF_FIFO: Control. If high DiSEqC controller sends interrupt when RX FIFO contains 8
or more bytes.
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DISEQCFIFO DiSEqC FIFO register

7 6 5 4 3 2 1 0
DISEQCFIFO

Type: R/W
Reset: 0x00
Description: DiSEqC FIFO register. See also Section 12.6: DiSEqC 2.x interface.
[7:0] DISEQCFIFO: DiSEqC transmitter FIFO or DiSEqC receiver FIFO 16 bytes deep.
DISEQCSTA1 DiSEqC transmitter status register 1
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7 6 5 4 3 2 1 0
TX_FAIL FIFO_FULL TX_IDDLE TXFIFO_BYTES

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Type: R
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Reset: 0x00
Description: DiSEqC transmitter status register 1. See also Section 12.6: DiSEqC 2.x interface.
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[7] TX_FAIL: Status.

1: Transmit failed.
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[6] FIFO_FULL: Status.

1: FIFO is full.
[5] TX_IDDLE: Status.
1: Tx FIFO is empty.
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[4:0] TXFIFO_BYTES[4:0]: Status, number of bytes in Tx FIFO (waiting to be transmitted).
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DISEQCSTA2 DiSEqC transmitter status register 2

7 6 5 4 3 2 1 0
GAPBURST_FLAG
RESERVED
TIM_CMD
Type: R/W
Reset: 0x04
Description: DiSEqC transmitter status register 2. See also Section 12.6: DiSEqC 2.x interface.
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[7:4] RESERVED: Must be programmed to zero.
[3:1] TIM_CMD[2:0]: Gap length, number of 22 kHz periods between successive bursts.
000: 330
001: 440
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010: 550
011: 660
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100: 1320
101: 1760
110: 2200
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111: 2640
[0] GAPBURST_FLAG: Status. When active, Tx gap (as programmed in <TIM_CMD>) has not yet
expired.
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DISRX_ST0 DiSEqC receiver status register 1

7 6 5 4 3 2 1 0
RX_NON_BYTE
FIFO_EMPTY
CONT_TONE
ABORT_DIS
RX_ACTIVE
8BFIFORDY
RESERVED
RX_END
Address: QPSKBaseAddress + 0x0A

Type: R
Reset: 0x00
Description: DiSEqC receiver status register 1. See also Section 12.6: DiSEqC 2.x interface.
[7] RX_END: Status.

1: Reception is ended.
[6] RX_ACTIVE: Status.
1: Receiver is activated.
[4] CONT_TONE: Status.
1: More than 33 pulse widths of tone burst has been detected (continuous tone present).
114/294 Doc ID 8141465 Rev 5

[3] 8BFIFORDY: Status.

1: There are 8 or more bytes in the FIFO ready for reading.
[2] FIFO_EMPTY: Status.
1: FIFO is empty.
[1] RX_NON_BYTE: Status.
1: Indicates an incorrect number of bits have been received to make a byte (receive error).
[0] ABORT_DIS: Status.
1: Indicates an issue with reception.
DISRX_ST1 DiSEqC receiver status register 2

7 6 5 4 3 2 1 0
RX_FAIL PARITY_FAIL FIFO_OVER FIFO_BYTENBR
l
Address: QPSKBaseAddress + 0x0B
tia
Type: R
Reset: 0x00
Description: DiSEqC receiver status register 2. See also Section 12.6: DiSEqC 2.x interface.
en
Confidential
[7] RX_FAIL: Status.

1: Reception is failed.
fid
[6] PARITY_FAIL: Status.

1: Parity error is detected in present FIFO contents (receive error).
[5] FIFO_OVER: Status.
1: Receiver FIFO has overflowed.
on
[4:0] FIFO_BYTENBR[4:0]: Status, number of bytes in receiver FIFO.
F22FR DiSEqC 22 kHz transmit frequency tone control

C
7 6 5 4 3 2 1 0
FFTX_REG

Type: R/W
Reset: 0x8E
Description: DiSEqC 22 kHz transmit frequency tone control. See also Section 12.6: DiSEqC 2.x
interface.
[7:0] FFTX_REG: Tone modulation frequency control.

FDiSEqC_Tx = FMCLK / (32 x F22FRdec)
For 22 kHz operation and FMCLK=100 MHz, F22FR = 142dec, 0x8Ehex.
Doc ID 8141465 Rev 5 115/294

F22RX DiSEqC 22 kHz receiver frequency tone control

7 6 5 4 3 2 1 0
FFRX_REG

Type: R/W
Reset: 0x8E
Description: DiSEqC 22 kHz receiver frequency tone control. See also Section 12.6: DiSEqC 2.x
interface.
[7:0] FFRX_REG: Tone modulation frequency control.
l
FDiSEqC_Rx = FMCLK / (32 x F22RXdec).
tia
For 22 kHz operation and FMCLK=100 MHz, F22RX = 142dec, 0x8Ehex.
13.2 DVB-S and DIRECTV registers

en
AGC1C AGC1 control register and DC offset compensation
Confidential
control
7 6 5 4 3 2 1 0
fid
AGC_OPDRAIN
AVERAGE_ON
AGCIQ_BETA
ENA_DCADJ
IAGC
on
Address: QPSKBaseAddress + 0x0E

Type: R/W
Reset: 0xC4
C
Description: AGC1 control register and DC offset compensation control. See also Section : AGC1.
[7] ENA_DCADJ:
1: DC offset compensation is ON.
[6] AVERAGE_ON:
0: DC offset compensation is frozen to its last value.
[5] AGC_OPDRAIN: Set AGCRF pad in open drain configuration.
0: Pushpull pad
1: OP drain pad
[4] IAGC: Inverted shape of AGCRF pin.
0: No inversion
1: Polarity is inverted
[3:0] AGCIQ_BETA[3:0]: Gain coefficient of AGC1.
116/294 Doc ID 8141465 Rev 5

AGC1REF AGC1 reference control register

7 6 5 4 3 2 1 0
AGC1REF
Address: QPSKBaseAddress + 0x0F

Type: R/W
Reset: 0x2A
Description: AGC1 reference control register. See also Section : AGC1.
[7:0] AGC1REF[7:0]: Unsigned I and Q module reference.
AGC1IN AGC1 accumulator status register
l
tia
7 6 5 4 3 2 1 0
AGC1_VALUE

en
Type: R
Confidential
Description: AGC1 accumulator status register. See also Section : AGC1.

fid
[7:0] AGC1_VALUE[7:0]: Integrated value of the difference between the modulus of I, Q input and
the programmable threshold m1 = 4.AGCREF. (unsigned value).
TSREG Transport stream control register

on
7 6 5 4 3 2 1 0
SERIAL_O_D0
RESERVED
OUTRS_HZ
C
Address: QPSKBaseAddress + 0x0D

Type: R/W
Reset: 0x00
Description: Transport stream control register. This register is accessible in standby mode.

[1] SERIAL_O_D0: In the serial mode, data is on bit 7 or 0.
0: Data on bit[7].
1: Data on bit[0].
[0] OUTRS_HZ: TS in high Z or not.
Doc ID 8141465 Rev 5 117/294

RTC Timing recovery control register

7 6 5 4 3 2 1 0
ALPHA_TMG[3:0] BETA_TMG[3:0]

Type: R/W
Reset: 0x35
Description: Timing recovery control register. See also Section : Timing control.
[7:4] ALPHA_TMG: Timing loop control, refer to timing recovery loop section for details.
[3:0] BETA_TMG: Timing loop control, refer to timing recovery loop section for details.
l
tia
RTFM Timing recovery control register
7 6 5 4 3 2 1 0
TIMING_LOOP_FREQ_MSB
en
Confidential
Type: R/W
fid
[7:0] TIMING_LOOP_FREQ_MSB: Timing frequency register MSB (signed number).
RTFL Timing recovery control register

on
7 6 5 4 3 2 1 0
TIMING_LOOP_FREQ_LSB

C
Type: R/W
[7:0] TIMING_LOOP_FREQ_LSB: Timing frequency register LSB.
118/294 Doc ID 8141465 Rev 5

SFRH Timing recovery control register

7 6 5 4 3 2 1 0
SYMB_FREQ_HSB

Type: R/W
Reset: 0x80
[7:0] SYMB_FREQ_HSB: Symbol frequency register (MSBs). The reset value corresponds to
FMCLK / 2.
l
SFRM Timing recovery control register
tia
7 6 5 4 3 2 1 0
SYMB_FREQ_MSB

en
Type: R/W
Confidential
Reset: 0x00
fid
[7:0] SYMB_FREQ_MSB: Symbol frequency register (middle byte).

on
SFRL Timing recovery control register

7 6 5 4 3 2 1 0
SYMB_FREQ_LSB RESERVED
C

Type: R/W
Reset: 0x00
[7:4] SYMB_FREQ_LSB: Symbol frequency register (LSBs).

Doc ID 8141465 Rev 5 119/294

STEP1 Timing lock control register

7 6 5 4 3 2 1 0
STEP1_MINUS STEP1_PLUS

Type: R/W
Reset: 0x84
Description: Timing lock control register. See also Section : Timing lock indicator.
[7:4] STEP1_MINUS: Timing lock setting register. Must be programmed to 8.
[3:0] STEP1_PLUS: Timing lock setting register. Must be programmed to 4.
l
tia
TLIRM Timing lock control register
7 6 5 4 3 2 1 0
TMG_LOCK RESERVED TMG_FINAL_IND_MSB

en
Confidential
Type: R
fid
[7] TMG_LOCK: Timing lock flag.

[6:5] RESERVED
on
[4:0] TMG_FINAL_IND_MSB: Timing lock indicator register (signed).
TLIRL Timing lock control register

C
7 6 5 4 3 2 1 0
TMG_FINAL_IND_LSB

Type: R
[7:0] TMG_FINAL_IND_LSB: Timing lock indicator register.
120/294 Doc ID 8141465 Rev 5

AGC2COEF Post-Nyquist AGC coefficient control register

7 6 5 4 3 2 1 0
RESERVED AGC2_COEFF

Type: R/W
Reset: 0x03
Description: Post-Nyquist AGC coefficient control register. See also Section : Nyquist root and
interpolation filters.
[7:3] RESERVED
l
[2:0] AGC2_COEFF[2:0]: Gain coefficient of AGC2.
tia
AGC2REF Post-Nyquist AGC reference control register
7 6 5 4 3 2 1 0
en
RESERVED AGC2_REF

Confidential
Type: R/W
fid
Reset: 0x48
Description: Post-Nyquist AGC reference control register. See also Section : Nyquist root and
on
[7] RESERVED
[6:0] AGC2_REF[6:0]: Reference value of AGC2.
C
AGC2IM AGC2 and offset control register (MSB)

7 6 5 4 3 2 1 0
AGC2_INTEGRATOR_MSB

Type: R/W
Reset: 0x00
Description: AGC2 and offset control register (MSB). See also Section : Nyquist root and
[7:0] AGC2_INTEGRATOR_MSB: MSB of post-Nyquist filter AGC integrator.
Doc ID 8141465 Rev 5 121/294

AGC2IL AGC2 and offset control register (LSB)

7 6 5 4 3 2 1 0
AGC2_INTEGRATOR_LSB

Type: R/W
Reset: 0x00
Description: AGC2 and offset control register (LSB). See also Section : Nyquist root and
[7:0] AGC2_INTEGRATOR_LSB: LSB of post-Nyquist filter AGC integrator.
l
CFD Carrier lock control register
tia
7 6 5 4 3 2 1 0
CFD_ON BETA_FC FDCT LDL

en
Type: R/W
Confidential
Reset: 0xF7
fid
Description: Carrier lock control register. See also Section : Carrier frequency offset detector.
[7] CFD_ON: Carrier frequency offset detector enable.

0: Disabled.
on
1: Coupled to carrier recover loop.

[6:4] BETA_FC[2:0]: Gain for carrier frequency offset detector.
[3:2] FDCT[1:0]: Time constant for carrier frequency offset detector.
C
[1:0] LDL[1:0]: Lock detector threshold to disable the carrier frequency offset detector.
00: -16
01: -32
10: -48
11: -64
122/294 Doc ID 8141465 Rev 5

LDI Carrier lock control register

7 6 5 4 3 2 1 0
LOCK_DET_INTEGR

Type: R
Description: Carrier lock control register. See also Section : Carrier lock detector.
[7:0] LOCK_DET_INTEGR: Lock detector value (signed number).
LDT Carrier lock control register
l
7 6 5 4 3 2 1 0
tia
LOCK_THRESHOLD

Type: R/W
en
Reset: 0x14
Confidential
fid
[7:0] LOCK_THRESHOLD: Lock threshold 1 (signed number).
LDT2 Carrier lock control register

on
7 6 5 4 3 2 1 0
LOCK_THRESHOLD2

Type: R/W
C
Reset: 0x00
[7:0] LOCK_THRESHOLD2: Lock threshold 2 (signed number).
Doc ID 8141465 Rev 5 123/294

ACLC Carrier recovery control register

7 6 5 4 3 2 1 0
DEROT_ON_OFF
ALPHA
NOISE
ACLC

Type: R/W
Reset: 0x88
Description: Carrier recovery control register. See also Section : Derotator frequency.
l
tia
[7] DEROT_ON_OFF: Derotator ON/OFF.
0: OFF
1: ON
[6] ACLC: ‘a’ coefficient for alpha = (2 + a) x 2b x 214
en
[5:4] NOISE[1:0]: Noise estimator time constant.
00: 4 k symbols
Confidential
01: 16 k symbols
10: 64 k symbols
11: 256 k symbols
fid
[3:0] ALPHA[3:0]: ‘b’ coefficient [3:0] for alpha = (2 + a) x 2b x 214
BCLC Carrier recovery control register

on
7 6 5 4 3 2 1 0
ALGO BETA

C
Type: R/W
Reset: 0x58
Description: Carrier recovery control register. See also Section 12.5.3: Carrier recovery and
derotator loop.
[7:6] ALGO[1:0]: Phase detector algorithm.

00: Algorithm 0 reserved.
01: Algorithm 1 (QPSK application)
10: Algorithm 2 (QPSK application)
11: Reserved
[5:0] BETA[5:0]:
Bits 5 to 2: e[3:0]
Bit 1: c
Bit 0: d
124/294 Doc ID 8141465 Rev 5

CFRM Carrier recovery frequency (MSBs) register

7 6 5 4 3 2 1 0
CARRIER_FREQUENCY_MSB

Type: R/W
Description: Carrier recovery frequency (MSBs) register. See also Section 12.5.3: Carrier
recovery and derotator loop.
[7:0] CARRIER_FREQUENCY_MSB: Carrier frequency (MSB) (signed value).
CFRL Carrier recovery frequency (LSBs) register
l
tia
7 6 5 4 3 2 1 0
CARRIER_FREQUENCY_LSB
Address: QPSKBaseAddress + 0x2C

en
Type: R/W
Description: Carrier recovery frequency (LSBs) register. See also Section 12.5.3: Carrier recovery
Confidential
and derotator loop.

fid
[7:0] CARRIER_FREQUENCY_LSB: Carrier frequency (LSB) (signed value).
NIRM Noise indicator (MSBs) register

on
7 6 5 4 3 2 1 0
NOISE_IND_MSB

C
Type: R
Description: Noise indicator (MSBs) register. See also Section 12.5.5: Noise indicator.
[7:0] NOISE_IND_MSB: Noise indicator (MSB) (not signed).
Doc ID 8141465 Rev 5 125/294

NIRL Noise indicator (LSBs) register

7 6 5 4 3 2 1 0
NOISE_IND_LSB

Type: R
Description: Noise indicator (LSBs) register. See also Section 12.5.5: Noise indicator.
[7:0] NOISE_IND_LSB: Noise indicator (LSB) (not signed).
EQUA Equalizer control and roll off control register
l
7 6 5 4 3 2 1 0
tia
RESET_EQUA
MODE_COEF
RESERVED
RESERVED
EQUA_ON
en
Type: R/W
Confidential
Reset: 0x13
fid
Description: Equalizer control and roll off control register. See also Section : Nyquist root and
[7:6] RESERVED: Must be set to 0.

on
[5] RESET_EQUA: Control.

1: All the equalizer taps are reset.
[4] EQUA_ON: Control.
C
1: Equalizer is ON.
[3] MODE_COEF: Nyquist filter roll-off factor.
0: Raised cosine at 35% (DVB-S)
1: Raised cosine at 20% (DIRECTV system)
126/294 Doc ID 8141465 Rev 5

EQUAI1 Equalizer TAP 1 I value

7 6 5 4 3 2 1 0
EQUAI1

Type: R
Reset: 0x00
Description: Equalizer TAP 1 I value.
[7:0] EQUAI1: Signed value. TAP 1 value of I equalizer path.
EQUAQ1 Equalizer TAP 1 Q value
l
tia
7 6 5 4 3 2 1 0
EQUAQI

en
Type: R
Confidential
Reset: 0x00
Description: Equalizer TAP 1 Q value.
fid
[7:0] EQUAQ1: Signed value. TAP 1 value of Q equalizer path.

on
7 6 5 4 3 2 1 0
EQUAI2

C
Type: R
Reset: 0x00
Doc ID 8141465 Rev 5 127/294


7 6 5 4 3 2 1 0
EQUAQ2

Type: R
Reset: 0x00
l
tia
7 6 5 4 3 2 1 0
EQUAI3

en
Type: R
Confidential
Reset: 0x00
fid

on
7 6 5 4 3 2 1 0
EQUAQ3

C
Type: R
Reset: 0x00
128/294 Doc ID 8141465 Rev 5


7 6 5 4 3 2 1 0
EQUAI4

Type: R
Reset: 0x00
l
tia
7 6 5 4 3 2 1 0
EQUAQ4

en
Type: R
Confidential
Reset: 0x00
fid

on
7 6 5 4 3 2 1 0
EQUAI5

C
Type: R
Reset: 0x00
Doc ID 8141465 Rev 5 129/294


7 6 5 4 3 2 1 0
EQUAQ5

Type: R
Reset: 0x00
VSTATUS Viterbi status register
l
tia
7 6 5 4 3 2 1 0
CF RESERVED PRF LK PR

en
Type: R
Confidential
Reset: 0x00
Description: Viterbi status register. This register is accessible in the standby mode. See also
fid
Section : Viterbi decoder and synchronization.
[7] CF: Carrier found flag. When CF (see Section : Carrier frequency offset detector) is set, a
QPSK signal is present at the input of the Viterbi decoder.
on

[4] PRF: Puncture rate found. PRF indicates the state of the puncture rate research.
0 for searching and 1 when found. This bit is irrelevant in manual mode.
C
[3] LK: Locked/Searching sync word. LK indicates the state of the sync word search:
0 for searching and 1 when found.
[2:0] PR[2:0]: Current puncture rate. The current puncture rate (CPR) bits hold the current puncture
rate indices, as follows:
000: Punctured 1/2
001: Punctured 2/3
010: Punctured 3/4
011: Punctured 5/6
100: Punctured 6/7
101: Punctured 7/8
110: Reserved
111: Reserved
130/294 Doc ID 8141465 Rev 5

VERROR Viterbi error register

7 6 5 4 3 2 1 0
ERROR_VAL

Type: R
Reset: 0x00
Description: Viterbi error register. See also Section : Viterbi decoder and synchronization.
[7:0] ERROR_VAL: (Not signed). Number of bits corrected by the Viterbi decoder per packet of
256 bits.
l
FECM FEC mode register
tia
7 6 5 4 3 2 1 0
RESERVED FECMODE RESERVED SYNC SYM

en
Type: R/W
Confidential
Reset: 0x00
fid
Description: FEC mode register. See also Section : FEC modes.

on
[6] FECMODE]: This field indicates the FEC operation mode.

0: DVB-S
1: DIRECTV system
C
[1] SYNC: Sync disable.

0: Sync search enable. Sync is processed.
1: Sync byte search disable. Bit to byte conversion is frozen in the current state.
[0] SYM: I, Q symmetry.
Doc ID 8141465 Rev 5 131/294

VITPROG Viterbi metric control register

7 6 5 4 3 2 1 0
MDIV_MANT[4:2]
MDIV_MANT[1:0]
SWAP_ENABLE
MDIVIDER
Type: R/W
Reset: 0x80
Description: Viterbi metric control register. See also Section : Viterbi decoder and synchronization.
l
tia
[7:5] MDIV_MANT[4:2]: Viterbi coefficient mantissa MSBs.
[4] SWAP_ENABLE: Allow automatic research of IQ symmetry
[3:2] MDIV_MANT[1:0]: Viterbi coefficient mantissa LSBs.
en
[1:0] MDIVIDER: Viterbi coefficient exponent. Selects division ratio at Viterbi decoder input:
Kdiv = MDIV_MANT[4:0] x 2 (MDIVIDER - 8)
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VTH12 Viterbi 1/2 threshold register

fid
7 6 5 4 3 2 1 0
RESERVED VTH12

on
Type: R/W
Reset: 0x1E
Description: Viterbi 1/2 threshold register. See also Section : Viterbi decoder and synchronization.
C

[6:0] VTH12: Rate = 1/2 puncture rate threshold.
132/294 Doc ID 8141465 Rev 5


7 6 5 4 3 2 1 0
RESERVED VTH23

Type: R/W
Reset: 0x14
l
tia
7 6 5 4 3 2 1 0
RESERVED VTH34
en
Confidential
Type: R/W
Reset: 0x0F
fid

on

C
7 6 5 4 3 2 1 0
RESERVED VTH56

Type: R/W
Reset: 0x09

Doc ID 8141465 Rev 5 133/294


7 6 5 4 3 2 1 0
RESERVED VTH67

Type: R/W
Reset: 0x0C
l
tia
7 6 5 4 3 2 1 0
RESERVED VTH78
en
Confidential
Type: R/W
Reset: 0x05
fid

on
PR Puncture rate and sync register

7 6 5 4 3 2 1 0
C
RESERVED PR_7_8 PR_6_7 PR_5_6 PR_3_4 PR_2_3 PR_1_2

Type: R/W
Reset: 0x1F
Description: Puncture rate and sync register. See also Section : Viterbi decoder and
synchronization.

[5] PR_7_8: Enable puncture rate 7/8.
134/294 Doc ID 8141465 Rev 5

VSEARCH Viterbi and sync search register

7 6 5 4 3 2 1 0
AM F SN[1:0] TO[1:0] H[1:0]

Type: R/W
Reset: 0x19
Description: Viterbi and sync search register. See also Section : Viterbi decoder and
synchronization.
l
tia
[7] AM:
0: Automatic search mode
1: Manual search mode
[6] F: Freeze
en
[5:4] SN[1:0]: This is the averaging period. The field gives the number of bits required to calculate
the rate error.
Confidential
00: 1024 bits

01: 4096 bits (reset value)
10: 16384 bits
fid
11: 65536 bits

[3:2] TO[1:0]: Timeout value (given in 1024-bit periods). This is used to program the maximum
duration of the sync word search in automatic mode. If no sync is found within this time and if
bit RS6 (sync enable) is set in the Reed–Solomon register, another phase or puncture rate is
on
tried. If RS6 = 0, the time-out has no effect.

00: 16 Kbit
01: 32 Kbit
10: 64 Kbit (reset value)
11: 128 Kbit
C
[1:0] H[1:0]: This is the hysteresis value. This field is used to program the maximum value of the
sync counter. The unit is the block duration (204 bytes in DVB-S, 147 in DIRECTV system).
00: 16 blocks
01: 32 blocks (reset value)
10: 64 blocks
11: 128 blocks
Doc ID 8141465 Rev 5 135/294

RS Reed–Solomon control register

7 6 5 4 3 2 1 0
DEINT OUTRS_PS RS DESCRAM ERR_BIT MPEG CLK_POL CLK_CFG

Type: R/W
Reset: 0xB8
Description: Reed–Solomon control register.
[7] DEINT: De-interleaver enable.

0: The input flow is not affected.
1: The input flow is de-interleaved.
l
tia
[6] OUTRS_PS: Output type.
0: Parallel output mode.
1: Serial output mode.
[5] RS: Reed-Solomon enable.
0: No correction happens, all the data is fed to the descrambler. The error signal remains
en
inactive.
1: The input code is corrected.
Confidential
[4] DESCRAM: Descrambler enable.

0: The descrambler is deactivated.
fid
1: The output flow from Reed–Solomon decoder is descrambled.

[3] ERR_BIT: Write error bit.
0: The output flow is unchanged.
1: If an uncorrectable error occurs in DVB-S, the MSB of the 1st byte following the sync byte is
on
forced to 1 after descrambling.

[2] MPEG: Block sync.
0: The first byte is the one that is received. In DVB-S, it should be the sync byte 0x47,
complemented 0xB8 every 8th packet.
1: The first byte of each packet is forced to 0x47 in DVB-S mode.
C
[1] CLK_POL: Output clock polarity.

0: The data and control signals are clocked during the low-to-high transition of CLK_OUT.
1: The data and control signals are clocked during the high-to-low transition of CLK_OUT.
[0] CLK_CFG: Output clock signal configuration during parity bytes.
0: CLK_OUT is continuous and the parity bytes are transmitted. If the packet contains more
than 8 errors, ERROR remains high during the entire packet.
1: D[7:0] and ERROR are null during the parity bytes. If the packet contains more than 8 errors,
ERROR only remains high during the data transmission. In the parallel mode, CLK_OUT
remains low during the parity bytes. In the serial mode, the output bit clock is always running.
136/294 Doc ID 8141465 Rev 5

RSOUT Reed–Solomon and output control register

7 6 5 4 3 2 1 0
EN_STBACKEND
INV_DERROR
ENA8_LEVEL
INV_DSTART
INV_DVALID

Type: R/W
Reset: 0x00
Description: Reed–Solomon and output control register.
l
tia
[7] INV_DVALID:
0: Normal mode.
1: DVALID is inverted.
[6] INV_DSTART:
en
0: Normal mode.
1: DSTART is inverted.
Confidential
[5] INV_DERROR:
0: Normal mode.
1: DERROR is inverted.
fid
[4] EN_STBACKEND: Rate compensation mode.

0: DP/packet clock puncturing.
1: CLK_OUT/byte clock puncturing.
on
[3:0] ENA8_LEVEL: Reed–Solomon output FIFO clock division ratio, on CLK_OUT/byte clock
0000: Output FIFO disable.
Parallel mode: output clock period = ENA8_LEVEL x 4 x TM_CLK.
0001: 4 x TM_CLK
0010: 8 x TM_CLK
C
0011: 12 x TM_CLK
0100: 16 x TM_CLK
...
1110: 56 x TM_CLK
1111: 60 x TM_CLK
Doc ID 8141465 Rev 5 137/294

ERRCTRL Error 1 control register

7 6 5 4 3 2 1 0
ERRMODE RESERVED ERR_SOURCE RESERVED RESET_CNT NOE

Type: R/W
Reset: 0x01
Description: Error 1 control register. See also Section : Error monitoring.
[7] ERRMODE: Error mode.

0: Error rate.
1: Error count.
l
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[5:4] ERR_SOURCE: Error source. The error sources are as follows:
00: QPSK bit errors.
01: Viterbi bit errors.
10: Viterbi byte errors.
en
11: Packet errors.
Confidential

[2] RESET_CNT:
0: Running counter.
fid
1: Counter reset.
[1:0] NOE: The NOE bits represent the count period in bytes (NB).
00: 212 bytes.
01: 214 bytes.
on
10: 216 bytes.

11: 218 bytes.
ECNTM Error 1 count register (MSB)

C
7 6 5 4 3 2 1 0
ERROR_COUNT_MSB

Type: R
Description: Error 1 count register (MSB). See also Section : Error monitoring.
[7:0] ERROR_COUNT_MSB: Error count register MSB byte (not signed).
138/294 Doc ID 8141465 Rev 5

ECNTL Error 1 count register (LSB)

7 6 5 4 3 2 1 0
ERROR_COUNT_LSB

Type: R
Description: Error 1 count register (LSB). See also Section : Error monitoring.
[7:0] ERROR_COUNT_LSB: Error count register LSB byte (not signed).
ERRCTRL2 Error 2 control register
l
7 6 5 4 3 2 1 0
tia
ERR_SOURCE2
RESET_CNT2
ERRMODE2
RESERVED
RESERVED
NOE2
en
Confidential
Type: R/W
Reset: 0x01
fid
Description: Error 2 control register. See also Section : Error monitoring.
[7] ERRMODE2: Error mode

on
0: Error rate.
1: Error count.
[5:4] ERR_SOURCE2[1:0]: Error source. The error sources are as follows:
C
00: QPSK bit errors.

01: Viterbi bit errors.
10: Viterbi byte errors.
11: Packet errors.
[2] RESET_CNT2:
0: Running counter.
1: Counter reset.
[1:0] NOE2[1:0]: The NOE bits represent the count period in bytes (NB):
00: 212 bytes.
01: 214 bytes.
10: 216 bytes.
11: 218 bytes.
Doc ID 8141465 Rev 5 139/294

ECNTM2 Error 2 count register (MSBs)

7 6 5 4 3 2 1 0
ERROR_COUNT2_MSB

Type: R
Description: Error 2 count register (MSBs). See also Section : Error monitoring.
[7:0] ERROR_COUNT2_MSB: Error count register MSB byte (not signed).
ECNTL2 Error 2 count register (LSBs)
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7 6 5 4 3 2 1 0
tia
ERROR_COUNT2_LSB

Type: R
en
Description: Error 2 count register (LSBs). See also Section : Error monitoring.
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[7:0] ERROR_COUNT2_LSB: Error count register LSB byte (not signed).

fid
on
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140/294 Doc ID 8141465 Rev 5

13.3 General-purpose registers
I2CRPT Serial bus repeater control register

7 6 5 4 3 2 1 0
ENARPT_LEVEL[2:0]
STOP_ENABLE
SDAT_VALUE
SCLT_VALUE
SCLT_DELAY
I2CT_ON

Type: R/W
l
Reset: 0x57
tia
Description: Serial bus repeater control register. This register is accessible in the standby mode.
See also Section 12.3.6: I2C bus repeater.
en
[7] I2CT_ON:
1: Switches on the I2C repeater block.
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[6:4] ENARPT_LEVEL[2:0]: Delay applied to applied to SDAT line. Advised value is 0x5. The units
are in cycles of FMCLK (100 MHz default).
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000: 128
001: 64
010: 32
011: 16
100: 8
on
101: 4
110: 64
111: 32
[3] SCLT_DELAY:
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1: The same delay as for the SDAT line is applied to the SCLT line.
[2] SCLT_VALUE: Force SCLT value I2CT_ON must be off.
[1] STOP_ENABLE:
1: The I2C repeater is automatically turned off at the end of the transaction (on first
encountered stop condition).
[0] SDAT_VALUE: Force sdat_value, I2CT_ON must be off.
Doc ID 8141465 Rev 5 141/294

ACR Auxiliary clock register

7 6 5 4 3 2 1 0
PRESCALER DIVIDER

Type: R/W
Reset: 0x2A
Description: Auxiliary clock register. See also Section 12.4.3: Clock registers.
[7:0] ACR PRESCALER AND DIVIDER:

This register is made up of the ACR [7:5] prescaler field and the ACR [4:0] divider field. The
values in these fields configure the auxiliary clock function, the prescaler value, the clock signal
l
frequency.
tia
The frequency range is given for FMCLK = 150 MHz.
ACR[7:0] Function Prescalar Signal frequency Range

en
000X XXX0 Output port N/A Output port = 0 N/A
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000X XXX1 Output port N/A Output port = 1 N/A

001X XXXX HF generator 1 fM_CLK / 2 / ACR[4:0] 2.3 to 75 MHz
fid
010X XXXX LF generator 64 fM_CLK / 2048 / (32 + ACR[4:0]) 2.3 to 1.16 kHz
011X XXXX LF generator 128 fM_CLK / 4096 / (32 + ACR[4:0]) 580 to 1150 Hz
on
C
In the LF generator, the programmable division factor is 32 + ACR[4:0]. In the HF

generator, it is simply ACR[4:0]. This allows the building of any frequency from 24 Hz
to 1.1 kHz (within ± 1.5%) in the full operating range. The output signal is square in all
cases. When the auxiliary register is written, the prescaler and the programmable
divider are reset.
142/294 Doc ID 8141465 Rev 5

DACR1 DAC register (MSB)

7 6 5 4 3 2 1 0
DACMODE RESERVED DACMSB

Type: R/W
Reset: 0x00
Description: DAC register (MSB). This register is accessible in the standby mode.
[7:5] DACMODE: This field controls the DAC:

000: Functions as output port. DAC permanently outputs 0.
001: Functions as output port. DAC permanently outputs 1.
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010: High impedance mode.
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100: Functions as DAC. Duty cycle modulated at FMCLK / 16.
101: Functions as DAC. Duty cycle modulated at FMCLK / 4.
110: Functions as DAC. Duty cycle modulated at FMCLK.
Others: Reserved functions.
en
[4] RESERVED: This bit must be programmed to zero.
[3:0] DACMSB: 4 MSBs.
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DACR2 DAC register (LSB)

fid
7 6 5 4 3 2 1 0
DACLSB

on
Type: R/W
Reset: 0x00
Description: DAC register (LSB). This register is accessible in the standby mode.
C
[7:0] DACLSB: 8 LSBs.
PLLCTRL Analog PLL divider control register

7 6 5 4 3 2 1 0
PLL_MDIV

Type: R/W
Reset: 0x14
Description: Analog PLL divider control register. This register is accessible in the standby mode.
See also Section 12.4.2: Internal clock generation.
Doc ID 8141465 Rev 5 143/294

SYNTCTRL Frequency synthesizer control register

7 6 5 4 3 2 1 0
PLL_SELRATIO
BYP_PLL_ADC
BYP_PLL_FSK
BYPASS_PLL
RESERVED
PLL_STOP
SEL_OSCI
STANDBY

Type: R/W
Reset: 0x23
Description: Frequency synthesizer control register. This register is accessible in standby mode.
See also Figure 16.
l
Note: FSK is not supported in STi5189.
tia
[7] STANDBY: Stop all clocks except I2C clock.
0: Device is in standby.
1: Device is active.
en
[6] RESERVED: Must be set to 0.
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[5] BYP_PLL_FSK: Bypass pll for FSK analog cell.

0: Internal clock generated by PLL.
1: Internal clock coming from XTAL or CLK_I.
fid
[4] PLL_STOP: Set PLL in standby.

0: PLL is active.
1: PLL is in standby mode
on
[3] SEL_OSCI: Select OSCI cell or not.

0: Clock input from CLK_I.
1: Clock input from XTAL.
[2] PLL_SELRATIO: Choice of divider ration in PLL. See PLLCTRL description.
C
[1] BYP_PLL_ADC: Bypass PLL for ADC.

[0] BYPASS_PLL: Bypass PLL.
144/294 Doc ID 8141465 Rev 5

TSTTNR1 Analog IPs control register

7 6 5 4 3 2 1 0
DISEQC_POFF
FSK_INV_CLK
ADC_INMODE
OSCI_POFF
RESERVED
RESERVED
FSK_POFF
ADC_PON
Type: R/W
Reset: 0x0C
Description: Analog IPs control register. This register is accessible in the standby mode.
Note: FSK is not supported in the STi5189.
l
tia
[7] FSK_INV_CLK: Invert clock for FSK analog IP.
en
[5] ADC_PON: ADCs power ON.
0: ADC is active.
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1: ADC is in standby mode.

[4] ADC_INMODE: Differential input voltage.
0: 1 Vpp
fid
1: 2 Vpp
[3] DISEQC_POFF: DiSEqC analog IP power OFF.
0: DiSEqC analog is active
1: DiSEqC analog is in standby.
on
Note: DiSEQC and FSK must not be both active.

[2] FSK_POFF: FSK analog IP power OFF.
0: FSK analog is active
1: FSK analog is in standby.
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Note: DiSEqC and FSK must not be both active.

[1] OSCI_POFF: OSCI power off.
0: OSCI is active.
1: OSCI is in standby.
Doc ID 8141465 Rev 5 145/294

SYMBCTRL Constellation sources control register

7 6 5 4 3 2 1 0
RESERVED SYMB_CHOICE

Type: R/W
Reset: 0x00
Description: Constellation sources control register. See also Section : I, Q symbol monitoring.
[1:0] SYMB_CHOICE: I and Q choice for reading.
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00: After demodulation.
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01: After polyphase filter.
10: After derotation.
11: After dc_adjust.
ISYMB I symbol register

en
7 6 5 4 3 2 1 0
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I_SYMB

fid
Type: R
Description: I symbol register. See also Section : I, Q symbol monitoring.
on
[7:0] I_SYMB[7:0]: 8 bits of I symbol (signed value).
QSYMB Q symbol register

C
7 6 5 4 3 2 1 0
Q_SYMB

Type: R
Description: I symbol register. See also Section : I, Q symbol monitoring.
[7:0] Q_SYMB: 8 bits of Q symbol (signed value).
146/294 Doc ID 8141465 Rev 5

SDATCFG SDAT I/O control register

7 6 5 4 3 2 1 0
SDAT_OD SDAT_CFG SDAT_XOR
Address: QPSKBaseAddress + 0xB0

Type: R/W
Reset: 0xB8
Description: General-purpose I/O control registers. These registers are accessible in standby
mode. See also Section l: generate interrupt if there are 8 or more bytes in the FIFO
ready for reading.
[7] SDAT_OD: Open drain configuration of GPIO pin.
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0: Push-pull.
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1: Open-drain.
[6:1] SDAT_CFG[5:0]: See Table 47.
[0] SDAT_XOR:
en
1: XOR the result of SDAT_CFG configuration.
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Table 47. General-purpose input and output configuration

Value Signal Description
fid
0 0 Force output to 0
1 1 Force output to 1
2 to 7 - Reserved
on
8 AGC AGC output

9 to 15 - Reserved
16 DISEQC_OUT DiSEqC 2.0 output
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17 DISEQCE_IN DiSEqC envelope input

18 to 20 - Reserved
21 OUTBIT -
22 DAC DAC output
23 IRQ IT output
24 to 27 - Reserved
28 SDAT Tuner dedicated SDA signal
29 SCLT Tuner dedicated SCL signal
30 to 51 - Reserved
52 AUX_CK Auxiliary signal
53 COARSE Coarse mode indicator
54 FINE Fine mode indicator
55 to 63 - Reserved
Doc ID 8141465 Rev 5 147/294

SCLTCFG SCLT I/O control register

7 6 5 4 3 2 1 0
SCLT_OD SCLT_CFG SCLT_XOR

Type: R/W
Reset: 0x3A
Description: SCLT I/O control register. This register is accessible in standby mode. Same as
SDATCFG except for address and reset values.
AGCCFG AGC I/O control register
7 6 5 4 3 2 1 0
l
tia
AGC_OD AGC_CFG AGC_XOR

Type: R/W
en
Reset: 0x90
Description: AGC I/O control register. This register is accessible in standby mode. Same as
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AUXCKCFG AUXCK I/O control register

7 6 5 4 3 2 1 0
AUXCK_OD AUXCK_CFG AUXCK_XOR

on

Type: R/W
Reset: 0x68
C
Description: AUXCK I/O control register. This register is accessible in standby mode. Same as
DISEQCCFG DISEQC_OUT I/O control register

7 6 5 4 3 2 1 0
DISEQC_OD DISEQC_CFG DISEQC_XOR
Address: QPSKBaseAddress + 0XB8

Type: R/W
Reset: 0x20
Description: DISEQC_OUT I/O control register. This register is accessible in standby mode. Same
as SDATCFG except for address and reset values.
148/294 Doc ID 8141465 Rev 5

IRQSTATx Interrupt request status registers 1 to 0

15 14 13 12 11 10 9 8
TMG_LOCK TMG_LOSS CF_LOCK CF_LOSS DIS_TX DIS_RX RS_OV VIT_LOCK
7 6 5 4 3 2 1 0
NVIT_LOCK RESERVED
Address: QPSKBaseAddress + 0x45 + x * 0x01 (where x = 0 to 1)

Type: R
Reset: 0x0000
Description: Interrupt request status register 1 to 0. Status register block giving the list of currently
pending interrupt request occurrences.
0: No interrupt request has been detected since last erase of this bit.
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1: An interrupt request has been detected since last erase of this bit.
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The bits of these registers are erased after a read. At offset address 0x045, register is
having MSB bits and at offset address 0x046, register is having LSB bits.
en
[15] TMG_LOCK: Demodulator symbol rate locked.
[14] TMG_LOSS: Demodulator symbol rate lost.
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[13] CF_LOCK: Demodulator carrier sync found event.

[12] CF_LOSS: Demodulator carrier sync lost.
fid
[11] DIS_TX: This interrupt flag is raised when any of the following events arise:
Gap burst terminated (gap burst flag going low).
DiSEqC transmitter FIFO now empty.
DiSEqC transmitter FIFO now has only 4 bytes.
on
[10] DIS_RX: DiSEqC receiver FIFO now has 8 more bytes waiting to be read or end of message
has been detected.
[9] RS_OV: Reed–Solomon FIFO overflow detected.
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[8] VIT_LOCK: Viterbi lock found.

[7] VIT_LOSS: Viterbi lock lost.
[6:0] RESERVED
Doc ID 8141465 Rev 5 149/294

IRQMSKx Enable interrupt lines

15 14 13 12 11 10 9 8
TMG_LOCK TMG_LOSS CF_LOCK CF_LOSS DIS_TX DIS_RX RS_OV VIT_LOCK
7 6 5 4 3 2 1 0
NVIT_LOCK RESERVED
Address: QPSKBaseAddress + 0x43 + x * 0x01 (where x = 0 to 1)

Type: R/W
Reset: 0x0000
Description: Enable interrupt request lines [15:0] as defined by register IRQSTATx. The value ‘1’ in
the required bit position enables the interrupt. These registers are accessible in
standby mode. At offset address 0x043, register is having MSB bits and at offset
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address 0x044, register is having LSB bits.
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[15] TMG_LOCK: Enable TMG_LOCK interrupt request.
[14] TMG_LOSS: Enable TMG_LOSS interrupt request.
en
[13] CF_LOCK: Enable CF_LOCK interrupt request.
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[12] CF_LOSS: Enable CF_LOSS interrupt request.

[11] DIS_TX: Enable DIS_TX interrupt request.
fid
[10] DIS_RX: Enable DIS_RX interrupt request.

[9] RS_OV: Enable RS_OV interrupt request.
[8] VIT_LOCK: Enable VIT_LOCK interrupt request.
on
[7] VIT_LOSS: Enable VIT_LOSS interrupt request.

[6:0] RESERVED
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150/294 Doc ID 8141465 Rev 5

13.4 Fast channel acquisition and blind search registers
ASCTRL Autoscan control register

7 6 5 4 3 2 1 0
FROZE_LOCK
RESERVED
COARSE
CENTER
FINE
KI
Type: R/W
Reset: 0x10
Description: Autoscan control register. See also Section : First step: coarse autosearch.
l
tia
[7:6] RESERVED: Must be set programmed to 0.
[5] FROZE_LOCK: Control.
1: Froze accu1 and accu2 (see registers ACCU1VAL and ACCU2VAL).
en
[5:3] KI[1:0]: Control, integration ratio of power spectrum measurements in the coarse mode.
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00: Freeze mode

01: 1/4
10: 1/8
fid
11: 1/16
[2] CENTER: Control.
1: Reduce residual offset of Fs.
on
[1] FINE:
1: Enabled fine mode.
[0] COARSE: Control.
1: Enable coarse mode.
C
COARP1 Autoscan control register

7 6 5 4 3 2 1 0
RESERVED KT

Type: R/W
Reset: 0x3A

[6:0] KT[6:0]: Control, fixed parameter KT.
Doc ID 8141465 Rev 5 151/294

COARP2 Autoscan control register

7 6 5 4 3 2 1 0
RESERVED KC KS

Type: R/W
Reset: 0x09
[5:3] KC[2:0]: Control, frequency carrier correction ratio.
l
[2:0] KS[2:0]: Control, frequency timing correction ratio.
FMINM
7 6 5 tia 4 3 2
FMIN register (MSB)
1 0
en
STOPON_FMIN
FMIN
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fid

Type: R/W
Reset: 0x00
on
Description: FMIN register (MSB). See also Section : Second step: fine scan.
[7] STOPON_FMIN: Control.

C
1: Stop fine mode if current timing frequency is below FMIN value.

[6:0] FMIN[14:8]: Control, minimum frequency bound.
FMINL FMIN register (LSB)

7 6 5 4 3 2 1 0
FMIN

Type: R/W
Reset: 0x00
Description: FMIN register (LSB). See also Section : Second step: fine scan.
[7:0] FMIN[7:0]: Control, minimum frequency bound.
152/294 Doc ID 8141465 Rev 5

FMAXM FMAX register (MSB)

7 6 5 4 3 2 1 0
STOPON_FMAX
FMAX
Type: R/W
Reset: 0x00
Description: FMAX register (MSB). See also Section : Second step: fine scan.
l
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[7] STOPON_FMAX: Control.
1: Stops fine mode if current timing frequency is above FMAX value.
[6:0] FMAX[14:8]: Control, maximum frequency bound.
en
FMAXL FMAX register (LSB)
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7 6 5 4 3 2 1 0
FMAX
fid

Type: R/W
Reset: 0x00
on
Description: FMAX register (LSB). See also Section : Second step: fine scan.
[7:0] FMAX[7:0]: Control, maximum frequency bound.

C
FINEINC Fine increment register

7 6 5 4 3 2 1 0
FINE_INCR

Type: R/W
Reset: 0x00
Description: Fine increment register. See also Section : Second step: fine scan.
[7:0] FINE_INCR[7:0]: 8-bit signed increment step (signed).
Doc ID 8141465 Rev 5 153/294

STEP2 Step2 register

7 6 5 4 3 2 1 0
STEP2_MINUS STEP2_PLUS

Type: R/W
Reset: 0x54
Description: Step2 register. See Section : Timing lock indicator.
[7:4] STEP2_MINUS[3:0]: Control, decrease by STEP2MINUS the accumulator of the second
indicator.
l
[3:0] STEP2_PLUS[3:0]: Control, increase by STEP2PLUS the accumulator of the second indicator.
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TH2 Threshold2 (MSB) register
7 6 5 4 3 2 1 0
en
TH2

Confidential
Type: R/W
fid
Reset: 0x86
Description: Threshold2 (MSB) register. See Section : Timing lock indicator.
on
[7:0] TH2[9:2]: Threshold2 value.
TH2ATH1 Threshold2 (LSB) and Threshold1 (MSB) register

C
7 6 5 4 3 2 1 0
TH2 RESERVED TH1

Type: R/W
Reset: 0x00
Description: Threshold2 (LSB) and Threshold1 (MSB) register. See Section : Timing lock
indicator.
[7:6] TH2[1:0]: LSB of TH2.

[5:2] RESERVED: Must be programmed to 0.
[1:0] TH1[9:8:0]: MSB of TH1.
154/294 Doc ID 8141465 Rev 5

TH1 Threshold 1 (LSB) register

7 6 5 4 3 2 1 0
TH1

Type: R/W
Reset: 0x9B
Description: Threshold1 (LSB) register. See Section : Timing lock indicator.
[7:0] TH1[7:0]: LSB of TH1.
l
THH Threshold H register
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7 6 5 4 3 2 1 0
RESERVED THH

en
Type: R/W
Confidential
Reset: 0x08
Description: Threshold H register. See Section : Timing lock indicator.
fid
[7:6] RESERVED: Must be programmed to 0.

[5:0] THH[5:0]: Unsigned value.
on
IND1MAX Indicator 1 limit register

7 6 5 4 3 2 1 0
C
IND1_THRESHOLD

Type: R/W
Reset: 0x1D
Description: Indicator 1 limit register. See Section : Timing lock indicator.
[7:0] IND1_THRESHOLD[7:0]: If IND1 is above this limit tmg_lock is asserted.
Doc ID 8141465 Rev 5 155/294

ACCU1VAL Accumulator 1 status register

7 6 5 4 3 2 1 0
ACCU1_VAL

Type: R/W
Description: Accumulator 1 status register. See Section : ASCTRL.
[7:0] ACCU1_VAL[7:0]: MSB of accumulator1. The accumulator1 MSB can be preset by writing in
this register.
ACCU2VAL Accumulator 2 status register
l
tia
7 6 5 4 3 2 1 0
ACCU2_VAL

en
Type: R/W
Description: Accumulator 2 status register. See Section : ASCTRL.
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fid
[7:0] ACCU2_VAL[7:0]: MSB of accumulator2. The accumulator2 MSB can be preset by writing in
this register.
on
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156/294 Doc ID 8141465 Rev 5

STi5189 Configuration registers
14 Configuration registers
The following functions are enabled and disabled using the configuration registers:
● alternative assignments on pins
● video DAC control
● audio DAC control
● interrupt direction
● FMI pull-ups
● smartcard clock selection
● DMAREQ direction and polarity
Note: Control and monitor registers A and B are high-speed (HS) registers and other registers are
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high-density (HD) registers.
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Addresses are provided as the ICHSBaseAddress and ICHDBaseAddress + offset.
The ICHSBaseAddress is 0xFD00 2000.
The ICHDBaseAddress is 0xFD90 1000.
en
.
Table 48. Configuration registers

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Address offset Register name Description Page
0x0008 CFG_MONITOR_A Interconnect configuration monitoring register A page 159

fid
0x000C CFG_MONITOR_B Interconnect configuration monitoring register B page 160

0x0020 CFG_MONITOR_C Interconnect configuration monitoring register C page 160
0x0024 CFG_MONITOR_D Interconnect configuration monitoring register D page 160
on
0x0028 CFG_MONITOR_E Interconnect configuration monitoring register E page 161

0x002C CFG_MONITOR_F Interconnect configuration monitoring register F page 162
0x0030 CFG_MONITOR_G Interconnect configuration monitoring register G page 162
C
0x0034 CFG_MONITOR_H Interconnect configuration monitoring register H page 162

0x0038 CFG_MONITOR_I Interconnect configuration monitoring register I page 163
0x003C CFG_MONITOR_J Interconnect configuration monitoring register J page 163
0x0060 CFG_MONITOR_K Interconnect configuration monitoring register K page 164
0x0064 CFG_MONITOR_L Interconnect configuration monitoring register L page 164
0x0068 CFG_MONITOR_M Interconnect configuration monitoring register M page 164
0x006C CFG_MONITOR_N Interconnect configuration monitoring register N page 165
0x0070 CFG_MONITOR_O Interconnect configuration monitoring register O page 165
0x0074 CFG_MONITOR_P Interconnect configuration monitoring register P page 165
0x0078 CFG_MONITOR_Q Interconnect configuration monitoring register Q page 166
0x007C CFG_MONITOR_R Interconnect configuration monitoring register R page 166
0x0000 CFG_CTRL_A Interconnect configuration control register A page 167
0x0004 CFG_CTRL_B Interconnect configuration control register B page 168
Doc ID 8141465 Rev 5 157/294

Configuration registers STi5189
Table 48. Configuration registers (continued)

0x0000 CFG_CTRL_C Interconnect configuration control register C page 169

0x0004 CFG_CTRL_D Interconnect configuration control register D page 171
0x0008 CFG_CTRL_E Interconnect configuration control register E page 173
0x000C CFG_CTRL_F Interconnect configuration control register F page 174
0x0010 CFG_CTRL_G Interconnect configuration control register G page 174
0x0014 CFG_CTRL_H Interconnect configuration control register H page 175
0x0018 CFG_CTRL_I Interconnect configuration control register I page 176
0x001C CFG_CTRL_J Interconnect configuration control register J page 177
0x0040 CFG_CTRL_K Interconnect configuration control register K page 177
l
tia
0x0044 CFG_CTRL_L Interconnect configuration control register L page 178
0x0048 CFG_CTRL_M Interconnect configuration control register M page 178
0x004C CFG_CTRL_N Interconnect configuration control register N page 179
en
0x0050 CFG_CTRL_O Interconnect configuration control register O page 180
0x0054 CFG_CTRL_P Interconnect configuration control register P page 180
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0x0058 CFG_CTRL_Q Interconnect configuration control register Q page 181

fid
0x005C CFG_CTRL_R Interconnect configuration control register R page 182

on
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158/294 Doc ID 8141465 Rev 5

14.1 Configuration monitor registers

The two groups of read only configuration monitor registers are:
● high-speed configuration monitor registers
● high-density configuration monitor registers
14.1.1 High-speed configuration monitor registers

This group of registers lies in the high-speed (HS) domain consists of set of two 32 bit
configuration monitor registers housed inside CPU_LMI subsystem and caters for
monitoring the status of ASBs and LMI DDR pad logic belonging to the CPU_LMI
subsystem.
CFG_MONITOR_A Configuration monitoring register A
l
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
tia
COMPENSATION_CODE_IN_NON_DDR_PAD
DLL_LOCK_TOCORE
DLL_CMD_TOCORE
en
RESERVED
RESERVED
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fid
on
Address: ICHSBaseAddress + 0x0008

Type: R
Reset: 0x0000
C
Description: Interconnect configuration monitoring register A.
[31:30] RESERVED: Read back 0.

[29:23] COMPENSATION_CODE_IN_NON_DDR_PAD: Value of ASRC bus for non-DDR
compensation cell.
[22] DLL_LOCK_TOCORE: DLL lock monitored.
[21:13] DLL_CMD_TOCORE: DDR padlogic DLL_CMD signal monitored
[12:0] RESERVED
Doc ID 8141465 Rev 5 159/294

CFG_MONITOR_B Configuration monitoring register B

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
Address: ICHSBaseAddress + 0x000C

Type: R
Reset: 0x0000
Description: Interconnect configuration monitoring register B.
[31:0] RESERVED
14.1.2 High-density configuration monitor registers
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This group of registers lies in the high-density (HD) domain which consists of a set of
sixteen 32-bit configuration monitor registers housed inside transport subsystem and caters
for monitoring the status of the rest of the chip.
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CFG_MONITOR_C Configuration monitoring register C
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
fid
Address: ICHDBaseAddress + 0x0020

Type: R
Reset: 0x0000
on
Description: Interconnect configuration monitoring register C.
[31:0] RESERVED
C
CFG_MONITOR_D Configuration monitoring register D

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED

Type: R
Reset: 0x0000
Description: Interconnect configuration monitoring register D.
[31:0] RESERVED
160/294 Doc ID 8141465 Rev 5

CFG_MONITOR_E Configuration monitoring register E

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMPENSATION_CODE_IN_NON_DDR_PAD
COMPENSATION_CODE_IN_DDR_PAD
USB_POWERDOWN_ACK
SPDIF_EOLATENCY
TST_VBGUP_EXT
ADAC_VMCUP
TST_UP_EXT
ADAC_BUSY
ADAC_VMC
RESERVED
RESERVED
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tia
Type: R
Reset: 0x0000
en
Description: Interconnect configuration monitoring register E.
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[31] RESERVED:
fid
[30] USB_POWERDOWN_ACK:
[29] TST_UP_EXT:
[28:22] COMPENSATION_CODE_IN_NON_DDR_PAD:
on
[21:15] COMPENSATION_CODE_IN_DDR_PAD:
[14:5] RESERVED
[4] ADAC_BUSY:
C
[3] SPDIF_EOLATENCY:
[2] ADAC_VMC: ADAC output
[1] ADAC_VMCUP: ADAC output
[0] TST_VBGUP_EXT: ADAC output
Doc ID 8141465 Rev 5 161/294

CFG_MONITOR_F Configuration monitoring register F

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
Address: ICHDBaseAddress + 0x002C

Type: R
Reset: 0x0000
Description: Interconnect configuration monitoring register F.
[31:0] RESERVED
CFG_MONITOR_G Configuration monitoring register G
l
tia
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED

en
Type: R
Confidential
Reset: 0x0000
Description: Interconnect configuration monitoring register G.
fid
[31:0] RESERVED
CFG_MONITOR_H Configuration monitoring register H

on
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_DEVICE_ID

C
Type: R/W
Reset: 0x0000
Description: Configuration monitoring register H.
[31:0] CPU_DEVICE_ID
162/294 Doc ID 8141465 Rev 5

CFG_MONITOR_I Configuration monitoring register I

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED

Type: R
Reset: 0x0000
Description: Interconnect configuration monitoring register I.
[31:0] RESERVED
CFG_MONITOR_J Configuration monitoring register J
l
tia
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMPENSATION_3V3_2_NON_DDR_OK
COMPENSATION_3V3_NON_DDR_OK
COMPENSATION_2V5_DDR_OK
QPSKBIST_OUT_COUNT_VAL
LMI_FMI_PMU_PDSTAT_CFG
TST_QPSK_PLL_BEND_BUS
TST_QPSK_PLL_BBAD_BUS
EXT_ST40_CORE_PDACK
FMI4_PWRDWN_ACK
en
QPSK_PLL_LOCK
RESERVED
RESERVED
Confidential
fid
on

Type: R/W
Reset: 0x0000
C
Description: Configuration monitoring register J.
[31] COMPENSATION_2V5_DDR_OK
[30] COMPENSATION_3V3_NON_DDR_OK
[29: 28] RESERVED
[27] COMPENSATION_3V3_2_NON_DDR_OK:
[26] QPSK_PLL_LOCK: QPSK PLL lock monitor.
[25] RESERVED:
[24] LMI_FMI_PMU_PDSTAT_CFG
[23] COMPENSATION_3V3_1_NON_DDR_OK
[22] COMPENSATION_3V3_0_NON_DDR_OK
[21] EXT_ST40_CORE_PDACK
[20] FMI4_PWRDWN_ACK
Doc ID 8141465 Rev 5 163/294

[19:18] TST_QPSK_PLL_BBAD_BUS: QPSK PLL bist bbad out.

[17:16] TST_QPSK_PLL_BEND_BUS: QPSK PLL bist bend out.
[15:0] QPSKBIST_OUT_COUNT_VAL: QPSK PLL bist.
CFG_MONITOR_K Configuration monitoring register K

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESERVED

Type: R/W
Reset: 0x0000
l
Description: Configuration monitoring register K.
[31:16] RESERVED
[15:0] RESERVED tia
en
CFG_MONITOR_L Configuration monitoring register L
Confidential
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
fid

Type: R/W
on
Reset: 0x0000
Description: Configuration monitoring register L.
C
[31:0] RESERVED
CFG_MONITOR_M Configuration monitoring register M

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED

Type: R/W
Reset: 0x0000
Description: Configuration monitoring register M.
[31:0] RESERVED
164/294 Doc ID 8141465 Rev 5

CFG_MONITOR_N Configuration monitoring register N

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED

Type: R/W
Reset: 0x0000
Description: Configuration monitoring register N.
[31:0] RESERVED
CFG_MONITOR_O Configuration monitoring register O
l
tia
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHIP_PUBLIC_ID

en
Type: R/W
Confidential
Reset: 0x0000
Description: Configuration monitoring register O.
fid
[31:0] CHIP_PUBLIC_ID:
CFG_MONITOR_P Configuration monitoring register P

on
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED

C
Type: R/W
Reset: 0x0000
Description: Configuration monitoring register P.
[31:0] RESERVED
Doc ID 8141465 Rev 5 165/294

CFG_MONITOR_Q Configuration monitoring register Q

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED

Type: R/W
Reset: 0x0000
Description: Configuration monitoring register Q.
[31:0] RESERVED
CFG_MONITOR_R Configuration monitoring register R
l
tia
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED

en
Type: R/W
Confidential
Reset: 0x0000
Description: Configuration monitoring register R.
fid
[31:0] RESERVED
on
C
166/294 Doc ID 8141465 Rev 5

14.2 Configuration control registers

The two groups of read only configuration control registers are:
● high-speed configuration control registers
● high-density configuration control registers
14.2.1 High-speed configuration control registers

This group of registers lies in the high-speed (HS) domain consists of set of two 32-bit
configuration control registers housed inside CPU_LMI subsystem and caters for controlling
the bits within the CPU_LMI subsystem.
CFG_CTRL_A Configuration control register A
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
l
tia
RESERVED

Type: R/W
en
Reset: 0x0000
Description: Interconnect configuration control register A.
Confidential
fid
[31:0] RESERVED
on
C
Doc ID 8141465 Rev 5 167/294

CFG_CTRL_B Configuration control register B

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET_THE_DESIGN_ON_SECURITY_BREACH
SH4_REQ_FILTER
STICKY_BIT
RESERVED
l
tia
Type: R/W
en
Reset: 0x0000
Description: Interconnect configuration control register B.
Confidential
fid
[31] STICKY_BIT: The post-reset value of this bit is 0. If set to 1, it can only be cleared by reset
operation.
[30] RESET_THE_DESIGN_ON_SECURITY_BREACH:
[29] SH4_REQ_FILTER:
on
[28:0] RESERVED
C
168/294 Doc ID 8141465 Rev 5

14.2.2 High-density configuration control registers

This group of registers lies in the high-density (HD) domain, which consists of a set of
sixteen 32-bit configuration control registers housed inside transport subsystem and caters
for controlling the bits for rest of the subsystem.
CFG_CTRL_C Configuration control C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFG_PIO_IN_MUX_ASC0_RXD
TSIS_SERIAL_NOT_PARALLEL
SELECT_ADDRESS_I2C_289
FMI_PULLUP_DISABLE[1:0]
GRANT_RETRACT_EN_INT
PTI_TS_BITBYTECLK_SEL
DMAREQ_POLARITY[1:0]
QPSK_DEBUG_CONFIG
DEBUG_OR_TS_OUT
SEL_1394_PHI_CLK
AUX_PIX_CLK_SEL
MASK_EXT_REQ
VOL_REQ_POFF
IRB_DISABLE
SEL_FE_TS
RESERVED
RESERVED
RESERVED
l
tia
en
Type: R/W
Reset: 0x0000
Confidential
Description: Interconnect configuration control C.

fid
[31:30] DMAREQ_POLARITY[1:0]: External PIO request selective inversion.

FDMA request mapping:
00: No invert
on
01: Invert DMAREQ[0]

10: invert DMAREQ[1]
11: invert DMAREQ[1:0]
[29:26] RESERVED
C
[25:24] FMI_PULLUP_DISABLE[1:0]
00: No disable
01: Reserved
11: Disable for FMI pull ups
10: Reserved
[23] AUX_PIX_CLK_SEL: Select recovered pix clock or aux clock at AUXCLKOUT pad.
0: Recovered clock (PIX_CLK)
1: Auxiliary clock (AUX_CLK)
[22] IRB_DISABLE: Enable/disable IRB
0: Enable (default)
1: Disable
[21:12] RESERVED
[11] VOL_REQ_POFF: Power off for voltage regulator. Default is normal mode.
0: Normal mode
1: Power down
[10] RESERVED
Doc ID 8141465 Rev 5 169/294

[9] MASK_EXT_REQ: Default is 1.

[8] GRANT_RETRACT_EN_INT: Default is 1.
[7] SELECT_ADDRESS_I2C_289: 289 I2C base address select.
0: write_address = 0xD0
1: write_address = 0xD2
[6] PTI_TS_BITBYTECLK_SEL: Select PTI TS bit-byte clock.
0: PTI_TSBYTECLK from TS0INBITORBYTECLK pad
1: PTI_TSBYTECLK from TS0OUTPACKETCLK pad
[5] SEL_1394_PHI_CLK:
0: TSMERGER_O_BYTE_CLK_PHI0 to TSOUT_BYTE_CLK_TOPAD
1: TSMERGER_O_BYTE_CLK_PHI1 to TSOUT_BYTE_CLK_TOPAD
[4] DEBUG_OR_TS_OUT:
l
0: FE TS out. TS0OUT pads direction is output.
tia
1: TSmerger 1394 output to pad.
[3] TSIS_SERIAL_NOT_PARALLEL: First TS configuration.
0: Parallel
1: Serial
en
[2] SEL_FE_TS: TS stream. Must be programmed to 0.
0: TS stream from QPSK
Confidential
[1] QPSK_DEBUG_CONFIG: Default 0. IP289 I2C inputs from PIO1[0] and PIO1[1].
1: IP289 inputs from BE COMMS SSC1 interface
fid
[0] CFG_PIO_IN_MUX_ASC0_RXD: Select UART0_RXD.

0: PIO0_0
1: PIO0_1
on
C
170/294 Doc ID 8141465 Rev 5

CFG_CTRL_D Configuration control D

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FUNC_CFG_SOFTPUPOVERIDE
ADAC_SOFT_MUTE_DISABLE
FUNC_CFG_NPDVRAMP_EXT
FUNC_CFG_CMDDOWN_EXT
ADAC_ANA_BG_PWR_DOWN
FUNC_CFG_VMCUP_DIGEXT
FUNC_CFG_VMCUP_ANEXT
FUNC_CFG_CMDUPN_EXT
ADAC_ANA_PWR_DOWN
PCM_LRCLOCK_INVERT
ADAC_DIG_PWR_DOWN
VID_DAC_POFF_YCC_N
TSTSTRUCTURAL_CFG
ADAC_GAIN_CTRL_INT
VID_DAC_CMDR_YCC
VID_DAC_CMDS_YCC
PCM_CHANNEL_SEL
ADAC_SOFT_RST_N
PCM_SOURCE_SEL
FDMA_CLK_SEL
VDAC_HZ_YCC
RESERVED
RESERVED
RESERVED
Type: R/W
l
tia
Reset: 0x0000
Description: Interconnect configuration control D.
en
[31:26] RESERVED
Confidential
[25:24] PCM_CHANNEL_SEL: Select PCM player output channel.

[23] PCM_SOURCE_SEL:
0: PCM data/clock from PCM player
fid
1: PCM data/clock from pad

[22] PCM_LRCLOCK_INVERT: The LR Clock polarity invert bit allows the LR Clock to reach
the Audio ADAC either uninverted or inverted.
0: No inversion
on
1: Invert LR lock
[21:20] RESERVED
[19] FDMA_CLK_SEL: FDMA clock source
C
0: From PLL
1: From frequency synthesizer
[18] ADAC_SOFT_MUTE_DISABLE:
0: SOFT_MUTE is ON
1: SOFT_MUTE is OFF
On reset mute is ON.
[17] ADAC_DIG_PWR_DOWN:
0: Digital power down. Overridden by TST_DCPATHOFF.
[16] ADAC_ANA_PWR_DOWN:
0: Analog power down. Overridden by TST_DCPATHOFF.
[15] ADAC_ANA_BG_PWR_DOWN:
0: Analog bandgap power down mode
[14] RESERVED
Doc ID 8141465 Rev 5 171/294

[13] ADAC_SOFT_RST_N: Soft reset of ADAC. The soft reset bit is inverted. Active low. Write 1 to
soft reset ADAC.
0: Soft reset applied
1: Soft reset inactive
[12] VID_DAC_POFF_YCC_N
0: Disable power of all three DACs. This bit is inverted so on power up it is low.
This bit is reset to 1 inside the Group3 wrapper.
[11] VID_DAC_CMDR_YCC: Level control for UOUT, WOUT, VOUT.
[10] VID_DAC_CMDS_YCC: Level control for UOUT, WOUT, VOUT.
[9] VDAC_HZ_YCC:
1: YCC outputs are high impedance
[8] FUNC_CFG_CMDDOWN_EXT: To control CMDDOWN, VRAMP input
l
[7] FUNC_CFG_CMDUPN_EXT: To control CMDUPN, VRAMP input
tia
[6] FUNC_CFG_SOFTPUPOVERIDE: Soft power up/down override
[5] FUNC_CFG_NPDVRAMP_EXT: To control NPDVRAMp, VRAMP input
[4] FUNC_CFG_VMCUP_DIGEXT: To control VMCUP, digital part input
en
[3] FUNC_CFG_VMCUP_ANEXT: To control VMCUP, VRAMP input
Confidential
[2:1] ADAC_GAIN_CTRL_INT: Analog output gain control

[0] TSTSTRUCTURAL_CFG: Structural test mode, active high
fid
on
C
172/294 Doc ID 8141465 Rev 5

CFG_CTRL_E Configuration control E

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETHERNET_INTERFACE_ON
DISABLE_MSG_FOR_WRITE
DISABLE_MSG_FOR_READ
SMARTCARD_CLK1_SEL
SMARTCARD_CLK0_SEL
MII_PHYCLK_OUT_EN
VCI_ACK_SOURCE
MAC_SPEED_SEL
ETHERNET_SEL
RESERVED
RESERVED
RESERVED
MII_MODE
Type: R/W
l
Reset: 0x0000
tia
Description: Interconnect configuration control E.
[31:18] RESERVED:
en
[17] SMARTCARD_CLK1_SEL: Clock select for smartcard 2
Confidential
[16:11] RESERVED
[10] SMARTCARD_CLK0_SEL:
fid
0: Smartcard clock is provided from external source through PIO0 [2] (default)
1: Smartcard clock is provided from system services.
[9] RESERVED
[8:7] ETHERNET_SEL: These pins are used together for MII/RMII Mode.
on
If CFG_CTRL_E[8:7] = 00, pads are used for transport in/out and Ethernet is not available.
If CFG_CTRL_E[8:7] = 10, pads are used for RMII Ethernet mode. During this time due to less
number of pins used by Ethernet, serial transport IN is available.
If CFG_CTRL_E[8:7] = 11, pads are used for MII mode Ethernet and no transport in/out is
C
available.
[6] MII_PHYCLK_OUT_EN: Ethernet PHY clock out direction control. Default is OUT.
1: PHYCLK_IN comes from TS0OUTERROR pad
[5] DISABLE_MSG_FOR_WRITE:
0: Message mode
1: IP requests write transactions in packet mode
[4] DISABLE_MSG_FOR_READ:
0: Message mode
1: IP requests read transactions in packet mode
[3] VCI_ACK_SOURCE:
1: Posted write
[2] MII_MODE: This is input to Ethernet IP. This bit decides MII/RMII mode in IP.
0: RMII mode
1: MII mode
[1] MAC_SPEED_SEL: Select MAC clock speed. 25/2.5 MHz
Doc ID 8141465 Rev 5 173/294

[0] ETHERNET_INTERFACE_ON: This is input to Ethernet IP. This states if TXCLK, RXCLK to
MAC are to be used from TXCLK, RXCLK pins of Ethernet IP or from internal clock divider
using clock from ClockGen.
0: TXCLK and RXCLK for MAC come from internal clock divider using clock from ClockGen.
1: TXCLK and RXCLK become MII/RMII (CFG_CTRL_E[2]) mode dependent.
RXCLK and TXCLK in MII mode should be given By PHY device.
RXCLK and TXCLK are not used in RMII mode, only PHY_CLK (Ref_Clk) is used.
CFG_CTRL_F Configuration control F

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PIO1_ALTFOP_MUX_SEL_BUS1 PIO1_ALTFOP_MUX_SEL_BUS0 PIO0_ALTFOP_MUX_SEL_BUS1 PIO0_ALTFOP_MUX_SEL_BUS0
l
Type: R/W
tia
Reset: 0x0000
Description: Interconnect configuration control F.
en
[31:24] PIO1_ALTFOP_MUX_SEL_BUS1: Selection of alternative functions on PIO port 1.
Confidential

fid
CFG_CTRL_G Configuration control G

on
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PIO3_ALTFOP_MUX_SEL_BUS1 PIO3_ALTFOP_MUX_SEL_BUS0 PIO2_ALTFOP_MUX_SEL_BUS1 PIO2_ALTFOP_MUX_SEL_BUS0

C
Type: R/W
Reset: 0x0000
Description: Interconnect configuration control G.

174/294 Doc ID 8141465 Rev 5

CFG_CTRL_H Configuration control H

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LMIPADPULLDOWN_CTRL_FROM_CORE
LMIPADPULLUP_CTRL_FROM_CORE
LMI_ZOUTPROGA_FROM_CORE
CFG_FMI4_MASTER_BOOTED
MODEZI_CTRL_FROM_CORE
VID_DAC_POFF_YCC_INT2
USB_POWERDOWN_REQ
PMU_FMI_PD_CFG
RESERVED
RESERVED
RESERVED
RESERVED
l
tia
Type: R/W
Reset: 0000
en
Description: Interconnect configuration control H.
Confidential
[31] MODEZI_CTRL_FROM_CORE: LMI pads modezi control.

0: DDR CMOS input mode
fid
1: DDR SSTL input mode

[30] LMIPADPULLDOWN_CTRL_FROM_CORE: LMI pads PDN (pull down) control.
0: Pull up
1: Pull down
on
This bit along with bit[29] used for LMI pads pull up/pull down control. Both should not be high
at the same time.
[29] LMIPADPULLUP_CTRL_FROM_CORE: Pull up control for LMI pads.
0: Pull down
C
1: Pull up
[28] LMI_ZOUTPROGA_FROM_CORE: LMI ZOUTPROGA control for LMI pads
0: DDR strong output
1: DDR weak output
[27] RESERVED
[26] PMU_FMI_PD_CFG: LMI power down request for self refresh mode
[25:22] RESERVED
[21] CFG_FMI4_MASTER_BOOTED: Configuration to gate FMI4 request until master has booted.
0: Gate the FMI4 request
1: FMI4 request from slave
[20:10] RESERVED
[9] VID_DAC_POFF_YCC_INT2: Video DAC2 power OFF
[8] USB_POWERDOWN_REQ: USB power down request
[7:0] RESERVED
Doc ID 8141465 Rev 5 175/294

CFG_CTRL_I Configuration control I

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CONFIG_PIO_IN_MUX_UART1_RXD
PIO_FUNCTIONALITY_ON_PIO1_7
PIO_FUNCTIONALITY_ON_PIO1_1
BLITTERS3_PRI_CTRL
BLITTERS2_PRI_CTRL
BLITTERS1_PRI_CTRL
ADAC_MODE_SELECT
FMI4_PWRDWN_REQ
BLITTERD_PRI_CTRL
ULPI_PHY_RST_O_N
BLITTERS3_ALT_PRI
BLITTERS2_ALT_PRI
BLITTERS1_ALT_PRI
BLITTERD_ALT_PRI
RESERVED
l
Type: R/W
tia
Reset: 0x0000
Description: Interconnect configuration control I.
en
[31] FMI4_PWRDWN_REQ: Power down request for FMI4.
Confidential
[30] CONFIG_PIO_IN_MUX_UART1_RXD: Control to take UART1_RXD signal either from PIO4[0]

or PIO4[1].
fid
Default 0 = UART1_RXD from PIO4[0], 1 = UART1_RXD from PIO4[1]

[29] RESERVED
[28:27] ADAC_MODE_SELECT: Audio DAC mode selection.
on
[26:25] BLITTERD_PRI_CTRL: Blitter priority.

[24:21] BLITTERD_ALT_PRI: Blitter priority.
[20:19] BLITTERS3_PRI_CTRL: Blitter priority.
[18:15] BLITTERS3_ALT_PRI: Blitter priority.
C

[2] PIO_FUNCTIONALITY_ON_PIO1_7: This bit must be programmed to 1 for PIO1[7].
[1] PIO_FUNCTIONALITY_ON_PIO1_1: This bit must be programmed to 1 for PIO1[1].
[0] ULPI_PHY_RST_O_N: Default at 0.
0: System reset is routed to USB_RESETB pad.
When programmed to 1, ulpi_phy_rst_o_n from USB IP is routed to USB_RESETB pad.
176/294 Doc ID 8141465 Rev 5

CFG_CTRL_J Configuration control J

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLL_EXT_CMD_CTRL
DLL_INT_CMD_CTRL
DLL_DE0_OFF_CMD
DLL_USER_CMD
DLL_OFF_CMD
RESERVED

Type: R/W
Reset: 0x0000
l
Description: Interconnect configuration control J.
[31:29] RESERVED
[28:20] DLL_DE0_OFF_CMD tia
en
[19:11] DLL_USER_CMD
Confidential
[10:2] DLL_OFF_CMD
[1] DLL_INT_CMD_CTRL
fid
[0] DLL_EXT_CMD_CTRL
CFG_CTRL_K Configuration control K

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
on
SC_RST_POLARITY_CFG
QPSK_TUNER_SELECT
DLL_DE1_RST_CMD
DLL_DE1_OFF_CMD
DLL_DE0_RST_CMD
RESERVED

Type: R/W
Reset: 0x0000
Description: Interconnect configuration control K.
[31] SC_RST_POLARITY_CFG: Reset polarity inversion for smartcard.

0: Normal reset from system services
1: Reset inverted
[30:28] RESERVED
[27] QPSK_TUNER_SELECT: Default 0. QPSK tuner signals to QPSK_SCLT and QPSK_SDAT
pads.
Doc ID 8141465 Rev 5 177/294

[26:18] DLL_DE1_RST_CMD:
[17:9] DLL_DE1_OFF_CMD:
[8:0] DLL_DE0_RST_CMD:
CFG_CTRL_L Configuration control L

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QPSKBIST_CMP_COUNT_VAL QPSKBIST_REF_COUNT_VAL

Type: R/W
Reset: 0x0000
l
Description: Interconnect configuration control L.
[31:16] QPSKBIST_CMP_COUNT_VAL: QPSK PLL bist

[15:0] QPSKBIST_REF_COUNT_VAL: QPSK PLL bist tia
en
CFG_CTRL_M Configuration control M
Confidential
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMPENSATION_3V3_SLEEPINHBT
COMPENSATION_3V3_CHIPSLEEP
COMPENSATION_2V5_ACCURATE
COMPENSATION_3V3_ACCURATE
fid
COMPENSATION_2V5_3V3_CFG
COMPENSATION_2V5_FREEZE
COMPENSATION_3V3_FREEZE
GLOBAL_POWER_DOWN_REG
QPSKBIST_PLL_SOURCE_VAL
QPSKBIST_CMP_MASK_VAL
LMI_MEM_BASE_ADDR_SIG
SPI_CS_WHEN_SSC_USED
QPSKBIST_KEEP_FAILS
SPI_BOOTNOTCOMMS
LMIVERF_CFG_CTRL
ULPI_DDR_EN_I
RESERVED
RESERVED
on
C

Type: R/W
Reset: 0x0000
Description: Interconnect configuration control M.
[31] GLOBAL_POWER_DOWN_REG: This bit is used as power down request to mask interrupt to
reach sh4.
[30] LMIVERF_CFG_CTRL: Enable LMIVREF
[29:28] RESERVED
[27] COMPENSATION_3V3_SLEEPINHBT: Compensation control
[26] COMPENSATION_3V3_CHIPSLEEP: Compensation control
[25] COMPENSATION_2V5_FREEZE: Compensation control
178/294 Doc ID 8141465 Rev 5

[24] COMPENSATION_3V3_FREEZE: Compensation control

[23] COMPENSATION_2V5_ACCURATE: Compensation control
[22] COMPENSATION_3V3_ACCURATE: Compensation control
[21] COMPENSATION_2V5_3V3_CFG: Configuration to select compensation from CPU
[20:15] RESERVED
[14] SPI_BOOTNOTCOMMS: Control to use SSC for SPI transactions. Default is 0. SSC0 interface
will be available at PIO1[7:6] and SPI interface will be available to SPI pads.
1: SSC0 will be used for SPI transactions and hence will not be available at PIO1[7:6]
[13] SPI_CS_WHEN_SSC_USED: SPI CS when SSC0 used for SPI transactions. Default is 0.
0: CS is active
[12] ULPI_DDR_EN_I: DDR enable for ULPI operation. Default is 0.
l
0: Normal 8-bit SDR ULPI operation
tia
1: 4-bit DDR ULPI operation
[11:4] LMI_MEM_BASE_ADDR_SIG: LMI memory base address. Default reset value is 0x0C for 29
bit. When program, reset value is 0x40 in 32-bit mode for LMI memory base address.
[3] QPSKBIST_KEEP_FAILS: QPSK bist
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[2] QPSKBIST_PLL_SOURCE_VAL: QPSK bist
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[1:0] QPSKBIST_CMP_MASK_VAL: QPSK bist
CFG_CTRL_N Configuration control N

fid
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
on

Type: R/W
Reset: 0x0000
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Description: Interconnect configuration control N.
[31:0] RESERVED
Doc ID 8141465 Rev 5 179/294

CFG_CTRL_O Configuration control O

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PIO4_ALTFOP_MUX_SEL_BUS1
PIO4_ALTFOP_MUX_SEL_BUS0
RESERVED
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Type: R/W
Reset: 0x0000
Description: Interconnect configuration control O.
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[31:16] RESERVED
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CFG_CTRL_P Configuration control P

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
on
RESERVED

Type: R/W
C
Reset: 0x0000
Description: Interconnect configuration control P.
[31:0] RESERVED
180/294 Doc ID 8141465 Rev 5

CFG_CTRL_Q Configuration control Q

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AD12PP_INMODE1_INT
AD12PP_INMODE0_INT
AD12PP_BIASCLK_INT
AD12PP_TREFM_INT
AD12PP_TREFP_INT
AD12PP_FS50M_INT
AD12PP_FS20M_INT
AD12PP_TVCM_INT
AD12PP_POFF_INT
AD12PP_ULP2_INT
AD12PP_ULP1_INT
AD8S_TREFQ_INT
AD12PP_TBG_INT
AD8S_TREFI_INT
AD8S_TBG_INT
RESERVED

Type: R/W
Reset: 0x0000
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Description: Interconnect configuration control Q.
[31:15] RESERVED
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[14] AD8S_TREFQ_INT: Dual ADCS control
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[13] AD8S_TREFI_INT: Dual ADCS control
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[12] AD8S_TBG_INT: Dual ADCS control

[11] AD12PP_POFF_INT: AD12PP controls
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[10] AD12PP_TBG_INT: AD12PP controls

[9] AD12PP_TVCM_INT: AD12PP controls
[8] AD12PP_BIASCLK_INT: AD12PP controls
on
[7] AD12PP_ULP2_INT: AD12PP controls

[6] AD12PP_ULP1_INT: AD12PP controls
[5] AD12PP_TREFP_INT: AD12PP controls
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[4] AD12PP_TREFM_INT: AD12PP controls

[3] AD12PP_INMODE1_INT: AD12PP controls
[2] AD12PP_INMODE0_INT: AD12PP controls
[1] AD12PP_FS50M_INT: AD12PP controls
[0] AD12PP_FS20M_INT: AD12PP controls
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CFG_CTRL_R Configuration control R

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
Type: R/W
Reset: 0x0000
Description: Interconnect configuration control R.
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[31:0] RESERVED
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on
C
182/294 Doc ID 8141465 Rev 5

STi5189 System services
15 System services
15.1 Brief overview

The system services block groups together a number of functions:
● clock generation and distribution
● low-speed, reduced power monitoring and control
● real-time counter
● integrated clock recovery using a digitally controlled oscillator (DCO)
● smartcard power control
● reset control
● CPU programmable interrupt
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Figure 24. STi5189 system services architecture
STBus
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System services
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DIV Subsystem
30 MHz domain DIV clocks
DIV
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PLL
DIV
VCXO DIV
Xtal Synths
30 MHz
Watchdog
on
Reset
CTRL Subsystem
CTRL reset
LP timer
C
NOT_RESET
Reset out
Wake up from comms
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System services STi5189
15.2 States of operation

Figure 25. States of operation diagram
Reset
x1
Event sw
Prog Rp
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Standby
sw
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There is one mode of operation, which is clock master. Within this mode there are three
states of operation:
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● x1
● programmable (reduced power mode exists within the programmable mode of
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operation)
● standby
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Following reset the system services block transitions into the x1 state causing all clocks to
be sourced from 30 MHz. All other transitions into the x1 state after reset are through
software by programming the MODE_CONTROL register or event-based from the standby
mode.
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To program the divider channels, the software must cause a transition to the x1 state. The
subsystem clocks are shut down (zeroed) in a clean way and then re-started synchronously
using the external 30 MHz clock. The divider channels can then be programmed. When
programming is complete a further software transition is made into the programmable state,
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this transition causes a second clean switch to the newly programmed clock divider outputs.
It is possible to transition from programmable mode to standby mode with software. The
return path transition to x1 mode only occurs if the low power alarm is activated. Also if there
is an external interrupt (wake up) from the comms subsystem.
The reason standby transitions to x1 mode is because the PLL could be disabled within
standby. Therefore, no PLL clocks are running.
15.2.1 Programming the registers

After reset, all registers are locked and cannot be written to. A write can only occur when the
lock register is unlocked. The following procedure can be used to unlock the registers:
1. Unlock the registers by writing the keyword followed by the bitwise inverse.
2. Configure the registers as required.
3. Lock the registers by writing a 1 to the KEY_LOCK bit (bit[8] of the
REGISTER_LOCK_CFG).
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15.3 Clock generation and distribution

The STi5189 clock generation provides the following features:
● Multiple subsystem clocks allowing decoupling of the CPU from the interconnect for
maximum performance
● Dynamic clock change for performance tuning or reduced power
● FMI master-only clock generation and de-skew
● LMI master-only clock generation de-skew is performed in the padlogic
● Digital VCXO clock recovery support for MPEG
STMicroelectronics provides a basic initialization procedure for clock generation setup,
which is available for standard modes.
For flexibility, the clocking scheme is based on two PLLs and two quadruple synthesizers.
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15.3.1 Subsystem clocks
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The subsystem clocks are generated using the frequency synthesizer PLLs as shown in the
following table. The resulting ranges are used to divide the blocks among a number of clock
domains. The CLK_DDR clock is not present in Table 49, which is 4 x CLK_LMI.
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Table 49. Subsystem clock frequencies
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Clock frequency (MHz)

Default
Subsystem Name
source
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Maximum Minimum Default
CLK_ST40_ICK PLL A
ST40 ICK 350 - 350
(700 MHz)
ST40 PCK CLK_ST40_PCK 133 - 133
on
DDR CLK_DDR 800 - 800

Interconnect, PTI, PDES,
CLK_SYS 133 - 133 PLL B
Comms, TVOut
(800 MHz)
C
Blitter CLK_BLT 200 - 200

Ethernet CLK_ETH 100 - 100
Audio decode, LCMPEG CLK_AV 100 - 100
FDMA CLK_FDMA 350 - 350 PLL A
LMI CLK_LMI 200 - 200 PLL B
Spare CLK_SPARE_FS 27 - 27
ADAC, PCM player CLK_PCM 13.8 - 13.8
QFS1
S/PDIF player CLK_SPDIF 13.8 - 13.8
Comms CLK_DSS 27 - 27
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Table 49. Subsystem clock frequencies (continued)

Clock frequency (MHz)
Default
Subsystem Name
source
Maximum Minimum Default
VDAC, TVOut CLK_PIX 54 - 54

Auxiliary clock CLK_AUX 27 - 27
QFS2
FDMA FS CLK_FDMA_FS 27 - 27
USB CLK_USB 48 - 48
LMI padlogic 4 x LMI_CLK 800 - 800 PLL B
15.3.2 PLL clocks
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The STi5189 uses two PLLs in a frequency synthesizer configuration, primarily driven from
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an external 30 MHz crystal.
The PLLs provide system clocks up to 800 MHz. These two clocks are individually
selectable by the programmable dividers that source the clocks shown in Table 49, resulting
in greater system flexibility.
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PLL frequency calculation
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The PLLs have three dividers, which are referred to as M (pre-divider), N (feedback-divider)
and P (post-divider). These dividers are located in the PLLx_CONFIGn registers. The output
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clock of the frequency of the PLL is controlled by binary values applied to the programmable
registers as defined by the following formula:
2× N
F ( clockout ) = ------------------- × F ( refclock )
on
P
M× 2
where the values of M, N and P must satisfy the following constraints:

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1 ≤M ≤256, 1 ≤N ≤256, 0 ≤P ≤5
F ( refclock )
1MHz ≤------------------------------- ≤200MHz
M
2× N
200MHz ≤⎛ --------------⎞ × F ( refclock ) ≤800MHz
⎝ M ⎠
1MHz ≤F ( refclock ) ≤400MHz
⎛ 2× N ⎞
6.25MHz ≤⎜ -------------------⎟ × F ( refclock ) ≤800MHz
⎝ M × 2 P⎠
186/294 Doc ID 8141465 Rev 5

Two PLL frequencies that fulfill the STi5189 system requirements are:
● CLOCKOUT = 700 MHz, NDIV = 70 PDIV = 0 MDIV = 6,
● CLOCKOUT = 800 MHz, NDIV = 80 PDIV = 0 MDIV = 6.
Note: To achieve the correct frequencies, PLLA and PLLB must be programmed with the values
0x2404 and 0x4406, respectively, following a reset, see PLLx_CONFIG0.
Using these frequencies, Table 50 gives subsystem frequencies for functional, reset and
reduced power modes.
Table 50. Clock frequency requirement for different modes

Functional mode Reset Standby mode Reduced power
Source
(1) Divide (2) Divide (3) divider
MHz MHz MHz MHz(4)
ratio ratio
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PLL
PLLxnA 700 N/A 800 N/A 0 0 N/A

PLLxnB 800 N/A 700 N/A 0 0 N/A
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Programmable dividers
CLK_DDR 800 1(B) 800 1(B) 0 30 1

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CLK_LMI 200 4(B) 200 4(B) 30 7.5 1

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CLK_BLT 200 4(B) 200 3(B) 0 15 2

CLK_SYS 133 6(A) 133 6(B) 30 7.5 3
CLK_FDMA 350 2(A) 350 2(A) 0 15 4
on
CLK_AV 100 8(B) 76 8(B) 0 3.75 6

CLK_ETH 100 8(B) 100 8(B) 0 3.75 8
CLK_ST40_ICK 350 2(A) 350 2(A) - 15 9
CLK_ST40_PCK 133 6(B) 133 6(B) - 5 10
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Frequency synthesizers
CLK_SPARE_FS 27 30 0 27 FS-A(0)
CLK_PCM 13.8 30 0 13.8 FS-A(1)
CLK_SPDIF 13.8 N/A 30 N/A 0 13.8 FS-A(2)
CLK_DSS 27 30 0 27 FS-A(3)
CLK_PIX 54 30 0 54 FS-B(0)
CLK_FDMA_FS 27 - 30 - 0 27 FS-B(1)
CLK_AUX 27 - 30 - 0 27 FS-B(2)
CLK_USB 48 - 30 - 0 48 FS-B(3)
1. Func1 frequencies are the recommended frequencies for STi5189.
2. These frequencies are fallback setting in case of X1 to programmable mode not functioning.
3. Stand by behavior of PLL divider clocks is influenced by the configuration of lp_mode_dis0 (0x118 register).
4. During reduced power mode, the programmable dividers are sourced with 30 MHz and the functional divide ratio applied.
For this table, the Func1 divide ratios will be applied.
Doc ID 8141465 Rev 5 187/294

Programmable clock divider

To program the dividers with a particular divide ratio, the following values should be used
from Table 51:
Table 51. Configuration values for programmable divide ratios

Divider
CLKDIVn_DEPTH(1) CLKDIVn_SEQ[19:0](2) CLKDIVn_HNO1 CLKDIVn_EVEN1
divide ratio
2 0x01 0x00AAA 0x1 0x1

3 0x01 0x00DB6 0x0 0x0
4 0x05 0x0CCCC 0x1 0x1
4.5 0x07 0x3399C 0x1 0x0
5 0x04 0x0739C 0x0 0x0
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5.5 0x00 0x0071C 0x1 0x0
6 0x01 0x00E38 0x1 0x1
6.5 0x02 0x01C78 0x1 0x0
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7 0x03 0x03C78 0x0 0x0
7.5 0x04 0x07878 0x1 0x0
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8 0x05 0xF0F0 0x1 0x1

8.5 0x06 0x1E1F0 0x1 0x0
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9 0x07 0x3E1FO 0x0 0x0

9.5 0x08 0x7C1F0 0x1 0x0
10 0x09 0xF83E0 0x1 0x1
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11 0x00 0x7E0 0x0 0x0

12 0x01 0x00FC0 0x1 0x1
13 0x02 0x01FC0 0x0 0x0
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14 0x03 0x03F80 0x1 0x1

15 0x04 0x7F80 0x0 0x0
16 0x05 0x0FF00 0x1 0x1
17 0x06 0x1FF00 0x0 0x0
18 0x07 0x3FE00 0x1 0x1
19 0x08 0x7FE00 0x0 0x0
20 0x09 0xFFC00 0x1 0x1
Semi-synchronous operation
2 0x01 0x00555 0x1 0x1

4 0x05 0x03333 0x1 0x1
6 0x01 0x001C7 0x1 0x1
1. CLKDIVn_CONFIG2
2. CLKDIVn_CONFIG0, CLKDIVn_CONFIG1
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15.3.3 Frequency synthesizer clocks

There are two quadruple frequency synthesizers used within the STi5189 with four
programmable output clocks per frequency synthesizer. The clocks are generated by each
frequency synthesizer using a fixed and stable 30 MHz reference clock. Internally, a
216 MHz frequency is generated as well as thirty two 216 MHz clocks with 32 different
phase offsets. Currently, two outputs from frequency synthesizer B are spare.
The output clock is obtained by a digital algorithm, which selects 1 out of 32 phases. Each
output clock is configurable between 1 MHz and 216 MHz.
Registers control the output frequency and set up using the following parameters:
● MD[4:0] in the [clock]_SETUP0 register: coarse selector for the phase taps selection
(-1 to -16)
● PE[15:0] in the [clock]_SETUP1 register: fine selector for the phase taps selection
(1 to 215)
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● SDIV[2:0] in the [clock]_SETUP0 register: output divider (2 to 256) - SDIV:
– SDIV = 000 divides by 2,
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– SDIV = 111 divides by 256.
Figure 26. Frequency synthesizer

on
32 clocks
30 MHz CLKREF FMX CLKOUT
00 NDIV[1:0]
PLL Phase Digital
1 SELF27 core selector algorithm
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POFF 32:1 Phase selection

216 MHz
MD [4:0]
PE [15:0]
SDIV [2:0]
The frequency of the output clock is given by the formula:

15
2 ⋅ F PLL
F out = --------------------------------------------------------------------------------------------------------------------------------------------------------
MD 15 MD + 1
sdiv × ⎛ pe ⋅ ⎛ 1 + ---------⎞ ⎞ – ⎛ ( PE – 2 ) ⋅ ⎛ 1 + -------------------⎞ ⎞
⎝ ⎝ 32 ⎠ ⎠ ⎝ ⎝ 32 ⎠ ⎠
where FPLL = 216 MHz (27 MHz osc) / 240 MHz (30 MHz osc).
To avoid glitches at the frequency synthesizer output, only the MD, PE and EN_PRG
parameters can be changed.
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Table 52. PCM audio frequency synthesizer (FS1) programming

Fs (kHz) 256 x Fs (MHz) MD [4:0] PE [15:0] SDIV [2:0]
8 2.048 0x1A = 26 0x5100 = 20736 6

11.025 2.8224 0x13 = 19 0x6F05 = 28421 6
12 3.072 0x11 = 17 0x3600 = 13824 6
16 4.096 0x1A = 26 0x5100 = 20736 5
22.05 5.6448 0x13 = 19 0x6F05 = 28421 5
24 6.144 0x11 = 17 0x3600 = 13824 5
(1)
32 8.192 0x1A = 26 0x5100 = 20736 4
44.11 11.2896 0x13 = 19 0x6F05 = 28421 4
1
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48 12.288 0x11 = 17 0x3600 = 13824 4
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64 16.384 0x1A = 26 0x5100 = 20736 3
96 24.576 0x11 = 17 0x3600 = 13824 3
88.2 22.5792 0x13 = 19 0x6F05 = 28421 3
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128 32.768 0x1A = 26 0x5100 = 20736 2
176.4 45.1584 0x13 = 19 0x6F05 = 28421 2
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192 49.152 0x11 = 17 0x3600 = 13824 2

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1. Audio decoder sampling frequency.
Table 53. S/PDIF frequency synthesizer (FS2) programming

S/PDIF_CLK (MHz) MD [4:0] PE [15:0] SDIV [2:0]
on
12.288 (48 kHz x 256) 0x11 = 17 0x3600 = 13824 4

11.2896 (44.1 kHz x 256) 0x13 = 19 0x6F05 = 28421 4
8.192 MHz (32 kHz x 256) 0x1A = 26 0x5100 = 20736 4
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Multiplexing after the frequency synthesizer outputs allows clock switching when in the
standby mode (LP_MODE_SYNTH_DIS[n]). A glitch free multiplexer (GFM) switches
cleanly between frequency synthesizer output when transitioning between the x1 and
programmable states. For further details, see Section 15.5.
For improved performance, FS_CLK[6] can be used as an additional source clock for
CLK_AUX. The switch between the divider clock output and FS_CLK[6] is glitch free and
controlled by the ALT_TRANSPORT_SELECT register. The advantage of using a frequency
synthesizer clock is the maximum frequency of 216 MHz with fine adjust capabilities.
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15.4 Reduced power mode

Reduced power mode gives power saving on individual subsystems and is programmed
through the REDUCED_POWER_CONTROL register. The reduced power is achieved by
sourcing the divider channel with 30 MHz and using the existing programmed divide ratio to
provide a divided 30 MHz subsystem clock output. Bit[11] of the register configures all
dividers to reduced power mode. Bits[10:0] configures all dividers to reduced power mode
for individual subsystems.
15.5 Dynamic power control

The approach to achieve the dynamic power control modes has been to use the divider low
power mode as well as use clock gating for clocks which are shared across the system.
Like CLK_SYS which is being shared widely within the system, a clock gating approach
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using notech cbuf cells is being implemented for the full STi5189 chip. Here, a register
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based configuration bits can switch on and off various IP’s running on CLK_SYS. The
register used for this purpose is DYNAMIC_POWER_CONFIG (0x128: inside the system
services).
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Note the timings to switch OFF a subsystem and then switch it ON again lies with the
software control. Here, the host will take responsibility to make sure when to switch off a
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subsystem by receiving the acknowledgment signals from the IPs and also whether to give a
reset to the system on powering up.
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Figure 27. Dynamic power control architecture
CLK_SYS CP
Cbuf G GDMA
E E
on
TE
G CLK_SYS
CP
CP Blitter
Cbuf G
E
C
CLK_SYS
CP
Cbuf cells
Cbuf G FMI
E
CLK_SYS CLK_SYS CP
Cbuf G TS merger
E
System services Dynamic power control
CLK_SYS
CP
Cbuf G PTI
E
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15.6 Standby mode

Low power control (standby mode) is the shutdown of subsystems in aid of power
consumption. The systems services block is kept operational with crystal 30 MHz and
restarts the subsystem clocks in the event of:
● low power alarm
● external wake up
For additional power saving, the PLLs and frequency synthesizers can also be turned off.
When transitioning back to x1, the subsystems are first clocked off 30 MHz. If registers need
to be programmed, this can also be done during the transition.
Standby mode, like reduced power mode, is software configurable. After programming the
MODE_CONTROL register to the correct value, the system services block transitions from
Fmax subsystem clock to logic 0. Software can also override the standby mode so that
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instead of transitioning to logic 0 the resultant subsystem clock is 30 MHz.
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Note: All divider clocks behavior in the standby mode can be defined (30 MHz/0 MHz) using the
LP_MODE_DIS0 and LP_MODE_DIS1 register.
15.6.1 Low power control

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The low power alarm (LPA) is enabled by LP_COUNT_ENABLE. On assertion of
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LP_COUNT_ENABLE, the LP_COUNT figure is decremented from the preloaded value on

a 1 second timer tick. When the decremented count reaches 0, the low power alarm is
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asserted (the maximum count is 12 days before the low power alarm is asserted).This
causes the control FSM to transition to x1 mode. The other event is the active high external
wake up. This is synchronized into the 30 MHz domain as shown in the following figure:
Figure 28. Low power control architecture

on
25-bit counter
30 MHz
LP_COUNT_ENABLE_REG 1s tick
C
30 MHz
20-bit decrement counter Low
power
alarm Standby
LP_COUNT_REGx*x event
EN =0
D
30 MHz
logic0
External wake up
30 MHz
192/294 Doc ID 8141465 Rev 5

15.7 Real-time counter (RTC)

There are two real-time counters (RTCs) in system services, both run continuously within
separate clock domains. RTC_LP runs at the 32 kHz LPCLKIN (LP clock domain) and
RTC_27 runs at the 30 MHz CLK27IN (30 MHz clock domain). Both RTCs keep track of real
time and run in parallel. System requirements determine which RTC is used. The 32 kHz
LPCLKIN clock is generated inside the system services using the CLK_27 (30 MHz) input.
15.7.1 RTC_LP
RTC_LP is a 64-bit counter. It is shadowed by two 32-bit registers (RTCS_LSB_LP and
RTCS_MSB_LP) in the 30 MHz domain. RTC_LP is never reset and is only programmed
through the shadow registers.
Note: Data is always available for reading and the returned value always agrees with what was last
written, even if not yet accepted by the RTC_LP.
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When a previous write has not yet been accepted, a second write cannot take place.
15.7.2 RTC_27
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RTC_27 runs continuously from a divided CLK27IN tick. The control of the counter is
identical to the control of RTC_LP. The counter tick is a divide of 30 MHz to make it as close
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to 32 kHz (32.768 kHz) as possible. The tick generated is 30 MHz / 824. Therefore, the
generated LPCLKIN is 36.407 kHz.
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15.8 Integrated clock recovery (VCXO)

The integrated clock recovery system adjusts three local clocks generated from a triple
on
frequency synthesizer, which uses a fixed and stable 30 MHz clock produced by a crystal as
a reference.
These three clocks are:
● PIX_CLK (27 MHz) used for standard definition display
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● SPDIF_CLK (74.25 or 148.5 MHz) used for S/PDIF output

● PCM_CLK (256 x Fs where Fs can take several possible values, for example, 32 kHz,
44.1 kHz, 48 kHz) used for audio output
The VCXO (voltage-controlled crystal oscillator) clock recovery scheme is heavily reliant on
interaction between hardware and software. It periodically adjusts the fine adjustment inputs
on frequency synthesizer A and B for two of the outputs. The fine adjustment can be carried
out independently, while the frequency synthesizers give improved jitter performance.
Doc ID 8141465 Rev 5 193/294

Figure 29. Block diagram of the clock recovery module

Clock recovery module
Readable
Free-running counter register
DIN Capture Comparison FS2 set-up
S/PDIF (DCO_HD_CNT) by the CPU values update
frequency LD register with previous value
synthesizer SPDIF_CLK (CPT_SPDIF)
(FS2)
Programmable
30 MHz counter max value
(REF_MAX)
Standard Programmable Zero

definition video reference counter detect
frequency + Interrupt request
(DCO_REF_CNT) resync
synthesizer
(FS0) PIX_CLK
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PCM audio
frequency
synthesizer LD Capture Comparison FS1 set-up
Free-running counter by the CPU values update
(FS1) DIN register
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(CPT_PCM) with previous value
(DCO_PCM_CNT)
PCM_CLK Readable
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register
Note: The FS0 set-up values are updated using the PCR value included in the stream.
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The recovery is done as usual for PIX_CLK by comparing the 42-bit PCR value located in
the adaptation field of the stream, with the local STC value when a packet arrived. This
generates a potential correction that is applied to the PIX_CLK frequency synthesizer. The
frequency synthesizer is programmed with new set-up values to slow or accelerate the
clock.
on
For the audio PCM clock recovery, two counters are used.
● A PCM free-running counter clocked by the PCM audio frequency synthesizer FS1.
● A reference counter clocked by the standard definition video frequency synthesizer
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FS0. The maximum value of this counter is programmable defining the time interval
between two consecutive resets. This counter is used as a time-base.
When this reference counter resets, the values of the free-running counter clocked at
PCM_CLK is captured into a readable register. This event generates an interrupt to the
CPU. The CPU reads the value and compares it with the previously captured value. The
difference between two adjacent values gives an indication of the correction to apply to the
PCM audio frequency synthesizer FS1.
The decision to correct the frequency synthesizer set-up is under the control of the software.
The same principle applies for the recovery of the SPDIF_CLK. A free-running counter is
clocked with the S/PDIF frequency synthesizer FS2. The same reference counter is used.
When this counter resets, the output of the free-running counter clocked at SPDIF_CLK is
captured into a readable register.
The counters are 32-bit counters.
194/294 Doc ID 8141465 Rev 5

15.8.1 Clock recovery command

The clock recovery module accepts the clock recovery reset command, which resets the
reference counter, PCM counter and HD video counter. For further details, see register
DCO_CMD.
15.8.2 Clock recovery interrupts

An interrupt line is available, generated from the internal clock recovery mechanism. The
interrupt is asserted when the reference counter clocked at PIX_CLK resets.
This interrupt status is captured in the DCO_CMD register and only cleared when written.
15.9 Smartcard power control
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Smartcard power control detects when the smartcard has been removed from the system. It
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is hardware detect as power to the smartcard needs to be removed before software can
respond. Smartcard power can be disabled or inverted using SC_CONTROL_CONFIG[0]
as shown in the following figure:
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Figure 30. Smartcard power control architecture
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SC_CONTROL_CONFIG
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Smartcard detect Smartcard power

(internal signal)
on
SC_CONTROL_CONFIG
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15.10 Reset control

The number of different conditions that generate a subsystem or external reset are shown in
Figure 31. These are:
● NOT_RESET
● system services watchdog reset
● ST40 watchdog reset
● long time-out reset
● smartcard insertion reset
● programmable CPU interrupt
Doc ID 8141465 Rev 5 195/294

Figure 31. Reset architecture
30 MHz Other system services
NOT_RESET Timer
De-glitch 10 us
RESETEXTOUT
WATCHDOG_RST_REQ RST
CTRL SC RESET OUT
Watchdog
timer
LT_RST_REQ
Front panel Deglitch and
reset through
l
PIO input 4s timer
tia
en
Tap link Other system ST40-300 1 ms
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services Global asynchronous

reset
stretcher reset tree to all other
subsystems
fid
RESET_GLOBAL
Note: Reset de-assertion is re-timed at the IP level.

on
15.10.1 Combining resets

When RESET_SELECT_ALT in the RESET_STATUS register is selected, resets are
C
combined into one pulse of a minimum 200 ms (stretched reset). The stretched reset is
triggered internally by watchdog, long time-out, NOT_RESET and smartcard insertion
signals as well as by an external reset. Internal resets are maskable. Therefore, the
smartcard insertion reset can be disabled using maskable bits.
15.10.2 Power on reset

The power on reset is either the 200 ms stretched reset or the normal reset. When the
device powers up, if FMI address 23 is pulled high, the RESET_SELECT_ALT bit is written
and the reset stretched.
15.10.3 Watchdog
The watchdog timer is enabled by the WD_COUNT_ENABLE in the
WATCHDOG_COUNTER_CFG1 register. On assertion of WD_COUNT_ENABLE, the
WD_COUNT figure is decremented from the preloaded value on a 1 s timer tick. When the
decremented count reaches 1, the watchdog reset is asserted. This causes a subsystem
and global asynchronous reset. A masking bit in the RESET_STATUS register masks the
watchdog reset.
196/294 Doc ID 8141465 Rev 5

15.10.4 Long time-out reset timer

The long time-out reset timer generates a reset signal if the RST_LONGTIME pin is active
for approximately 4 s. The RST_LONGTIME pin is an enable of a counter that generates a 1
s timer tick. This timer tick clocks a second counter which generates a reset pulse when the
count reaches 4 s, as shown in Figure 32. A de-glitcher provides a clean enable signal to the
synchronous counter. The value of the count is zero when the enable is de-asserted.
A masking bit in the RESET_STATUS register masks the long time-out reset. For further
details, see the following figure:
Figure 32. Long time-out reset timer architecture
Synchronizer
l
RST_LONGTIME
MICRO_TICK (1 μs)
tia
30 MHz longtime counter 22-bit
EN
30 MHz
RESET_LONGTIME_IN_SENSE =4s Long time-out reset
en
Control
30 MHz
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30 MHz
RESET_MASK_BIT[1]
fid
30 MHz
RST_N_HW
on
15.10.5 Smartcard reset detect

When the STi5189 detects that a smartcard has been inserted, it asserts a reset pulse. A
C
deglitcher removes any bounce in the signal from the smartcard. Smartcard reset is enabled
by the SC_INS_RST_EN bit in the SC_INSERTION_RST_CFG register. The sense of the
detect signal can also be inverted using the SC_DETECT_SENSE bit in the same register.
Doc ID 8141465 Rev 5 197/294

15.10.6 SDRAM interface

There are two resets to the SDRAM interface.
● Asynchronous reset to the SDRAM: The SDRAM clock is disabled a number of
cycles before and after the asynchronous reset.
● Soft reset to the DLL: When system services are switched to x1 mode the DLL is
reset so that the lower frequency of SDRAM and LMI clocks does not affect the DLL.
When switching to programmable mode, the DLL comes out of soft reset. The timing
relationship between NOT_RST_DDR the SDRAM clock and the LMI clock is shown in
the following figure:
Note: LMI_CLK is divide by 4 of DDR_CLK.
Figure 33. SDRAM interface timing
l
DDR_CLK
tia
LMI_CLK
en
NOT_RST_DDR
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15.11 CPU programmable interrupt

fid
The CPU programmable interrupt is asserted when a count ranging from 1 ms to 100 ms
reaches zero. The counter (CPU_INT_COUNT_CONFIG[6:0] in CPU_INT_CFG) is
decremented on a microsecond tick. The reset condition is 10 ms but it can be programmed
on
over a range from 1 ms to 100 ms. The generated interrupt is synchronized into the CPU
clock domain. Its status is captured by a status bit in the CPU_INT_CFG register, which is
cleared when written to.
Note: Registers (except addresses 0x160 to 0x16F) are read only until they have been unlocked
C
(write access). This is carried out with the REGISTER_LOCK_CFG register (address
0x300). For further details, see Section 15.2.1: Programming the registers.
198/294 Doc ID 8141465 Rev 5

STi5189 System services registers
16 System services registers
Addresses are provided as the SysServBaseAddress + offset.

The SysServBaseAddress is:
0xFDC0 0000
.
Table 54. System services registers

0x0000 PLLA_CONFIG0 PLLA configuration 0 page 205

0x0004 PLLA_CONFIG1 PLLA configuration 1 page 205
0x008 PLLB_CONFIG0 PLLB configuration 0 page 206
l
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0x00C PLLB_CONFIG1 PLLB configuration 1 page 206
FS216_A setup configuration register
0x010 FS216X4_SETUP_A page 212
(required F10)
0x014 FS216X4_CLK1_SETUP0 FS216 x 4 set up configuration register page 214
en
0x018 FS216X4_CLK1_SETUP1 CLK_SPARE (channel 1) page 218
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0x001C - 0x001F RESERVED - -

0x0020, 0x0030, FS216 x 4 set up configuration register
FS216X4_CLKn_SETUP0 page 215
fid
0x0040 (channel 2, 3 and 4). Here n goes from 2 to 4.

CLK_PCM (channel 2) - required frequency is
13.8 MHz.
0x0024, 0x0034, CLK_SPDIF (channel 3) - required frequency
FS216X4_CLKn_SETUP1 is 13.8 MHz. page 218
0x0044
on
CLK_DSS (channel 4) - required frequency is

27 MHz.
0x0028 - 0x002F
0x0038 - 0x003F RESERVED - -
C
0x0048 - 0x004F
FS216_B setup configuration register
0x0050 FS216X4_SETUP_B page 213
(required F10)
0x0054 FS216X4_CLK5_SETUP0 FS216 x 4 set up configuration register page 216
CLK_PIX (channel 5). Required frequency is
0x0058 FS216X4_CLK5_SETUP1 54 MHz. page 219
0x0060, 0x0070, FS216 x 4 set up configuration register

FS216X4_CLKn_SETUP0 page 217
0x0080 (channel 6, 7 and 8). Here n goes from 6 to 8.
CLK_FDMA_FS (channel 6) - required
frequency is 27 MHz.
0x0064, 0x0074, Auxiliary clock (channel 7) - required
FS216X4_CLKn_SETUP1 frequency is 27 MHz. page 219
0x0084
CLK_USB (channel 8) - required frequency is
48 MHz
Doc ID 8141465 Rev 5 199/294

System services registers STi5189
Table 54. System services registers (continued)

0x005C - 0x005F
0x006C - 0x006F
RESERVED - -
0x0078 - 0x007F
0x0088 - 0x008F
0x090 CLKDIV0_CONFIG0 page 207
0x094 CLKDIV0_CONFIG1 Clock divider configuration page 208
0x098 CLKDIV0_CONFIG2 page 209
0x0A0 CLKDIVn_CONFIG0 page 207
0x0A4 CLKDIVn_CONFIG1 Clock divider configuration page 208
l
0x0A8 CLKDIVn_CONFIG2 page 210
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0x0B0 CLKDIVn_CONFIG0 page 207
0x0B4 CLKDIVn_CONFIG1 Clock divider configuration page 209
0x0B8 CLKDIVn_CONFIG2 page 211
en
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0x0110 MODE_CONTROL Mode FSM control page 201

REDUCED_POWER_CONTR
0x0114 Clock divider reduced power selects page 220
OL
fid
0x0118 LP_MODE_DIS0 Clock divider low power control page 221

0x011C LP_MODE_DIS1 Frequency synthesizer low power control page 222
0x0120 LP_MODE_COUNTER_CFG0 Low power count value page 222
on
0x0124 LP_MODE_COUNTER_CFG1 Low power count value and low power enable page 223
Dynamic power control capability for the full
0x0128 DYNAMIC_POWER_CONFIG page 234
chip
C
0x0128 - 0x012F RESERVED - -

WATCHDOG_COUNTER_CF
0x0130 Watchdog counter value page 231
G0
WATCHDOG_COUNTER_CF
0x0134 Watchdog counter value and watchdog enable page 232
G1
0x0138 - 0x013F RESERVED - -
0x140 RESET_STATUS Reset status page 230
0x144 SC_POWER_DETECT_CFG Smartcard power control page 229
0x148 SC_INSERTION_RST_CFG Smartcard insertion reset control page 231
0x0150 CPU_INT_CFG CPU interrupt control page 233
0x0154 - 0x015F RESERVED - -
0x0160 DCO_SD_COUNT DCO SD count value page 227
0x0164 DCO_CMD DCO command page 227
200/294 Doc ID 8141465 Rev 5

Table 54. System services registers (continued)

0x0168 DCO_PCM_COUNT DCO PCM count value page 228

0x016C DCO_HD_COUNT DCO HD count value page 228
0x0170 DCO_MODE_CFG DCO mode control for pixel/PCM clocks page 226
0x0174 - 0x017C RESERVED - -
0x0180 PLL_SELECT_CFG Multiplexer selects for PLL/dividers page 204
0x0184 FORCE_CFG Force of control FSM page 203
0x0188 CLOCK_OBSERVATION_CFG Multiplexer for o_freq_synth[6] page 202
0x0200 RTCS_LSB_LP Low power timer LSB page 223
l
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0x0204 RTCS_MSB_LP Low power timer MSB page 224
0x0208 RTCS_CONTROL_LP Low power timer control page 224
en
0x210 RTCS_LSB_27 Low power timer LSB page 225
0x214 RTCS_MSB_27 Low power timer MSB page 225
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0x218 RTCS_CONTROL_27 Low power timer control page 226

fid
0x021C - 0x02FF RESERVED - -

0x300 REGISTER_LOCK_CFG Locking/unlocking register control page 202
on
16.1 System services control registers
MODE_CONTROL System services mode control

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C
RESERVED
MODE
Address: SysServBaseAddress + 0x0110

Type: R/W
Reset: 0x0001
Description: Mode FSM control.
[31:2] RESERVED
[1:0] MODE: Mode control:
00: Stay in current state 01: Transition into X1 state
10: Transition into programmable mode 11: Transition into standby mode
Doc ID 8141465 Rev 5 201/294

REGISTER_LOCK_CFG Lock and unlock register control

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
KEY_LOCK
KEY
Type: R/W
Reset: 0x0100
Description: Lock and unlock register control. All registers (except the DCO registers at addresses
at SysServBaseAddress + 0x160 to 0x16F and at DCOBaseAddress) are read only
until they have been unlocked (given write access). This is carried out with this
l
register.
[31:9] RESERVED
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[8] KEY_LOCK: Signifies lock state of registers.
en
0: Registers unlocked for access.
1: All registers locked. Read access only.
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Write a 1 to KEY_LOCK bit to lock all registers.

[7:0] KEY: Unlocking keyword, write keyword followed by bit wise inverse to unlock. The keyword can
fid
be anything, for example:

key[7:0] = 11110000 followed in the next access by
key[7:0] = 00001111
on
CLOCK_OBSERVATION_CFG AUX_CLK alternative sources

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLOCK_OUT_SEL
CLOCK_OBS
RESERVED
C

Type: R/W
Reset: 0x0000
Description: AUX_CLK alternative source. Multiplexer for O_FREQ_SYNTH[6].
[31:6] RESERVED
[5] CLOCK_OBS: Observe alternate clocks on O_FREQ_SYNTH[6].
0: Frequency synthesizer AUX_CLK (default) on O_FREQ_SYNTH[6]
1: Alternate clocks selected by CLOCK_OUT_SEL[4:0]
202/294 Doc ID 8141465 Rev 5

[4:0] CLOCK_OUT_SEL: Select source O_FREQ_SYNTH[6] with other system clocks:

00000: Select O_PLL_CLOCK[0] div by 2 00001: Select O_PLL_CLOCK[1]
00010: Select O_PLL_CLOCK[2] div by 2 00011: Select O_PLL_CLOCK[3]
00100: Select O_PLL_CLOCK[4] div by 2 00101: Select O_PLL_CLOCK[5] div by 4
00110: Select O_PLL_CLOCK[6] 00111: Select O_PLL_CLOCK[7]
01000: Select O_PLL_CLOCK[8] 01001: Select O_PLL_CLOCK[9] div by 2]
01010: Select O_PLL_CLOCK[10] div by 2 01011: Select O_FREQ_SYNTH[0]
01100: Select O_FREQ_SYNTH[1] 01101: Select O_FREQ_SYNTH[2]
01110: Select O_FREQ_SYNTH[3] 01111: Select O_FREQ_SYNTH[4]
10000: Selects O_FREQ_SYNTH[5] 10001: Select O_FREQ_SYNTH[7]
10010: Select CLK_27 10011: Select CLK_LP
Note: The clock observation multiplexer divides clocks greater than 100 MHz to avoid high
frequency clocks on the PCB. Hence, except div6, div7 and div8 all other divider
l
clocks, which are selected on the observation multiplexer clocks, are divided by 2
tia
from their actual values. This is followed to avoid unpredictable behavior on the PCB.
The clock observation multiplexer is used for system testing. It will not be free of
glitches. It is needed purely for observation purposes.
en
FORCE_CFG Force to programmed output in X1 mode
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FS_FORCE[7:0]
PLL_FORCE
RESERVED
fid

on
Type: R/W
Reset: 0x0000
Description: Force to programmed output in X1 mode. Force of control FSM.
C
[31:19] RESERVED
[18:11] FS_FORCE[7:0]: Force frequency synthesizer clocks to programmed output when in X1 mode.
0: X1 mode output clock.
1: FS output clock.
[10:0] PLL_FORCE: Force divider clocks to programmed output when in X1 mode.
0: X1 mode output clock.
1: Divided PLL output clock.
PLL_FORCE[0] to select PLL for PLL_CLOCK[0].
PLL_FORCE[5] to select PLL for PLL_CLOCK[5].
Doc ID 8141465 Rev 5 203/294

16.2 PLL clock generation registers
PLL_SELECT_CFG PLL and divider selection

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALT_TRANSPORT_SELECT
PLL_27_SELECT
PLL_SELECT
RESERVED
l
tia
Type: R/W
Reset: 0x0BDE
Description: PLL and divider selection. Multiplexer selects for PLL/dividers.
en
[31:13] RESERVED
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[12] ALT_TRANSPORT_SELECT: Select source for CLK_AUX signal.

0: Select PLLA or PLLB generated clock divided output.
fid
1: Select FS-B channel 2 (CLK_AUX) as output.

Only glitch clean if programmed within X1 mode.
[11:1] PLL_SELECT: Select PLLA or PLLB for dividers[10:0]. Each bit is for selecting between PLLA
and PLLB for individual channels.
on
0: Select PLLA.
1: Select PLLB.
1 Bit/divider for system flexibility.
Only glitch clean if programmed within X1 mode.
C
The CLK_DDR is sourced from PLLB if either PLL_SELECT[1] or PLL_SELECT[5] = 1. The

source for CLK_DDR is PLLA when both PLL_SELECT[1] and PLL_SELECT[5] are set to 0.
[0] PLL_27_SELECT: Should be set to 0.
204/294 Doc ID 8141465 Rev 5

PLLA_CONFIG0 PLLA configuration 0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED N M

Type: R/W
Reset: 0x4606
Description: PLLA configuration 0. For the reset value 0x4606, frequency of PLLA is 700 MHz.
[31:16] RESERVED
[15:8] N: Pre-divider ratio setup from 1 to 256.
l
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[7:0] M: Pre-divider ratio setup from 1 to 126.
PLLA_CONFIG1 PLLA configuration 1

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
en
RESERVED
RESERVED
SETUP
LOCK
POFF
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P
fid

Type: R/W
Reset: 0x4838
on
Description: PLLA configuration 1.
[31:16] RESERVED
C
[15] LOCK: Read only.

[14] RESERVED
[13] POFF: Power down control.
0: Power ON
1: Power OFF
[12:3] SETUP: Not connected. Reserved.
[2:0] P: Post-divider ratio setup from 1 to 32.
Doc ID 8141465 Rev 5 205/294

PLLB_CONFIG0 PLLB configuration 0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED N M

Type: R/W
Reset: 0x5006
Description: PLLB configuration 0. For the reset value 0x5006, frequency of PLLB is 800 MHz.
[31:16] RESERVED
[15:8] N: Pre-divider ratio setup from 1 to 256.
l
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[7:0] M: Pre-divider ratio setup from 1 to 126.
PLLB_CONFIG1 PLLB configuration 1

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
en
RESERVED
RESERVED
SETUP
LOCK
POFF
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P
fid
Address: SysServBaseAddress + 0x000C

Type: R/W
Reset: 0x4838
on
Description: PLLB configuration 1.
[31:16] RESERVED
C
[15] LOCK: Read only.

[14] RESERVED
[13] POFF: Power down control.
0: Power ON
1: Power OFF
[12:3] SETUP: Not connected. Reserved.
[2:0] P: Post-divider ratio setup from 1 to 32.
206/294 Doc ID 8141465 Rev 5

CLKDIV0_CONFIG0 Clock divider sequence bit pattern

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CLKDIV_SEQ

Type: R/W
Reset: 0x0DB6
Description: Clock divider sequence bit pattern.
[31:16] RESERVED
[15:0] CLKDIV_SEQ: Clock divider divides sequence bit pattern.
l
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CLKDIVn_CONFIG0 Clock divider sequence bit pattern
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CLKDIV_SEQ
en
Address: SysServBaseAddress + 0x0A0 + (n - 1) * 0x0C (where n = 1 to 4)
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Type: R/W
fid
Reset: 0xCCCC, 0xCCCC, 0x0E38, 0x0AAA

on
[31:16] RESERVED

C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CLKDIV_SEQ
Address: SysServBaseAddress + 0x0D0 + (n - 6) * 0x0C (where n = 6 to 10)

Type: R/W
Reset: 0xF0F0, 0xF0F0, 0xF0F0, 0x0AAA, 0x0E38
[31:16] RESERVED
Doc ID 8141465 Rev 5 207/294


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLKDIV_SEQ[19:16]
RESERVED
Type: R/W
Reset: 0x0000
l
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[31:5] RESERVED
[4:0] CLKDIV_SEQ[19:16]: Clock divider divides sequence bit pattern.
en
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLKDIV_SEQ[19:16]
fid RESERVED
on

Type: R/W
Reset: 0x0000, 0x0000, 0x0000, 0x0000
C
[31:5] RESERVED
208/294 Doc ID 8141465 Rev 5


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLKDIV_SEQ[19:16]
RESERVED
Type: R/W
Reset: 0x0000, 0x0000, 0x0000, 0x0000, 0x0000
l
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[31:5] RESERVED
en
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLKDIV_DEPTH
CLKDIV_EVEN
CLKDIV_HNO
CLKDIV_EN
RESERVED
fid
on

Type: R/W
Reset: 0x0011
C
[31:7] RESERVED
[6] CLKDIV_HNO:
EVEN 0 HNO 0: Divide by odd whole number, for example, 5
EVEN 0 HNO 1: Divide by half ratio, for example, 4.5
EVEN 1 HNO 1: Divide by even whole number, for example, 6
EVEN 1 HNO 0: RESERVED
[5] CLKDIV_EVEN:
EVEN 1 HNO 0: RESERVED
[4] CLKDIV_EN: RESERVED. This bit is always set to 1.
Doc ID 8141465 Rev 5 209/294

[3:0] CLKDIV_DEPTH: Number of sequence bits, binary coded.

If depth 0000 = 11 bits, then increments by 1 up to 19 bits.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLKDIV_DEPTH
CLKDIV_EVEN
CLKDIV_HNO
CLKDIV_EN
RESERVED
Type: R/W
l
Reset: 0x0075, 0x0075, 0x0071, 0x0071
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[31:7] RESERVED
en
[6] CLKDIV_HNO:
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fid
EVEN 1 HNO 0: Reserved

[5] CLKDIV_EVEN:
on

[4] CLKDIV_EN: Reserved. This bit is always set to 1.
C

210/294 Doc ID 8141465 Rev 5


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLKDIV_DEPTH
CLKDIV_EVEN
CLKDIV_HNO
CLKDIV_EN
RESERVED
Type: R/W
Reset: 0x0075, 0x0075, 0x0075, 0x0071, 0x0071
l
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[31:7] RESERVED
[6] CLKDIV_HNO:
en
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[5] CLKDIV_EVEN:
fid

on
[4] CLKDIV_EN: Reserved. This bit is always set to 1.

C
Doc ID 8141465 Rev 5 211/294

16.3 Frequency synthesizer clock generation registers
FS216X4_SETUP_A Set up frequency synthesizer

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SELBW_X4[1:0]
NSB_X4[3:0]
RESERVED
RESERVED
SELSDIV3
POFF_X4
NRST
NDIV
Type: R/W
Reset: 0xF10
l
Description: FS216_A set up configuration register (required F10).
[31:12] RESERVED
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[11:8] NSB_X4[3:0]: Active low standby for digital parts of frequency synthesizer.
en
NSB[0] = FS / CLK1
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[7] SELSDIV3(1): Common div3 control.

0: Disable
1: Enable
fid
[6:5] SELBW_X4[1:0]: Select clock bandwidth.

[4] NRST: Active low reset of digital part of frequency synthesizer (gated with reset).
[3] POFF_X4: QUAD FS216x4 control.
on
0: Analog part switched ON

1: Analog part switched OFF
[2:1] RESERVED
C
[0] NDIV: QUAD FS216x4 control. Coding of the input divider, if NDIX is set to:
0: Input frequency is 27 MHz (24 MHz and 30 MHz).
1: Input frequency is 54 MHz.
1. SELSDIV3 functionality is not supported by the Quad FS analog IP. Hence, whether SELSDIV3 is 0 or 1 does not in any
way affect the FS operation.
212/294 Doc ID 8141465 Rev 5

FS216X4_SETUP_B Set up frequency synthesizer

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SELBW_X4[1:0]
NSB_X4[3:0]
RESERVED
RESERVED
SELSDIV3
POFF_X4
NRST
NDIV
Type: R/W
Reset: 0xF10
Description: FS216_B set up configuration register (required F10).
l
tia
[31:12] RESERVED
[11:8] NSB_X4[3:0]: Active low standby for digital parts of frequency synthesizer.
NSB[0] = FS / CLK1
[7] SELSDIV3(1): Common div3 control.
en
0: Disable
1: Enable
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[6:5] SELBW_X4[1:0]: Select clock bandwidth.

fid
[4] NRST: Active low reset of digital part of frequency synthesizer (gated with reset).
[3] POFF_X4: QUAD FS216 x 4 control
0: Analog part switched ON.
1: Analog part switched OFF.
on
[2:1] RESERVED
[0] NDIV: QUAD FS216 x 4 control. Coding of the input divider, if NDIX is set to:
0: Input frequency is 27 MHz (24 MHz and 30 MHz).
1: Input frequency is 54 MHz.
C
1. SELSDIV3 functionality is not supported by the Quad FS analog IP. Hence, whether SELSDIV3 is 0 or 1 does not in any
way affect the FS operation.
Doc ID 8141465 Rev 5 213/294

FS216X4_CLK1_SETUP0 Clock set up 0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
RESERVED
SEL_OUT
EN_PRG
OP_EN
SDIV3
SDIV
MD
Type: R/W
Reset: 0x0AF1
Description: FS216 x 4 set up configuration register for channel 1. The required frequency of
channel 1 (clk_spare) is 27 MHz.
l
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[31:13] RESERVED
[12] SDIV3: Div3 control option.
0: Disable
1: Enable
en
This is inverted to the quad frequency synthesizer macro for backwards compatibility.
[11] OP_EN: Output enable for CLK.
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0: Output disable
1: Output enable
fid
This bit should always be set at 1.

[10] RESERVED
[9] SEL_OUT
0: CLK is the signal given by EXT_CLK.
on
1: CLK is the clock generated by the frequency synthesizer (normal use).

[8:6] SDIV: Programming of the output divider from 2 to 256 for CLK generation.
[5] EN_PRG: New incoming data (ME and PE) are taken into account when set to 1.
C
EN_PRG has no effect for PIX_CLK, PCM_CLK and SPDIF_CLK clocks. The EN_PRG pin for
these channels is controlled by the DCO_MODE_CFG register.
[4:0] MD: Coarse selector bus for digital algorithm of the phase taps choice.
214/294 Doc ID 8141465 Rev 5

FS216X4_CLKn_SETUP0 Clock set up 0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
RESERVED
SEL_OUT
EN_PRG
OP_EN
SDIV3
SDIV
MD
Address: SysServBaseAddress + 0x020 + (n-2) * 0x010 (where n = 2 to 4)
Type: R/W
Reset: 0xB31, 0xB31, 0x0AF1
Description: FS216 x 4 set up configuration registers for channel 2, 3 and 4. The required
frequency of:
channel 2 (CLK_PCM) is 13.8 MHz,
l
tia
channel 3 (CLK_SPDIF) is 13.8 MHz,
channel 4 (CLK_DSS) is 27 MHz.
en
[31:13] RESERVED
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0: Disable
1: Enable
fid
0: Output disable
1: Output enable
on

[10] RESERVED
[9] SEL_OUT
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Doc ID 8141465 Rev 5 215/294


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
RESERVED
SEL_OUT
EN_PRG
OP_EN
SDIV3
SDIV
MD
Type: R/W
Reset: 0xAB1
Description: FS216 x 4 set up configuration register for channel 5. The required frequency for
channel 5 (CLK_PIX) is 54 MHz. Recommended frequency is 27 MHz. Hence,
program the value 0x0EBF.
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[31:13] RESERVED
0: Disable
en
1: Enable
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0: Output disable
fid
1: Output enable
[10] RESERVED
[9] SEL_OUT
on

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216/294 Doc ID 8141465 Rev 5


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
RESERVED
SEL_OUT
EN_PRG
OP_EN
SDIV3
SDIV
MD
Address: SysServBaseAddress + 0x060 + (n - 6) * 0x010 (where n = 6 to 8)
Type: R/W
Reset: 0xAF1, 0xAF1, 0x0AB3
frequency for:
channel 6 (CLK_FDMA_FS) is 27 MHz,
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channel 7 (auxiliary clock) is 27 MHz,
channel 8 (CLK_USB) is 48 MHz.
en
[31:13] RESERVED
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0: Disable
1: Enable
fid
0: Output disable
1: Output enable
on

[10] RESERVED
[9] SEL_OUT
C

these channels is controlled by DCO_MODE_CFG.
Doc ID 8141465 Rev 5 217/294


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED PE

Type: R/W
Reset: 0x01C72
Description: FS216 x 4 set up configuration register for channel 1. The required frequency of
channel 1 (CLK_SPARE) is 27 MHz.
[31:16] RESERVED
l
[15:0] PE: Fine selector bus for digital algorithm of the phase taps choice.
FS216X4_CLKn_SETUP1
tia
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6
Clock set up 1
5 4 3 2 1 0
en
RESERVED PE
Confidential
Address: SysServBaseAddress + 0x024 + (n-2) * 0x010 (where n = 2 to 4)

Type: R/W
fid
Reset: 0x4DEA, 0x4DEA, 0x1C72

frequency of:
on
channel 2 (CLK_PCM) is 13.8 MHz,

channel 3 (CLK_SPDIF) is 13.8 MHz,
channel 4 (CLK_DSS) is 27 MHz.
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[31:16] RESERVED
218/294 Doc ID 8141465 Rev 5


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED PE

Type: R/W
Reset: 0x1C72
Description: FS216 x 4 set up configuration register for channel 5. The required frequency for
channel 5 (CLK_PIX) is 54 MHz. Recommended frequency is 27 MHz. Hence,
program the value 0x0EBF.
l
[31:16] RESERVED
tia

en
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED PE
Confidential
Address: SysServBaseAddress + 0x064 + (n - 6) * 0x010 (where n = 6 to 8)

fid
Type: R/W
Reset: 0x1C72, 0x1C72, 0x0000
on
frequency for:
channel 6 (CLK_FDMA_FS) is 27 MHz,
channel 7 (auxiliary clock) is 27 MHz,
C
channel 8 (CLK_USB) is 48 MHz.
[31:16] RESERVED
Doc ID 8141465 Rev 5 219/294

16.4 Reduced power control
REDUCED_POWER_CONTROL Select reduced power mode.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RP_SEL_ETHERNET
RP_SEL_ST40_PCK
RP_SEL_ST40_ICK
RP_SEL_SPARE
RP_SEL_FDMA
RP_SEL_DDR
RP_SEL_SYS
RP_SEL_LMI
RP_SEL_BIT
RP_SEL_AV
RESERVED
RESERVED
PLL_SEL
Type: R/W
l
Reset: 0x0000
tia
Description: Select reduced power mode. Bit[11] of this register configures all dividers to reduced
power mode. Bits[10:0] configures all dividers to reduced power mode on an
individual basis and selects reduced power mode for a particular programmable
divider.
en
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[31:12] RESERVED
[11] PLL_SEL: Select reduced power for all programmable dividers.
fid
[10] RP_SEL_ST40_PCK: Select reduced power mode for CLK_ST40_PCK.

[9] RP_SEL_ST40_ICK: Select reduced power mode for CLK_ST40_ICK.
[8] RP_SEL_ETHERNET: Select reduced power mode for CLK_ETH (Ethernet clock).
on
[7] RP_SEL_SPARE: Spare clock.

[6] RP_SEL_AV: Select reduced power for CLK_AV going to LCMPEG.
[5] RP_SEL_DDR: Select reduced power for DDR.
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General information:
Bit[1] or bit[5]) = DDR reduced power
Bit[1] is for LMI clock and bit[5] is for DDR clock.)
[4] RP_SEL_FDMA: Select reduced power for CLK_FDMA.
[3] RP_SEL_SYS: Select reduced power for CLK_SYS, which is being shared and going to
multiple locations.
[2] RP_SEL_BIT: Select reduced power for CLK_BIT.
[1] RP_SEL_LMI: Select reduced power for CLK_LMI.
[0] RESERVED
220/294 Doc ID 8141465 Rev 5

16.5 Low power control registers
LP_MODE_DIS0 Subsystem clocks when in standby mode

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LP_MODE_PLL_DIS
LP_MODE_DIV_DIS
RESERVED
Type: R/W
l
Reset: 0x07F5
tia
Description: Clock divider low power control register.
[31:13] RESERVED
en
[12:11] LP_MODE_PLL_DIS: Disables PLL clocks when in the standby mode.
Confidential
If bit[11] is 1, PLLA is at logic 0 when in the standby mode.

If bit[12] is 1, PLLB is at logic 0 when in the standby mode.
This is to give lower power requirements in the standby mode.
fid
[10:0] LP_MODE_DIV_DIS: Disable sub-system clock when in the standby mode.

If bit[0] is 1, O_PLL_CLOCK[0] is at logic 0 when in the standby mode.
If bit[4] is 1, O_PLL_CLOCK[4] is at logic 0 when in the standby mode.
on
If not asserted then O_PLL_CLOCK[*] is 27 MHz.

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Doc ID 8141465 Rev 5 221/294

LP_MODE_DIS1 Subsystem clocks when in standby mode

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LP_MODE_FS216X4_DIS
LP_MODE_SYNTH_DIS
Address: RESERVED
SysServBaseAddress + 0x011C
Type: R/W
Reset: 0x00FF
l
Description: Frequency synthesizer low power control register.
[31:10] RESERVED
tia
[9:8] LP_MODE_FS216X4_DIS: Disable frequency synthesizer clocks when in the standby mode.
en
This is to give lower power requirements in the standby mode: 10 mW max (analog), 8 mW max
(digital).
Confidential
If bit[8] is 1, FS216_A analog component is switched off.

If bit[9] is 1, FS216_B analog component is switched off.
fid
[7:0] LP_MODE_SYNTH_DIS: Disable sub-system clock when in the standby mode.

If bit[0] is 1, O_SYNTH_CLOCK[0] is at logic0 when in the standby mode.
If bit[4] is 1, O_SYNTH_CLOCK[4] is at logic0 when in the standby mode.
At this stage, O_SYNTH_CLOCK[7:6] are not used.
on
If not asserted then O_SYNTH_CLOCK[*] is 27 MHz.
LP_MODE_COUNTER_CFG0 Low power counter configuration

C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED LP_COUNT

Type: R/W
Reset: 0xFFFF
Description: Low power count value.
[31:16] RESERVED
[15:0] LP_COUNT: Low power count. Binary coded.
LP_COUNT[19:0]. Maximum count of 1048576 seconds.
222/294 Doc ID 8141465 Rev 5

LP_MODE_COUNTER_CFG1 Low power counter configuration

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LP_COUNT_ENABLE
LP_COUNT[19:16]
RESERVED
Type: R/W
Reset: 0x000F
Description: Low power count value and low power enable.
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[31:5] RESERVED
[4] LP_COUNT_ENABLE: Low power counter enable.
en
[3:0] LP_COUNT[19:16]: Low power count value programmed by comms subsystem through
interconnect. Binary coded.
Confidential
LP_COUNT[19:0]. Maximum count of 1048576 seconds.

fid
16.6 Real-time counter registers
16.6.1 CLK_LP
on
RTCS_LSB_LP Low power timer LSB

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCS_LSB
C

Type: R/W
Reset: 0x00000000
Description: Low power timer LSB register.
[31:0] RTCS_LSB(1): LSW and MSW of RTC_LP register except during the low power mode and
when writing a new value to the RTC.
1. This is overwritten by the counter on the first CLK_LP after reset removal.
Doc ID 8141465 Rev 5 223/294

RTCS_MSB_LP Low power timer MSB

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCS_MSB

Type: R/W
Reset: 0x00000000
Description: Low power timer MSB register.
[31:0] RTCS_MSB(1): LSW and MSW of RTC_LP register except during the low power mode and
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1. This is overwritten by the counter on the first CLK_LP after reset removal.
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RTCS_CONTROL_LP Low power timer control
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTC_START_REG
en RESERVED
Confidential
fid

Type: R/W
on
Reset: 0x0000
Description: Low power timer control.
[31:1] RESERVED
C
[0] RTC_START_REG
0: Does not stop counting
1: Starts RTC_LP counting
224/294 Doc ID 8141465 Rev 5

16.6.2 CLK_27
RTCS_LSB_27 Low power timer LSB

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCS_LSB

Type: R/W
Reset: 0x00000000
Description: Low power timer LSB register.
l
[31:0] RTCS_LSB(1): LSW and MSW of RTC_27 register except during the low power mode and
tia
1. This is overwritten by the counter on the first rtc27 tick after reset removal.
RTCS_MSB_27 Low power timer MSB

en
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Confidential
RTCS_MSB
fid

Type: R/W
Reset: 0x00000000
on
Description: Low power timer MSB register.
[31:0] RTCS_MSB(1): LSW and MSW of RTC_27 register except during the low power mode and
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1. This is overwritten by the counter on the first rtc27 tick after reset removal.
Doc ID 8141465 Rev 5 225/294

RTCS_CONTROL_27 Low power timer control

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTC_START_REG
RESERVED
Type: R/W
Reset: 0x0000
Description: Low power timer control.
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[31:1] RESERVED
[0] RTC_START_REG
0: Does not stop counting
en
1: Starts RTC_27 counting
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16.7 Integrated clock recovery (DCO) registers

fid
DCO_MODE_CFG DCO mode control

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNTHESIZER_MODE
on
RESERVED
C

Type: R/W
Reset: 0x0000
Description: DCO mode control for pixel/PCM clocks.
[31:1] RESERVED
[0] SYNTHESIZER_MODE: DCO FSM control bit.
0: Program complete/switch to glitch free clock.
1: Program EN/PE/MD bits.
226/294 Doc ID 8141465 Rev 5

DCO_SD_COUNT DCO reference counter

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCO_SD_CNT

Type: R/W
Reset: 0x00000000
Description: DCO SD reference count load value.
[31:0] DCO_SD_CNT: DCO SD reference count load value is read when DCP_CMD/LD is 1 or
SD_COUNT is 0.
l
DCO_CMD DCO command
tia
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
INT
LD
en
Confidential

Type: R/W
fid
Reset: 0x0001
Description: DCO command register.
on
[31:2] RESERVED
[1] INT: Interrupt
When read:
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0: No interrupt
1: Interrupt
When 1 is written to this bit, the interrupt is cleared and the bit must return to 0 to allow correct
operation.
[0] LD: Reference counter load.
0: Allows counting.
1: Loads reference counter (SD) with DCO_SD_COUNT and PCM/HD count loaded with zero.
Doc ID 8141465 Rev 5 227/294

DCO_PCM_COUNT DCO PCM count value

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCO_PCM_CNT

Type: R
Reset: 0x00000000
Description: DCO OCM count value.
[31:0] DCO_PCM_CNT: DCO PCM count value, when int = 1.
l
DCO_HD_COUNT DCO HD count value
tia
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCO_HD_CNT
en
Address: SysServBaseAddress + 0x016C
Type: R
Confidential
Reset: 0x00000000
fid
Description: DCO HD count value.
[31:0] DCO_HD_CNT: DCO HD count value, when int = 1.

on
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228/294 Doc ID 8141465 Rev 5

16.8 Smartcard power control registers
SC_POWER_DETECT_CFG Smartcard power control

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SC_CTRL_SMARTCARD1_DISAB
SC_CTRL_SMARTCARD0_DISAB
SC_CTRL_SMARTCARD1_EN
SC_CTRL_SMARTCARD0_EN
RESERVED
l
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Type: R/W
Reset: 0x0000
en
Description: Smartcard power control.
Confidential
[31:4] RESERVED
fid
[3] SC_CTRL_SMARTCARD1_DISABLE: Disable smartcard power control for smartcard1.

0: Disable
1: Enable
[2] SC_CTRL_SMARTCARD1_EN: Enable non-inverted/inverted sense power control for
on
smartcard1.
0: Enable non-inverted sense
1: Enable inverted sense
[1] SC_CTRL_SMARTCARD0_DISABLE: Disable smartcard power control for smartcard0.
C
0: Disable
1: Enable
[0] SC_CTRL_SMARTCARD0_EN: Enable non-inverted/inverted sense power control for
smartcard0.
Doc ID 8141465 Rev 5 229/294

16.9 Reset control registers
RESET_STATUS Reset status

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TST_SCANMODE_RESET_STATUS
LONG_TIMEOUT_RESET_STATUS
RESET_LONGTIME_IN_SENSE
SC_DETECT_RESET_STATUS
RESET_SC_OUT_SENSE
RESET_MASK_BITS[2:0]
RESET_SELECT_ALT
RST_N_PAD_STATUS
WD_RESET_STATUS
RESERVED
RESERVED
RESERVED
l
tia
Type: R/W
Reset: 0x05C0
en
Description: Reset status.
Confidential
[31:14] RESERVED
fid
[13] RESET_LONGTIME_IN_SENSE
0: Active high 1: Active low
[12] RESET_SC_OUT_SENSE
0: Active high 1: Active low
on
(1):
[11] RESET_SELECT_ALT Select 200 ms reset for all reset sources. Alternate reset
capabilities.
0: Select 200 ms reset pulse 1: Select other resets
[10:9] RESERVED
C
[8:6] RESET_MASK_BITS[2:0]:
0: No mask on reset 1: Mask on reset
bit[6] mask for watchdog reset. bit[7] mask for long time reset.
bit[8] mask for smartcard detect reset.
[5] TST_SCANMODE_RESET_STATUS(2):
0: No scanmode reset asserted 1: Scanmode reset asserted
(2)
[4] RST_N_PAD_STATUS
0: No pad reset asserted 1: Reset state
(2)
[3] SC_DETECT_RESET_STATUS
0: No smartcard detect reset asserted 1: Smartcard detect reset asserted
[2] RESERVED
[1] LONG_TIMEOUT_RESET_STATUS(2)
0: No long time out reset asserted 1: Long time out reset asserted
(2)
[0] WD_RESET_STATUS
0: No watchdog reset asserted 1: Watchdog reset asserted
1. Do not select this within 200 ms of a normal non 200 ms reset as it will go into another reset.
230/294 Doc ID 8141465 Rev 5

2. To clear status bits[5:0], write 0 operation followed by write 1 operation for that bit is required to clear it.
WATCHDOG_COUNTER_CFG0 Watchdog counter 0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED WD_COUNT

Type: R/W
Reset: 0xFFFF
Description: Watchdog count value.
l
[31:16] RESERVED
tia
[15:0] WD_COUNT: Watchdog program value. Binary coded.
Maximum count of 1048576 seconds. This does not record the current watchdog count.
SC_INSERTION_RST_CFG Smartcard insertion reset control

en
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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SC1_RDP_CONTROL_ENABLE
SC0_RDP_CONTROL_ENABLE
SC_DETECT_SENSE
fid
SC_INS_RST_EN
RESERVED
on

C
Type: R/W
Reset: 0x0000
Description: Smartcard insertion reset control.
[31:6] RESERVED
[5] SC1_RDP_CONTROL_ENABLE
SC1_RDP_CONTROL_ENABLE active high onto O_SYS_SER_SPARE[1]. When high,
override all other functional controls on SC0 set of pads.
[4] SC0_RDP_CONTROL_ENABLE
SC0_RDP_CONTROL_ENABLE active high onto O_SYS_SER_SPARE[0]. When high,
override all other functional controls on SC0 set of pads.
Doc ID 8141465 Rev 5 231/294

[3:2] SC_DETECT_SENSE: Enable non-inverted/inverted sense of smartcard insertion.

bit[2] is for smartcard 0.
[1:0] SC_INS_RST_EN: This is an echostar specific requirement.
0: No hardware insertion reset
1: Hardware insertion reset
Note: Software should always set bit[1] and bit[3] to 0 value. Software should never assert
the reset generation for smartcard 1.
l
WATCHDOG_COUNTER_CFG1 Watchdog counter 1
tia
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WD_COUNT_ENABLE
WD_COUNT[19:16]
RESERVED
en
Confidential
fid

Type: R/W
Reset: 0x000F
on
Description: Watchdog count value and watchdog enable.
[31:5] RESERVED
C
[4] WD_COUNT_ENABLE: Watchdog counter enable (loads and starts count).

[3:0] WD_COUNT[19:16]: Watchdog count. Binary coded.
Maximum count of 32767 seconds.
232/294 Doc ID 8141465 Rev 5

16.10 CPU programmable interrupt timer register
CPU_INT_CFG CPU interrupt control configuration

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_INT_COUNT_CONFIG
CPU_INT_STATUS
RESERVED
l
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Type: R/W
Reset: 0x000A
Description: CPU interrupt control configuration.
en
[31:8] RESERVED
Confidential
[7] CPU_INT_STATUS: When read shows status of interrupt:

0: Interrupt not reached
fid
1: Interrupt reached
Writing 0 clears interrupt and status.
Writing from 0 to 1, loads a new count value and the count is started. Leave at 1 to continue
counting.
on
[6:0] CPU_INT_COUNT_CONFIG: Count value programmable between 1.024 ms to ~130 ms in

1.024 ms increments.
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Doc ID 8141465 Rev 5 233/294

16.11 Dynamic power control register
DYNAMIC_POWER_CONFIG Dynamic power control capability

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DP_CONTROL_TSMERGER_SYS
DP_CONTROL_AUD_DECODER_
DP_CONTROL_ETHERNET_SYS
DP_CONTROL_TILERAM_SYS
DP_CONTROL_LCMPEG_SYS
DP_CONTROL_GDMA_SYS
DP_CONTROL_FDMA_SYS
DP_CONTROL_PDES_SYS
DP_CONTROL_CLKBDISP
DP_CONTROL_CLKFDMA
DP_CONTROL_BLIT_SYS
DP_CONTROL_USB_SYS
DP_CONTROL_FMI_SYS
DP_CONTROL_PTI_SYS
DP_CONTROL_CLKUSB
DP_CONTROL_SPARE
DP_CONTROL[0]
l
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Type: R/W
Reset: 0x0000
en
Description: Dynamic power control capability for the full chip.
Confidential
[31:16] DP_CONTROL_SPARE: Spare bits to further support clock gating and power within the chip.
fid
[15] DP_CONTROL[0]: Spare.

0: No clock gating, normal clock.
1: Power down, clock is stopped to the IP/system concerned.
[14] DP_CONTROL_CLKFDMA: FDMA clock gating control for CLK_FDMA.
on

[13] DP_CONTROL_CLKUSB: USB clock gating control for CLK_USB.
C

[12] DP_CONTROL_CLKBDISP: Blitter clock gating control for CLK_BDISP.
[11] DP_CONTROL_PDES_SYS: PDES clock gating control for CLK_SYS.
[10] DP_CONTROL_TILERAM_SYS: Tile RAM clock gating control for CLK_SYS.
[9] DP_CONTROL_BLIT_SYS: Blitter clock gating control for CLK_SYS.
[8] DP_CONTROL_FMI_SYS: FMI clock gating control for CLK_SYS.
234/294 Doc ID 8141465 Rev 5

[7] DP_CONTROL_FDMA_SYS: FDMA clock gating control for CLK_SYS.

[6] DP_CONTROL_ETHERNET_SYS: Ethernet clock gating control for CLK_SYS.
[5] DP_CONTROL_PTI_SYS: PTI clock gating control for CLK_SYS.
[4] DP_CONTROL_TSMERGER_SYS: TS merger clock gating control for CLK_SYS.
[3] DP_CONTROL_AUD_DECODER_SYS: Audio decoder clock gating control for CLK_SYS.
l
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[2] DP_CONTROL_USB_SYS: USB clock gating control for CLK_SYS.
en
[1] DP_CONTROL_GDMA_SYS: GDMA clock gating control for CLK_SYS.
Confidential

fid
[0] DP_CONTROL_LCMPEG_SYS: LCMPEG clock gating control for CLK_SYS.

Note: For the top-level SoC integrator, use inverter and cbuf cells as shown in Figure 27.
on
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Doc ID 8141465 Rev 5 235/294

Interrupt system STi5189
17 Interrupt system
17.1 Overview
The interrupt system allows an on-chip module or external interrupt pin to interrupt an active
process so that an interrupt handling process can be run. Interrupts are signaled by one of
the following:
● a signal on an external interrupt pin
● a signal from an internal peripheral or subsystem
● software asserting an interrupt in the pending register
Interrupts are implemented by an on-chip interrupt controller (For further details, see
Section 17.2: Interrupt controller) and an on-chip interrupt level controller (ILC) (For further
l
details, see Section 17.3: Interrupt handlers). The ILC multiplexes the 46 incoming interrupt
tia
sources onto the 20 programmable ILC interrupt level inputs (16 to the CPU and 4 available
externally). Multiplexing is controlled by software. An overview of the interrupt system is
shown in the following figure:
Figure 34. Interrupt network

en
ST40-300
Confidential
Interrupt
To PIO3[0:3] controller
interrupt steering output Four external, off chip interrupts
NMI
fid
IRL[3:0]
System services Wake up interrupt Priority encoder
Comms
ILC
on
Internal LPC
External
(16 interrupt levels)
wake up
Comms Infrared
module
transmitter
/receiver
C
Data from pins

IRB_PPM_IN wake up
IRB_UHF_IN
Comms
irq
TVOut Transport
Off chip external Video

interrupt pins EXT(0, 1, 2)
PCM
Low power mode player
S/PDIF
player
FDMA Blitter
Pins INTERRUPT[3:0] can be connected to both the interrupt steering outputs or the four
external interrupt inputs.
Note: The four remote OFF chip interrupts are routed from the ILC to PIO3 pads, two of which are
routed are as DMAREQ, PIO3[0,1] and two are routed as external interrupts
EXT_INT_OUT, PIO3[0] and PIO3[4].
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STi5189 Interrupt system
17.2 Interrupt controller
17.2.1 Internal and external interrupts

The ST40-300 CPU has two types of interrupts:
External interrupts
● NMI: external interrupt source.
● IRLINT: four eternal interrupt sources IRL0 to IRL3, which can be configured as four
independent interrupts or encoded to provide 15 external interrupt levels.
These interrupts are managed by the INTC interrupt controller integrated into the ST40-300
CPU core.
The four external asynchronous interrupts are routed to the ILC3 interrupt controller before
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reaching the ST40 in order to synchronize and change the polarity, if needed.
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Internal peripheral interrupts
● On-chip peripherals interrupt sources.
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The INTC controls all the on-chip peripherals interrupts.
All interrupts (except NMI) are assigned a priority level between 0 and 15: level 15 is the
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highest and level 1 the lowest, level 0 means that the interrupt is masked. The NMI is
defined to have a fixed priority level of 16.
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INTC controls the following interrupt sources:

● NMI, IRL[3...0] from external inputs
● ST40-P130 peripheral interrupts:
on
– user debug interface (UDI)

– timer unit (TMU0, 1)
– real time clock (RTC)
The on-chip peripheral interrupts are routed to INTC through ILC and priority encoder, which
C
generates IRl[3:0] and NMI.
Interrupt service routine address

Whenever an interrupt occurs, the ST40 CPU branches to the interrupt handling vector
address determined by adding the fixed offset 0x600 to the vector base address (VBR)
register. Each interrupt type is assigned a code which is stored in the INTEVT (Interrupt
Event) register when the interrupt occurs. This enables the interrupt service routine to
identify the interrupt source type.
The interrupt controller is responsible for mapping each interrupt to its code (INTEVT).
The Table 55 lists the codes for INTEVT and the order of interrupt priority. Each interrupt
source is assigned a unique code. The start address of the interrupt handler is common to
each interrupt source. This is why, for instance, the value of INTEVT is used as offset at the
start of the interrupt handler and branched to identify the interrupt source.
The order of priority of the on-chip peripheral module is set in the priority levels 0 to 15 using
the interrupt priority level set in registers A, B, C and D (IPRA to IPRD). The order of priority
of the on-chip peripheral module is set to 0 by a reset.
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When the priorities for multiple interrupt sources are set to the same level and such
interrupts are generated at the same time, they are handled according to the default order
listed in Table 55.
Updating of interrupt priority level setting registers A, B, C and D should only be performed
whilst the BL bit in SR is set to 1. To prevent erroneous interrupt acknowledgment, first read
any of the interrupt priority level setting registers, then clear the BL bit to 0. This secures the
necessary timing internally.
Table 55. ST40 core interrupt exception vectors and rankings

Interrupt Priority
INTEVT IPR (bit Default
Interrupt source priority (initial within IPR
code numbers) priority
value) setting unit
NMI - 0x1C0 16 - - High
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IRL3 to IRL0 = F 0x200 15 - -
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IRL3 to IRL0 = E 0x220 14 - -
IRL3 to IRL0 = D 0x240 13 - -
IRL3 to IRL0 = C 0x260 12 - -
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IRL3 to IRL0 = B 0x280 11 - -
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IRL3 to IRL0 = A 0x2A0 10 - -

IRL3 to IRL0 = 9 0x2C0 9 - -
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IRL3 to IRL0 = 8 0x2E0 8 - -

IRL3 to IRL0 = 7 0x300 7 - -
IRL IRL3 to IRL0 = 6 0x320 6 - -
on
IRL3 to IRL0 = 5 0x340 5 - -

IRL3 to IRL0 = 4 0x360 4 - -
IRL3 to IRL0 = 3 0x380 3 - -
C
IRL3 to IRL0 = 2 0x3A0 2 - -

IRL3 to IRL0 = 1 0x3C0 1 - -
IRL0 0x240 15 to 0 (13) IPRD [15:12] -
IRL1 0x2A0 15 to 0 (10) IPRD [11:8] -
IRL2 0x300 15 to 0 (7) IPRD [7:4] -
IRL3 0x360 15 to 0 (4) IPRD [3:0] - Low
UDI Reserved 0x600 15 to 0 (0) IPRC[3:0] - -
(1)
EXP - - - - - -
TMU0 TUNI0 0x400 15 to 0 (0) IPRA[15:12] - -
TMU1 TUNI1 0x420 15 to 0 (0) IPRA[11:8] - -
TMU2 TUNI2 0x440 15 to 0 (0) IPRA[7:4] - -
238/294 Doc ID 8141465 Rev 5

Table 55. ST40 core interrupt exception vectors and rankings (continued)
Interrupt Priority
INTEVT IPR (bit Default
Interrupt source priority (initial within IPR
code numbers) priority
value) setting unit
0x460
0x480
0x4A0
0x4C0
Reserved(2) -
0x700
0x740
0x760
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0x780
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WDT ITI 0x560 15 to 0 (0) IPRB[15:12] - -
- Reserved 0x3E0 -
Other interrupts are device specific.
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1. Default priority position of external interrupts using the expander. The details of interrupts in this group are an integration
option.
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2. These INTEVT codes are used by CSP modules present in other ST40 series. These codes should be avoided when
allocating new codes for cascaded interrupt controllers to avoid potential software conflicts.
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The ST40-300 interrupt network is described in the following figure:
Figure 35. ST40 interrupt network

ST40-300
on
ST40-C230 IRQ
(CPU core)
C
ST40-P130 Interrupt status signals
WDT TMU UDI
INTC
NMI IRL[3:0] Interrupt expansion signals:

External
interrupt INTREQ_N
sources Priority INTLEVEL[3:0]
encoder INTEVENT[8:0]
EXT_INTSTB
ILC (comms)
On-chip
peripherals
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17.3 Interrupt handlers

The sequence of interrupt operations is as follows:
1. The interrupt request sources send interrupt request signals to the interrupt controller.
2. The interrupt controller selects the highest priority interrupt from the interrupt requests
sent, according to the priority levels set in interrupt priority registers A to C (IPRA to
IPRC) and the INTPRI registers. Lower priority interrupts are held pending. If two of
these interrupts have the same priority level or if multiple interrupts occur in a single
module, the interrupt with the highest default priority or the highest priority within its IPR
setting unit is selected.
3. The priority level of the interrupt selected by the interrupt controller is compared with
the interrupt mask bits (I3 to I0) in SR of the CPU. If the request priority level is higher
than the level in bits I3–I0, the interrupt controller accepts the interrupt and sends an
interrupt request signal to the CPU.
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4. The CPU receives an interrupt at a break in instructions.
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5. The interrupt source code is set in INTEVT.
6. SR and program counter (PC) are saved to SSR and SPC, respectively.
7. The block bit (BL), mode bit (MD) and register bank bit (RB) in SR are set to 1.
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8. The CPU jumps to the start address of the interrupt handler (the sum of the value set in
the vector base register (VBR) and 0x0000 0600). The interrupt handler may branch
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with the INTEVT register value as it is offset to identify the interrupt source. This
enables it to branch to the handling routine for the individual interrupt source.
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Note: 1 The interrupt mask bits[I3:I0) in SR are not changed by acceptance of an interrupt in the
CPU.
2 The interrupt source flag should be cleared in the interrupt handler. To ensure that an
interrupt request that should have been cleared is not inadvertently accepted again, read
on
the interrupt source flag after it has been cleared, before clearing the BL bit or executing an
RTE instruction.
17.3.1 Nested interrupts

C
To handle nested interrupts, an interrupt handler should include the following procedure:
1. Branch to a specific interrupt handler corresponding to a code set in INTEVT. The code
in INTEVT can be used as a branch-offset for branching to the specific handler.
2. Clear the cause of the interrupt in each specific handler.
3. Save SSR and SPC to memory.
4. Clear the BL bit in SR and set the accepted interrupt level in the interrupt mask bits in
SR.
5. Handle the interrupt.
6. Set the BL bit in SR to 1.
7. Return the SSR and SPC from memory.
8. Execute the RTE instruction.
When this procedure is followed in order, an interrupt of higher priority than the 1 being
handled can be accepted after clearing BL in step 4.
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17.4 Interrupt level controller

The interrupt level controller multiplexes 64 internal and 8 external interrupt source signals
on to the 16 interrupt level inputs of the interrupt controller. In this way, it gives
programmable control of the priority of the interrupt sources and extends the number of
possible interrupts. In addition, interrupt steering is provided to allow routing of a further four
interrupts off chip, any interrupt source may be mapped on to any of the four outputs.
The incoming interrupt signals can be generated by on-chip subsystems or received from
external pins. Table 56: STi5189 interrupt assignments assigns each of the interrupt
sources to a number n from 0 to 63. Software assigns a signal n to one of the 16 interrupt
levels by writing the priority of the required input in the ILC_PRIORITYn register. Each of the
44 interrupt sources in the interrupt level controller can be selectively enabled or disabled at
source, by writing to the ILC_ENABLEn register. This is in addition to the individual masking
of the 16 levels in the interrupt controller. This disables the interrupt source from generating
an interrupt, without disabling all other interrupt sources mapped on to that interrupt level.
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This would be the case if the INC_MASK register in the interrupt controller was used.
All internal interrupts are assumed to be level sensitive and active high.
Each external interrupt source can be used to trigger an interrupt and can be programmed
to trigger on rising or falling (or either) edges or on the high or low logic level of the incoming
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interrupt source signal. This is controlled by writing to the ILC_MODEn registers.
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The default state of the interrupt level controller trigger mode registers is no trigger,
therefore, these registers need to be programmed if external interrupts are to be enabled.
The default state of the enable registers is low, therefore these registers need to be
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programmed before internal interrupts can be serviced.

When setting trigger modes in the interrupt level controller, the corresponding trigger mode
for the interrupt level in the interrupt controller that the source(s) are mapped to, must be
programmed to high level. Otherwise, the trigger mode in the interrupt controller and the
on
interrupt level controller may conflict. The ILC_INPUT_INTERRUPTn register has the same
function as in the STi5500, STi5505, STi5508, STi5518 and can be used to indicate the
current logic state of all the interrupt sources. This register is just a buffered version of the
interrupt source signals before the trigger mode detection stage. ILC_INPUT_INTERRUPTn
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does not latch the signal, as the ILC_STATUSn register does, for interrupt sources defined
with an edge sensitive trigger mode. The ILC_STATUSn register is more useful because of
this feature, as it can be read by the interrupt handler software routine to determine which
interrupt sources have triggered.
For example, if the interrupt source is external and provides a pulse, the interrupt level
controller would have the interrupt source trigger mode set to be rising edge. On a rising
edge, the corresponding bit in the ILC_STATUSn register would be set high and would
remain set until explicitly cleared by the interrupt handler routine writing to the
corresponding bit in the ILC_CLEAR_STATUSn register. However if the pulse was short, by
the time the interrupt handler was executed and had read the ILC_INPUT_INTERRUPTn
register, the pulse may have returned to a logic low and the bit would be read as zero. Thus,
the cause of interrupt could not be determined if more than one interrupt source had been
multiplexed on to the interrupt level.
So now, using the ILC_STATUSn register, it is possible to multiplex interrupt sources of
different types, including edge sensitive, on to the same interrupt level in the interrupt
controller.
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The STi5189 interrupt level controller also has two registers mapped into its register
address space, which have no connection with normal interrupt operation. These registers
control the wake up of the CPU by an external interrupt pin, when it has been put into low
power mode, by the low power controller module. The register INC_SELNOTINV controls
whether the four external interrupt pins are active high or low, to wake up the CPU from low
power mode. The setting of this register has no effect on the triggering of the external
interrupt pins in the interrupt level controller. The register INC_EN_INT is a mask register to
enable or disable the external interrupt pins from waking up the CPU from low power mode.
Again, this has no effect on the masking of these interrupts in the interrupt level controller.
17.5 Interrupt assignments

All interrupts are active high. Interrupts from the internal peripherals and external pins are
assigned as shown in the following table:
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Table 56. STi5189 interrupt assignments
INT n Peripheral Description of the function
0 PIO0 Compare function

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5 SSC0 SSC0TIR, SSC0RIR and SSC0EIR I2C master
on
7 ASC0 ASC0TIR, ASC0TBIR, ASC0RIR and ASC0EIR

9 pcpl_interrupt PCPL
10 avi_interrupt AVI
C
11 irq_nandflash_interrupt NAND Flash

14 PTI Programmable transport interface
15 nds PDES
16 o_int_ram_overflow Transport
18 Reserved -
19 IRB IRB
20 CEC CEC
21 Reserved -
22 Video decoder Video decoder
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Table 56. STi5189 interrupt assignments (continued)

23 Audio decoder Audio decoder

24 ETH_INT Ethernet
25 ETHERNET_MDINT Management data interrupt from PHY
26 Audio S/PDIF Audio S/PDIF player
27 PCM interrupt Audio PCM player
28 USB_OHCI_INT USB
29 USB_EHCI_INT USB
30 Reserved Reserved
31 Reserved Reserved
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32 VTG 1 TVOut
33 VTG 2 TVOut
34 FDMA FDMA interrupts
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35 BLIT CQ1 Blitter
36 BLIT CQ2 Blitter
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37 BLIT AQ1 Blitter

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38 BLIT AQ2 Blitter

39 BLIT AQ3 Blitter
40 BLIT AQ4 Blitter
41 DCO_CORRECTION System services
on
42 CPU Tick Timer interrupt from system services

43 PWM timer interrupt Timer interrupt from CPU (PWM 4)
44 BLITGeneric interrupt req0 Blitter
C

48 to 63 Reserved
External inputs
64
ExtIntIn0
(EXT0)
From external devices
65(EXT1) ExtIntIn1
66(EXT2) ExtIntIn2
67(EXT3) Reserved -
68
IR wake up From pins through pulse stretcher
(EXT4)
69 to 70 Reserved -
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Table 56. STi5189 interrupt assignments (continued)

FDMA (from FDMA

71 EXT7 FDMA
gp_output)
External outputs
0(EXT0) ExtIntOUT0
To external devices dmareq_to_pads
1 (EXT1) ExtIntOUT1
2 to 5 Reserved -
6 (EXT6) FDMA REQ0 External DMA request to pad
7 (EXT7) FDMA REQ1 External DMA request to pad
Wake up Wake up Wake up system services
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0 to 15 C1 interrupts
en ILC_INTERRUPT_LOCAL_OUT
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on
C
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STi5189 Interrupt system registers
18 Interrupt system registers
Addresses are provided as either the IntControllerBaseAddress or the ILCBaseAddress +

offset.
The IntControllerBaseAddress is 0xFFD0 0000.
The ILCBaseAddress is 0xFD10 0000.
.
Table 57. Interrupt system registers

Interrupt controller registers(1)
0x0000 INTC_ICR Interrupt control page 246
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0x0004 INTC_IPRA Interrupt priority level A page 247
0x0008 INTC_IPRB Interrupt priority level B page 247
0x000C INTC_IPRC Interrupt priority level C page 247
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0x0010 INTC_IPRD Interrupt priority level D page 248
(2)
Interrupt level controller registers
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0x0080 - 0x008C ILC_INPUT_INTERRUPTn Input interrupt register page 248

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0x0200 - 0x020C ILC_STATUSn Status register page 249

0x0280 - 0x028C ILC_CLEAR_STATUSn Clear status locations page 249
0x0400 - 0x040C ILC_ENABLEn Enable registers page 250
on
0x0480 - 0x048C ILC_CLEAR_ENABLEn Clear enable locations page 250

0x0500 - 0x050C ILC_SET_ENABLEn Set enable locations page 251
0x608 ILC_WAKEUP_ENABLE Wake up enable registers page 251
0x688 ILC_WAKEUP_ACTIVE_LEVEL Wake up level registers page 252
C
0x0800 - 0x0878 ILC_PRIORITYn Priority register n (where n = 0 to 15) page 252

0x0A04 - 0x0A0C ILC_MODEn Mode registers 0 and 1 page 253
0xA14 ILC_MODE2 Mode register 2 page 254
1. Uses IntControllerBaseAddress as the base address.
2. Uses ILCBaseAddress as the base address.
Doc ID 8141465 Rev 5 245/294

Interrupt system registers STi5189
18.1 Interrupt control registers
INTC_ICR Interrupt control

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
RESERVED
NMIB
NMIE
NMIL
IRLM
MAI
Address: IntControllerBaseAddress + 0x0000

Type: R/W
Description: Interrupt control register. This register is a 16-bit register that sets the input signal
detection mode for external interrupt input pin NMI and indicates the input signal level
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at the NMI pin. This register is initialized by a power-on reset or manual reset. Initial
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value is 0x8000 when the NMI pin is high, 0x0000 when the NMI pin is low.
[15] NMIL: NMI interrupt level. Reports the level of the signal input at the NMI pin. This bit can be
read to determine the NMI pin level. It cannot be modified.
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0: NMI input level is low
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1: NMI input level is high

[14] MAI: NMI interrupt mask. Specifies whether or not all interrupts are to be masked while the NMI
pin input level is low, irrespective of the CPU’s SR.BL bit.
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0: Interrupts are enabled even while NMI pin is low

1: Interrupts are disabled while NMI pin is low (NMI interrupts are accepted in normal operation
and in sleep mode.)
[13:10] RESERVED:
on
[9] NMIB: NMI block mode. Selects whether NMI requests are held pending or immediately
detected when the SR.BL bit is 1. If an interrupt request is accepted while SR.BL = 1, the
previous exception information is lost, so should be saved beforehand. This bit is cleared
automatically when an NMI interrupt is accepted.
C
0: NMI interrupt requests are held pending when SR.BL = 1

1: NMI interrupt requests are detected when SR.BL = 1
[8] NMIE: NMI edge select. Selects whether the falling or rising edge of the interrupt request signal
to the NMI is detected.
0: An interrupt request is detected on the falling edge of NMI input
1: An interrupt request is detected on the rising edge of NMI input
[7] IRLM: IRL pin mode. Selects whether pins IRL3 to IRL0 are used for level-encoded interrupt
requests or for four independent interrupt requests
0: IRL pins are used for level-encoded interrupt requests
1: IRL pins are used for four independent interrupt requests
[6:0] RESERVED:
246/294 Doc ID 8141465 Rev 5

INTC_IPRA Interrupt priority level A

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMU0 TMU1 TMU2 RESERVED

Type: R/W
Description: Interrupt priority level A register. This register is initialized by a power-on reset or
manual reset. Initial value is 0x0000.
[15:12] TMU0:
[11:8] TMU1:
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[7:4] TMU2:
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[3:0] RESERVED:
INTC_IPRB Interrupt priority level B

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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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WDT RESERVED

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Type: R/W
Description: Interrupt priority level B register. This register is initialized by a power-on reset or
on
[15:12] WDT:
[11:0] RESERVED:
C
INTC_IPRC Interrupt priority level C

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED UDI
Address: IntControllerBaseAddress + 0x000C

Type: R/W
Description: Interrupt priority level C register. This register is initialized by a power-on reset or
[15:4] RESERVED:
[3:0] UDI:
Doc ID 8141465 Rev 5 247/294

INTC_IPRD Interrupt priority level D

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IRL0 IRL1 IRL2 IRL3

Type: R/W
Description: Interrupt priority level D register. This register is initialized by a power-on reset or
manual reset. Initial value is 0xDA74.
[15:12] IRL0:
[11:8] IRL1:
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[7:4] IRL2:
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[3:0] IRL3:
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18.2 Interrupt level controller registers
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ILC_INPUT_INTERRUPTn ILC input interrupt

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ILC_INPUT_INTER
RESERVED EXT[7:0]
RUPT0
ILC_INPUT_INTER
on
RESERVED
RUPT1
ILC_INPUT_INTER
RESERVED INT[43:32]
RUPT2
ILC_INPUT_INTER
INT[31:0]
RUPT3
C
Address: ILCBaseAddress + 0x080 + n * 0x04 (where n = 0 to 3)

Type: R
Reset: 0
Description: ILC input interrupt. The synchronized version of all the interrupt numbers can be read
from this register. There are two input interrupt registers from 0x080 to 0x084. The
contents of this register are set to logic 0 on reset.
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ILC_STATUSn ILC status registers

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ILC_STATUS0 RESERVED EXT[7:0]
ILC_STATUS1 RESERVED
ILC_STATUS2 RESERVED INT[43:32]
ILC_STATUS3 INT[31:0]

Type: R
Reset: 0
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Description: ILC status registers
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The status of the interrupt numbers is inferred by reading this register. The bit in the
status register is at logic 1 on the following conditions:
– If the corresponding interrupt number is internal (synchronous), then the
interrupt number should be at logic 1.
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– If the corresponding interrupt number is external (asynchronous), then the
interrupt number should match the programmed trigger condition.
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There are two status registers from 0x200 to 0x27C. The contents of this register are
at logic 0 on reset.
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ILC_CLEAR_STATUSn Clear status locations

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
on
ILC_CLEAR_STA
RESERVED EXT[7:0]
TUS0
ILC_CLEAR_STA
RESERVED
TUS1
ILC_CLEAR_STA
RESERVED INT[43:32]
C
TUS2
ILC_CLEAR_STA
INT[31:0]
TUS3

Type: W
Reset: Undefined
Description: Clear status locations. This location is used to clear bits in the status register. The
locations that correspond to external interrupts are valid. The status is cleared only if
the interrupt trigger mode is edge sensitive, that is, the rising edge, falling edge or any
edge. To clear the status bit, a clear bit operation is to be performed on this location.
Clear bit operation is performing a write operation with logic 1 on data bus
corresponding to the locations which have to be cleared.
There are two clear status locations at 0x280 and 0x284.
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ILC_ENABLEn Enable registers

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ILC_ENABLE0 RESERVED EXT[7:0]
ILC_ENABLE1 RESERVED
ILC_ENABLE2 RESERVED INT[43:32]
ILC_ENABLE3 INT[31:0]

Type: RW
Reset: 0
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Description: Enable registers. Interrupt generation from an interrupt number is enabled only if the
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corresponding bit in the enable register is set to logic 1. The contents of this register
are at logic 0 on reset.
There are two enable registers at 0x400 and 0x404.
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ILC_CLEAR_ENABLEn Clear enable locations
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ILC_CLEAR_E
RESERVED EXT[7:0]
NABLE0
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ILC_CLEAR_E
RESERVED
NABLE1
ILC_CLEAR_E
RESERVED INT[43:32]
NABLE2
ILC_CLEAR_E
on
INT[31:0]
NABLE3

Type: W
C
Reset: Undefined
Description: Clear enable locations. Any bit in the enable register can be cleared by performing a
clear bit operation on the appropriate location.
There are two locations at 0x480 and 0x484 corresponding to respective enable
registers.
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ILC_SET_ENABLEn Set enable locations

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ILC_SET_ENABL
RESERVED EXT[7:0]
E0
ILC_SET_ENABL
RESERVED
E1
ILC_SET_ENABL
RESERVED INT[43:32]
E2
ILC_SET_ENABL
INT[31:0]
E3

Type: W
Reset: Undefined
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Description: Set enable locations. Any bit in the enable register can be set by performing a set bit
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operation on the appropriate location (set bit operation is performing a write operation
with logic 1 on the data bus corresponding to the location which has to be set).
There are two locations at 0x500 and 0x504 corresponding to respective enable
registers.
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ILC_WAKEUP_ENABLE Wake up enable
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
fid
RESERVED EXT[7:0] RESERVED
Address: ILCBaseAddress + 0x608

Type: R
on
Reset: 0
Description: This register is used to enable the external interrupt (asynchronous) for wake up by
interrupt generation. Only the locations corresponding to external interrupts are valid.
C
The external interrupt enables the wake up by interrupt generation only if the
corresponding bit in this register is set to logic 1. The contents of this register are set
to logic 0 on reset.
The location at 0x604 corresponds to respective interrupt numbers.
Note: Interrupts EXT4 to EXT7 are not valid outputs, see Table 56: STi5189 interrupt
assignments for a list of interrupt numbers.
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ILC_WAKEUP_ACTIVE_LEVEL Wake up level

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED EXT[7:0] RESERVED
Address: ILCBaseAddress + 0x688

Type: R
Reset: 1
Description: This register is used to program the polarity of the external interrupt line on which a
wake up by interrupt is to be generated. If a bit in this register is set to 1 then a wake
up by interrupt is generated, only if the corresponding external interrupt is at logic 1.
Writing logic 0 generates the wake up by interrupt when corresponding external
interrupt pin is at logic 0. The contents of this register are set to logic 1 on reset.
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The location at 0x688 corresponds to respective interrupt numbers.
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Note: Interrupts EXT4 to EXT7 are not valid outputs, see Table 56: STi5189 interrupt
assignments for a list of interrupt numbers.
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ILC_PRIORITYn ILC priority
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED PRIORITY_LEVELS_0_TO_15
fid

Type: RW
on
Reset: 0
Description: The priority register assigns the interrupt number to one of the available interrupt
levels. The assignment is done by writing appropriate word into the priority register.
Bits[14:4] must be set to 0 all the time.
C
To map an interrupt number on the interrupt level of a local processor (ST40 core), a
value between 0x0000 to 0x7FFF needs to be written. For example, the ST40 core
has 16 interrupt levels, values between 0x0000 to 0x000F are valid. Other values
from 0x0010 to 0x7FFF are invalid.
To map an interrupt number on the interrupt level of an external processor, a value
between 0x8000 to 0xFFFF has to be written. ILC can only map on to four interrupt
levels of an external processor, therefore, the values between 0x8000 to 0x8003 are
valid. Other values from 0x8004 to 0xFFFF are invalid.
For example,
If bit[15] is set to 1, bits 0 and 1 are used to determine which of the four external
interrupts is to be set.
If bit[15] is set to 0, bits 0 to 3 are used to determine which of the 16 interrupt levels
are to be set.
The register is set to 0x0000 on reset. The address of the priority register
corresponding to interrupt number n is at 0x800 + (n x 0x008).
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ILC_MODEn Mode registers

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED MODE[2:0]
RESERVED MODE[2:0]
Address: ILCBaseAddress + 0xA04 + n * 0x08 (where n = 0 to 1)

Type: RW
Reset: 0
Description: The mode register is used to program the trigger mode for a given interrupt number.
This is a 3-bit register. The mode register is present only for external interrupts. No
mode register is present for internal interrupts. All the internal interrupt numbers are
assumed active high.
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– The trigger modes can be programmed to appropriate trigger levels by writing
the values as shown in the following table. Use the syntax 0xnnnn nnnn for the
address.
– Include the values outside the address range.
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ILC_MODE0: [31:3]
RESERVED
ILC_MODE1: [31:3]
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ILC_MODE0: [2:0] MODE[2:0]:

ILC_MODE1: [2:0] 000: No trigger mode 001: High-level trigger mode
010: Low level trigger mode 011: Rising edge trigger mode
100: Falling edge trigger mode 101: Any edge trigger mode
on
110: No trigger mode 111: No trigger mode
The mode register is set to 0x00 on reset.

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ILC_MODE2 Mode registers

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED MODE[2:0]
Address: ILCBaseAddress + 0x0A14

Type: RW
Reset: 0
Description: The mode register is used to program the trigger mode for a given interrupt number.
This is a 3-bit register. The mode register is present only for external interrupts. No
mode register is present for internal interrupts. All the internal interrupt numbers are
assumed active high.
– The trigger modes can be programmed to appropriate trigger levels by writing
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the values as shown in the following table. Use the syntax 0xnnnn nnnn for the
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address.
– Include the values outside the address range.
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[31:3] RESERVED
[2:0] MODE[2:0]
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000: No trigger mode 001: High-level trigger mode

010: Low level trigger mode 011: Rising edge trigger mode
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100: Falling edge trigger mode 101: Any edge trigger mode
110: No trigger mode 111: No trigger mode
The mode register is set to 0x00 on reset.

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STi5189 Memory system
19 Memory system
The STi5189 has a fully unified memory system based on 16-bit SDRAM main memory.
19.1 Memory map

The internal peripherals addresses are located in ST40-300 P4 region. Grouping is done so
that peripherals that belong to the same physical block have contiguous addresses,
requiring only one address decoder in each physical block.
The base address of the external interfaces and internal peripherals are given in the
following table:
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Table 58. Internal peripheral base addresses
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Target name Start offset End offset Size
FMI 0000_0000 07FF_FFFF 128 MB

TileRAM 0800_0000 087F_FFFF 8 MB
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LMI (29-bit) 0C00_0000 1BFF_FFFF 256 MB
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LMI (32-bit) 4000_0000 7FFF_FFFF 1024 MB

ST40 core debug(1) FC00_0000 FCFF_FFFF 16 MB
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NHS1 prg cfg FD00_0000 FD00_0FFF 4 KB

Reserved FD00_1000 FD00_1FFF 4 KB
HS config_monitor FD00_2000 FD00_2FFF 4 KB
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Comms FD10_0000 FD1F_FFFF 1 MB

TS Merger FD30_0000 FD3F_FFFF 1 MB
S/PDIF cfg FD40_0000 FD47_FFFF 512 KB
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PCM player cfg FD48_0000 FD4F_FFFF 512 KB

NHD2 prg cfg FD50_0000 FD50_0FFF 4 KB
Video cfg FD60_0000 FD6F_FFFF 1 MB
TVout (GDMA) cfg FD70_0000 FD7F_FFFF 1 MB
Blitter cfg FD80_0000 FD8F_FFFF 1 MB
NHD3 prg cfg FD90_0000 FD90_0FFF 4 KB
HD config_monitor FD90_1000 FD90_1FFF 4 KB
PTI cfg FDA0_0000 FDA7_FFFF 512 KB
PCPL cfg FDA8_0000 FDAB_FFFF 256 KB
AVI cfg FDAC_0000 FDAF_FFFF 256 KB
FDMA cfg FDB0_0000 FDBF_FFFF 1 MB
System serv cfg FDC0_0000 FDCF_FFFF 1 MB
USB cfg FDD0_0000 FDDF_FFFF 1 MB
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Memory system STi5189
Table 58. Internal peripheral base addresses (continued)

Target name Start offset End offset Size
Ethernet cfg FDE0_0000 FDE0_FFFF 64 KB

TSmerger cfg FDE2_0000 FDE2_FFFF 64 KB
FMISS router FDE3_0000 FDE3_FFFF 64 KB
CEC config FDE4_0000 FDE4_FFFF 64 KB
System EM1 config(2) FDF0_0000 FDFF_FFFF 1 MB
LMI config address(3) FE00_0000 FE00_0FFF 4 KB
(1)
ST40 core peripherals FF00_0000 FFFF_FFFF 16 MB
1. ST40 target interface.
2. To be decoded on FMI port.
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3. To be decoded on LMI ports.
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Note: Address ranges which are not assigned to any IP are reserved and any access to these
addresses get R_OPC[0] = 1.
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STi5189 Memory system
19.2 ST40-300 CPU memory management
19.2.1 External memories and on-chip peripherals address map

The STi5189 memory space is populated with non-volatile memories, with external
peripherals (FMI) at base address 0 (ST40 boots at address 0) and with DDR-SDRAM
devices (LMI) at base address 0x0C00 0000 (128 Mbytes) in 29-bit mode or at base
address 0x4000 0000 (1024 Mbytes) in 32-bit mode.
When using either 29-bit mode or 32-bit mode, the maximum memory size of external
DDR-SDRAM is limited to:
● 128 Mbytes, configured as two 64 MB x 8 (512 Mbit) devices, or
● 64 Mbytes, configured as one 32 MB x 16 (512 Mbit) device
The STi5189 on-chip peripherals are mapped in area 6 of the ST40 in 29-bit mode. The
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STi5189 memory and peripheral mapping is shown in the following figure:
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Figure 36. STi5189 memory and peripheral mapping
0x0000 0000
FMI 128 MB
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0x0800 0000
Tile SRAM Bank 0
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0x0880 0000
RESERVED
RESERVED ST40 29-bit

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0x0C00 0000 addressing mode Bank 1
LMI (29-bit) 256 MB
Bank 2
on
RESERVED
RESERVED
0x4000 0000
Bank 3
LMI 1024 MB
(32 bit)
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0x8000 0000
RESERVED
0xFC00 0000 DDR 128 MB
ST40 core debug 16 MB (max)
0xFD00 0000
On chip ST40 32-bit addressing mode
peripherals 32 MB
0xFF00 0000
ST40 core 16 MB
peripherals
0xFFFF FFFF
Note: The path to the LMI in the STBus nodes has to consider the two LMI address ranges (29-
and 32-bit)
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Electrical specifications STi5189
20 Electrical specifications
20.1 Absolute maximum ratings

Table 59. Absolute maximum ratings
Symbol Parameter Min Max Units
VDD3V3 3.3 V I/O supply voltage -0.5 5.45 V

VDDCore Core power supply -0.5 1.78 V
VDDE2V5 Core 2.5 V power supply -0.5 4.44 V
Pads 3.3 V power supply -0.5 5.45 V
VDDE3V3
For 8 volts -0.5 8.8 V
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LMI supply voltage for 2.5 V DDR -0.5 4.44 V
VDD33_25
LMI supply voltage for 3.3 V SDR -0.5 5.45 V
VDD1V0 1.0 V supply for core and analog -0.5 1.78 V
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VDD1V0_FE Common supply for AD12, FEOSC and FEPLL -0.5 1.78 V
VDDA2V5_BE Common supply for FS and PLL -0.5 4.44 V
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VCCA2V5_DACS Common supply for audio and video DACs -0.5 4.44 V
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VCCA2V5_FE 2.5 V analog supply of the front end -0.5 4.44 V

ADAC_VCCAH Audio DAC output buffer power supply -0.5 8.8 V
VO3MAX DC voltage on 3.3 V tolerant pins GND - 0.5(1) VDD33 + 0.5(1) V
IOMAX DC output current - 20 mA
on
TSMAX Storage temperature (ambient) -40 125 °C

TAMAX Temperature under bias (ambient) -40 125 °C
VESD_HBM Electrostatic discharge voltage - JESD22-A114(2) - Class 1C -
C
(2)
VESD_RCDM Electrostatic discharge voltage - JESD22-C101 - Class I -
1. AC transient overshoot of 0.7 V above VDD33 + 0.5 V is allowed for a maximum period of 2 ns.
2. For a definition of the ESD classes, see the relevant JEDEC standards or contact STMicroelectronics customer support.
Note: 1 These AMR values are applicable to all pins powered to the given voltage.
2 These are the maximum limits. Exceeding them may result in permanent damage to the
device. Operation at these limits is not intended.
3 Stresses greater than those listed in Table 59 may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other
conditions outside those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
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STi5189 Electrical specifications
20.2 Operating conditions
Table 60. Operating conditions

Symbol Parameter Min Typ Max Units Note
VDD33 3.3 V I/O supply voltage 3.0 3.3 3.6 V -

LMI supply voltage for 2.5 V DDR 2.5 2.6 2.7 V 7
VDD33_25
LMI supply voltage for 3.3 V SDR 3.0 3.3 3.6 V -
VDD1V0 1.0 V supply for core and analog 1.0 1.05 1.15 V -
VDD1V0_FE Common supply for AD12, FEOSC and FEPLL 1.0 1.05 1.15 V -
VDDA2V5_BE Common supply for FS and PLL 2.3 2.5 2.7 V -
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VCCA2V5_DACS Common supply for audio and video DACs 2.3 2.5 2.7 V -
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VCCA2V5_FE 2V5 analog supply of the front end. 2.3 2.5 2.7 V -
ADAC_VCCAH Audio DAC Output buffer power supply 7.2 8.0 8.8 V -
I3V3 3.3V I/O supply current - 0.040 0.050 A 1, 2, 3
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I33_25 LMI supply current at 2.6V - 0.035 0.040 A 1, 2, 3
Combined 1V0 supply current:
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I1V0 - 0.35 0.57 A 1, 2, 3

(VDD1V0 + VDD1V0_FE)
Combined 2.5V supply current:
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I2V5 - 0.170 0.180 A 1, 2, 3

(VDDA2V5_BE + VCCA2V5_DACS + VCCA2V5_FE)
I8V0 Audio DAC output buffer supply current. - 0.005 0.005 A 1, 2, 3
PD Full power dissipation - 1.060 1.460 W 1, 2, 3, 7
on
PDLP Power dissipation in low power mode4 - 90 154 mW 1, 4, 5, 6

CL Load capacitance per pin - - 100 pF -
TA Operating temperature (ambient) 0 - 70 °C -
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TJunction Operating junction temperature 0 - 125 °C -

Thermal resistance junction - ambient (for
- 35 - ° C/W -
15 mm x 15 mm package)
RthJA(1)
Thermal resistance junction - ambient (for
- 25 - ° C/W -
23 mm x 23 mm package)
1. The reported RthJA value should be considered as an approximate indication as the thermal performance of an electronic
package varies depending on board design, size, thickness, materials, etc.
Note: 1 The power consumption depends on chip activity and silicon temperature. Silicon
temperature depends on the PCB layout. The values in this table are measured in the ST
application environment and may vary from one application to another.
2 Typical values correspond to the power consumption for standard devices at typical voltage
conditions at an ambient temperature of 70 ° C.
3 Maximum current values correspond to the maximum power consumption for corner devices
with maximum power supplies at an ambient temperature of 70 ° C.
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4 All IP’s powered down with the exception of the ST40, timers and interrupt handler running
at a reduced clock speed, the DDR in self-refresh mode and with the LMI pad supply
VDD33_25 powered down.
5 Typical value corresponds to the power consumption of standard devices at typical voltage
conditions at an ambient temperature of 25 ° C.
6 Maximum value corresponds to the power consumption for corner devices at maximum
voltage conditions at an ambient temperature of 25 ° C.
7 DDR is running at 200 MHz.
20.3 System: oscillator

Refer to Table 61 for the recommended oscillator circuitry.
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Table 61. Oscillator specifications (for a 30 MHz oscillator frequency)
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Symbol Parameter Min Typical Max Units
CL1 Parallel capacitance1 value - (1) - pF
CL2 Parallel capacitance2 value - (1) - pF

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CSTRAY Parasitic capacitance at crystal pins - 10 - pF
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Rs Series resistance value - 600 - Ohms
Tol Tolerance - - +/- 30 ppm

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FSTAB Frequency stability - - +/- 30 ppm
VIN Amplitude of IN signal 0.9 1.28 1.4 Vpp

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VOSC Amplitude of OSC signal 0.9 1.28 1.4 Vpp
1. CLOAD value depends on the crystal specifications

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20.4 Standard digital 3.3V pad DC specifications

The standard pad specification is for the following interfaces:
● System
● JTAG (debug) port
● Transport/Ethernet
● FMI
● SPDIF
● CEC
● SPI
● USB ULPI
● PIOs (and corresponding alternate functions)
● QPSK
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Table 62. Standard digital 3.3 V pad DC specifications
Symbol Parameter Min Typical Max Units Note
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VIH Logic 1 (high-level) input voltage 2.0 - VDD33 + 0.5 V -
VIL Logic 0 (low-level) input voltage -0.5 - 0.8 V -
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IIN Input current (input pin) - - ±5 μA 1

IOZ Off state digital output current - - ±50 μA -
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IWPU Input weak pull-up current - - 110 μA -

IWPD Input weak pull-down current - - 110 μA -
VOH Logic 1 (high-level) output voltage 2.4 - - V 2
on
VOL Logic 0 (low-level) output voltage - - 0.4 V 2

CIN Input capacitance (input pins) - - 10 pF -
Input capacitance (bi-directional
CIO - - 15 pF -
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pins)
COUT Output capacitance - - 15 pF -
VHYS Schmitt trigger hysteresis voltage 0.495 - 0.62 V 3
Note: 1 0 ≤VI ≤VDD3V3

2 ILoad = 4 mA for all outputs (sink/source).
3 For all pads which are TTL compatible except for I2C pads which have hysteresis in the
range from 0.310 to 0.380 V.
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20.5 LMI pads DC/AC specifications for DDR-based systems

The LMI pads are compliant with the SSTL class 2 specifications.
Table 63. LMI pads DC/AC specifications for DDR-based systems

Symbol Parameter Min Typ Max Units Notes
Positive core power supply

VDD1V0 1.0 1.05 1.15 V -
voltage
2.6 V for
Positive I/O supply voltage,
VDD33_25 2.5 2.6 2.7 V 200 MHz
that is, VDD33_25
DDR
VREF Reference voltage 0.49 x VDD33_25 - 0.51 x VDD33_25 V -
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VIH(DC) DC input logic high (VIN) VREF + 0.15 - VDD33_25 + 0.3 V -
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VIL(DC) DC input logic low (VIN) -0.3 - VREF - 0.15 V -
VIH(AC) AC input logic high (VIN) VREF + 0.31 - VDD33_25 + 0.3 V -
VIL(AC) AC input logic low (VIN) Vss - 0.3 - VREF - 0.31 V -
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VOH Output logic 1 voltage VREF + 0.76 - V -
VOL Output logic 0voltage - - VREF - 0.76 V -
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COUT Output capacitance 2 - 12 pF -

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Logic 1 switching current at

IOH -16.2 - - mA -
VOH = 1.95 V
Logic 0 switching current at
IOL 16.2 - - mA -
VOL = 0.35 V
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(1)
Output rise slew rate 1.0 - 4 V/ns
SRR
0.5 - 4 - -
1.0 - 4 V/ns (2)
SRF Output fall slew rate
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0.5 - 4 - -
Freq Operational frequency - - 200 MHz -
1. Vout from VREF - 0.76 V to Vref + 0.76 V
2. Vout from VREF + 0.76 V to Vref - 0.76 V
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20.6 LMI pads DC/AC specifications for SDR-based systems

The LMI pads are compliant to the LVTTL specifications.
Table 64. LMI pads DC/AC specifications for SDR-based systems

Symbol Parameter Condition Min Typ Max Units
Positive I/O supply voltage,

VDD33_25 that is, VDD33_25 = 3.3 V for - 3.0 3.3 3.6 V
SDR
VIL DC input logic low - -0.3 - 0.8
VDD33_25 +
VIH DC input logic high - 2 - V
0.3
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VDD33_25 = 3.135V
2 - -
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Iout = -12mA
VDD33_25 = 3.135V
VOH Output logic 1 voltage 2.4 - - V
Iout = -12mA
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VDD33_25 = 3.135V
2.8 - -
Iout = -100uA
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VDD33_25 = 3.135V
- - 0.45
Iout = -12mA
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VDD33_25 = 3.135V
VOL Output logic 0 voltage - - 0.4 V
Iout = -12mA
VDD33_25 = 3.135V
- - 0.2
Iout = -100uA
on
Cout Output capacitance - 0 - 35 pF

Operational frequency - - - 200 MHz
Output rise slew rate Between 0.8 and 2 V 1 - - V/ns
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Frequency Output fall slew rate Between 0.8 and 2 V 1 - - V/ns

Output rise time Between 0.8 and 2 V - - 1.2 ns
Output fall time Between 0.8 and 2 V - - 1.2 ns
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20.7 Audio DAC specifications

Table 65. Audio DAC operating conditions
Symbol Parameter Min Typ Max Units Notes
VDD1V0 Digital supply voltage 1.0 1.05 1.15 V -

VCCA2V5_DACS Analog power supply 2.3 2.5 2.7 V -
ADAC_VCCAH Output buffer power supply 7.5 8.0 8.5 V -
20.7.1 Audio DAC parameters
Table 66. Audio DAC parameters
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Parameter Typical Unit
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SNR 90 at Fs = 44.1 kHz, 48 kHz, 96 kHz @ 2 Vrms dB
Dynamic range(1) -90 at Fs = 44.1 kHz, 48 kHz, 96 kHz @ 2 Vrms dB
66 at Fs = 44.1 kHz, 48 kHz, 96 kHz @ 2 Vrms
THD + Noise(2) dB
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72 at Fs = 44.1 kHz, 48 kHz, 96 kHz @ 1.4 Vrms
Noise floor -80 to 100 (20 Hz to 50 Hz) @ 2 Vrms dB
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-80 at 1kHz @ 2 Vrms

Interchannel isolation dB
-82 at 1kHz @ 1.4 Vrms
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Interchannel gain mismatch +/- 0.5 @ 2 Vrms dB

1. The specified value is obtained by adding 60 dB to the measured THD+N at full scale -60dB, with A-Weighting filter.
2. The values are obtained by adding 3 dB to the measure at full scale -3 dB, with A-Weighting filter.
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20.8 Video DAC parameters

Table 67. Operating conditions Mono and Triple DACs
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Symbol Parameter Min Typ Max Units
Output 3 dB bandwidth @
BDW DC to 30 - - MHz
Fclk = 160 MHz
F_clk Clock speed - - 160 MHz
VCCA2V5_DACS Analog supply 2.3 2.5 2.7 V
VDD1V0 Digital supply 1.0 1.05 1.15 V
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20.8.1 Mono video DAC performance

Table 68. Static electrical performance (Rref = 2.05 kohm, Rload = 37.5 ohm)
Nb DAC resolution - 10 - bits

INL Integral non-linearity - - +/- 1.0 LSB
DNL Differential non-linearity - - +/- 0.5 LSB
DAC to DAC matching DAC to DAC matching (1) - - +/- 3 %
Output compliance Delta I/Iout
Compliance - - 6.5 µA
0 V < Vout < 1.4 V
Iout 0 37.4
DAC output current - mA
Rref = 2.05 kOhms (code min) (code max)
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Full scale gain error Full scale gain error (5) - - +/- 7 %
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Rout DAC output resistance @ DC 100 - - kOhms
Note: 1 Under ideal power supply conditions.

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2 This value includes 1% variation of reference resistor (Rref) and 1% variation of load resistor
(Rload).
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Table 69. Dynamic electrical performance

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Symbol Parameter Min. Typ. Max. Unit
Total harmonic distortion

THD -47 -50 - dB
Fin = 4 MHz, F_clk = 160 MHz
on
Spurious free dynamic range

SFDR Fin = 4 MHz, F_clk = 160 MHz 49 52 - dB
Output full scale
Power supply rejection ratio @ 1 Hz (full
-48 -60 - dB
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PSRR scale)
(dVout/dVvcca) Power supply rejection ratio @ 1 MHz
-26 -29 - dB
(full scale)
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20.8.2 Triple video DAC performance
Table 70. Static electrical performance Rref = 7.73 kohm, Rload = 140 ohm
Nb DAC resolution - 10 - bits

INL Integral non-linearity - - +/- 1.0 LSB
DNL Differential non-linearity - - +/- 0.5 LSB
DAC to DAC
DAC to DAC matching (1) - - +/- 3 %
matching
Output compliance Delta I
Compliance - - 1 µA
0 V < Vout < 1.4 V
Iout
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DAC output current 0 (code min) - 10.0 (code max) mA
Rref = 7.73 kOhms
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Full scale gain error Full scale gain error (2) - - +/- 7 %
Rout DAC output resistance @ dc 100 - - kOhms
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Note: 1 Under ideal supply conditions.
2 This value includes the 1% variation of reference resistor (Rref) and 1% of load.
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Table 71. Dynamic electrical performance


-45 -46 - dB
on
Fin = 4 MHz, F_clk = 160 MHz

THD
-45 -46 - dB
Fin = 6.5 MHz, F_clk = 27 MHz
Spurious free dynamic range
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SFDR Fin = 4 MHz, Fclk = 160 MHz 47 48 - dBc

Output full scale
Power supply rejection ratio @ 1 Hz (full
-30 -60 - dB
PSRR scale)
(dVout/dVvcca) Power Supply rejection ratio @1 MHz
-22 -25 - dB
(full scale)
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20.9 Front-end interface: ADC

Table 72. Front-end ADCs DC specifications
Symbol Parameter Min Typ Max Unit
Power consumption in active mode on

P2V5 0 80 123 mW
analog supply
Poff Power consumption in inactive mode - - 8 µW
INL Integral non linearity - - +/- 1.0 LSB
DNL Differential non linearity - - +/- 0.5 LSB
GE Gain error - - 5% FSR -
GM I/Q gain mismatch - - 4.5% -
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Table 73. Front-end ADCs AC specifications
Symbol Parameter Min Typ Max Unit
FCLK Clock frequency - - 200 MHz

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Fin = 60 MHz; Fs = 100 MHz; 2Vpp 7.5 - - eff. bit
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Fin = 60 MHz; Fs = 200 MHz; 2Vpp 7.0 - - eff. bit

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Timing specification STi5189
21 Timing specification
This chapter contains I/O specifications for the following interfaces:

● System (reset, XTAL_IO, low power mode) on page 268
● 16-bit LMI (SDRAM/DDR interface) on page 270
● 16-bit FMI (flash and peripherals) on page 270
● SPI Interface on page 283
● Transport (PTI) on page 272
● TAP on page 274
● PIO port, including digital I/O on page 276
●
Digital I/O
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– DMA requests on page 276
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– asynchronous serial controller on page 276
– synchronous serial controller on page 277
– infrared receiver/transmitter on page 278
● Video outputs on page 278
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● Audio outputs on page 274
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● USB ULPI on page 280

● Ethernet on page 281
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Load capacitance on the tester differs according to the way measurements are taken. In
standard mode, it is evaluated to approximately 50 pF whereas for high speed
measurements with 50 Ω termination the figure is around 15 pF.
The default drive strength setting used for all characterization and simulation work is 25 pF.
on
21.1 System
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21.1.1 System AC specification
Table 74. System input/output port timings

Power supply stabilization to NOT_RESET signal

tRESET 1 - ms
deassertion
tMODSRST Inputs setup to NOT_RESET 5 - ns
tMODHRST Inputs hold from NOT_RESET 1.2 - ms
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STi5189 Timing specification
Figure 37. Reset timing

tRESET
Power supplies
NOT_RESET
MODE inputs
tMODSRST
tMODHRST
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21.1.2 Reset timing
The tRSTHRSTL value in the following figure and table is for power-on reset when the device
is cold:
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Figure 38. Reset timings
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NOT_RESET
tRSTLRSTH
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Table 75. Reset timings

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Symbol Parameter Min Nom Max Units
tRSTLRSTH NOT_RESET pulse width low(1) 10 - - ms

1. This is to allow for crystal oscillator start-up times which can be long.
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21.1.3 Watchdog reset out

NOT_WD_RESET is found on ball RESETEXTOUT.
Figure 39. NOT_WD_RESET timing
NOT_WD_RESET
tWDRSTLRSTH
Table 76. NOT_WD_RESET

NOT_WD_RESET pulse width not_rst + not_rst + not_rst +

tWDRSTLRSTH ms
low (COLD RST) 199 200 201
NOT_WD_RESET pulse width
tWDRSTLRSTH 199 200 201 ms
low (WARM RST)
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21.1.4 System clock

External 30 MHz clock
Either a 30 MHz clock can be fed into XTAL_IO or a crystal pi network may be connected
between XTAL_I and XTAL_O. The recommended method is to use a crystal and internal
VCO.
Crystal requirements
The external 30 MHz crystal has the following requirements:
● 30.000 MHz fundamental frequency
● parallel resonance
● 40 ppm accuracy
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21.2 LMI interface specification
The LMI is compliant with the DDR1 JEDEC specification for operation up to 200 MHz.
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21.3 Flexible memory interface (FMI)
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All the outputs come from a multiplexer controlled by the clock. It is assumed that the FMI
will be programmed so that all the outputs will be changed on the falling edge of the clock.
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The following tables assume an external load of 25 pF on every FMI pads.
21.3.1 Synchronous devices

on
All synchronous transactions originate and terminate at flip flops within the padlogics.
Outputs are generated with respect to the falling edge of the bus clock and inputs are
sampled with respect to the rising edge of the bus clock.
FMI-clock: FMIFLASHCLK
C
FMI-outputs: FMIADDR[*], FMIDATA[*], NOT_FMICS*, NOT_FMIBE[*], NOT_FMIOE,

NOT_FMILBA, NOT_FMIBAA, FMIRDNOTWR, CSn[*],
FMI-inputs: FMIDATA[*], FMIWAIT, NAND_WAIT, RBn[*]
270/294 Doc ID 8141465 Rev 5

Figure 40. FMI interface timings for synchronous transactions
tFMI-clock
FMI-clock
tECHEOV
FMI-outputs
tEIVECH
tECHEIX
l
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FMI-inputs
tECHEOZ
en
FMI tri-state
outputs
Confidential
tECHEON
fid
Table 77. FMI synchronous interface parameters

on
Input clock FMIFLASHCLK period 10 30 ns

tECHEOV Bus clock falling edge to valid data 0 4 ns
tEIVECH Input valid to rising clock edge (input setup time) 5.5 - ns
C
tECHEIX Rising clock edge to input invalid (input hold time) 0 - ns

tECHEON Falling clock edge to data valid (after tri-state output) 2 - ns
tECHEOZ Falling clock edge to data valid (before tri-state output) - -3 ns
These values are static offsets within a bus cycle, they should be read in conjunction with
the waveforms in flexible memory interface (FMI), which are cycle accurate only.
Doc ID 8141465 Rev 5 271/294

21.4 Transport stream timings

Each live input can support 27 Mbit/s in the parallel mode and 100 Mbit/s in the serial mode.
A stream coming in on TS0INDATA at 27 Mbyte/s will be retimed to the system clock
frequency of 108 MHz.
In the serial mode, the data arrives in on TS0INDATA[0].
Table 78. Maximum bit clock frequencies supported by TSIS

Transport steam format Max bit clock frequency Period
Parallel 27 Mbit/s 37 ns
Serial 100 Mbit/s 10 ns
Figure 41. Parallel transport stream input timings (27 Mbyte/s input rate)
l
tia
tLCLLCL
TS0INBITORBYTECLK
en
tLCLLCL tLCHLCH
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fid
TS0INBITORBYTECLKVALID
TS0INDATA[7:0]
TS0INPACKETCLK
on
tLDVLCH
tLCHLDX
C
Table 79. TSIN timings: parallel input mode

tLCLLCL TS0INBITORBYTECLK period 10 37 - ns

tLCHLCH TS0INBITORBYTECLK pulse width high 10 - - ns
tLCLLCL TS0INBITORBYTECLK pulse width low 10 - - ns
TS0IN signals valid to
tLDVLCH 3 - - ns
TS0INBITORBYTECLK high
TS0IN signals hold after
tLCHLDX 0 - - ns
TS0INBITORBYTECLK high
272/294 Doc ID 8141465 Rev 5

Figure 42. Serial transport stream input timings (100 Mbit/s input data rate)
tLCLLCL
TS0INBITORBYTECLK
tLCLLCL tLCHLCH
TS0INBITORBYTECLKVALID
TS0INDATA[0]
TS0INERROR
TS0INPACKETCLK
l
tLDVLCH tLCHLDX
Table 80. tia

TSIn timings - serial input mode
en
Confidential
tLCLLCL TS0INBITORBYTECLK period 10 - - ns

tLCHLCH TS0INBITORBYTECLK pulse width high 3 - - ns
fid
tLCLLCL TS0INBITORBYTECLK pulse width low 3 - - ns

tLDVLCH TS0IN signals valid to TSnINBITORBYTECLK high 3 - - ns
tLCHLDX TS0IN signals hold after TS0INBITORBYTECLK high 0 - - ns
on
21.5 Transport - output

Figure 43. Transport output timing diagram
C
tVOREF
TS0OUTBITORBYTECLK
tVOCHAOV1
TS0OUTDATA[7:0]
TSOUTERROR
TS0OUTBITORBYTECLKVALID
TS0OUTPACKETCLK
Table 81. Transport - output timing values

tVOREF Clock 7.5 - - ns

tVOCHAOV1 Output delay - - 8.4 ns
Doc ID 8141465 Rev 5 273/294

21.6 TAP timing

Figure 44. TAP timing
tTCHTCH
TCK
tTCHTIX
TDI
TMS
tTIVTCH
TDO
l
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tTCHTOV
Table 82. TAP timings

en
Confidential
tTCHTCH TCK period 20 - - ns

tTIVTCH TAP inputs set-up time(1) 4 - - ns
fid
tTCHTIX TAP input hold time 0 - - ns

tTCHTOV TCK low to TAP output valid - - 6 ns
1. Setup and hold time should be equivalent to 20% of the given TCK period.
on
21.7 Audio
21.7.1 S/PDIF
C
The S/PDIF output is Manchester encoded and hence self-clocking. There are no
requirements on this signal relative to other chip signals.
21.7.2 PCM decoder output interface

The PCM interface can be found on the alternate 2 function of PIO2.
The PCM decoder output interface can be clocked off both edges.
274/294 Doc ID 8141465 Rev 5

Figure 45. PCM data output
PCM_MCLK
Tms Tmd Tml

PCM_SCLK
PCM_DATAOUT
PCM_LRCLKOUT
Table 83. PCM data output
l
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Tms PCM_SCLK delay from PCM_MCLK rising edge 1.5 - ns

Tmd PCM_DATAOUT delay from PCM_MCLK rising edge 1.5 - ns
en
Tml PCM_LRCLKOUT delay from PCM_MCLK rising edge 1.5 - ns
Confidential
21.7.3 External audio DAC interface timing requirements

fid
Figure 46. PCM timings for audio DAC
MCLK
on
Tms Tmd Tml

SCLK
PCMDATA
C
LRCLK
Table 84. PCM data timing at audio DAC

Tms SCLK delay from MCLK rising edge 1.5 - ns

Tmd SDIN delay from MCLK rising edge 1.5 - ns
Tml LR delay from MCLK rising edge 1.5 - ns
Doc ID 8141465 Rev 5 275/294

21.8 General PIO

Figure 47. General PIO timing
PIOREF
tPCHPOV
PIOOUT V
tPCHWDZ
PIOREF is any PIO pin
l
PIOOUT
PIOOUT is any other PIO pin
Table 85.
tia
General PIO timing parameters
en
tPCHPOV PIOREF transition to PIO output valid -20.0(1) 0.0 ns

Confidential
tPCHWDZ PIO tri-state after PIOREF transition -20.0 5.0 ns

fid
1. These apply to all GPIO outputs with the exception of the two SSC ports. See Table 86 for PIO timings when in alternate
function.
Table 86. SSC (I2C) PIO timing parameters

on
tPCHPOV PIOREF transition to PIO output valid -20.0 0.0 ns

tPCHWDZ PIO tri-state after PIO REF transition -20.0 5.0 ns
C
21.9 Digital I/O
21.9.1 DMA requests

A pair of request signals for DMA (FDMA_REQ[1:0]). These are used mostly by the FDMA
and are asynchronous. These pins are on alternate functions of the PIO’s - see
Section 9.24: Programmable I/O ports (GPIO and PIO).
21.9.2 External interrupts

External interrupts EXINT0, EXINT1 and EXTIN2 are available on alternate functions of the
PIO’s - see Section 9.24: Programmable I/O ports (GPIO and PIO).
21.9.3 ASC
There are four UARTs. These are, by definition, asynchronous and have no skew or timing
constraints.
276/294 Doc ID 8141465 Rev 5

21.9.4 SSC
There are three SSC interfaces and alternate functions of the PIO’s. See Section 9.24:
Programmable I/O ports (GPIO and PIO). The maximum bit rate for SPI is 10 Mbit/s. The
SSC supporting SPI can be configured to sample on either the rising or falling edge. Data is
sampled using a majority scheme based on communications clock sampling, therefore,
timing constraints are defined in periods of the communications clock.
Figure 48. SSC clock relationship waveform
TCHCH
SSCn_SCLKINOUT
TiCHDV
SSCn_M[TS/RS]R_DIN
l
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TiCHDH ToCLDV
SSCn_M[TS|RS]R_DOUT
SSCn_MRST_DINOUT
en
(n = 0, 1, 2)
Confidential
Table 87. SSC timing parameters

fid
Symbol Parameter Min(1) Nom Max1 Units
tCHCH Input clock period (rising-rising) - 200 - ns

Required time elapsed from rising (capture) clock edge to input
tiCHDV - - 2T ns
on
data stable
Required time elapsed from rising (capture) clock edge for input
tiCHDH 6T + 10 - - ns
data to hold
Required time elapsed from falling (launch) clock to output data
toCLDV 2T - 3T + 10 ns
C
stable
1. T is 1 period communications clock, 16.7 ns for standard 60 MHz communications frequency.
Figure 49. SSC I2C clock relationship waveform
TCHCH
SSCn_SCLKINOUT
TiCHDS TiCHDH
SSCn_M[TS/RS]R_DIN
SSCn_M[TS/RS]R_DOUT
SSCn_MRST_DINOUT
Doc ID 8141465 Rev 5 277/294

Table 88. SSC I2C timing parameters

High speed Fast mode STD mode
Symbol Parameter Units
Min Nom Max Min Nom Max Min Nom Max
tCHCH Input clock period 589 - - 2500 - - 10000 - - ns

(1)
tiCHDS Data set-up time 10 - - 100 - - 250 - - ns
tiCHDH Data hold time 0(2) - 150 300 - 900 300 - 3450 ns
TCL SCLK low period 320 - - 1300 - - 4700 - - ns
TCH SCLK high period 120 - - 600 - - 4000 - - ns
20+
TrTf(3) SDA/SCLK rise/fall 20 - 80 - 300 - - 1000 ns
0.1Cb(4)
l
1. The data is launched during the low period of the clock but captured during the high period of the clock. There is no clock
inversion.
tia
2. A device must internally provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of
the SCLK signal.
3. Both SDA and SCLK are considered data signals and are synchronized with respect to the communications clock. All
parameters are fully programmable in H9 IP block.
en
4. Capacitive load for clock and data bus is 400 pF maximum for I2C. (10 pF per I2C device) Other devices, such as a serial
EEPROM, have a typical value of 8 pF.
Confidential
21.9.5 IRB
There are two inputs and one output and are alternate functions of the PIO - see
fid
Section 9.24: Programmable I/O ports (GPIO and PIO). No constraints on timing or skew.
21.10 Video interface output: YUV dataout (DENC output)

on
Figure 50. Video interface - output timing diagram

tVOREF
C
PAD_DENC_TZ[8]
tVOCHAOV1
PAD_DENC_TZ[7:0]
TVOCHAOV2
PAD_HSYNC
PAD_VSYNC
Table 89. Video interface - output timing values

tVOREF PIXCLK period 27 - 54 MHz

tVOCHAOV1 Output delay of PAD_DENC_TZ[7:0] - - 10.02 ns
TVOCHAOV2 Output delay of PAD_VSYNC and PAD_HSYNC - - 10.94 ns
278/294 Doc ID 8141465 Rev 5

21.11 DVO
Figure 51. DVO timing diagram
tVOREF
DVOCLK
tVOCHAOV1
DVO_DATA[7:0]
l
Table 90. DVO timing values tia
en
Confidential
tVOREF DVOCLK period 18.5 - 37 ns

tVOCHAOV1 Output delay of DVO_DATA[7:0] - - 9.44 ns
fid
on
C
Doc ID 8141465 Rev 5 279/294

21.12 USB ULPI 2.0

USB_DATA to USB_STP: False as RTL will ensure logic blocked by ehci_own[0].
USB_DIR to USB_DATA: Path goes to OEN of the pad.
Figure 52. ULPI timing diagram

Clock
clk_usb_pad
TSC THC
Control in
USB_NXT,
USB_DIR TSD THD
Data in
l
USB_DATA[7:0]
tia
TSDD THDD
Data in
USB_DATA[3:0]
TDC
TSDD THDD
Control out TDC
en
USB_STP
TDD
Confidential
Data out
USB_DATA[7:0]
fid
TDDD TDDD
Data out
USB_DATA[3:0]
on
Table 91. USB timing values

USB_CLOCK_FROM_PAD - - - 60 MHz
C
TSC, TSD Setup time (control in, 4-bit data in) - - 9 ns

TSC, TSD Setup time (control in, 8-bit data in) - - 7.5 ns
THC, THD Hold time (control in, 8-bit data in) 0.0 - - ns
THC, THD Hold time (control in, 4-bit data in) 0.0 - - ns
TDC, TDD Output delay (control out, 4-bit data out) - - 9.6 ns
TDC, TDD Output delay (control out, 8-bit data out) - - 7.5 ns
TSDD Setup time (4-bit data in) (optional) - - 4 ns
THDD Hold time (4-bit data in) (optional) 0.0 - - ns
TDDD Output delay (4-bit data out) (optional) - - 4.33 ns
280/294 Doc ID 8141465 Rev 5

21.13 Ethernet interface AC specifications

The Ethernet interface is compliant to the MII and RMII specifications.
21.13.1 MII interface

MII receive interface
The timing waveform for the receive MII interface is shown in the following figure:
Figure 53. Receive signal timing relationship at the MII PHY interface
RXCLK
l
tia
tsetup thold
RX_DV
RX_ER
en
RX_D*
Confidential
fid
MII transmit interface

The timing waveform for the transmit MII interface is shown in the following figure:
Figure 54. Transmit signal timing relationship at the MII PHY interface
on
TXCLK
C
tsetup thold
TX_EN
TX_D*
Doc ID 8141465 Rev 5 281/294

Table 92. MII interface

Parameter Min Nom Max Units
TXCLK - 25 - MHz
TXD[3:0], TX_EN, RXD[3:0], RX_DV, RX_ER
30 - - ns
(data setup to REF_CLK rising edge)
TXD[3:0], TX_EN, RXD[3:0], RX_DV, RX_ER
0 - - ns
(data hold from REF_CLK rising edge)
RXCLK - 25 - MHz
RX_DV, RX_ER
30 - - ns
(data setup to REF_CLK rising edge)
RXD[3:0], RX_DV, RX_ER
l
0 - - ns
tia
(data hold from REF_CLK rising edge)
MII control interface

The timing waveform for the MII control interface is shown in the following figure:
en
Figure 55. Control signal timing relationship at the MII PHY interface
Confidential
fid
400ns
MDC
10ns
on
MDIO
(Output)
C
400ns
MDC
10ns 0ns
MDIO
(input)
282/294 Doc ID 8141465 Rev 5

21.13.2 RMII interface

RMII timing parameters
The RMII timings parameters are described in the following table:
Table 93. RMII timing parameters

Parameter Min Nom Max Units
REF_CLK frequency (from PHY device) - 50 - MHz

TXD[1:0], TX_EN,RXD[1:0], CRS_DV, RX_ER (data setup to
30 - - ns
REF_CLK rising edge)
TXD[1:0], TX_EN, RXD[1:0], CRS_DV, RX_ER (data hold
0 - - ns
from REF_CLK rising edge)
l
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21.14 SPI timing
Table 94. SPI timing parameters

en
Confidential
TCLOCK Clock period of the SPI clock 20 - ns

TIS Input data setup time (SPI_DATAIN, SPI_DATAOUT) 1.4 - ns
fid
TIH Input data hold time (SPI_DATAIN, SPI_DATAOUT) 0 - ns

TOV Output data valid (SPI_DATAIN, SPI_DATAOUT) 18 - ns
on
Figure 56. SPI timing

TCLOCK
SPI_CLOCK
C
t
t
TIS
TIH
DATAIN
TOV
Doc ID 8141465 Rev 5 283/294

21.15 QPSK output

Figure 57. QPSK output timing diagram
tVOREF
QPSK_CLK
tVOCHAOV1
TS0OUTDATA[7:0]
TS0OUTPACKETCLK
TS0OUTERROR
l
TS0OUTBITORBYTECLKVALID
Table 95. tia

QPSK output timing values
en
Confidential
tVOREF QPSK_CLK 8 - - ns
Output delay with respect
tVOCHAOV1 - - 1.60 ns
fid
to QPSK_CLK
on
C
284/294 Doc ID 8141465 Rev 5

STi5189 Licenses
22 Licenses
Supply of this product does not convey a license under the relevant intellectual property of
the companies mentioned in this chapter nor imply any right to use this intellectual property
in any finished end-user or ready to use final product. An independent license for such use
is required and can be obtained by contacting the company or companies concerned.
Once the license is obtained, a copy must be sent to STMicroelectronics.
The details of all the features requiring licenses are not provided within the datasheet and
register manual. They are provided only after a copy of the license has been received by
STMicroelectronics.
The features requiring licenses include:
l
CSS
tia
CSS DVD Copy Protection is intellectual property of Matsushita Electronics Industrial Co.
The CSS DVD Copy Protection license allows the use of the CSS decryption cell embedded
in the STi5189.
en
For all details, contact Matsushita at:
Matsushita Electronics Industrial Co. LTD, CSS Interim License
Confidential
Organization, 1006 Kadoma, Kadoma-Shi, Osaka 571-8503 JAPAN
Dolby® Digital EX, Pro Logic® II, MLP Lossless™

fid
Dolby Digital, Pro Logic and MLP Lossless are intellectual properties of Dolby Labs. The
Dolby Digital, Pro Logic or MLP Lossless license allows the use of the corresponding
decoder embedded in the STi5189.
on
Two types of license exist: S license must be obtained for samples (up to 25 units). P license
must be obtained for production.
For all details, contact Dolby Labs at:
Dolby Labs, 100 Potrero Avenue, San Francisco, CA 94103, USA
C
Rovi™
Compliant Devices can only be sold or distributed to Authorized Buyers.
In the event that the Rovi variant of this Device is supplied, attention is drawn to the following
notice:
This device is protected by U.S. patent numbers 6,516,132; 5,583,936; 6,836,549; and
7,050,698 and other intellectual property rights. The use of Rovi Corporation's copy
protection technology in the device must be authorized by Rovi Corporation and is intended
for home and other limited pay-per-view uses only, unless otherwise authorized in writing by
Rovi Corporation. Reverse engineering or disassembly is prohibited.
Dwight Cavendish
The STi5189 is enabled with the Dwight Cavendish Copy Protection Process. Activation of
the Dwight Cavendish Copy Protection is subject to Dwight Cavendish Intellectual Property
Rights and is not permitted otherwise than with an express written license from Dwight
Cavendish.
Doc ID 8141465 Rev 5 285/294

Licenses STi5189
TruSurround XT™, CircleSurround™ II

The CircleSurround II, TruSurround XT and SRS technology rights incorporated in this chip
are owned by SRS Labs, a U.S. corporation and licensed to ST Microelectronics.
Purchasers of this chip, who use the SRS technology incorporated herein, must sign a
license for use of the chip and display of the SRS trademarks. Any product using the SRS
technology incorporated in this chip must be sent to SRS Labs for review. Circle Surround II,
TruSurround XT and SRS are protected under U.S. and foreign patents issued and/or
pending.
Neither the purchase of this chip, nor the corresponding sale of audio enhancement
equipment conveys the right to sell commercialized recordings made with any SRS
technology. SRS requires all set makers to comply with all rules and regulations as outlined
in the SRS Trademark Usage Manual.
For all details, contact SRS Labs at:
l
SRS Labs Inc., 2909 Daimler Street, Santa Ana, CA 92705 USA
tia
DTS® (ES, 96/24, Neo)
DTS ES, DTS 96/24 and DTS Neo are intellectual properties of Digital Theater Systems Inc.
The DTS licenses allow the use of the corresponding decoder executed in the STi5189.
en
For all details, contact Digital Theater Systems Inc at:
DTS, 5171 Clareton Drive, Agoura Hills, CA 91301, USA
Confidential
Windows Media® (audio [WMA] and video [WMV])

fid
Windows Media is intellectual property of Microsoft Corporation. The Windows Media

license allows the use of the Windows Media audio and video decoders executed in the
STi5189.
on
For all details, contact Microsoft at:

Microsoft Corporation, One Microsoft Way, Redmond, WA 98052-6399, USA
DVB-MHP
Manufacturers of set-top boxes and other receiving devices are required to obtain the MHP
C
Test Suite, which is used to ensure that the specification has been correctly implemented.
The completion of this certification process enables a manufacturer to apply to use the MHP
logo on their products as a mark of compliance. A license fee is also payable to the holders
of essential IPR in the MHP specifications. The patent holders have formed a patent pool
which is administered by Via Licensing. The schedule of fees due can be seen on the Via
Licensing website http://www.vialicensing.com/licensing/MHP_index.cfm.
For more information on licensing costs for device manufacturers, and to see a list of
companies with the right to display the MHP logo on their equipment see Implementing
MHP http://www.mhp.org/manufacturers.htm.
286/294 Doc ID 8141465 Rev 5

STi5189 Licenses
USB (Universal Serial Bus)

USB is intellectual property of USB-IF. The USB license gives the right to display the
certified USB logo with a product when the product has passed USB-IF compliance testing
for product quality.
For all details, contact USB-IF:
USB Implementers Forum, Inc., 5440 SW Westgate Drive, Suite 217, Portland, OR 97221,
USA
AACS
AACS is an intellectual property of AACS LA, LLC. The AACS license allows the use of
AACS in the STi5189.
For all details, contact AACS LA, LLC at:
c/o AACS Administration, 5440 SW Westgate Drive, Suite 217, Portland, Oregon 97221
l
tia
AAC
AAC is an intellectual property of Fraunhofer Institut Integrierte Schaltungen.
For all details, contact Fraunhofer Institute IIS, Am Wolfsmantel 33, 91058 Erlangen,
Germany.
en
Confidential
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Doc ID 8141465 Rev 5 287/294

List of registers STi5189
List of registers
ID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 VSTATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

DISEQC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 VERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
DISEQC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 FECM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
DISEQCFIFO . . . . . . . . . . . . . . . . . . . . . . . . .113 VITPROG . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
DISEQCSTA1 . . . . . . . . . . . . . . . . . . . . . . . . .113 VTH12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
DISEQCSTA2 . . . . . . . . . . . . . . . . . . . . . . . . .114 VTH23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
DISRX_ST0. . . . . . . . . . . . . . . . . . . . . . . . . . .114 VTH34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
DISRX_ST1. . . . . . . . . . . . . . . . . . . . . . . . . . .115 VTH56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
F22FR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 VTH67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
F22RX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 VTH78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
AGC1C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 PR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
l
AGC1REF . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 VSEARCH . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
tia
AGC1IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 RS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
TSREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 RSOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 ERRCTRL. . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
RTFM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 ECNTM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
en
RTFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 ECNTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
SFRH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 ERRCTRL2. . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Confidential
SFRM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 ECNTM2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

SFRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 ECNTL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
STEP1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 I2CRPT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
fid
TLIRM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 ACR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

TLIRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 DACR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
AGC2COEF . . . . . . . . . . . . . . . . . . . . . . . . . .121 DACR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
AGC2REF . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 PLLCTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
on
AGC2IM . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 SYNTCTRL. . . . . . . . . . . . . . . . . . . . . . . . . . . 144

AGC2IL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 TSTTNR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
CFD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 SYMBCTRL . . . . . . . . . . . . . . . . . . . . . . . . . . 146
LDI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 ISYMB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
LDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 QSYMB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
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LDT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
ACLC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 SDATCFG . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
BCLC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 SCLTCFG. . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
CFRM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 AGCCFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
CFRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 AUXCKCFG . . . . . . . . . . . . . . . . . . . . . . . . . . 148
NIRM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 DISEQCCFG . . . . . . . . . . . . . . . . . . . . . . . . . 148
NIRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 IRQSTATx . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
EQUA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 IRQMSKx . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
EQUAI1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 ASCTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
EQUAQ1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 COARP1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
EQUAI2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 COARP2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
EQUAQ2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 FMINM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
EQUAI3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 FMINL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
EQUAQ3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 FMAXM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
EQUAI4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 FMAXL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
EQUAQ4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 FINEINC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
EQUAI5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 STEP2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
EQUAQ5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 TH2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
288/294 Doc ID 8141465 Rev 5

STi5189 List of registers
TH2ATH1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .154 CLKDIVn_CONFIG0. . . . . . . . . . . . . . . . . . . . 207

TH1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 CLKDIVn_CONFIG0. . . . . . . . . . . . . . . . . . . . 207
THH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 CLKDIV0_CONFIG1. . . . . . . . . . . . . . . . . . . . 208
IND1MAX . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 CLKDIVn_CONFIG1. . . . . . . . . . . . . . . . . . . . 208
ACCU1VAL . . . . . . . . . . . . . . . . . . . . . . . . . . .156 CLKDIVn_CONFIG1. . . . . . . . . . . . . . . . . . . . 209
ACCU2VAL . . . . . . . . . . . . . . . . . . . . . . . . . . .156 CLKDIV0_CONFIG2. . . . . . . . . . . . . . . . . . . . 209
CFG_MONITOR_A . . . . . . . . . . . . . . . . . . . . .159 CLKDIVn_CONFIG2. . . . . . . . . . . . . . . . . . . . 210
CFG_MONITOR_B . . . . . . . . . . . . . . . . . . . . .160 CLKDIVn_CONFIG2. . . . . . . . . . . . . . . . . . . . 211
CFG_MONITOR_C . . . . . . . . . . . . . . . . . . . . .160 FS216X4_SETUP_A . . . . . . . . . . . . . . . . . . . 212
CFG_MONITOR_D . . . . . . . . . . . . . . . . . . . . .160 FS216X4_SETUP_B . . . . . . . . . . . . . . . . . . . 213
CFG_MONITOR_E . . . . . . . . . . . . . . . . . . . . .161 FS216X4_CLK1_SETUP0 . . . . . . . . . . . . . . . 214
CFG_MONITOR_F . . . . . . . . . . . . . . . . . . . . .162 FS216X4_CLKn_SETUP0 . . . . . . . . . . . . . . . 215
CFG_MONITOR_G . . . . . . . . . . . . . . . . . . . . .162 FS216X4_CLK5_SETUP0 . . . . . . . . . . . . . . . 216
CFG_MONITOR_H . . . . . . . . . . . . . . . . . . . . .162 FS216X4_CLKn_SETUP0 . . . . . . . . . . . . . . . 217
CFG_MONITOR_I. . . . . . . . . . . . . . . . . . . . . .163 FS216X4_CLK1_SETUP1 . . . . . . . . . . . . . . . 218
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CFG_MONITOR_J . . . . . . . . . . . . . . . . . . . . .163 FS216X4_CLKn_SETUP1 . . . . . . . . . . . . . . . 218
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CFG_MONITOR_K . . . . . . . . . . . . . . . . . . . . .164 FS216X4_CLK5_SETUP1 . . . . . . . . . . . . . . . 219
CFG_MONITOR_L . . . . . . . . . . . . . . . . . . . . .164 FS216X4_CLKn_SETUP1 . . . . . . . . . . . . . . . 219
CFG_MONITOR_M. . . . . . . . . . . . . . . . . . . . .164 REDUCED_POWER_CONTROL. . . . . . . . . . 220
CFG_MONITOR_N . . . . . . . . . . . . . . . . . . . . .165 LP_MODE_DIS0 . . . . . . . . . . . . . . . . . . . . . . 221
en
CFG_MONITOR_O . . . . . . . . . . . . . . . . . . . . .165 LP_MODE_DIS1 . . . . . . . . . . . . . . . . . . . . . . 222
CFG_MONITOR_P . . . . . . . . . . . . . . . . . . . . .165 LP_MODE_COUNTER_CFG0 . . . . . . . . . . . . 222
Confidential
CFG_MONITOR_Q . . . . . . . . . . . . . . . . . . . . .166 LP_MODE_COUNTER_CFG1 . . . . . . . . . . . . 223

CFG_MONITOR_R . . . . . . . . . . . . . . . . . . . . .166 RTCS_LSB_LP. . . . . . . . . . . . . . . . . . . . . . . . 223
CFG_CTRL_A . . . . . . . . . . . . . . . . . . . . . . . . .167 RTCS_MSB_LP . . . . . . . . . . . . . . . . . . . . . . . 224
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CFG_CTRL_B . . . . . . . . . . . . . . . . . . . . . . . . .168 RTCS_CONTROL_LP . . . . . . . . . . . . . . . . . . 224

CFG_CTRL_C. . . . . . . . . . . . . . . . . . . . . . . . .169 RTCS_LSB_27 . . . . . . . . . . . . . . . . . . . . . . . . 225
CFG_CTRL_D. . . . . . . . . . . . . . . . . . . . . . . . .171 RTCS_MSB_27 . . . . . . . . . . . . . . . . . . . . . . . 225
CFG_CTRL_E . . . . . . . . . . . . . . . . . . . . . . . . .173 RTCS_CONTROL_27 . . . . . . . . . . . . . . . . . . 226
on
CFG_CTRL_F . . . . . . . . . . . . . . . . . . . . . . . . .174 DCO_MODE_CFG . . . . . . . . . . . . . . . . . . . . . 226

CFG_CTRL_G . . . . . . . . . . . . . . . . . . . . . . . .174 DCO_SD_COUNT . . . . . . . . . . . . . . . . . . . . . 227
CFG_CTRL_H. . . . . . . . . . . . . . . . . . . . . . . . .175 DCO_CMD . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
CFG_CTRL_I . . . . . . . . . . . . . . . . . . . . . . . . .176 DCO_PCM_COUNT. . . . . . . . . . . . . . . . . . . . 228
CFG_CTRL_J . . . . . . . . . . . . . . . . . . . . . . . . .177 DCO_HD_COUNT . . . . . . . . . . . . . . . . . . . . . 228
C
CFG_CTRL_K . . . . . . . . . . . . . . . . . . . . . . . . .177 SC_POWER_DETECT_CFG . . . . . . . . . . . . . 229

CFG_CTRL_L . . . . . . . . . . . . . . . . . . . . . . . . .178 RESET_STATUS . . . . . . . . . . . . . . . . . . . . . . 230
CFG_CTRL_M . . . . . . . . . . . . . . . . . . . . . . . .178 WATCHDOG_COUNTER_CFG0. . . . . . . . . . 231
CFG_CTRL_N. . . . . . . . . . . . . . . . . . . . . . . . .179 SC_INSERTION_RST_CFG . . . . . . . . . . . . . 231
CFG_CTRL_O . . . . . . . . . . . . . . . . . . . . . . . .180 WATCHDOG_COUNTER_CFG1. . . . . . . . . . 232
CFG_CTRL_P . . . . . . . . . . . . . . . . . . . . . . . . .180 CPU_INT_CFG. . . . . . . . . . . . . . . . . . . . . . . . 233
CFG_CTRL_Q . . . . . . . . . . . . . . . . . . . . . . . .181 DYNAMIC_POWER_CONFIG . . . . . . . . . . . . 234
CFG_CTRL_R. . . . . . . . . . . . . . . . . . . . . . . . .182 INTC_ICR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
MODE_CONTROL . . . . . . . . . . . . . . . . . . . . .201 INTC_IPRA. . . . . . . . . . . . . . . . . . . . . . . . . . . 247
REGISTER_LOCK_CFG . . . . . . . . . . . . . . . .202 INTC_IPRB. . . . . . . . . . . . . . . . . . . . . . . . . . . 247
CLOCK_OBSERVATION_CFG . . . . . . . . . . .202 INTC_IPRC. . . . . . . . . . . . . . . . . . . . . . . . . . . 247
FORCE_CFG . . . . . . . . . . . . . . . . . . . . . . . . .203 INTC_IPRD. . . . . . . . . . . . . . . . . . . . . . . . . . . 248
PLL_SELECT_CFG . . . . . . . . . . . . . . . . . . . .204 ILC_INPUT_INTERRUPTn. . . . . . . . . . . . . . . 248
PLLA_CONFIG0 . . . . . . . . . . . . . . . . . . . . . . .205 ILC_STATUSn . . . . . . . . . . . . . . . . . . . . . . . . 249
PLLA_CONFIG1 . . . . . . . . . . . . . . . . . . . . . . .205 ILC_CLEAR_STATUSn . . . . . . . . . . . . . . . . . 249
PLLB_CONFIG0 . . . . . . . . . . . . . . . . . . . . . . .206 ILC_ENABLEn . . . . . . . . . . . . . . . . . . . . . . . . 250
PLLB_CONFIG1 . . . . . . . . . . . . . . . . . . . . . . .206 ILC_CLEAR_ENABLEn . . . . . . . . . . . . . . . . . 250
CLKDIV0_CONFIG0 . . . . . . . . . . . . . . . . . . . .207 ILC_SET_ENABLEn. . . . . . . . . . . . . . . . . . . . 251
Doc ID 8141465 Rev 5 289/294

List of registers STi5189
ILC_WAKEUP_ENABLE . . . . . . . . . . . . . . . . .251
ILC_WAKEUP_ACTIVE_LEVEL . . . . . . . . . . .252
ILC_PRIORITYn . . . . . . . . . . . . . . . . . . . . . . .252
ILC_MODEn . . . . . . . . . . . . . . . . . . . . . . . . . .253
ILC_MODE2 . . . . . . . . . . . . . . . . . . . . . . . . . .254
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290/294 Doc ID 8141465 Rev 5

STi5189 Revision history
23 Revision history
Table 96. Document revision history

Date Revision Changes
25-May-2009 A Initial release.

- Replaced PBGA 15x15 with LFBGA 15x15 throughout the document.
- Replaced ‘STv0299B demodulator’ with ‘STv0289B demodulator’ in
Section 12.5.1.
- Added the Chapter 22: Licenses.
- Updated the features and cover page diagram as per the new template.
- Updated the electrical and timing specifications chapter.
- Replaced EMI with FMI.
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- Added pin E13 and K8 in Table 11.
- Added Alt2 function in Table 39.
10-Nov-2009 B
- Updated Alt1 and Alt3 function of PIO4[3] and Alt2 function of PIO4[0] in
Table 41.
- Added Chapter 1: Related documents.
en
- Reversed the bank numbers in Figure 36.
Confidential
- Added Section 21.1.1: System AC specification.

- Updated Section 20.9: Front-end interface: ADC.
- Updated the interrupt controller registers.
fid
- Updated the Chapter 16: System services registers.

- Updated the bit[5] description of the TSTTNR1 register.
on
C
Doc ID 8141465 Rev 5 291/294

Revision history STi5189
Table 96. Document revision history (continued)

- Replaced RX_CLK by RXCLK in Figure 53.

- Replaced TX_CLK by TXCLK in Figure 54.
- Replaced Macrovision with Rovi throughout the datasheet.
- Replaced the Macrovision information with the new Rovi information in
the Chapter 22.
- Added the RthJA in Table 60.
- Added the DCS information in Section 2.1, Section 3.6, Section 5.2.7
and Chapter 22.
- Replaced 16 bpp with 16 bpp/32 bpp throughout the document.
- Updated the description of the SPI pins in Table 27.
- Renamed the V4 ball in 15 x 15 mm package and AD15 ball in
l
23 x 23 mm package throughout the datasheet.
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- Added the RESETEXTOUT signal in Table 13.
- Updated Table 29.
- Updated PIO3[7] in Table 40.
- Updated table headings in Table 49.
en
- Updated the “Parameter” column in Table 74.
- Renamed the signal name in Figure 37.
Confidential
- Updated the description of Section 21.1.3: Watchdog reset out.

03-Dec-2010 C - Replaced the word “pin” by “ball” throughout the datasheet.
- Updated description of Section 19.2.1 and Figure 36.
fid
- Correct the naming of E2 and E3 balls for 15 x 15 mm package in

Table 11.
- Updated the Chapter 1: Related documents.
- Updated the maximum voltage of VDD1V0_FE in Table 60.
on
- Updated the maximum value of VDD1V0 in Table 60, Table 63, Table 65
and Table 67.
- Updated Table 59.
- Added ARGB8888 throughout the datasheet where ARGB4444 is
C
mentioned.
- Updated description of bit [11:1] in the PLL_SELECT_CFG register.
- Renamed the headings of Table 5, Table 6, Table 7, Table 8, Table 9 and
Table 10.
- Added note 1 in Section 20.1: Absolute maximum ratings.
- Added a footnote below Table 4.
- Updated row ‘b’ of the Table 3.
- Added Section 20.3: System: oscillator.
- Updated Section 3.7: Processor and memory.
- Updated feature “Target speed at 350 MHz delivering > 630 DMIPs” in
Section 2.1: STi5189 features summary.
292/294 Doc ID 8141465 Rev 5

STi5189 Revision history
Table 96. Document revision history (continued)

- Updated the value of FPLL below the equation in Section 15.3.3:

Frequency synthesizer clocks.
- Updated the description of bit[7] of the SYNTCTRL register.
- Updated the functional mode divide ratio of CLK_BLT, CLK_SYS,
CLK_AV and CLK_ETH in Table 50: Clock frequency requirement for
02-Jan-2012 4
different modes.
- Updated the AACS license.
- Added note 1 in Section 20.1: Absolute maximum ratings.
- Updated the maximum value of VDDE3V3 and TSMAX in Table 59:
Absolute maximum ratings.
03-Apr-2012 5 Updated Table 91: USB timing values on page 280.
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Doc ID 8141465 Rev 5 293/294

STi5189
CONFIDENTIALITY OBLIGATIONS:
This document contains sensitive information.
Its distribution is subject to the signature of a Non-Disclosure Agreement (NDA).
It is classified “CONFIDENTIAL”.
At all times you should comply with the following security rules
(Refer to NDA for detailed obligations):
Do not copy or reproduce all or part of this document
Keep this document locked away
Further copies can be provided on a “need to know basis”, please contact your local ST sales office.
Please Read Carefully:
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Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
en
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
Confidential
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
fid
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
on
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
C
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2012 STMicroelectronics - All rights reserved
STMicroelectronics group of companies

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STi5189

Low-cost QPSK demodulator and MPEG2 decoder

Features ■ Active and passive low power modes

processing single chip, suitable for MPEG2-based satellite

the latest CA requirements STBs).

clocks PCM I/O STB peripherals I/O

CPU/FPU Audio I/O Peripherals System Flash, SFlash

Transport Video decoder Display Video I/O

Transport streams IQ in Digital video SD in/out

April 2012 Doc ID 8141465 Rev 5 1/294

3.5 Graphics and display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.7 Processor and memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.10 Clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.13 Package options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4 Audio and video summary specification . . . . . . . . . . . . . . . . . . . . . . . 21

2/294 Doc ID 8141465 Rev 5

5.2.4 Transport stream processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8 BGA footprint and ball list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8.1 Ball grid array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

9.1 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Doc ID 8141465 Rev 5 3/294

11 Register base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

4/294 Doc ID 8141465 Rev 5

13.3 General-purpose registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

14 Configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

14.1.1 High-speed configuration monitor registers . . . . . . . . . . . . . . . . . . . . . 159

14.2.1 High-speed configuration control registers . . . . . . . . . . . . . . . . . . . . . 167

15 System services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

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15.6 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

15.10.6 SDRAM interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

16 System services registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

16.2 PLL clock generation registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

16.5 Low power control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

17 Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

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17.2 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

18 Interrupt system registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

20 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

20.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

20.4 Standard digital 3.3V pad DC specifications . . . . . . . . . . . . . . . . . . . . . 261

20.7 Audio DAC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

21 Timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

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21.1.4 System clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

21.9.3 ASC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

21.9.5 IRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

21.12 USB ULPI 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

21.13.2 RMII interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

23 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

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USB 2.0 host controller/ULPI and Ethernet MAC MII/RMII interface.

● Embedded QPSK demodulator:

– Digital cancellation of A/D offset

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– Concurrent decoding of audio description

– Four 10-bit video DACs, outputting RGB/CVBS/YC analog video signals

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– Secure control words

– JTAG interface locking

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The STi5189 will be available in two packages, LFBGA 15 mm x 15 mm and PBGA