Lecture 17 --- Multipliers

"There are 3 kinds of people: those who

make things happen, those who watch
things happen, and those who wonder
what the hell just happened.“

George Carlin --- Comedian

 Recall Binary Multiplication
input_1

In decimal: In binary:
input_2
01100
12 x01101
x13 01100 01101
36 00000 01101
+12 01100 01101
x 1_ 01100 01101
156 + 00000____ 01101
010011100

When multiplying binary numbers, the multiplicand is either copied or not copied to the
partial products for addition. Therefore, a serial multiplier can be implemented with an
array of additions and shifting.
 Multiplication Architecture

input_1 & zeros

+
sum
1 0 select
multiplexor

right shift 1 bit (0 inserted from left)

zeros input_2
product_reg LSB of
product_reg
 Multiplication Architecture
From our example earlier…

01100 & 00000

+
sum
1 0 select
multiplexor

right shift 1 bit (0 inserted from left)

00000 0110 1
product_reg LSB of product_reg
In this cycle, it’s also the
LSB of input_2
 Multiplication Architecture
From our example earlier…

00000 01101

01100 00000
+
sum
1 0 select
multiplexor

right shift 1 bit (0 inserted from left)

00000 0110 1
product_reg LSB of
product_reg
 Multiplication Architecture
From our example earlier…

00000 01101

01100 00000
+
sum
1 0 select
multiplexor
01100 01101

right shift 1 bit (0 inserted from left)

00000 0110 1
product_reg LSB of
product_reg
 Multiplication Architecture
From our example earlier…

00000 01101

01100 00000
+
sum
1 0 select
multiplexor
01100 01101

right shift 1 bit (0 inserted from left)

00110 00110 (now update product_reg)
00000 0110 1
product_reg LSB of
product_reg
 Multiplication Architecture
From our example earlier…

Next iteration!
00110 00110

01100 00000
+
sum
1 0 select
multiplexor
01100 01101

right shift 1 bit (0 inserted from left)

00110 00110

00110 0011 0
product_reg LSB of
product_reg
 Multiplication Architecture
From our example earlier…

00110 00110

01100 00000
+
sum
1 0 select
multiplexor
00110 00110

right shift 1 bit (0 inserted from left)

00110 00110

00110 0011 0
product_reg LSB of
product_reg
 Multiplication Architecture
From our example earlier…

00110 00110

01100 00000
+
sum
1 0 select
multiplexor
00110 00110

right shift 1 bit (0 inserted from left)

00011 00011

00110 0011 0
product_reg LSB of
product_reg
 Multiplication Architecture
From our example earlier…

And so on…
00110 00110

01100 00000
+
sum
1 0 select
multiplexor
00110 00110

right shift 1 bit (0 inserted from left)

00011 00011

00011 0001 1
product_reg LSB of
product_reg
 Serial Multiplication: Example
# iterations = # bits of input_2

input_1 & zeros

zeros & input_2

Iteration input_1 product_reg Description

0 01100 00000 00000 01101 Look at LSB, 1: Add and Shift
1 01100 00000 00110 00110 Look at LSB, 0: Shift
2 01100 00000 00011 00011 Look at LSB, 1: Add and Shift
3 01100 00000 00111 10001 Look at LSB, 1: Add and Shift
4 01100 00000 01001 11000 Look at LSB, 0: Shift
5 01100 00000 00100 11100 Result
 State Machine
start_mult = ‘0’
init

start_mult = ‘1’
start = ‘0’

start = ‘1’ done load

count = maxcount

count /= maxcount right_shift

 Edge Detection Circuitry
start_mult_lead
start_mult

start
D Q D Q

clk Q clk Q
rst rst not(start_mult_follow)

clk start_mult is
triggered at beginning of
start occurs next clock cycle
in middle of
start_mult clock cycle

start

clk
 mult_1.vhd

User defined type for state

machine. Use 2 signals,
“state”, and “nxt_state”

Define intermediate
signals and registers
mult_1.vhd
State machine moves to the
next state at clock edge

Initialize the control

signals at the beginning
of the state machine
process

Control signals
‘add_and_shift’
and ‘shift’ are used
to determine whether
or not we ‘add and
shift’ or just ‘shift’,
respectively
mult_1.vhd

Counter to keep track

of shifts and adds

Replace ‘?’ with the Reset the input_1_reg and

correct code! product_reg registers

Load the input_1_reg and

product_reg registers

Add input_1_reg to the

product_reg and shift

Shift the product_reg to the right

test_mult_1.vhd
test_mult_1.vhd
test_mult_1.vhd
mult1_input.vhd
Simulation Results
 Combinational Logic Multipliers

• Determine product in a single clock cycle

• Require large amounts of combinational logic

• Most FPGAs have dedicated multiplication

units
– Quartus – “Embedded Multiplier Elements”
Combinational Multiplier
mult_2.vhd
Combinational Multiplier
mult_2.vhd
Simulation Results
Serial vs. Combinational
mult_2 Technology View
 Pin Assignments

product

data_ready

reset

input_1 (8 bits) input_2 (8 bits) start

 Lab 12 Time
Compile and Simulate:
mult_1.vhd, mult_2.vhd
Synthesize and implement on the DE2 board:
mult_1.vhd

I need to see mult_1.vhd successfully implemented on your DE2 board