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RT9245

Multi-Phase PWM Controller for CPU Core Power Supply


General Description Features
RT9245 is a multi-phase buck DC/DC controller integrated z Multi-Phase Power Conversion with Automatic
with all control functions for Intel® GHz CPU which is Phase Selection
VRD10.X-compliant. The RT9245 could be operated with z 6-bits VRD10.x DAC Output with Active Droop
2, 3 or 4 buck switching stages operating in interleaved Compensation for Fast Load Transient
phase set automatically. The multiphase architecture z Smooth VCORE Transition at VID Jump
provides high output current while maintaining low power z Power Stage Thermal Balance by DCR Current
dissipation on power devices and low stress on input and Sense
output capacitors. The high equivalent operating frequency z Hiccup Mode Over-Current Protection
also reduces the component dimension and the output z Programmable Switching Frequency (50kHz to
voltage ripple in load transient. 400kHz per Phase), Under-Voltage Lockout and Soft-
Start
RT9245 implements both voltage and current loops to
z High Ripple Frequency Times Channel Number
achieve good regulation, response and power stage
z 28-TSSOP Package
thermal balance.
z RoHS Compliant and 100% Lead (Pb)-Free
RT9245 applies the DCR sensing technology newly. The
RT9245 extracts the ESR of output inductor as sense Applications
component to deliver a precise load line regulation and z Intel® Processors Voltage Regulator : VRD10.x
good thermal balance for next generation processor z Low Output Voltage, High Current DC-DC Converters
application. z Voltage Regulator Modules
Current sense setting, droop tuning, VCORE initial offset
and over current protection are independent on Pin Configurations
compensation circuit of voltage loop. The feature greatly (TOP VIEW)
facilitates the flexibility of CPU power supply design and VID4 28 VCC
VID3 2 27 PWM1
tuning. The DAC output of RT9245 supports VRD10.x with
VID2 3 26 PWM2
6-bit VID input, precise offset value & smooth VCORE VID1 4 25 PWM3
transient at VID jump. The IC monitors the VCORE voltage VID0 5 24 PWM4
VID125 6 23 CSP4
for PGOOD and over-voltage protection. Soft-start, over- SGND 7 22 CSP2
current protection and programmable under-voltage lockout FB 8 21 CSP3
COMP 9 20 CSP1
are also provided to assure the safety of microprocessor
PGOOD 10 19 GND
and power system. The RT9245 comes to a small footprint DVD 11 18 ADJ
package TSSOP-28. SS 12 17 NC
RT 13 16 CSN
VOSS 14 15 IMAX

Ordering Information TSSOP-28


RT9245
Note :
Package Type
C : TSSOP-28 RichTek Pb-free and Green products are :
Operating Temperature Range `RoHS compliant and compatible with the current require-
P : Pb Free with Commercial Standard
ments of IPC/JEDEC J-STD-020.
G : Green (Halogen Free with Commer-
cial Standard) `Suitable for use in SnPb or Pb-free soldering processes.
`100% matte tin (Sn) plating.

DS9245-06 March 2007 www.richtek.com


1
2
VIN
ATX 1uH
12V

+
C11 C12
ATX 1000uF 1uF
C14
12V C10
0.1uF 1000uF

+
C13
R22 C15

www.richtek.com
1000uF
RT9245

10 D1 R23 1uF
1N4148 RT9603 Q1
1 8 0
BST DRVH L1
4 1uH
VCC 7 IPD09N03LA
C9 SW
VCC 0.1uF R24 R25
Q2
5V 2 5 0 2.2
IN DRVL
3
NC PGND IPD06N03LA C16
R9 6 3.3nF
10

ATX
C4 12V C18 VIN C20 C21
RT9245 0.1uF 0.1uF 1000uF 1000uF
+

1 28 C19
Typical Application Circuit

VID4 VID4 VCC R26


R10 0
VOUT
2 27 10 D2 1uF
VID3 PWM1 RT9603 R27 Q3
VID3 1N4148 8
R11 1 0
3 26 0 BST DRVH
VID2 VID2 PWM2 L2 C35 to C46
4 1uH 1000uF x 12
25 R12 0 VCC 7 IPD09N03LA +
4 PWM3 SW
VID1 VID1 C17
R13 0 0.1uF
5 PWM4 24 R28 Q4 R29
VID0 VID0 2 5 0 2.2
23 R14 10k IN DRVL +
6 CSP4 3
VID125 VID125 C5 NC IPD06N03LA C22
PGND C47 to C50
R1 0 7 22 0.1uF R15 10k 3.3nF
SGND CSP2 6 10uF x 4
C6
N.C 8 21 0.1uF R16 10k
FB CSP3
C7 ATX
C1 33pF 9 20 0.1uF
COMP CSP1 12V C24
VIN C26 C27
R2 3k R17 0.1uF 1000uF 1000uF
C2
+

19 R18 0 10k
R3 15k 10nF GND C25
VCC 10 C8 R30
PGOOD 18 R19 82 1uF
5V ADJ 0.1uF 10 D3
R31
R4 10k 1N4148 RT9603 Q5
ATX R5 9.1k 11 1 8 0
DVD 17 BST DRVH
12V NC L3
C3 12 R20 330 4 1uH
SS CSN 16 VCC 7 IPD09N03LA
0.1uF SW
13 C23
R6 RT 0.1uF R33
2k 15 NC R32 Q6
R7 30k 14 IMAX 5 0 2.2
VOSS 2
IN DRVL
R8 100k 3
R21 NC PGND IPD06N03LA C28
6.8k 6 3.3nF

ATX C30 VIN C32 C33


12V 0.1uF 1000uF 1000uF
+

C31
R34
10 D4
R35 1uF
RT9603 Q7
1N4148 1 8 0
BST DRVH L4
4 1uH
VCC 7 IPD09N03LA
C29 SW
0.1uF R36 Q8 R37
2 5 0 2.2
IN DRVL
3
NC PGND IPD06N03LA C34
6 3.3nF

DS9245-06 March 2007


RT9245
Functional Pin Description
VID4 (Pin 1), VID3 (Pin 2), VID2 (Pin 3), VID1 (Pin 4), IMAX (Pin 15)
VID0 (Pin 5) & VID125 (Pin 6) Programmable over currert setting.
DAC voltage identification inputs for VRD10.x. These pins
are internally pulled to 1.2V if left open. CSN (Pin 16)
Current sense negative input of all channels.
SGND (Pin 7)
VCORE differential sense negative input. NC (Pin 17)
No Connection.
FB (Pin 8)
Inverting input of the internal error amplifier. ADJ (Pin 18)
Current sense output for active droop adjust. Connect a
COMP (Pin 9) resistor from this pin to GND to set the load droop.
Output of the error amplifier and input of the PWM
comparator. GND (Pin 19)
Ground for the IC.
PGOOD (Pin 10)
Power good open-drain output. CSP1 (Pin 20), CSP2 (Pin 22), CSP3 (Pin 21) & CSP4
(Pin 23)
DVD (Pin 11) Current sense positive inputs for individual converter
Programmable power UVLO detection input. Trip threshold channel current sense.
= 1.2V at VDVD rising.
PWM1 (Pin 27), PWM2 (Pin 26), PWM3 (Pin 25) &
SS (Pin 12) PWM4 (Pin 24)
Connect this SS pin to GND with a capacitor to set the PWM outputs for each driven channel. Connect these pins
soft-start time interval. Pulling this pin below 1V (ramp to the PWM input of the MOSFET driver. For systems
valley of sawtooth wave in pulse width modulator) would which use 3 channels, connect PWM4 high. Two channel
make all PWMs low, turn on low side MOSFETs, and turn systems connect PWM3 high.
off high side MOSFETs.
VCC (Pin 28)
RT (Pin 13) IC power supply. Connect this pin to a 5V supply.
Switching frequency setting. Connect this pin to GND with
a resistor to set the frequency.

VOSS (Pin 14)


VCORE initial value offset. Connect this pin to GND with a
resistor to set the negative offset value. Connect this pin
to VCC to set positive offset value.

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4
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RT9245

IMAX PGOOD VCC DVD RT

+ INH PWM Logic


Oscillator PWM1
VID4 OCP - & Driver
VID3 Setting Power On Reset & + +
VID2 Sawtooth
VID1 DAC PWMCP
VID0 INH
Function Block Diagram

VID125 INH + PWM Logic


PWM2
- & Driver
+ +
PWMCP
OVP Trip + INH
Point
+ PWM Logic
PWM3
- - & Driver
+ +
PWMCP
PG Trip
INH
+
DAC + Droop + PWM Logic
Point PWM4
-
- & Driver
+ +
PWMCP
Phase Control
+
+ - Current
CSP1
- Correction
+ CSP2
Error MUX
Amplifier
- CSP3
GAP
Offset Currrent Amplifier CSP4
+ +
Source/Sink +
SS MUX -
-
Control
- CSN
+
-

SUM/M

VOSS FB COMP SS ADJ GND

DS9245-06 March 2007


RT9245
Table 1. Output Voltage Program
Pin Name
Nominal Output Voltage DACOUT
VID4 VID3 VID2 VID1 VID0 VID125
1 1 1 1 1 X No CPU
0 1 0 1 0 0 0.8375V
0 1 0 0 1 1 0.850V
0 1 0 0 1 0 0.8625V
0 1 0 0 0 1 0.875V
0 1 0 0 0 0 0.8875V
0 0 1 1 1 1 0.900V
0 0 1 1 1 0 0.9125V
0 0 1 1 0 1 0.925V
0 0 1 1 0 0 0.9375V
0 0 1 0 1 1 0.950V
0 0 1 0 1 0 0.9625V
0 0 1 0 0 1 0.975V
0 0 1 0 0 0 0.9875V
0 0 0 1 1 1 1.000V
0 0 0 1 1 0 1.0125V
0 0 0 1 0 1 1.025V
0 0 0 1 0 0 1.0375V
0 0 0 0 1 1 1.050V
0 0 0 0 1 0 1.0625V
0 0 0 0 0 1 1.075V
0 0 0 0 0 0 1.0875V
1 1 1 1 0 1 1.100V
1 1 1 1 0 0 1.1125V
1 1 1 0 1 1 1.125V
1 1 1 0 1 0 1.1375V
1 1 1 0 0 1 1.150V
1 1 1 0 0 0 1.1625V
1 1 0 1 1 1 1.175V
1 1 0 1 1 0 1.1875V
1 1 0 1 0 1 1.200V
1 1 0 1 0 0 1.2125V
To be continued

DS9245-06 March 2007 www.richtek.com


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RT9245
Table 1. Output Voltage Program
Pin Name
Nominal Output Voltage DACOUT
VID4 VID3 VID2 VID1 VID0 VID125
1 1 0 0 1 1 1.225V
1 1 0 0 1 0 1.2375V
1 1 0 0 0 1 1.250V
1 1 0 0 0 0 1.2625V
1 0 1 1 1 1 1.275V
1 0 1 1 1 0 1.2875V
1 0 1 1 0 1 1.300V
1 0 1 1 0 0 1.3125V
1 0 1 0 1 1 1.325V
1 0 1 0 1 0 1.3375V
1 0 1 0 0 1 1.350V
1 0 1 0 0 0 1.3625V
1 0 0 1 1 1 1.375V
1 0 0 1 1 0 1.3875V
1 0 0 1 0 1 1.400V
1 0 0 1 0 0 1.4125V
1 0 0 0 1 1 1.425V
1 0 0 0 1 0 1.4375V
1 0 0 0 0 1 1.450V
1 0 0 0 0 0 1.4625V
0 1 1 1 1 1 1.475V
0 1 1 1 1 0 1.4875V
0 1 1 1 0 1 1.500V
0 1 1 1 0 0 1.5125V
0 1 1 0 1 1 1.525V
0 1 1 0 1 0 1.5375V
0 1 1 0 0 1 1.550V
0 1 1 0 0 0 1.5625V
0 1 0 1 1 1 1.575V
0 1 0 1 1 0 1.5875V
0 1 0 1 0 1 1.600V
Note: (1) 0 : Connected to GND
(2) 1 : Open
(3) X : Don't Care
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RT9245
Absolute Maximum Ratings (Note 1)
z Supply Voltage, VCC ------------------------------------------------------------------------------------------- 7V
z Input, Output or I/O Voltage ---------------------------------------------------------------------------------- GND − 0.3V to VCC + 0.3V
z Package Thermal Resistance
TSSOP-28, θJA -------------------------------------------------------------------------------------------------- 100°C/W
z Junction Temperature ------------------------------------------------------------------------------------------ 150°C
z Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------- 260°C
z Storage Temperature Range --------------------------------------------------------------------------------- −65°C to 150°C
z ESD Susceptibility (Note 2)
HBM (Human Body Mode) ----------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions (Note 3)
z Supply Voltage, VCC ------------------------------------------------------------------------------------------- 5V ± 10%
z Ambient Temperature Range --------------------------------------------------------------------------------- 0°C to 70°C
z Junction Temperature Range --------------------------------------------------------------------------------- 0°C to 125°C

Electrical Characteristics
(VCC = 5V, TA = 25°C, unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Units
VCC Supply Current
Nominal Supply Current ICC PWM 1,2,3,4 Open -- 12 16 mA
Power-On Reset
POR Threshold VCCRTH VCC Rising 4.0 4.2 4.5 V
Hysteresis VCCHYS 0.2 0.5 -- V
Trip (Low to High) VDVDTP Enable 1.1 1.2 1.3 V
VDVD Threshold
Hysteresis VDVDHYS -- 50 -- mV
Oscillator
Free Running Frequency fOSC RRT = 32kΩ 170 200 230 kHz
Frequency Adjustable Range fOSC_ADJ 50 -- 400 kHz
Ramp Amplitude ΔVOSC RRT = 32kΩ -- 1.9 -- V
Ramp Valley VRV 0.7 1.0 -- V
Maximum On-Time of Each Channel 62 66 75 %
RT Pin Voltage VRT RRT = 32kΩ 1.4 1.60 1.8 V
Reference and DAC
VDAC ≥ 1V −1 -- +1 %
DACOUT Voltage Accuracy ΔVDAC
VDAC < 1V −10 -- +10 mV
DAC (VID0-VID125) Input Low VILDAC -- -- 0.4 V
DAC (VID0-VID125) Input High VIHDAC 0.8 -- -- V
DAC (VID0-VID125) Bias Current IBIAS_DAC 25 50 75 μA
VOSS Pin Voltage VVOSS RVOSS = 100kΩ 1.5 1.65 1.8 V
To be continued
DS9245-06 March 2007 www.richtek.com
7
RT9245
Parameter Symbol Test Conditions Min Typ Max Units
Error Amplifier
DC Gain -- 85 -- dB
Gain-Bandwidth Product GBW -- 10 -- MHz
Slew Rate SR COMP = 10pF -- 3 -- V/μs
Current Sense GM Amplifier
CSN Full Scale Source Current IISPFSS 100 -- -- μA
CSN Current for OCP 150 -- -- μA
Protection
SS Current ISS VSS = 1V 8 13 18 μA
Over-Voltage Trip (VSEN/DACOUT) ΔOVT 130 140 150 %
IMAX Voltage VIMAX RIMAX = 32k 1.4 1.60 1.8 V
Power Good
Output Low Voltage VPGOODL IPG = 4mA -- -- 0.2 V

Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are
for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. The device is not guaranteed to function outside its operating conditions.

www.richtek.com DS9245-06 March 2007


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RT9245
Typical Operating Characteristics
GM1 GM2
300 300
VADJ VADJ
250 250

200
Voltage (mV)

200

Voltage (mV)
VP VP
150 150

100 100

50
VN VN
50

0 0
0 25 50 75 100 125 150 0 25 50 75 100 125 150
Vx (mV) Vx (mV)

GM3 GM4
300 300
VADJ VADJ
250 250

200 200
Voltage (mV)

Voltage (mV)

VP VP
150 150

100 100

50 VN 50 VN

0 0
0 25 50 75 100 125 150 0 25 50 75 100 125 150
Vx (mV) Vx (mV)

Adjustable Frequency Linearity of each PWM


450 3

400 2.8

350 2.6
2.4
300 PWM2
FOSC (kHz)

V COMP (V)

2.2 PWM3
250
2 PWM1
200 PWM4
1.8
150
1.6
100 1.4
50 1.2
fOSC = 200k
0 1
0 25 50 75 100 125 150 175 0 500 1000 1500 2000 2500 3000 3500

RRT (kΩ)
(k⎠ ) Pulse Width (ns)

DS9245-06 March 2007 www.richtek.com


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RT9245

Load Transient Response Load Transient Response


V CORE V CORE

Phase1
Phase
Phase2
CH1: (500mV/Div)
IOUT
CH2: (10V/Div) Phase3
VADJ CH3: (50A/Div) CH1: (500mV/Div), CH2: (10V/Div)
CH4: (100mV/Div) CH3: (10V/Div), CH4: (10V/Div)

Time (5μs/Div) Time (5μs/Div)

Relationship Between Inductor


Current and VADJ Power-Off @ IOUT = 60A
CH1:(5V/Div)
CH2:(5V/Div)

PWM PWM
CH1:(5V/Div)
CH2:(20V/Div)
VSS
UGATE
CH3:(10V/Div)
VADJ CH4:(1V/Div)
LGATE

IL CH3:(50mV/Div)
CH4:(20A/Div)
VCOMP

Time (25ms/Div) Time (10μs/Div)

Power-On @ IOUT = 60A


CH1:(5V/Div)
CH2:(5V/Div)

VSS
PWM

UGATE
CH3:(20V/Div)
CH4:(10V/Div)
LGATE

Time (10ms/Div)

www.richtek.com DS9245-06 March 2007


10
RT9245
Application Information
Load Droop
RT9245 is a multi-phase DC/DC controller that precisely
regulates CPU core voltage and balances the current of The sensed power channel current signals regulate the
different power channels. The converter consisting of reference of DAC to form an output voltage droop
RT9245 and its companion MOSFET driver RT9603/ proportional to the load current. The droop or so call “active
RT9603A provides high quality CPUpower and all voltage positioning” can reduce the output voltage ripple
protection functions to meet the requirement of modern at load transient and the LC filter size.
VRM.
Fault Detection
Voltage Control The chip detects FB for over voltage and power good
RT9245 senses the CPU VCORE by SGND pin to sense detection. The “hiccup mode” operation of over current
the return of CPU to minimize the voltage drop on PCB protection is adopted to reduce the short circuit current.
trace at heavy load. OVP is sensed at FB pin. The internal The in-rush current at the start up is suppressed by the
high accuracy VID DAC provides the reference voltage for soft start circuit through clamping the pulse width and
VRD10.X compliance. Control loop consists of error output voltage.
amplifier, multi-phase pulse width modulator, driver and
Phase Setting and Converter Start Up
power components. As conventional voltage mode PWM
RT9245 interfaces with companion MOSFET drivers (like
controller, the output voltage is locked at the VREF of
RT9603, RT9602 series) for correct converter initialization.
error amplifier and the error signal is used as the control
The tri-state PWM output (high, low and high impedance)
signal of pulse width modulator. The PWM signals of
senses its interface voltage when IC POR acts (both VCC
different channels are generated by comparison of EA
and DVD trip). The channel is enabled if the pin voltage is
output and split-phase sawtooth wave. Power stage
1.2V less than VCC. Tie the PWM to VCC and the
transforms VIN to output by PWM signal on-time ratio.
corresponding current sense pins to GND or left float if
Current Balance the channel is unused. For example, for 3-Channel
RT9245 senses the inductor current via inductor's DCR application, connect PWM4 high.
for channel current balance and droop tuning. The
Current Sensing Setting
differential sensing GM amplifier converts the voltage on
RT9245 senses the current flowing through inductor via
the sense component (can be a sense resistor or the
its DCR for channel current balance and droop tuning. The
DCR of the inductor) to current signal into internal balance
differential sensing GM amplifier converts the voltage on
circuit.
the sense component (can be a sense resistor or the
The current balance circuit sums and averages the current DCR of the inductor) to current signal into internal circuit
signals and then produces the balancing signals injected (see Figure 1).
to pulse width modulator. If the current of some power
L VC
channel is larger than average, the balancing signal = R × C VC = DCR × IL I X =
DCR R CSN
reduces that channels pulse width to keep current balance. L DCR
The use of single GM amplifier via time sharing technique
to sense all inductor currents can reduce the offset errors
and linearity variation between GMs. Thus it can greatly
R
C
improve signal processing especially when dealing with
+
such small signal as voltage drop across DCR. -
RCSN
GMx

Ix
Figure 1. Current Sense Circuit

DS9245-06 March 2007 www.richtek.com


11
RT9245
Figure 2 is the test circuit for GM. We apply test signal at Time Sharing of GM
GM inputs and observe its signal process output at ADJ CH1:(2V/Div)
pin. Figure 3 shows the variation of signal processing of CH2:(50mV/Div)
CH3:(50mV/Div)
all channels. We observe zero offsets and good linearity
between phases.
PWM3

L DCR
VCSP4

ESR VCSP4 V CSN


VX
VCSP and
+
VCSN V CSN
-
RCSN
GMx
1k Time (1μs/Div)
Ix Figure 4

Figure 2. The Test Circuit of GM


Over Current Protection
RT9245 uses an external resistor R IMAX to set a
GM programmable over current trip point. OCP comparator
300
compares each inductor current with this reference current.
250 RT9245 uses hiccup mode to eliminate fault detection of
OCP or reduce output current when output is shorted to
200 ground.
VADJ (mV)

1 VIMAX 1 IL × DCR
150 × ⇔ ×
2 RIMAX 3 R COMMON
100
OCP Comparator
50 1/3 IX
+
- 1/2 IIMAX
0
0 25 50 75 100 125 150 Figure 5. Over Current Comparator
Vx (mV)
Over Current Protection
Figure 3. The Linearity of GMx
CH1:(5V/Div)
CH2:(5V/Div)
Figure 4 shows the time sharing technique of GM amplifier.
We apply test signal at phase 4 and observe the waveforms
at both pins of GM amplifier. The waveforms show time PWM
sharing mechanism and the perfomance of GM to hold
both input pins equal when the shared time is on.

VSS

Time (25ms/Div)

Figure 6. The Over Current Protection in the soft start


interval
www.richtek.com DS9245-06 March 2007
12
RT9245
L
Over Current Protection Thus if = (R1//R2) × C
DCR
CH1:(5V/Div)
R2
CH2:(5V/Div) Then VC = × DCR × IL
R1+ R2

PWM
With internal current balance function, this phase would
share (R 1+R 2)/R 2 times current than other phases.
Figure 9 &10 show different settings for the power stages.
Figure 11 shows the performance of current ratio compared
with conventional current balance function in Figure 12.
VSS

Time (25ms/Div)
Figure 7. Over Current Protection at steady state

Current Ratio Setting

Figure 9. GM4 Setting for current ratio function

Figure 8. Application circuit for current ratio setting


Figure 10. GM1~3 Setting for current ratio function
For some case with preferable current ratio instead of
current balance, the corresponding technique is provided.
Due to different physical environment of each channel, it Current Ratio Function
35
is necessary to slightly adjust current loading between
IL4
channels. Figure 8 shows the application circuit of GM for 30
current ratio requirement. Applying KVL along L+DCR
25
branch and R1+C//R2 branch :
20 IL3
I L (A)

dI V dV
L L + DCR × IL = R1( C + C C ) + VC IL2
dt R2 dt 15 IL1
dVC R1 + R 2
= R1C + VC 10
dt R2
R2 5
For VC = DCR × IL
R1 + R 2
0
Look for its corresponding conditions : 0 15 30 45 60 75 90

I OUT (A)
dIL dI
L + DCR × IL = (R1//R2)× C × DCR × L + DCR × IL
dt dt Figure 11
L
Let = (R1//R2)× C
DCR

DS9245-06 March 2007 www.richtek.com


13
RT9245
Current Balance Function Assume the negative inductor valley current is −5A at no
30
IL3 load, then for
25 IL4 RCSN1 = 330Ω, RADJ = 160Ω, VOUT = 1.300

20 IL1 1.3V −5A × 1mΩ



RCSN2 330Ω
I L (A)

IL2
15
RCSN2 ≤ 85.8kΩ
10
Choose RCSN2 = 82kΩ
5

Load Line without dead zone at light loads


0
1.31
0 20 40 60 80 100

I OUT (A) 1.3

1.29
Figure 12
1.28
V CORE (V)
L DCR 1.27 RCSN2 open

1.26

1.25 RCSN2 = 82k


ESR
C
V 1.24
+ CSP
VCSN
- 1.23
RCSN1
GMx 0 5 10 15 20 25

Ix
I OUT (A)
RCSN2
Figure 14

VID on the Fly


Figure13. Application circuit of GM
With external pull up resistors tied to VID pins, RT9245
For load line design, with application circuit in Figure 13, converters different VID codes from CPU into output
it can eliminate the dead zone of load line at light loads. voltage. Figure 12 and Figure 13 show the waveforms of
VCSP = VOUT +IL x DCR VID on the fly function.
if GM holds input voltages equal, then
VID on the Fly (Falling)
VCSP = VCSN
V I × DCR
IX = CSN + L PWM
RCSN2 RCSN1
V CORE
VOUT + IL × DCR IL × DCR
= + VFB
RCSN2 RCSN1
VOUT IL × DCR IL × DCR CH1:(5V/Div) CH3:(500mV/Div)
= + + CH2:(500mV/Div) CH4:(1V/Div)
RCSN2 R CSN2 RCSN1
For the lack of sinking capability of GM, RCSN2 should be
small enough to compensate the negative inductor valley VID125
VDAC = 1.500, IOUT = 5A
current especially at light loads.
VCSN I × DCR Time (25μs/Div)
≥ L
RCSN2 RCSN1 Figure 15
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14
RT9245
VID on the Fly (Rising) Voltage Offset Function
1.284

1.282
PWM
1.28
V CORE
1.278

V CORE (V)
VFB
1.276
CH3:(500mV/Div) CH1:(5V/Div)
CH4:(1V/Div) CH2:(500mV/Div) 1.274

1.272

1.27
VID125
VDAC = 1.500, IOUT = 5A
1.268
50 60 70 80 90 100 110
Time (25μs/Div)
(kٛ )
ROSS (kΩ)
Figure 16
Figure 18

1/4 IVOSS PGOOD Waveform


CH1:(500mV/Div)
RB1
- CH2:(5V/Div)
EA CH3:(5V/Div)
+

VDAC-VADJ

V CORE
Figure 17
PGOOD

Output Voltage Offset Function


To meet Intel's requirement of initial offset of load line,
VSS
RT9245 provides programmable initial offset function. With
an external resistor RVOSS and voltage source at VOSS pin
to set offset current IVOSS. One quart of IVOSS flows through Time (10ms/Div)

RB1. Error amplifier would hold the inverting pin equal to Figure 19
VDAC-V ADJ. Thus output voltage is subtracted from
VDAL − VADJ for a constant offset voltage.
VDD

PGOOD Function
RPGOOD
To indicate the condition of multiphase converter, RT9245
VPGOOD
provides PGOOD signal through an open drain connection.
The waveforms of PGOOD function are shown in Figure
15.

Figure 20. PGOOD Test Circuit

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RT9245
Error Amplifier Characteristic EA Rising Slew Rate
For fast response of converter to meet stringent output
current transient response, RT9245 provides large slew VFB

rate capability and high gain-bandwidth performance.

EA Falling Slew Rate

VFB VCOMP CH1:(500mV/Div)


CH2:(2V/Div)

Time (250ns/Div)
Figure 22. EA Falling Transient with 10pF Loading;
Slew Rate=8V/us
VCOMP CH1:(500mV/Div)
CH2:(2V/Div)
4.7k
Time (250ns/Div)
B 4.7k - A
Figure 21. EA Rising Transient with 10pF Loading; Slew EA
+
Rate=10V/us
VREF

Figure 23. Gain-Bandwidth Measurement by signal A


divided by signal B

0dB

180°

Figure 24. EA Frequency Response with closed loop gain set at 0db to observe gain-bandwidth product; -3dB at
10.86MHz
www.richtek.com DS9245-06 March 2007
16
RT9245
Design Procedure Suggestion 1. Compensation Setting
a.Output filter pole and zero (Inductor, output capacitor a. Modulator Gain, Pole and Zero:
value & ESR). From the following formula:
b.Error amplifier compensation & sawtooth wave amp- Modulator Gain =VIN/VRAMP =12/2.4=5 (i.e 14dB)
litude (compensation network).
where VRAMP : ramp amplitude of saw-tooth wave
c.Kelvin sense for VCORE.
LC Filter Pole = = 1.45kHz and
Current Loop Setting ESR Zero =3.98kHz
a.GM amplifier S/H current (current sense component
b. EA Compensation Network:
DCR, CSN pin external resistor value).
Select R1 = 4.7k, R2 = 15k, C1 = 12nF, C2 = 68pF and
b.Over-current protection trip point (RIMAX resistor).
use the Type 2 compensation scheme shown in Figure
25. By calculation, the FZ = 0.88kHz, FP = 322kHz and
VRM Load Line Setting
Middle Band Gain is 3.19 (i.e 10.07dB).
a.Droop amplitude (ADJ pin resistor).
b.No load offset (RCSN2)
C2 68pF
c.DAC offset voltage setting (VOSS pin & compen- sation
RB2 C1
network resistor RB1).
15k 12nF
RB1
Power Sequence & SS -
4.7k EA
+
DVD pin external resistor and SS pin capacitor.

PCB Layout Figure 25. Type 2 compensation network of EA

a.Kelvin sense for current sense GM amplifier input.


The bode plot of EA compensation is shown as Figure 26.
b.Refer to layout guide for other items.
The bode plot of power stage is shown as Figure 27. The
Voltage Loop Setting total loop gain is in Figure 28.

Design Example 3. Over-Current Protection Setting

Given: Consider the temperature coefficient of copper


3900ppm/°C,
Apply for four phase converter
1 VIMAX 1 IL × DCR
VIN = 12V × ⇔ ×
2 RIMAX 3 R COMMON
VCORE = 1.5V
1 1.690V 1 40A × 1.39m Ω
× ⇔ ×
ILOAD (MAX) = 100A 2 RIMAX 3 330Ω
VDROOP = 100mV at full load (1mΩ Load Line)
Let RIMAX = 14kΩ
OCP trip point set at 40A for each channel (S/H)
DCR = 1mΩ of inductor at 25°C 4. Soft-Start Capacitor Selection
L = 1.5μH For most application cases, 0.1μF is a good engineering
value.
COUT = 8000μF with 5mΩ equivalent ESR.

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RT9245

0dB

-180°

Figure 26. The Frequency Response of the Compensator Network

0dB

-180°

Figure 27. The Frequency Response of Power Stage

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RT9245

0dB

-180°

Figure 28. The Loop Gain of Converter

Layout Guide
Place the high-power switching components first, and separate them from sensitive nodes.

1. Most critical path: the current sense circuit is the most sensitive part of the converter. The current sense
resistors tied to CSP1,2,3,4 and CSN should be located not more than 0.5 inch from the IC and away from
the noise switching nodes. The PCB trace of sense nodes should be parallel and as short as possible.
Kelvin connection of the sense component (additional sense resistor or Inductor DCR) ensures the accurate
stable current sensing.

Keep well Kelvin sense to ensure the stable operation!


2. Switching ripple current path:
a. Input capacitor to high side MOSFET.
b. Low side MOSFET to output capacitor.
c. The return path of input and output capacitor.
d. Separate the power and signal GND.
e. The switching nodes (the connection node of high/low side MOSFET and inductor) is the most noisy points.
Keep them away from sensitive small-signal node.
f. Reduce parasitic R, L by minimum length, enough copper thickness and avoiding of via.

3. MOSFET driver should be closed to MOSFET.

4. The compensation, bypass and other function setting components should be near the IC and away from the noisy
power path.

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RT9245

L1
SW1

VIN VOUT

RIN
COUT
CIN RL
V
L2
SW2

Figure 29. Power Stage Ripple Current Path

Next to IC +12V or +5V


+12V
PWM VCC +5VIN
0.1uF
CBP
CBOOT RT
VCC BST VOSS Next to IC
PVCC COMP
DRVH SGND
LO1
VCORE
CC
IN SW
COUT
RT9603 CIN RCSN RT9245
RC
DRVL CSN
Kelvin
Sense FB Locate next
GND to FB Pin
RFB
CSPx
Locate near MOSFETs
ADJ
GND

For Thermal Couple

Figure 30. Layout Consideration

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RT9245

Figure 31. Layout of power stage

Test Conditions :
VIN : 12V
VOUT : 1.300V
FSW : 200kHz
IOUT : 80A
Phase Number : 4 Phases
U-MOSFET : IR3707 x 1 (9.5mΩ x 9.6nC)
L-MOSFET : IR8113 x 2 (6.0mΩ x 22nC)
L : 1.5uH
DCR : 1m
CIN : 1000uF x 8
COUT : 1000uF x 8
Snubber : 2R2+3.3nF
Air Speed : Using MAGIC MGA8012HS FAN with 5VDC drive.

P1 P1 P1 P1 P2 P2 P2 P2
Driver M1 M2 M3 Driver M4 M5 M6
55°C 58°C 58°C 56°C 56°C 60°C 60°C 60°C

P3 P3 P3 P3 P4 P4 P4 P4
Driver M7 M8 M9 Driver M10 M11 M12
55°C 64°C 64°C 65°C 59°C 69°C 66°C 61°C

Note: VIN= 10.835V; IIN = 10.6A; VOUT = 1.2127V; IOUT = 80A; η =84.47%

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RT9245
Outline Dimension

E E1

A A2
A1
b

Dimensions In Millimeters Dimensions In Inches


Symbol
Min Max Min Max
A 0.850 1.200 0.033 0.047
A1 0.050 0.152 0.002 0.006
A2 0.800 1.050 0.031 0.041
b 0.178 0.305 0.007 0.012
D 9.601 9.804 0.378 0.386
e 0.650 0.026
E 6.300 6.500 0.248 0.256
E1 4.293 4.496 0.169 0.177
L 0.450 0.762 0.018 0.030

28-Lead TSSOP Plastic Package

Richtek Technology Corporation Richtek Technology Corporation


Headquarter Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City 8F, No. 137, Lane 235, Paochiao Road, Hsintien City
Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)89191466 Fax: (8862)89191465
Email: marketing@richtek.com

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