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Multi-Phase PWM Controller For CPU Core Power Supply: General Description Features
Multi-Phase PWM Controller For CPU Core Power Supply: General Description Features
+
C11 C12
ATX 1000uF 1uF
C14
12V C10
0.1uF 1000uF
+
C13
R22 C15
www.richtek.com
1000uF
RT9245
10 D1 R23 1uF
1N4148 RT9603 Q1
1 8 0
BST DRVH L1
4 1uH
VCC 7 IPD09N03LA
C9 SW
VCC 0.1uF R24 R25
Q2
5V 2 5 0 2.2
IN DRVL
3
NC PGND IPD06N03LA C16
R9 6 3.3nF
10
ATX
C4 12V C18 VIN C20 C21
RT9245 0.1uF 0.1uF 1000uF 1000uF
+
1 28 C19
Typical Application Circuit
19 R18 0 10k
R3 15k 10nF GND C25
VCC 10 C8 R30
PGOOD 18 R19 82 1uF
5V ADJ 0.1uF 10 D3
R31
R4 10k 1N4148 RT9603 Q5
ATX R5 9.1k 11 1 8 0
DVD 17 BST DRVH
12V NC L3
C3 12 R20 330 4 1uH
SS CSN 16 VCC 7 IPD09N03LA
0.1uF SW
13 C23
R6 RT 0.1uF R33
2k 15 NC R32 Q6
R7 30k 14 IMAX 5 0 2.2
VOSS 2
IN DRVL
R8 100k 3
R21 NC PGND IPD06N03LA C28
6.8k 6 3.3nF
C31
R34
10 D4
R35 1uF
RT9603 Q7
1N4148 1 8 0
BST DRVH L4
4 1uH
VCC 7 IPD09N03LA
C29 SW
0.1uF R36 Q8 R37
2 5 0 2.2
IN DRVL
3
NC PGND IPD06N03LA C34
6 3.3nF
SUM/M
Electrical Characteristics
(VCC = 5V, TA = 25°C, unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Units
VCC Supply Current
Nominal Supply Current ICC PWM 1,2,3,4 Open -- 12 16 mA
Power-On Reset
POR Threshold VCCRTH VCC Rising 4.0 4.2 4.5 V
Hysteresis VCCHYS 0.2 0.5 -- V
Trip (Low to High) VDVDTP Enable 1.1 1.2 1.3 V
VDVD Threshold
Hysteresis VDVDHYS -- 50 -- mV
Oscillator
Free Running Frequency fOSC RRT = 32kΩ 170 200 230 kHz
Frequency Adjustable Range fOSC_ADJ 50 -- 400 kHz
Ramp Amplitude ΔVOSC RRT = 32kΩ -- 1.9 -- V
Ramp Valley VRV 0.7 1.0 -- V
Maximum On-Time of Each Channel 62 66 75 %
RT Pin Voltage VRT RRT = 32kΩ 1.4 1.60 1.8 V
Reference and DAC
VDAC ≥ 1V −1 -- +1 %
DACOUT Voltage Accuracy ΔVDAC
VDAC < 1V −10 -- +10 mV
DAC (VID0-VID125) Input Low VILDAC -- -- 0.4 V
DAC (VID0-VID125) Input High VIHDAC 0.8 -- -- V
DAC (VID0-VID125) Bias Current IBIAS_DAC 25 50 75 μA
VOSS Pin Voltage VVOSS RVOSS = 100kΩ 1.5 1.65 1.8 V
To be continued
DS9245-06 March 2007 www.richtek.com
7
RT9245
Parameter Symbol Test Conditions Min Typ Max Units
Error Amplifier
DC Gain -- 85 -- dB
Gain-Bandwidth Product GBW -- 10 -- MHz
Slew Rate SR COMP = 10pF -- 3 -- V/μs
Current Sense GM Amplifier
CSN Full Scale Source Current IISPFSS 100 -- -- μA
CSN Current for OCP 150 -- -- μA
Protection
SS Current ISS VSS = 1V 8 13 18 μA
Over-Voltage Trip (VSEN/DACOUT) ΔOVT 130 140 150 %
IMAX Voltage VIMAX RIMAX = 32k 1.4 1.60 1.8 V
Power Good
Output Low Voltage VPGOODL IPG = 4mA -- -- 0.2 V
Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are
for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. The device is not guaranteed to function outside its operating conditions.
200
Voltage (mV)
200
Voltage (mV)
VP VP
150 150
100 100
50
VN VN
50
0 0
0 25 50 75 100 125 150 0 25 50 75 100 125 150
Vx (mV) Vx (mV)
GM3 GM4
300 300
VADJ VADJ
250 250
200 200
Voltage (mV)
Voltage (mV)
VP VP
150 150
100 100
50 VN 50 VN
0 0
0 25 50 75 100 125 150 0 25 50 75 100 125 150
Vx (mV) Vx (mV)
400 2.8
350 2.6
2.4
300 PWM2
FOSC (kHz)
V COMP (V)
2.2 PWM3
250
2 PWM1
200 PWM4
1.8
150
1.6
100 1.4
50 1.2
fOSC = 200k
0 1
0 25 50 75 100 125 150 175 0 500 1000 1500 2000 2500 3000 3500
RRT (kΩ)
(k⎠ ) Pulse Width (ns)
Phase1
Phase
Phase2
CH1: (500mV/Div)
IOUT
CH2: (10V/Div) Phase3
VADJ CH3: (50A/Div) CH1: (500mV/Div), CH2: (10V/Div)
CH4: (100mV/Div) CH3: (10V/Div), CH4: (10V/Div)
PWM PWM
CH1:(5V/Div)
CH2:(20V/Div)
VSS
UGATE
CH3:(10V/Div)
VADJ CH4:(1V/Div)
LGATE
IL CH3:(50mV/Div)
CH4:(20A/Div)
VCOMP
VSS
PWM
UGATE
CH3:(20V/Div)
CH4:(10V/Div)
LGATE
Time (10ms/Div)
Ix
Figure 1. Current Sense Circuit
L DCR
VCSP4
1 VIMAX 1 IL × DCR
150 × ⇔ ×
2 RIMAX 3 R COMMON
100
OCP Comparator
50 1/3 IX
+
- 1/2 IIMAX
0
0 25 50 75 100 125 150 Figure 5. Over Current Comparator
Vx (mV)
Over Current Protection
Figure 3. The Linearity of GMx
CH1:(5V/Div)
CH2:(5V/Div)
Figure 4 shows the time sharing technique of GM amplifier.
We apply test signal at phase 4 and observe the waveforms
at both pins of GM amplifier. The waveforms show time PWM
sharing mechanism and the perfomance of GM to hold
both input pins equal when the shared time is on.
VSS
Time (25ms/Div)
PWM
With internal current balance function, this phase would
share (R 1+R 2)/R 2 times current than other phases.
Figure 9 &10 show different settings for the power stages.
Figure 11 shows the performance of current ratio compared
with conventional current balance function in Figure 12.
VSS
Time (25ms/Div)
Figure 7. Over Current Protection at steady state
dI V dV
L L + DCR × IL = R1( C + C C ) + VC IL2
dt R2 dt 15 IL1
dVC R1 + R 2
= R1C + VC 10
dt R2
R2 5
For VC = DCR × IL
R1 + R 2
0
Look for its corresponding conditions : 0 15 30 45 60 75 90
I OUT (A)
dIL dI
L + DCR × IL = (R1//R2)× C × DCR × L + DCR × IL
dt dt Figure 11
L
Let = (R1//R2)× C
DCR
IL2
15
RCSN2 ≤ 85.8kΩ
10
Choose RCSN2 = 82kΩ
5
1.29
Figure 12
1.28
V CORE (V)
L DCR 1.27 RCSN2 open
1.26
Ix
I OUT (A)
RCSN2
Figure 14
1.282
PWM
1.28
V CORE
1.278
V CORE (V)
VFB
1.276
CH3:(500mV/Div) CH1:(5V/Div)
CH4:(1V/Div) CH2:(500mV/Div) 1.274
1.272
1.27
VID125
VDAC = 1.500, IOUT = 5A
1.268
50 60 70 80 90 100 110
Time (25μs/Div)
(kٛ )
ROSS (kΩ)
Figure 16
Figure 18
VDAC-VADJ
V CORE
Figure 17
PGOOD
RB1. Error amplifier would hold the inverting pin equal to Figure 19
VDAC-V ADJ. Thus output voltage is subtracted from
VDAL − VADJ for a constant offset voltage.
VDD
PGOOD Function
RPGOOD
To indicate the condition of multiphase converter, RT9245
VPGOOD
provides PGOOD signal through an open drain connection.
The waveforms of PGOOD function are shown in Figure
15.
Time (250ns/Div)
Figure 22. EA Falling Transient with 10pF Loading;
Slew Rate=8V/us
VCOMP CH1:(500mV/Div)
CH2:(2V/Div)
4.7k
Time (250ns/Div)
B 4.7k - A
Figure 21. EA Rising Transient with 10pF Loading; Slew EA
+
Rate=10V/us
VREF
0dB
180°
Figure 24. EA Frequency Response with closed loop gain set at 0db to observe gain-bandwidth product; -3dB at
10.86MHz
www.richtek.com DS9245-06 March 2007
16
RT9245
Design Procedure Suggestion 1. Compensation Setting
a.Output filter pole and zero (Inductor, output capacitor a. Modulator Gain, Pole and Zero:
value & ESR). From the following formula:
b.Error amplifier compensation & sawtooth wave amp- Modulator Gain =VIN/VRAMP =12/2.4=5 (i.e 14dB)
litude (compensation network).
where VRAMP : ramp amplitude of saw-tooth wave
c.Kelvin sense for VCORE.
LC Filter Pole = = 1.45kHz and
Current Loop Setting ESR Zero =3.98kHz
a.GM amplifier S/H current (current sense component
b. EA Compensation Network:
DCR, CSN pin external resistor value).
Select R1 = 4.7k, R2 = 15k, C1 = 12nF, C2 = 68pF and
b.Over-current protection trip point (RIMAX resistor).
use the Type 2 compensation scheme shown in Figure
25. By calculation, the FZ = 0.88kHz, FP = 322kHz and
VRM Load Line Setting
Middle Band Gain is 3.19 (i.e 10.07dB).
a.Droop amplitude (ADJ pin resistor).
b.No load offset (RCSN2)
C2 68pF
c.DAC offset voltage setting (VOSS pin & compen- sation
RB2 C1
network resistor RB1).
15k 12nF
RB1
Power Sequence & SS -
4.7k EA
+
DVD pin external resistor and SS pin capacitor.
0dB
-180°
0dB
-180°
0dB
-180°
Layout Guide
Place the high-power switching components first, and separate them from sensitive nodes.
1. Most critical path: the current sense circuit is the most sensitive part of the converter. The current sense
resistors tied to CSP1,2,3,4 and CSN should be located not more than 0.5 inch from the IC and away from
the noise switching nodes. The PCB trace of sense nodes should be parallel and as short as possible.
Kelvin connection of the sense component (additional sense resistor or Inductor DCR) ensures the accurate
stable current sensing.
4. The compensation, bypass and other function setting components should be near the IC and away from the noisy
power path.
L1
SW1
VIN VOUT
RIN
COUT
CIN RL
V
L2
SW2
Test Conditions :
VIN : 12V
VOUT : 1.300V
FSW : 200kHz
IOUT : 80A
Phase Number : 4 Phases
U-MOSFET : IR3707 x 1 (9.5mΩ x 9.6nC)
L-MOSFET : IR8113 x 2 (6.0mΩ x 22nC)
L : 1.5uH
DCR : 1m
CIN : 1000uF x 8
COUT : 1000uF x 8
Snubber : 2R2+3.3nF
Air Speed : Using MAGIC MGA8012HS FAN with 5VDC drive.
P1 P1 P1 P1 P2 P2 P2 P2
Driver M1 M2 M3 Driver M4 M5 M6
55°C 58°C 58°C 56°C 56°C 60°C 60°C 60°C
P3 P3 P3 P3 P4 P4 P4 P4
Driver M7 M8 M9 Driver M10 M11 M12
55°C 64°C 64°C 65°C 59°C 69°C 66°C 61°C
Note: VIN= 10.835V; IIN = 10.6A; VOUT = 1.2127V; IOUT = 80A; η =84.47%
E E1
A A2
A1
b