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CAN FD Network Design Hints and Recommendations: Holger Zeltwanger
CAN FD Network Design Hints and Recommendations: Holger Zeltwanger
2016-01-0060
Published 04/05/2016
Copyright © 2016 SAE International
doi:10.4271/2016-01-0060
saepcelec.saejournals.org
ABSTRACT
The CAN FD protocol internationally standardized in ISO 11898-1:2015 just describes how to implement it into silicon. The ISO
11898-2:2016 standard specifies the physical media attachment (PMA) sub-layer of the CAN (FD) physical layer. The design of CAN
FD networks is not in the scope of these standards. In general, the physical layer design of CAN FD networks requires more attention
compared with Classical CAN networks. First recommendations have been developed. Different standardization bodies have already
specified or are in the process of specifying higher-layer protocols, for example ISO for on-board diagnostic, ASAM for calibration, etc.
CITATION: Zeltwanger, H., "CAN FD Network Design Hints and Recommendations," SAE Int. J. Passeng. Cars – Electron. Electr. Syst.
9(1):2016, doi:10.4271/2016-01-0060.
Edition 2016 of the ISO 11898-2 standard (merging the legacy ISO
THE CAN FD PROTOCOL AND ITS IMPACTS 11898-2, -5, and -6 standards) specifies the transceiver characteristics.
ON THE PHYSICAL LAYER There are three new parameters of interest: the loop-delay from TxD
to RxD, the Tx delay, and the Rx delay. The transceiver loop-delay is
The CAN FD protocol introduces a second bit-rate to be used in the
the time between receiving the bit at TxD and transmitting it at RxD
data phase, when just one node is transmitting bits. All other nodes in
from the viewpoint of the transceiver. The recessive-to-dominant
the network are receivers. This means, it is not necessary to be
edge is measured at 30 percent and the dominant-to-recessive edge at
synchronized. In this phase there is no in-bit time sampling required
70 percent. The symmetry for both delays is important for the
as in the arbitration phase, when several nodes are transmitting
transmitting node. The most critical situation is the recessive bit after
identifier bits or the ACK (acknowledge) bit. This means, the bit-rate
five dominants. If the transceiver is very asymmetric, the recessive
is not dependent on the network length. The network and transceiver
bit-time is shortened or expanded in relation to the nominal bit-time.
propagation delays are not more relevant. The bit-time setting for the
Therefore the ISO 11898-2:2016 standard specifies the minimum and
data-phase is similar to the arbitration phase. The user needs to
maximum values for recessive bits as shown in Table 1. The values
configure the time-quantum, the SYNC segment and the sample-
are given for a network load on the bus-lines (CAN_H and CAN_L)
point. ISO 11898-1:2015 provides just a framework for the bit-time
of 60 Ω and 100 pF.
settings, e.g. to use the same oscillator frequency in all nodes. In
order to keep the quantization error as small as possible, it is Table 1. Loop-delay symmetry (source: ISO 11898-2:2016)
recommended to use an equal time-quantum length for both bit-rates.
ISO 11898-1 contains some formulas to calculate the maximum
allowed oscillator frequency tolerance at a given data-phase bit-rate.
When the ratio of data-phase bit-rate and arbitration bit-rate is low
(e.g. 6:1) the Classical CAN oscillator tolerance is sufficient. For
higher ratios, the tolerance needs to be calculated using the
referenced formulas.
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90 Zeltwanger / SAE Int. J. Passeng. Cars – Electron. Electr. Syst. / Volume 9, Issue 1 (May 2016)
The allowed transmitter supply voltage tolerance, the network load, CAN FD NODE DESIGN
and temperature effects cause this asymmetry. In order to reduce the RECOMMENDATIONS
emission the transmitter controls the slew-rate of the falling and rising
Besides using CAN transceivers compliant with ISO 11898-2:2016,
edge to the lowest value possible at a given bit-rate. Table 2 shows the
the CiA 601-1 specification gives further hints and recommentations
specified values as given in ISO 11898-2:2016 for a network load on
on the design of CAN FD connectable electronic control units (ECU).
the bus-lines (CAN_H and CAN_L) of 60 Ω and 100 pF.
Figure 2 shows a typical communication network with a transmitting
Table 2. Transceiver Tx delay symmetry (source ISO 11898-2:2016) node, a receiving node and the wire in between. The symmetry of the
RxD signal on the receiving node is defined by the symmetry
performance of the transmitting and receiving node. To guarantee a
robust communication between two or more nodes in a network, the
transceiver Tx delay symmetry of the transmitting node and the
transceiver Rx delay symmetry of the receiving node shall be very
accurate. The loop-delay symmetry cannot cover this in total. It could
be that one ECU in the network has a transceiver with a very
symmetric transmitter part and an asymmetric receiver part. The
The transceiver Rx delay depends on production dispersion, behavior of a transceiver from another supplier may behave vice
temperature variation, receiver thresholds, supply voltage variation, versa. Therefore, in CiA 601-1 additional parameters are defined for
and the slew rate. The delay is a calculated value as given in Table 3. the transmitter and receiver symmetry.
The ΔtRec(min) value shortens the recessive bit-length and ΔtRec(max)
lengthens the recessive bit-length.
Table 4 provides the resulting min and max values for the recessive
Figure 1 shows the impacts between the TxD signal of the bit length seen by a receiving node. They are valid for a 60- Ω and
transmitting node, the Vdiff differential bus voltage, and the possible 100-pF busload. The following effects are not considered in this part
recessive bit-time duration at the RxD pin of the receiving node. The of the document, but in the CiA 601-4 specification (not yet released):
rising edges can jitter, and the falling edges are stable. the behavior of the network itself such as ringing or additional
propagation delay of the dominant to recessive transition, and clock
tolerances.
Table 4. Recessive bit-time at the receiving node’s RxD pin (source: CiA
601-1)
Figure 1. Jitter of the rising edge at a receiving node’s RxD pin (source: CiA
601-1)
The range marked in green is the variation of the transmitter and the
range marked in yellow is the variation of the receiver. To calculate
the worst-case scenario, both parameters are added [2].
CAN FD nodes with configured data-phase bit-rate of 1 or 2 Mbit/s The sample-point of the data-phase bit-rate is independent of the
should use transceiver chips compliant to ISO 11898-2:2016 qualified arbitration point-rate sample-point. The setting depends on the
for 2 Mbit/s. Nodes using a data-phase bit-rate of 5 Mbit/s should transmitting node delay (TD). The TD is the delay from the CAN
implement transceivers qualified for 5 Mbit/s as specified in ISO controller’s transmit flip-flop (FF) to its receive flip-flop. This means,
11898-2:2016 or for higher bit-rates (not yet standardized in ISO when the CAN controller sends a bit, this bit appears at the CAN
11898-2:2016). controller’s input after TD. This TD is the sum of the following delays:
Zeltwanger / SAE Int. J. Passeng. Cars – Electron. Electr. Syst. / Volume 9, Issue 1 (May 2016) 91
• Transceiver loop delay TxD to RxD, (printed circuit board) capacitance. Te typical value for this is 10 ns
• Propagation delay from RxD transceiver port to RxD micro- for the transmitting and receiving node. Also the chosen topology
controller port, may cause bit asymmetry, which is not included in the transceiver
• Propagation delay from RxD micro-controller port to CAN asymmetry values. Some relalistic values are given in [6]. They and
controller Rx-FF output, other research results will be summarized in the CiA 601-3 CAN FD
system design recommendation, which is under development.
• Propagation delay of the galvanic isolation devices (if
available).
If the sample-point is within the phase margin, it is necessary to use
the secondary sample-point (SSP) as defined in ISO 11898-1:2015. It
If there are any additional components in the interface between
is recommended to configure the SSP, so that it is somewhere in the
transceiver and micro-controller, the delay increases. At higher
middle of the remaining bit (this is the time after phase-margin A and
bit-rates the transmitting node shall compensate the TD to be able to
before phase-margin B).
compare its transmitted bits to the current bit on the CAN network.
The feature in the transmitting node that allows compensating the TD
Another critical point is the ringing on the bus-line. It can be reduced
is called transmitting node delay compensation (TDC). TD does not
by using a bus-line topology with very short stub-lines (daisy-chain).
affect receiving nodes.
But even, when there is ringing, dedicated circuitry may reduce the
ringing. One option is the ringing suppression circuitry (RSC) as
The recessive-to-dominant edge observed at the RxD pin of a
proposed in CiA 601-4 [3]. The RSC adjusts dynamically the network
transceiver is rather stable but the dominant-to-recessive edge can
overall impedance. It reduces the impedance for configured time. The
shift. The components between CAN transceiver and CAN controller
most critical nodes needs to be equipped with such circuitry. The
have a low impact on the stability of the edge. Consequently, the
RSC may be integrated in CAN transceiver chips.
measurement of the TD is performed at a recessive-to-dominant edge.
In case TDC function is enabled, a CAN controller acting as
Unfortunately, there is not sufficient experience available to give
transmitter measures the TD based on the recessive-to-dominant edge
general guidelines for all topologies. Additional research is necessary.
from FDF-bit to res-bit. It performs the measurement once within
It seems that star topologies with ferrties are possible for data-phase
each FD frame that uses bit-rate switching. The CAN controller
bit-rates up to 2 Mbit/s [5].
compares its transmitted bit to the received bit at the secondary
sample point (SSP).
The SAE develops currently recommended practices for the design of
high-speed CAN (HSC) for vehicle applications at 500 kbit/s with
CAN FD data-phase bit-rates of 2 Mbit/s respecively 5 Mbit/s
(J2284-4 and J2284-5). The 2-Mbit/s approach is indented for
bus-line topology, while the 5-Mbit/s solution is intended for
point-topoint communication.
92 Zeltwanger / SAE Int. J. Passeng. Cars – Electron. Electr. Syst. / Volume 9, Issue 1 (May 2016)
can be reduced by the factor of 3 compared with legacy J1939 network. Therefore, it is necessary to design the network with more
network running at 500 kbit/s. Another impact is the reduced number care as Classical CAN networks. It could be already critical to use
of interrupt requests. The CiA 602 series is intented to be submitted cables with temperature-dependent isolation material. SAE’s and
to SAE to be released as a joint CiA/SAE specification. CiA’s recommendations (J2284 series and CiA 601 series) will give
also not so experienced users a chance to design CAN FD networks
properly. In general, you need to optimize network topology, in order
to reduce the ringing. Additionally, the bit-timing should be
optimized, in order to minimize the bit-rate dependent part of the
phase margin. Of course, a careful selection of physical layer
components (e.g. cable, connectors, PCB layout, transceiver,
micro-controller ports) is necessary, to avoid bit asysmmetry.
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Positions and opinions advanced in this paper are those of the author(s) and not necessarily those of SAE International. The author is solely responsible for the content of the paper.