CONFIDENTIAL EE/TEST 2/MAR-JULY 2021/ELE654

FACULTY OF ELECTRICAL ENGINEERING

UiTM, SHAH ALAM
TEST 2

COURSE : ADVANCED DIGITAL DESIGN AND COMPUTER

ARCHITECTURE
COURSE CODE : ELE654
DATE : 16 July 2021
TIME : 1.5 Hrs

INSTRUCTIONS TO CANDIDATES:

1. This test paper consists of 3 questions with a maximum total of 40 marks. Answer ALL
questions.
2. The Estimation Student Answering Time (E-SAT) is also shown for each question.
3. Start answering each question on a new page.
4. Please attach this cover page with your answer script.
Detach this section and submit to DMU, Level 9, FKE
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FILL IN THE FOLLOWING PARTICULARS:

1. Name : ____________________________________________

2. I/D UiTM :

3. Program Code : ____

4. Group : EE_______

5. LECTURER : ____________________________________________

SUBJECT ELE654 TEST 1

QUESTION CO PO MAXIMUM MARKS GRADED MARKS

Q1 1 PO1 5

Q2 2 PO2 10

Q3 1 PO1 15

Q4 1 PO1 10

TOTAL 40

This test paper consists of 3 printed pages

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CONFIDENTIAL EE/TEST 2/MAR-JULY 2021/ELE654

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CONFIDENTIAL EE/TEST 2/MAR-JULY 2021/ELE654

QUESTION 1 (5 Marks)

Let 5BCA0000 be a floating-point number in IEEE format, expressed in hexadecimal.

What is the decimal value of the number?

QUESTION 2 (10 marks)

Consider the following two code snippets. Assume R1 holds i and that R0 holds the
base address of the vals array.

int i; int i;
int vals[200]; int vals[200];
for (i=0; i < 200; i=i+1) for (i=199; i >= 0; i = i-1)
vals[i] = i; vals[i] = i;
(a) (b)

(a) Are the code snippets functionally equivalent?

(b) Write each code snippet using ARM assembly language. Use as few instructions as
possible.
(c) Discuss any advantages or disadvantages of one construct over the other

QUESTION 3 (15 marks)

In this problem , you will modify the single-cycle datapath we build in Lab4 to support LDRB.
The datapath that we will start with is provided in Figure Q2. Your job is to implement the
necessary data and control signals to support LDRB instruction, which we define to have the
following semantics:

LDRB Rd, [Rn, ±Src2] ; Rd ← Mem[Adr]7:0

Mark up a copy of Figure Q2 to indicate the changes to the datapath. Name any new
control signals.

Figure Q2

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CONFIDENTIAL EE/TEST 2/MAR-JULY 2021/ELE654

QUESTION 4 (10 marks)

Suppose a CPU with 32-bit instructions has an instruction cache with block size of 16-
bytes.Addresses refer to bytes in memory. The cache is initially empty. Instructions are then
fetched from the following addresses in order:

0, 4, 8, 92, 96, 100, 4, 8, 12, 16.

a)For each fetch, determine whether the cache hits or misses. Assume no lines are replaced
during execution of the sequence.

b)If you use a direct mapped cache with a cache size of 1 KB and a block size of 8 bytes (2
words), how many sets are in the cache?

End of Questions

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