Name: Muhammad Souban Javaid

Roll No: FA20-BEE-146

Lab report: Digital Logic Design EEE241

Section: BEE-2C

Instructor’s name: Sir Tahir Khan

Dated: 23-02-2021
LAB #01: Introduction to Basic Logic Gate ICs on Digital Logic
Trainer and Proteus Simulation

Part 1: Basic Logic Gate Integrated Circuits (ICs)

Equipment needed:
• KL-31001 Digital Logic Lab
• Logic gates ICs
o 4001 quad 2-input NOR
o 4011 quad 2-input NAND
o 4070 quad 2-input XOR
o 4071 quad 2-input OR
o 4077 quad 2-input XNOR
o 4081 quad 2-input AND
o 4069 Six Inverting Buffer NOT
Procedure:
• Place the ICs on the breadboard.
• Connect pin7 of the IC to the ground terminal.
• Connect pin14 of the IC to the trainer board having 5V DC power supply.
• Use the power supply available at KL-31001 Digital Logic Lab trainer.
• Make connection between the pins of the IC and the combination switches
SW0-SW3
• Select number of possible combinations of inputs using the slide switches.
• Take note of the output with the help of LED for all gate ICs.
• LD0-LD14 located on KL-31001 Digital Logic Lab can also be used.
• Make sure to keep the trainer board off during the setup of circuit as
precaution.
In-lab Task 1:

Lab task 02: Proteus Simulation

Procedure:
• Firstly, open the Proteus application installed in the lab computer.
• Using the ‘new’ menu and create a new project
• Search for a gate and click on it and press enter to select
• Place the gate on the project canvas by clicking on it throught
devices and then clicking on the desired location.
• By opening the p menu again, search for the ‘logic state’ and this
would serve as a virtual power supply.
• Select the logic state , open the p menu again and search for the
‘logic probe'.
 • On the output side of the logic gate, place the logic probe and
connect it to the logic gate by alternatively clicking on the ends of
both the first logic probe’ and the output of the gate.
• Repeat it for the logic state.
• To begin simulation, click on the ‘play’ button.
• Try different combinations by clicking on the switches of the logic
state.
• Take note of the results and try to cross-check for the precision of
the results.
Observations and Calculations:

Post lab questions:.

1. Make a list of the logic gate ICs of TTL family and CMOS family
along the ICs names.
2, What is Fan-In and Fan-out?
Fan-In:
Fan-In is defined as the maximum number of inputs a logic gate can
allow. If the number of inputs are close to this number, the output remains
unknown or inaccurate. It is included in the data sheet and is solely
defined by its manufacturer.
Fan-out:
Fan-out is the maximum number of inputs connected to the gate output
without the usual operation being disturbed. The determination of the Fan-
out is based on the amount of current present at the gate output and the
amount of current needed at every connecting gate input. It is included in
the data sheet and is solely defined by its supplier. If the defined limit is
exceeded then it may be a cause of malfunction as the circuit will be
unable to supply the required power.
Conclusion:
• We have gained the ability to recognize unknown logic gates
by making their respective truth tables via conduction of
experiment and observation.
• We have learned of the TTL and CMOS series ICs.
• We have successfully distinguished and learned about the use
of different ICs.
• We have studied about the connection of different pins on
different ICs.
• We have learned how to use Proteus software to stimulate
logic gates.