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Lab Report: Digital Logic Design EEE241
Lab Report: Digital Logic Design EEE241
Lab Report: Digital Logic Design EEE241
Objectives:
• This lab is devised to simulate and implement any logic function by using universals
gates (NAND/NOR).
• To build the understanding of how to construct any combinational logic function using
NAND or NOR gates only.
Pre-Lab:
Background concept:
Digital circuits are more often constructed with universal gates. The NAND and NOR gates are
called universal gates. Any Boolean logic function can only be implemented using NAND or
NOR gates. NAND and NOR gates are easier to manufacture with electronic components than
basic gates. Due to the prominence of universal gates in the design of digital circuits, rules and
procedures for converting from the Boolean function to the AND, OR and NOT equivalent
NAND and NOR logic diagrams have been developed.
Read the universal gates and understand them. List the truth tables of the gates AND, OR, NOT,
NAND, NOR and XOR. Identify NAND and NOR ICs and their specification for the families of
CMOS and TTL.
Apparatus required:
• KL-31001 Digital Logic Lab
• Logic gates ICs
• Proteus 8 Professional (Circuit simulation software)
In Lab:
There are two parts to this lab. In the first part, simulation and implementation of any logical
expression is done using only NAND gates. In the second part, the same procedure is performed
by using the NOR gates only.
In-Lab Tasks-Part-1
Procedure:
• Simulate NOT, AND and OR gates in Proteus software, using only NOR gates. Verify
their truth tables.
• Now, mount the ICs on the trainer’s breadboard.
• Use one or more of the NOR gates of the IC for this experiment.
• For output indication, connect the output pin of the circuit to any one of the LEDs of the
trainer (L0 to L15).
In-Lab Tasks-Part-2
In-Lab Task 2.1: Verification of NOT function
• Connect the circuit as shown in Figure 2.6.
• Make connection between +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
• By setting the switches to 1 and 0, check that the output (F) of the circuit conforms to the
output of the NOT gate. the Record your observations in Table below.