 Whati

sCMOSTechnol
ogy
?

 WhyNMOSt
echnol
ogyi
spr
efer
redmor
ethanPMOSt
echnol
ogy
?

 Whatar
ethest
epsi
nvol
vedi
nmanuf
act
uri
ngofI
C?

 Whatar
ethepr
ocessesi
nvol
vedi
nphot
oli
thogr
aphy
?

 Whatar
ethest
epsi
nvol
vedi
ntwi
n-t
ubpr
ocess?

 Whati
sLat
ch–up?

 Whatar
etheot
heral
ter
nat
ivesof
twar
eapar
tfr
om xi
l
li
nxusedf
orVLSIdesi
gn?

 Whati
sRTL?

 Whathappenswhent
hePMOSandNMOSar
eint
erchangedwi
thoneanot
heri
nan
i
nver
ter
?

 What
’st
hedi
ff
erencebet
weenTest
ing&Ver
if
icat
ion?

 Expl
ainwhypr
esentVLSIci
rcui
tsuseMOSFETsi
nst
eadofBJTs?

 VHDLst
andsfor“
VHSICHardwareDescr
ipt
ionLanguage.
”VHSIC,i
nturn,st
andsfor
“Ver
yHi
ghSpeedInt
egr
atedCir
cuit
,”whi
chwasaU. S.Depar
tmentofDefensepr
ogram.

  
WhichI
sTheDefaul
tDel
ayI
nVhdl
?
A5:
 
delt
adel
ay.

 Li
stOutTheObjectsOfVhdl?
A7:
 Si
gnal
,Var
iable,Const
ant
.

 Whatcanbet
hevari
oususesofVHDL?
A11:
 
TheVHDLlanguagecanbeusedf
orsev
eral
goal
sli
ke–

 i
)Tosynthesi
zedi git
al ci
rcui
ts
i
i
)Toveri
f yandv ali
datedi gi
tal
designs
i
i
i)Togeneratetestv ectorstotestci
rcui
ts
i
v)Tosi
mul atecircui
ts

 Whatisthediff
erencebetweenConcur rent&Sequent ialSt
atement s?
A13: 
Concurr
entstatementsdefineint
er connect edprocessesandbl ocksthatt
ogether
descri
beadesign’soveral
lbehaviororst r
ucture.Theycanbegr oupedusingblock
stat
ement.Groupsofblockscanal sobepar t i
ti
onedi ntootherblocks.Att
hesamel evel
,
aVHDLcomponentcanbeconnect edt odefinesi gnalswit
hinthebl ocksI
tisarefer
ence
toanentit
yApr ocesscanbeasi nglesignal assignmentst at
ementoraser i
esof
sequenti
alst
atements(SS)Wi t
hinapr ocess, proceduresandf uncti
onscanpar t
it
ionthe
 sequent
ial
stat
ement
s

 Thest
ruct
ural
codef
or4-
bitadderi
sgi
venbel
ow.

 COMPONENTadderI
S
 GENERI
C(n:
INTEGER:
=3)
;
 PORT(
input:
INBI
T_VECTOR(
nDOWNTO0)
;
 out
put:
OUTBI
T_VECTOR(
nDOWNTO0)
);
 ENDCOMPONENT;
 Ifuserwantt
oconv
ertt
hisi
nan8bi
tadder
,whi
choft
hef
oll
owi
ngv
ari
abl
eshoul
dbe
changed?
a)n
b)i
nput
c)output
d)component

 
WhatDoWeNeedToGenerat
eHar
dwar
eFr
om Vhdl
Model
?
A9:
 
Weneedf
oll
owi
ngtool
s

 Si
mulati
ontool.
 Synt
hesi
stool.
 I
mplementati
ontool
.


 Tel
lmesomeofconst
rai
ntsy
ouusedandt
hei
rpur
posedur
ingy
ourdesi
gn?

Therear elotofconst raintsandwi l

l varyfortooltotool,
Iam li
stingsomeofXi l
i
nx
const r
aints
a)Tr anslateonandTr ansl ateof f
: t
heVer i
logcodebet weenTransl at
eonandTr ansl
ate
offisignoredf orsynthesi s.
b)CLOCK_ SIGNAL: isasy nt hesisconst rai
nt.Inthecasewher eacl ocksignalgoes
throughcombi natori
al l
ogi cbef orebei ngconnect edtotheclocki nputofafli
p-f
lop,XST
cannoti dentif
ywhati nputpi nori nternalnetisther eal
clocksignal.Thisconstr
aint
all
owsy out odefinethecl ocknet .
c)XOR_ COLLAPSE: i
ssy nt hesisconst r
aint.I
tcont r
olswhethercascadedXORsshoul d
becol lapsedintoasi ngleXOR.
Formor econst r
aintsdet aileddescr ipti
onr efert
oconst rai
ntguide.


Supposeforapieceofcodeequiv
alentgat
ecounti
s600andforanothercode
equi
valentgat
ecountis50,
000willthesi
zeofbi
tmapchange?
inotherwordswil
lsi
zeof
bi
tmapchangei tgat
ecountchange?
Thesizeofbi
tmapi
si r
respect
iveofr
esour
ceuti
li
zati
on,
iti
sal
way
sthesame,
for
Spar
tanxc3s5000i
tis1.56MBandwi l
lnev
erchange.

Whatar
ediff
erentty
pesofFPGAprogr
ammi
ngmodes?
whatar
eyoucur
rent
lyusi
ng
?howtochangefrom onet
oanot
her?

Beforepoweringont heFPGA, confi

gurati
ondataisstoredexter
nall
yinaPROM orsome
othernonvol
at i
l
emedi um eit
heronorof ftheboar
d.Af t
erapplyi
ngpower,t
he
confi
gurati
ondat ai
swr it
tentotheFPGAusi nganyoff i
v edi
ff
erentmodes:Master
Parall
el,
SlaveParal
lel,
Mast erSeri
al,
SlaveSeri
al,
andBoundar yScan(JTAG).The
MasterandSl aveParall
elmodes
Modesel ect
ingpinscanbesett oselectthemode, r
eferdatasheetforf
urt
herdetai
ls.

Tel
lmesomeoff
eat
uresofFPGAy
ouar
ecur
rent
lyusi
ng?

Iam t
aki
ngexampl
eofxc3s5000t
oanswer
ingt
hequest
ion.

Veryl owcost , high-per for mancel ogicsoluti

onfor
hi
gh- vol ume, consumer -
or ientedappl icati
ons
-Densi tiesashi ghas74, 880l ogi ccel l
s
-Upt o784I /Opi ns
-622Mb/ sdat at ransf err ateperI /O
-18si ngl e-endedsi gnal standar ds
-6di fferent i
al I
/ Ost andar dsi ncludingLVDS, RSDS
-Ter mi nationbyDi gitall
yCont roll
edI mpedance
-Signal swingr angingf r
om 1. 14Vt o3. 45V
-Doubl eDat aRat e( DDR)suppor t
•Logi cr esour ces
-Abundantl ogiccel l
swi thshi ftr egistercapabi
li
ty
-Wi demul tipl
exer s
-Fastl ook- aheadcar rylogi c
-Dedi cat ed18x18mul tipli
er s
-Upt o1, 872Kbi tsoft otal blockRAM
-Upt o520Kbi tsoft ot al distributedRAM
•Digital ClockManager( upt of ourDCMs)
-Clockskewel imi nation
•Eightgl obalcl ockl inesandabundantr outi
ng

Cany
oul
i
stoutsomeofsy
nthesi
zabl
eandnonsy
nthesi
zabl
econst
ruct
s?

notsynt
hesizabl
e->>>>
i
nit
ial
i
gnoredforsynthesi
s.
delays
i
gnor edforsy nthesi
s.
events
notsuppor ted.
real
Real datatypenotsuppor ted.
ti
me
Timedat at ypenotsuppor ted.
forceandr elease
Forceandr el
easeofdat aty pesnotsuppor
ted.
forkjoin
Usenonbl ockingassi gnment stogetsameeffect
.
userdef i
nedpr imiti
ves
Onlygat elevelprimit
ivesaresupported.

synt
hesi
zabl
econstr
uct
s->>
assi
gn,
forl
oop,
GateLev
el Pr
imi
ti
ves,
repeatwi
thconst
antv
alue.
..

Di
ff
erencebet
weenFPGAandCPLD?

FPGA:
a)SRAM basedtechnol
ogy.
b)Segmentedconnecti
onbetweenelements.
c)Usual
lyusedforcomplexl
ogiccir
cui
ts.
d)Mustbereprogrammedoncet hepowerisoff
.
e)Costl
y

CPLD:
a)
FlashorEPROM basedt echnol
ogy.
b)
Continuousconnectionbetweenelements.
c)
Usuallyusedforsi
mpl erormoderatel
ycomplexl
ogicci
rcui
ts.
d)
Neednotber eprogrammedoncet hepowerisof
f.
e)
Cheaper

Whatar
edcm'
s?whyt
heyar
eused?

Digi
talcl
ockmanager( DCM)isaf ull
ydigi
talcontr
olsyst
em that
usesfeedbacktomai nt
aincl
ocksi gnal
character
ist
icswitha
highdegreeofpreci
siondespit
enor malvari
ati
onsinoperati
ng
temperat
ureandv ol
tage.
Thatiscl
ockoutputofDCM i sstableoverwiderangeoftemperat
ureandv
olt
age,
and
al
soskewassoci
atedwi
thDCM i
smi ni
malandallphasesofi
nputcl
ockcanbeobt
ained
.Theout
putofDCM comingf
orm gl
obalbuf
fercanhandlemorel
oad.

whati
ssl
i
ce,
cl
b,l
ut?

Iam t
aki
ngexampl
eofxc3s500t
oanswert
hisquest
ion

TheConf i
gur
ableLogicBlocks(CLBs)const
itut
ethemai nlogi
cresourcefor
i
mpl ementi
ngsynchronousaswel lascombinat
ori
al ci
rcui
ts.
CLBar econf
igur
ablelogi
cblocksandcanbeconf iguredtocombo,ram orrom
dependingoncodingstyl
e
CLBconsistof4slicesandeachsliceconsi
stoftwo4- i
nputLUT(lookupt abl
e)F-
LUT
andG-LUT.

Canacl
bconf
igur
edasr
am?

YES.

Thememoryassignmenti
saclockedbehav
ior
alassignment
,Readsfr
om t
hememory
areasy
nchr
onous,Andall
theaddressl
i
nesaresharedbythereadandwr
it
est
atement
s.

Whati
spur
poseofaconst
rai
ntf
il
ewhati
sit
sext
ensi
on?

TheUCFf il
eisanASCI If
il
especi
fyingconstr
aintsont helogicaldesi
gn.Youcreatethi
s
fi
l
eandent eryourconstr
aint
sinthef i
l
ewithat exteditor
.Youcanal sousetheXi l
i
nx
Constrai
ntsEdi
tortocreat
econstraint
swithi
naUCF( extent
ion)fil
e.Theseconstr
aints
aff
ecthowt helogi
caldesi
gnisimplementedint hetargetdev i
ce.Youcanuset hefi
leto
overr
ideconstr
aint
sspecifi
edduri
ngdesignent ry.

Howmanygl
obal
buf
fer
sar
ether
einy
ourcur
rentf
pga,
whati
sthei
rsi
gni
fi
cance?

Thereare8oft hem i
nxc3s5000
Anexternalclocksourceenter
st heFPGAusi ngaGl obalClockI
nputBuf f
er(I
BUFG)
,
whichdirect
lyaccessestheglobalclocknetworkoranI nputBuff
er(IBUF).Cl
ocksi
gnal
s
withi
ntheFPGAdr i
veaglobalclocknetusingaGl obalClockMultipl
exerBuff
er
(BUFGMUX) .Theglobalclocknetconnectsdirect
lytotheCLKI Ninput.

Whyi
smap-
ti
mingopt
ionused?

Timi
ng-dr
ivenpacki
ngandpl
acementisrecommendedt
oimpr
ovedesi
gnper
for
mance,
ti
ming,
andpackingforhi
ghl
yuti
l
izeddesigns.

Whatar
edi
ff
erentt
ypesoft
imi
ngv
eri
fi
cat
ions?
Dynami ctimi ng:
a.Thedesi gnissi mulat edinf ull
t i
mingmode.
b.Notal lpossibi l
i
t i
est estedasi tisdependentont heinputtestv
ector s.
c.Si
mul ationsi nf ull
timi ngmodear eslowandr equirealotofmemor y.
d.Bestmet hodt ocheckasy nchr onousi nter
facesori nter
facesbetweendi ff
erentt
imi
ng
domai ns.
Stat
ict i
mi ng:
a.Thedel ay sov erallpat hsar eaddedup.
b.Allpossi bi
lit
ies, i
ncludingf alsepat hs,veri
fi
edwi thouttheneedf ortestvector
s.
c.Muchf ast erthansi mul at
ions,hour sasopposedt odays.
d.Notgoodwi thasy nchr onousi nterfacesori nt
erfacesbet weendiff
erenttiming
domai ns.

Suggestsomeway
stoi
ncr
easecl
ockf
requency
?

·Checkcr
it
ical
pathandopt i
mizeit
.
·Addmoretimingconstr
aint
s(overconst
rai
n).
·pi
peli
net
hear chi
tect
uretothemaxpossibl
eextentkeepi
ngi
nmi
ndl
atencyr
eq'
s.

Whati
sDFT?

DFTmeansdesi gnfortestabili
ty.'
DesignforTestorTest abili
ty'-amet hodologythat
ensuresadesi gnwor kspr oper l
yaft
ermanuf acturi
ng, whi
chl aterfacili
tat
esthefail
ure
analy
sisandf alseproduct /piecedetecti
on
Otherthanthef uncti
onal logic,
youneedt oaddsomeDFTl ogiciny ourdesign.
Thiswil
l
helpyouintest i
ngthechi pf ormanuf act
uri
ngdef ectsafteritcomef rom fab.
Scan,MBIST,LBIST,I
DDQt estingetcareallpartofthis.(t
hisisahotf i
eldandwi t
hlotsof
opportuni
ti
es)

TherearetwomajorFPGAcompanies:Xi
li
nxandAl
ter
a.Xil
inxtendstopromotei
tshar
d
processorcor
esandAlt
erat
endstopromoteit
ssof
tprocessorcores.Whati
sthe
di
fferencebet
weenahardpr
ocessorcoreandasof
tprocessorcore?

Ahar dprocessorcoreisapre-desi
gnedblockthati
sembeddedont othedevice.I
nthe
Xil
inxVirt
exII-
Pro,someoft helogi
cblockshavebeenr emov ed,andthespacet hatwas
usedf ort
heselogicblocksi
susedt oimplementapr ocessor.TheAlteraNios,onthe
otherhand,isadesignthatcanbecompi ledt
ot henormal FPGAl ogi
c.

Thecont
aminationdelayofthedatapat
hinasequenti
alci
rcuiti
scri
ti
cal
fort
hehol
d
ti
meatthefli
pflopwher ei
tisexi
ti
ng,i
nthi
scaseR2.
mathemati
call
y,th(R2)<=t
cd(R1)+tcd(
CL2)
Contami
nati
ondel ayisal
socall
edtminandPropagat
iondelayisal
socal
ledt
maxin
 manydat
asheet
s.

Whenar
eDFTandFor
mal
ver
if
icat
ionused?

DFT:
·manufactur
ingdefectsli
kest
uckat"
0"or"1"
.
·t
estforsetofrul
esf ol
loweddur
ingt
heini
ti
aldesi
gnst
age.

Formalveri
fi
cat
ion:
·Veri
fi
cati
onoftheoper
ati
onofthedesi
gn,i
.e,
toseei
fthedesi
gnfol
l
owsspec.
·gatenetl
i
st==RTL?
·usi
ngmat hemati
csandst
ati
sti
calanal
ysi
stocheckf
orequi
val
ence.

Whati
sSy
nthesi
s?

Synthesisisthestageinthedesignf l
owwhi chisconcer nedwi t
ht r
anslat
ingyourVeri
log
codeintogat es-andthat'
sput t
ingitverysimply
!Firstofal l
,theVer i
logmustbewr it
ten
i
napar t
icularwayforthesynthesistoolthaty
ouareusi ng.Ofcour se,asy nt
hesi
stool
doesn'tactuall
yproducegates-i twil
loutputanetl
i
stoft hedesi gnthatyouhav e
synthesi
sedt hatrepr
esentsthechi pwhichcanbef abricatedt hroughanASI CorFPGA
vendor.

Thestr
uctur
alcodef
or4-
bitadderi
s
gi
venbel
ow.
COMPONENTadderIS
GENERIC(n:
INTEGER:=3)
;
PORT(i
nput : I N BI T_VECTOR(
n
 DOWNTO0) ;
output:OUT BI
T_VECTOR(
nDOWNTO
0))
;
ENDCOMPONENT;