By TIM MCDONALD, Senior Advisor to CoolGaN
Technology Development at Infineon Technologies
Can Silicon Qualification
Standards be Applied
to GaN HEMT Power
Converters?
The industry needs a robust qualification strategy that allows manufacturers to
demonstrate their devices can provide a high level of reliability. Infineon came up with
a four-stage plan.
T
he end markets serviced by the semiconductor indus-
try are rapidly adopting power semiconductor devices
based on wide-bandgap (WBG) semiconductors,
including silicon carbide (SiC) and gallium nitride on
silicon (GaN-on-Si). Initially, much of the effort from manu-
facturers using GaN materials has been in the development of
high-electron-mobility transistors (HEMTs) for RF applica-
tions such as radar.
More recently GaN-on-Si HEMT technology has been de-
veloped for power-conversion applications. This new class of
power transistor delivers significant efficiency gains over ex-
isting Si power MOSFETs. This has direct benefits in terms of
the total cost of ownership for power conversion. GaN devices
are already employed in such applications and are being used
today in front-end PFC circuits in telecom rectifier systems.
Furthermore, GaN enables higher power density; therefore,
conversion solutions can be physically smaller. This is particu-
larly important in certain application areas such as network-
ing and data communications, where users seek to add extra
features (e.g., backup battery power) without sacrificing other
performance in a fixed server rack space.
In short, HEMTs can be beneficial in any application where
power conversion takes place at a relatively high voltage, in-
cluding ac-ac, ac-dc, and dc-dc. GaN technology is applicable
in a diverse range of applications, from data center and tele-
com, to wireless power, motor control, and audio. The sup-
ply chains in these markets have matured to the point that
it becomes vital for the semiconductor industry to be able to
deliver power transistors based on new technology (such as
GaN HEMTs) that are (system-) cost-effective and just as reli-
☞ LEARN MORE @ electronicdesign.com |
able as silicon-based power MOSFETs.
Infineon, a manufacturer of GaN HEMTs called the Cool-
GaN product family, gives insight into its qualification meth-
od that serves as a benchmark and provides the baseline for
industry qualification standards.
The Need for a GaN Qualification Plan
The industry has been manufacturing silicon-based devices
and perfecting the qualification processes involved for more
than 50 years. By comparison, GaN HEMT production is still
nascent, with relatively scarce historical test data. While some
manufacturers now promote their GaN-on-Si devices as being
JEDEC (Joint Electron Device Engineering Council) or AEC
Q101 qualified, presently these standards are based on silicon
device requirements.
Accordingly, JEDEC has established the JC-70 Wide Band-
gap Power Electronic Conversion Semiconductor committee
to define how the industry at large should address this gap
in common qualification standards. JC-70 contains two sub-
committees: JC-70.1 for GaN and JC-70.2 for SiC. JC-70.1 has
recently published its first guideline (JEP173 at www.JEDEC.
org).
Si vs. GaN
To better understand the possible risks of using qualifica-
tion standards established for silicon devices, it’s informative
to study the differences between Si and GaN device structures
and materials and the related qualification tests.
Consider the structure of a SJ MOSFET (Fig. 1a), which
shows the source, gate, and drain terminals. During normal
1
operation, electrons flow vertically from source to drain,
thanks to an inversion of the channel from p-type to n-type.
This is caused by applying a sufficiently high voltage across the
gate dielectric, as shown by the red arrow.
In this diagram, the area indicated by the number 1 shows
the p-n body diode, which is stressed during high-tempera-
ture reverse-bias (HTRB) testing. The area near the number
2 shows the gate oxide, which is stressed by high-temperature
gate-bias (HTGB) testing. The area near the number 3 repre-
sents device edge passivation and molding compound, which
are stressed during temperature cycling and temperature/
humidity/bias testing (THB). The area near the number 4 in-
dicates that top-layer source aluminum and bond wires are
stressed during high-temperature operating life.
When we compare this structure to that of the GaN HEMT
(Fig. 1b), which has a horizontal structure with lateral current
flow, it’s clear that there are significant differences. Perhaps
most fundamentally is the formation of the two-dimensional
electron gas that forms between the aluminium-gallium-
nitride layer (AlGaN) and the GaN layer. The GaN HEMT
has no p-n drain to source body diode (number 1 in Fig. 1a).
There’s no gate dielectric (number 2 in Fig. 1a). For a typical
GaN HEMT, the field terminates at the surface and in mul-
tiple locations across the surface, as opposed to the Si SJ FET
where the high field terminates at the surface only at the edge
of the device (number 3 in Fig. 1a).
Because of these differences, Infineon developed exten-
sions to the standard qualification plan to better stress test
its CoolGaN family of GaN-on-Si HEMT devices, which
target high-voltage power management and conversion ap-
plications. Space prevents a full description (consult www.
infineon.com/gan, “whitepaper” for a complete discussion),
but what follows is a brief summary of the qualification meth-
odology that the company employs for these devices.
Qualifying GaN
To comprehend the device and structure differences out-
lined above, the qualification approach developed by Infineon
involves a four-stage plan (Fig. 2). This includes an applica-
☞ LEARN MORE @ electronicdesign.com |
tion profile, a quality requirement profile, reliability investiga-
tions, and degradation models. These stages are described in
brief, below.
First, the application profile defines how the device will op-
erate and be stressed in a given application. This sets the ex-
pectations based on the end-market and gives the GaN device
manufacturer a clear indication of what needs to be delivered.
Through close cooperation with lead customers, the param-
eters for a specific application or category of applications can
be defined.
The second stage determines quality requirements for the
application, which will include the maximum cumulative
failure rate and parametric drift limits, as well as moisture-
sensitivity-level rating. The example on which Infineon based
its initial CoolGaN qualification is the external environment
telecom rectifier, where a 15-year lifetime is required with a
failure rate of 1 per billion device-hours (1 FIT). Other ap-
plications may have different target lifetimes and failure rates.
The third element is a comprehensive study of the GaN
devices’ reliability failure mechanisms. In particular, failure
modes must be characterized into two groups. “Intrinsics” are
failures caused by inherent wearout of the device materials
1. Illustrated are the cross-
section of a silicon MOSFET
showing a vertical current
path (a) and the cross-section
of a GaN HEMT showing lat-
eral current flow (b).
2

and structures, while “extrinsics” fail earlier and arise from de-
fects or processing variation. The investigations are complete
when an improvement path is identified to eliminate or reduce
extrinsics.
Figure 3 shows a plot that identifies fraction of failure versus
time. An example of a Weibull plot that’s commonly used in
studying failure behavior for reliability, it’s particularly useful
to sort intrinsic from extrinsic failures, as shown.
Degradation models—the fourth part of the qualification
plan—allow users to predict failure rates under real applica-
☞ LEARN MORE @ electronicdesign.com |
2. The GaN Qualifica-
tion Plan developed by
Infineon for its Cool-
GaN family of HEMT
power devices.
tion stress conditions over the intended lifetime. Such models
are generated based on accelerated test to failure data: Devices
operate under stress well beyond designed use conditions to
force failure to occur at much shorter times (tens or hundreds
of hours) as compared to an expected 15 years of target life-
time.
Testing multiple groups of samples at varying stress condi-
tions allows for extraction of a mathematical model that can
provide the required predicted failure rate at a much longer
duration of operation under less stressful, normal use condi-
tions.
GaN Failure Modes
Several failure modes are docu-
mented for GaN HEMTs that either
don’t apply to silicon power devices
or elicit a more sensitive response
from GaN devices than from devices
fabricated from silicon. These failure
modes may represent a potentially
high risk of failure during use if not
properly accounted for during device/
technology qualification.
Such failure modes include dc bias
degradation, repetitive (hard) switch-
ing failure (DHTOL), temperature hu-
midity and bias, and dynamic RDS(ON).
3. Here’s a Weibull plot showing fraction
(%) of failed devices versus time. Extrinsic
failures fail earlier than intrinsic failures.
3
4. A Weibull plot and model extraction for dc bias failure mode.

For the sake of brevity, we will focus on one of the four failure pose user risk if not properly accounted for during technology
modes as an illustrative example; interested readers can ex- development and device qualification. The industry needs a
plore details of the other three by consulting the Infineon re- robust qualification plan that allows manufacturers to demon-
liability white paper (www.infineon.com/gan, “whitepaper”). strate that their devices can provide a high level of reliability.
One failure mechanism that applies to GaN HEMTs but not Infineon has qualified its CoolGaN GaN-on-Si devices fol-
to silicon devices is dc bias degradation. While silicon devices lowing a four-stage method that models device failure behavior
are also prone to dc bias failure, resulting in the need to per- against stresses during application. Detailed application stress
form HTRB stress testing, GaN HEMTs exhibit a failure rate conditions were established, including target lifetime and reli-
that depends strongly on both voltage and temperature when ability. Extensive reliability investigations illuminated extrinsic
tested at accelerated voltage and temperature conditions. and intrinsic failure mechanisms and blazed a path to improv-
The Weibull plot shown in Figure 4 demonstrates the ac- ing device robustness. Finally, degradation models enable the
celerated stress time to failure data with dc bias and tempera- projection of failure rates based on accelerated testing.
ture stress applied to samples of Infineon’s 190-mΩ CoolGaN
600-V e-mode HEMTs at varying voltage and temperature.
The failure time responds to both voltage and temperature,
with very sensitive voltage dependence. Silicon devices don’t
behave in this manner.
Note the data shows linear behavior on a logarithmic plot.
We can therefore utilize a model for fractional failure in time,
F(t), using an equation of the form shown in the purple box.
The equation F(t) has an exponential dependence on both
voltage and (1/T); the constants γ and Ea can be extracted
from the plot in Figure 4.

Conclusion
GaN-on-Si wide bandgap devices are now available, and
they make it possible to achieve higher levels of efficiency
and density in power-conversion applications. However, these
new materials and device structures behave differently from
their silicon-based counterparts with failure mechanisms that

☞ LEARN MORE @ electronicdesign.com | 4