Name:

HARSH MALPANI…………………………………………………………………………………………………………………………..

Affiliation (Institution/Company):

Birla Institute of technology Mesra…………………………………………………………………………………….

Email: hmalpani5@gmail.com………………………………………………………………

Phone: 9110012673…………………………………………………….

Title of Internship Program Undertaken:

Design and verification using verilog ………………………………………………………………………………

Assignment No and Title

1 Verification using Verilog ………………………………………………………………………………………………………….

Important Instructions:
1) All assignment results should be computer screenshot or computer typed. Handwritten and
scanned copies shall not be considered for evaluation
2) Due date for all assignment submission is 1 Week from the last date of internship
3) All assignment questions should be captured along with solutions/answers.
4) Code snippets, simulation results should be captured properly
5) Use only the JPEG image format for capturing the simulation results and name/label the results
appropriately.
6) The description of answers should be short and crisp. Provide only the required information,
answered copied or cut and pasted from google shall not be considered.

PRIVATE & CONFIDENTIAL

Entuple Technologies and/or Excel VLSI Technologies
SHIFT REGISTER
module shiftregister ( d1,d2, ld ,clk,a,b,sum);

input [3:0]d1,d2 ;

input clk ,ld,sum;

output reg [3:0]a,b;

always@(posedge clk)

begin

if(ld)

begin

a<=d1;

b<=d2;

end

else

begin

a<=a>>1;

a[3]<=sum;

b<=b>>1;

b[3]<=b[0];

end

end

endmodule

FULL ADDER
module fulladder( a ,b,cin,sum,cout);

input a,b,cin;

output sum,cout;

assign { cout,sum}=a+b+cin;

Endmodule

PRIVATE & CONFIDENTIAL

Entuple Technologies and/or Excel VLSI Technologies
D-FLIP FLOP
module dff( clk , in , out);

input clk,in ;

output out;

reg out;

always@(posedge clk )

begin

out<=in;

end

endmodule

SERIAL ADDER MAIN MODULE

module serialadder(d1,d2,ld,clk,sum,cout);

input [3:0]d1,d2;

input ld,clk;

output cout,sum;

wire cin;

wire [3:0]a,b ;

shiftregister A( d1,d2, ld ,clk,a,b,sum);

Dff B(clk,cout,cin);

fulladder C( a ,b,cin,sum,cout);

endmodule

TEST BENCH
module bit4serialadd_tb;

reg [3:0]d1,d2;

reg clk,ld;

wire cout,sum;

PRIVATE & CONFIDENTIAL

Entuple Technologies and/or Excel VLSI Technologies
serialadder DUT(d1,d2,clk,ld,sum,cout);

initial

begin

clk=1'b0;

ld=1'b0;

end

always #5 clk=~clk;

initial

begin

ld=1'b1;

d1=4'b1111;

d2=4'b1111;

#10 ld=1'b0;

end

initial

$monitor($time," sum=%b cout=%b cin=%b A=%b B=%b",sum,cout,DUT.cin,DUT.a,DUT.b);

endmodule

# 0 sum=x cout=x cin=x A=xxxx B=xxxx

# 5 sum=0 cout=0 cin=x A=0000 B=0000

# 6 sum=0 cout=0 cin=0 A=0000 B=0000

# 15 sum=0 cout=0 cin=0 A=1010 B=1010

# 25 sum=0 cout=0 cin=0 A=0101 B=0101

# 35 sum=0 cout=1 cin=0 A=0010 B=1010

# 36 sum=0 cout=1 cin=1 A=0010 B=1010

# 45 sum=1 cout=0 cin=1 A=0001 B=0101

# 46 sum=1 cout=0 cin=0 A=0001 B=0101

PRIVATE & CONFIDENTIAL

Entuple Technologies and/or Excel VLSI Technologies
# 55 sum=0 cout=1 cin=0 A=1000 B=1010

# 56 sum=0 cout=1 cin=1 A=1000 B=1010

PRIVATE & CONFIDENTIAL

Entuple Technologies and/or Excel VLSI Technologies
 USER SPACE

PRIVATE & CONFIDENTIAL

Entuple Technologies and/or Excel VLSI Technologies
 USER SPACE

PRIVATE & CONFIDENTIAL

Entuple Technologies and/or Excel VLSI Technologies
 USER SPACE

PRIVATE & CONFIDENTIAL

Entuple Technologies and/or Excel VLSI Technologies