International Journal of Pure and Applied Mathematics

Volume 119 No. 16 2018, 1225-1229

ISSN: 1314-3395 (on-line version)
url: http://www.acadpubl.eu/hub/
Special Issue
http://www.acadpubl.eu/hub/

AREA AND POWER EFFICIENT IMAGE RETRIEVAL USING PULSED REGISTERS

IN VRC
Krishnaveni+ Dr.B.Rajan, Sakthivel Raja
+
Research Scholar, St Peters University
Senior Web Designer, ZOHO Corporation, Chennai.

ABSTRACT functions used are given in Table 1. All these major

In this paper, a area and power efficient VRC for activities require registers.
image retrieval is proposed. The VRC reconfigures
itself many times and process the whole image again
and again until the Mean Difference Per Pixel Genetic Algorithm
(MDPP) is in acceptable range. Hence the power
optimization plays a major role towards multiple Configuration Word
factors such as Lifetime of the component, reducing
fault, lowering thermal effect etc…, We propose the In1
use of pulsed registers for the logical operators in 25 In2
PE1 PE5 PE21
processing elements (PE’s) VRC. The proposed
architecture reduces the area by 30% and power by In3
38%. In4 PE2 PE6 PE22
PE25
Keywords: Genetic Algorithm, Virtual In5
PE3 PE7 PE23
Reconfigurable Circuit, Image Retrieval, Evolvable In6
Hardware.
In7
In8 PE4 PE8 PE24
INTORDUCTION

The image processing has a vast area of Figure 1. Architecture of VRC

applications, almost in all fields virtually. The recent
developments in image processing include using Table 1: 13 functions of PE
Generic Algorithm (GA) for Reconfiguring Function Code Function
Architecture. Most researchers concentrates on the F0: 0000 X << 1
number of operator, providing fault tolerant, finding
optimization parameter, limit cycles etc…, The other
F1: 0001 ~X
factors which are as important as others is Area and F2: 0010 X|Y
Power. The number of cycles it process or F3: 0011 X^Y
components used to process a image is very high. F4: 0100 (X+Y) >> 2
Therefore thermal breakdowns are more common. As
F5: 0101 (X+Y) >> 1
the quality of the image increases the size of the
registers or word-length of the registers also increases F6: 0110 X & “F0”
in processing. Hence area and power reduction F7: 0111 X | “F0”
becomes vital. F8: 1000 X | “0F”
F9: 1001 Min (X,Y)
GENERAL ARCHITECTURE OF VRC F10: 1010 Max (X,Y)
We have used the 13 function VRC for our
F11: 1011 X >> 1
testing. The Generic Algorithm (GA) [1] decides the F12: 1100 X+Y
functions to be selected and their corresponding input
output flow. The architecture is shown in Figure 1. PROPOSED ARCHITECTURE
The GA generates the configuration words which The block diagram of the existing [3] and
contain the name of the function to be used and their proposed architecture is given in Figure 3 and Figure
corresponding input output flow. The VRC[2] is 4. In GA based EHW (Evolvable Hardware), the
configured based on this configuration word. The number of registers used for processing is
whole image is processed pixel by pixel again and comparatively high. All the registers have been
again until the condition is satisfied. The various replaced with pulsed registers. The single clock pulse

1225
International Journal of Pure and Applied Mathematics Special Issue

replaced with series of pulse [4] (pulsed registers)

provides better management towards pipelined
architecture with reduced response time. We have
used 13 functions VRC [5] with 25 processing
……..
elements. The proposed and existing architecture of
the register is given in figure 1 and figure 2. [6]
discussed about a system, a low power area reduced Processing elements
and speed improved serial type daisy chain memory
register also known as shift Register is proposed by
using modified clock generator circuit and SSASPL
(Static differential Sense Amplifier based Shared
Pulsed Latch). This latch based shift register
consumes low area and low power than other latches. Clock GA
There is a modified complementary pass logic based
generator
4 bit clock pulse generator with low power and low
area is proposed that generates small clock pulses
with small pulse width. These pulses are given to the
conventional shift register that results high speed. Figure 4. Existing architecture
The system is designed by the Cadence virtuoso 180
nm technology. The Maximum supply voltage for the
system, clock source and input source are 1.8V. The
complementary pass logic based proposed system ……..
reduces the area about 7% for the total system and
about 23% for the 4 bit clock pulse generator circuit. Processing elements
The Power is reduced by 26% than the conventional
system. The speed is improved about 7% than the
existing system.

Pulse GA
generator

Figure 5. Proposed architecture

SIMULATION RESULTS

System Considerations

Figure 2: Regular Register Parameter Used

Images : IEEE Test Image
Functions Used : 13 Function VRC
Noise Model : Gaussian Noise
Filter : Median Filter

The Power and area comparison graph is given in

figure 6 and Figure 7. It is evident that from the
figures the area and power consumed by VRC with
pulsed registers has decreased by 30% and 38%
respectively.

Figure 3: Pulsed Register

1226
International Journal of Pure and Applied Mathematics Special Issue

The filters are implemented in Evolvable Hardware

(EHW) and analysis is studied. The net-list is
compared with the existing architecture, i.e. without
pulsed registers Figure 2 and with pulsed registers
Figure 3. The application of the proposed VRC setup
functioning as Gaussian noise removal filter is
studied and compared in Table 3 and Table 4 with the
parameters as Mean Square Error (MSE) and Mean
Difference Per Pixel (MDPP)[7]. The MDPP is used
as evaluator module as it is easier for hardware
architecture than the calculation of PSNR. The fitness
function using MDPP is given by equation

1
MDPP  𝑁
𝑖,𝑗 =1 |orig i, j − filt i, j |
𝑁𝑥𝑁
Figure 6. Area Consumption Comparison
Where orig i, j − filt i, j is the absolute difference
between the original and filtered images.

Table 3. Comparison of Mean Square Error value

Image Variance Existing[7] Proposed
Chemical
0.006 21.08 21.11
Plant
Man 0.009 23.14 23.10
Moon 0.01 20.98 20.95

Table 4. Comparison of MDPP Values

Figure 7. Power Consumption Comparison Varian Existing Propose

Image [7] d
ce
Chemical
0.006 143152 143400
The decrease in response time to the input due to Plant
efficient implementation of pipelined architecture
Man 0.009 180606 180532
using pulsed registers is shown in Table 2.
Moon 0.01 143384 143290

Table 2. Comparison of Processing Time. From the table it’s clear that the MSE or the MDPP
Components Processing Time (Sec) has not degraded due to the proposed change. Instead
CLB’s FF’s Existing[7] Proposed for the same value, the area and power reduced,
considerable increase in speed is achieved by the
563 286 5.376 4.125 pulsed register (Proposed) architecture.
6.726
1200 551 8.496 CONCLUSION
6.786 In this paper, implementation of pulsed register to
1213 732 8.598 reduce area and power consumption and to increase
6.921 the speed considerably has been presented. The
1226 766 8.756 results is been compared with the existing method.
6.992 The result shows the reduction of area by 30% and
1290 799 9.040
power consumption by 38%.
7.085
1301 832 9.276

1227
International Journal of Pure and Applied Mathematics Special Issue

REFERENCE
[1] P. Reyes, P. Reviriego, J. A. Maestro, O.
Ruano,“New protection techniques against SEUs for
moving average filters in a radiation
environment,”IEEE Trans. Nucl. Sci., Vol. 54, No. 4,
pp. 957–964, Aug.2007.
[2] V. Stojanovic, V. Oklobdzija,“Comparative
analysis of masterslavelatches and flip-flops for high-
performance and low-power systems”, IEEE J. Solid-
State Circuits, Vol. 34, No. 4, pp. 536–548, Apr.
1999.
[3] M. Hatamianet al.,“Design considerations for
gigabit ethernet 1000base-T twisted pair
transceivers,” Proc. IEEE Custom Integr.
CircuitsConf., pp. 335–342, 1998.
[4] H. Yamasaki, T. Shibata,“A real-time image-
featureextraction and vector-generation vlsi
employing arrayedshift-register architecture,” IEEE J.
Solid-State Circuits, Vol. 42, No. 9, pp. 2046–2053,
Sept. 2007.
[5] H.-S. Kim, J.-H.Yang, S.-H.Park, S.-T.Ryu, G.-H.
Cho, “A 10-bitcolumn-driver IC with parasitic-
insensitive iterative charge-sharing based capacitor-
string interpolation for mobile active-matrix LCDs,”
IEEE J. Solid-State Circuits, Vol. 49, No. 3, pp. 766–
782, Mar. 2014.
[6] Christo Ananth, S. Dinesh, "Area power and
speed optimized serial type daisy chain memory
using modified CPG with SSASPL," 2015
International Conference on Control, Instrumentation,
Communication and Computational Technologies
(ICCICCT), Kumaracoil, India, IEEE Data retrieved
from
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnu
mber=7475302&isnumber=7475237 2015, pp. 344-
349.
[7] “Self Healing Evolvable Hardware Architecture
on FPGA Platform for On-Chip Adaptive Image
Processing” Thesis by B.Rajan, Dr.S.Ravi, April
2009
[8] S. Heo, R. Krashinsky, K. Asanovic,“Activity-
sensitive flipflopand latch selection for reduced
energy,” IEEE Trans. Very Large Scale Integr.
(VLSI) Syst., Vol. 15, No. 9, pp. 1060–1064, Sep.
2007.
[9] S. Naffziger, G. Hammond,“The implementation
of the nextgeneration64 b itanium microprocessor,”
In IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig.
Tech. Papers, Feb. 2002, pp. 276–504.

1228
1229
1230