Unit-1 Introduction

 Functional units of digital system and their interconnections

 Buses, bus architecture

 Types of buses

 Bus arbitration

 Register, bus and memory transfer

 Processor organization

o general registers organization

o stack organization
o addressing modes
Digital Computer: A digital computer can be defined as a programmable machine which reads
the binary data passed as instructions, processes this binary data, and displays a calculated digital
output. Therefore, Digital computers are those that work on the digital data.

Various Functional units

 Input Unit : The input unit consists of input devices that are attached to the computer.
These devices take input and convert it into binary language that the computer understands.
Some of the common input devices are keyboard, mouse, joystick, scanner etc.
 Central Processing Unit (CPU0 : Once the information is entered into the computer by
the input device, the processor processes it. The CPU is called the brain of the computer
because it is the control center of the computer. It first fetches instructions from memory
and then interprets them so as to know what is to be done. If required, data is fetched from
memory or input device. Thereafter CPU executes or performs the required computation
and then either stores the output or displays on the output device. The CPU has three main
components which are responsible for different functions – Arithmetic Logic Unit (ALU),
Control Unit (CU) and Memory registers
 Arithmetic and Logic Unit (ALU) : The ALU, as its name suggests performs
 mathematical calculations and takes logical decisions. Arithmetic calculations include
addition, subtraction, multiplication and division. Logical decisions involve comparison
of two data items to see which one is larger or smaller or equal.
 Control Unit : The Control unit coordinates and controls the data flow in and out of CPU
and also controls all the operations of ALU, memory registers and also input/output units.
It is also responsible for carrying out all the instructions stored in the program. It decodes
the fetched instruction, interprets it and sends control signals to input/output devices until
the required operation is done properly by ALU and memory.
  Memory Registers : A register is a temporary unit of memory in the CPU. These are
used to store the data which is directly used by the processor. Registers can be of
different sizes(16 bit, 32 bit, 64 bit and so on) and each register inside the CPU has a
specific function like storing data, storing an instruction, storing address of a location in
memory etc. The user registers can be used by an assembly language programmer for
storing operands, intermediate results etc. Accumulator (ACC) is the main register in the
ALU and contains one of the operands of an operation to be performed in the ALU.
 Memory : Memory attached to the CPU is used for storage of data and instructions and is
called internal memory The internal memory is divided into many storage locations, each
of which can store data or instructions. Each
 memory location is of the same size and has an address. With the help of the address, the
computer can read any memory location easily without having to search the entire
memory. when a program is executed, it’s data is copied to the internal memory ans is
stored in the memory till the end of the execution. The internal memory is also called the
Primary memory or Main memory. This memory is also called as RAM, i.e. Random
Access Memory. The time of access of data is independent of its location in memory,
therefore this memory is also called Random Access memory (RAM). Read this
for different types of RAMs
 Output Unit : The output unit consists of output devices that are attached with the
computer. It converts the binary data coming from CPU to human understandable form.
The common output devices are monitor, printer, plotter etc.

Buses, bus architecture, types of buses and bus arbitration

Bus is a group of conducting wires which carries information, all the peripherals are connected to
microprocessor through Bus.
There are three types of buses.
1.Address-bus –
It is a group of conducting wires which carries address only. Address bus is unidirectional
because data flow in one direction, from microprocessor to memory or from
microprocessor to Input/output devices (That is, Out of Microprocessor).
Length of Address Bus of 8085 microprocessor is 16 Bit (That is, Four Hexadecimal
Digits), ranging from 0000 H to FFFF H, (H denotes Hexadecimal). The microprocessor
8085 can transfer maximum 16 bit address which means it can address 65, 536 different
memory location.
The Length of the address bus determines the amount of memory a system can address.
Such as a system with a 32-bit address bus can address 2^32 memory locations. If each
memory location holds one byte, the addressable memory space is 4 GB. However, the
actual amount of memory that can be accessed is usually much less than this theoretical
limit due to chipset and motherboard limitations.
2. Data-bus –
It is a group of conducting wires which carries Data only. Data bus is bidirectional
because data flow in both directions, from microprocessor to memory or Input/Output
devices and from memory or Input/Output devices to microprocessor.
Length of Data Bus of 8085 microprocessor is 8 Bit (That is, two Hexadecimal Digits),
ranging from 00 H to FF H. (H denotes Hexadecimal).
When it is write operation, the processor will put the data (to be written) on the data bus,
when it is read operation, the memory controller will get the data from specific memory
block and put it into the data bus.
The width of the data bus is directly related to the largest number that the bus can carry,
such as an 8 bit bus can represent 2 to the power of 8 unique values, this equates to the
number 0 to 255.A 16 bit bus can carry 0 to 65535.
3. Control-bus –
It is a group of conducting wires, which is used to generate timing and control signals to
control all the associated peripherals, microprocessor uses control bus to process data, that
is what to do with selected memory location. Some control signals are:
 Memory read
 Memory write
 I/O read
 I/O Write
 Opcode fetch
If one line of control bus may be the read/write line. If the wire is low (no electricity flowing)
then the memory is read, if the wire is high (electricity is flowing) then the memory is written.
Bus Arbitration
 A device that initiates data transfers on the bus at any given time is called a bus master.
 In a computer system, there may be more than one bus master such as a DMA controller
or a processor etc.
 These devices share the system bus and when a current master bus relinquishes another
bus can acquire the control of the processor.
 Bus arbitration is a process by which next device becomes the bus controller by
transferring bus mastership to another bus.
Types of Bus Arbitration
There are two types of bus arbitration namely

1. Centralized Arbitration.
2. Distributed Arbitration.

Only single bus arbiter performs the required arbitration and it can be either a processor or a
separate DMS controller.
There are three arbitration schemes which run on centralized arbitration.
 a) Daisy Chaining − It is a simple and cheaper method where all the masters use the
same line for making bus requests.
 b) Polling Method − In this method, the controller is used to generate address lines for
the master. For example, if there are 8 masters connected in a system at least 3 address
lines are required.
 c) Independent Request − In this scheme, each bus has its own bus request and a grant.
The built-in priority decoder selects the highest priority requests and asserts the system.
Distributed Arbitration

 Here, all the devices participate in the selection of the next bus master.
 Each device on the bus is assigned a4 bit identification number.
 When one or more devices request control of the bus, they assert the start arbitration
signal and place their 4-bit identification numbers on arbitration lines through ARB3.
 Each device compares the code and changes its bit position accordingly.
 It does so by placing a 0 at the input of their drive.
 The distributed arbitration is highly reliable because the bus operations are not dependent
on devices.

Register, bus and memory transfer

A digital system composed of many registers, and paths must be provided to transfer information
from one register to another. The number of wires connecting all of the registers will be
excessive if separate lines are used between each register and all other registers in the system.

A bus structure, on the other hand, is more efficient for transferring information between
registers in a multi-register configuration system.

A bus consists of a set of common lines, one for each bit of register, through which binary
information is transferred one at a time. Control signals determine which register is selected by
the bus during a particular register transfer.
The following block diagram shows a Bus system for four registers. It is constructed with the
help of four 4 * 1 Multiplexers each having four data inputs (0 through 3) and two selection
inputs (S1 and S2).

We have used labels to make it more convenient for you to understand the input-output
configuration of a Bus system for four registers. For instance, output 1 of register A is connected
to input 0 of MUX1.

The two selection lines S1 and S2 are connected to the selection inputs of all four multiplexers.
The selection lines choose the four bits of one register and transfer them into the four-line
common bus.

When both of the select lines are at low logic, i.e. S1S0 = 00, the 0 data inputs of all four
multiplexers are selected and applied to the outputs that forms the bus. This, in turn, causes the
bus lines to receive the content of register A since the outputs of this register are connected to the
0 data inputs of the multiplexers.

Similarly, when S1S0 = 01, register B is selected, and the bus lines will receive the content
provided by register B.
The following function table shows the register that is selected by the bus for each of the four
possible binary values of the Selection lines.

Note: The number of multiplexers needed to construct the bus is equal to the number of bits in
each register. The size of each multiplexer must be 'k * 1' since it multiplexes 'k' data lines. For
instance, a common bus for eight registers of 16 bits each requires 16 multiplexers, one for each
line in the bus. Each multiplexer must have eight data input lines and three selection lines to
multiplex one significant bit in the eight registers.

3-state buffer bus system

A bus system can also be constructed using three-state gates instead of multiplexers.

The three state gates can be considered as a digital circuit that has three gates, two of which are
signals equivalent to logic 1 and 0 as in a conventional gate. However, the third gate exhibits a
high-impedance state.

The most commonly used three state gates in case of the bus system is a buffer gate.

The graphical symbol of a three-state buffer gate can be represented as:

The following diagram demonstrates the construction of a bus system with three-state buffers.
 o The outputs generated by the four buffers are connected to form a single bus line.
o Only one buffer can be in active state at a given point of time.
o The control inputs to the buffers determine which of the four normal inputs will
communicate with the bus line.
o A 2 * 4 decoder ensures that no more than one control input is active at any given point
of time.

Memory Transfer

Most of the standard notations used for specifying operations on memory transfer are stated
below.

o The transfer of information from a memory unit to the user end is called
a Read operation.
o The transfer of new information to be stored in the memory is called a Write operation.
o A memory word is designated by the letter M.
o We must specify the address of memory word while writing the memory transfer
operations.
o The address register is designated by AR and the data register by DR.
o Thus, a read operation can be stated as:

1. Read: DR ← M [AR]
o The Read statement causes a transfer of information into the data register (DR) from the
memory word (M) selected by the address register (AR).
o And the corresponding write operation can be stated as:

1. Write: M [AR] ← R1
o The Write statement causes a transfer of information from register R1 into the memory
word (M) selected by address register (AR).
 Arithmetic Micro-operations

In general, the Arithmetic Micro-operations deals with the operations performed on numeric data
stored in the registers.

The basic Arithmetic Micro-operations are classified in the following categories:

1. Addition
2. Subtraction
3. Increment
4. Decrement
5. Shift

Some additional Arithmetic Micro-operations are classified as:

1. Add with carry

2. Subtract with borrow
3. Transfer/Load, etc.

The following table shows the symbolic representation of various Arithmetic Micro-operations.

Symbolic Representation Description

R3 ← R1 + R2 The contents of R1 plus R2 are transferred to R3.

R3 ← R1 - R2 The contents of R1 minus R2 are transferred to R3.

R2 ← R2' Complement the contents of R2 (1's complement)

R2 ← R2' + 1 2's complement the contents of R2 (negate)

R3 ← R1 + R2' + 1 R1 plus the 2's complement of R2 (subtraction)

R1 ← R1 + 1 Increment the contents of R1 by one

R1 ← R1 - 1 Decrement the contents of R1 by one

Processor organization

Single Accumulator based CPU organization

The computers, present in the early days of computer history, had accumulator-based CPUs.
In this type of CPU organization, the accumulator register is used implicitly for processing all
instructions of a program and store the results into the accumulator.
The instruction format that is used by this CPU Organization is One address field.
Due to this the CPU is known as One Address Machine.
The main points about Single Accumulator based CPU Organization are:
1. In this CPU Organization, the first ALU operand is always stored into the Accumulator and
the second operand is present either in Registers or in the Memory.
2. Accumulator is the default address thus after data manipulation the results are stored into
the accumulator.
3. One address instruction is used in this type of organization.
The format of instruction is: Opcode + Address
Opcode indicates the type of operation to be performed.
Mainly two types of operation are performed in single accumulator based CPU organization:

1. Data transfer operation –

In this type of operation, the data is transferred from a source to a destination.
For ex: LOAD X, STORE Y
Here LOAD is memory read operation that is data is transfer from memory to accumulator
and STORE is memory write operation that is data is transfer from accumulator to memory.
2. ALU operation –
In this type of operation, arithmetic operations are performed on the data.
For ex: MULT X
where X is the address of the operand. The MULT instruction in this example performs the
operation,
AC <-- AC * M[X]
AC is the Accumulator and M[X] is the memory word located at location X.
1. This type of CPU organization is first used in PDP-8 processor and is used for process
control and laboratory applications. It has been totally replaced by the introduction of the
new general register based CPU.
Advantages –
 One of the operands is always held by the accumulator register. This results in short
instructions and less memory space.
 Instruction cycle takes less time because it saves time in instruction fetching from memory.
Disadvantages –
 When complex expressions are computed, program size increases due to the usage of many
short instructions to execute it. Thus memory size increases.
 As the number of instructions increases for a program, the execution time increases.
Stack based CPU Organization

The computers which use Stack-based CPU Organization are based on a data structure
called stack. The stack is a list of data words. It uses Last In First Out (LIFO) access method
which is the most popular access method in most of the CPU. A register is used to store the
address of the topmost element of the stack which is known as Stack pointer (SP). In this
organization, ALU operations are performed on stack data. It means both the operands are
always required on the stack. After manipulation, the result is placed in the stack.
The main two operations that are performed on the operators of the stack are Push and Pop.
These two operations are performed from one end only.
1. Push –
This operation results in inserting one operand at the top of the stack and it decrease the
stack pointer register. The format of the PUSH instruction is:
1. PUSH
It inserts the data word at specified address to the top of the stack. It can be implemented
as:
//decrement SP by 1
SP <-- SP - 1

//store the content of specified memory address

//into SP; i.e, at top of stack
SP <-- (memory address)
2. Pop –
This operation results in deleting one operand from the top of the stack and it increase the
stack pointer register. The format of the POP instruction is:
POP
It deletes the data word at the top of the stack to the specified address. It can be
implemented as:
//transfer the content of SP (i.e, at top most data)
//into specified memory location
(memory address) <-- SP

//increment SP by 1
SP <-- SP + 1
Operation type instruction does not need the address field in this CPU organization. This is
because the operation is performed on the two operands that are on the top of the stack. For
example:
SUB
This instruction contains the opcode only with no address field. It pops the two top data from the
stack, subtracting the data, and pushing the result into the stack at the top.
PDP-11, Intel’s 8085 and HP 3000 are some of the examples of the stack organized computers.
The advantages of Stack based CPU organization –
 Efficient computation of complex arithmetic expressions.
 Execution of instructions is fast because operand data are stored in consecutive memory
locations.
 Length of instruction is short as they do not have address field.
The disadvantages of Stack based CPU organization –
 The size of the program increases.

Note: Stack based CPU organization uses zero address instruction.

Applications of Stack
1. Stacks can be used for expression evaluation.
2. Stacks can be used to check parenthesis matching in an expression.
3. Stacks can be used for Conversion from one form of expression to another.
4. Stacks can be used for Memory Management.
5. Stack data structures are used in backtracking problems

General registers organization

Registers are a type of computer memory used to quickly accept, store, and transfer data and
instructions that are being used immediately by the CPU. The registers used by the CPU are
often termed as Processor registers.

A processor register may hold an instruction, a storage address, or any data (such as bit sequence
or individual characters).

The computer needs processor registers for manipulating data and a register for holding a
memory address. The register holding the memory location is used to calculate the address of the
next instruction after the execution of the current instruction is completed.

Following is the list of some of the most common registers used in a basic computer:

Register Symbol Number of Function

bits

Data register DR 16 Holds memory operand

Address register AR 12 Holds address for the

memory

Accumulator AC 16 Processor register

Instruction register IR 16 Holds instruction code

 Program counter PC 12 Holds address of the
instruction

Temporary register TR 16 Holds temporary data

Input register INPR 8 Carries input character

Output register OUTR 8 Carries output character

The following image shows the register and memory configuration for a basic computer.

o The Memory unit has a capacity of 4096 words, and each word contains 16 bits.
o The Data Register (DR) contains 16 bits which hold the operand read from the memory
location.
o The Memory Address Register (MAR) contains 12 bits which hold the address for the
memory location.
o The Program Counter (PC) also contains 12 bits which hold the address of the next
instruction to be read from memory after the current instruction is executed.
o The Accumulator (AC) register is a general purpose processing register.
o The instruction read from memory is placed in the Instruction register (IR).
o The Temporary Register (TR) is used for holding the temporary data during the
processing.
o The Input Registers (IR) holds the input characters given by the user.
o The Output Registers (OR) holds the output after processing the input data.
 General Register based CPU Organization

When we are using multiple general purpose registers, instead of single accumulator register, in
the CPU Organization then this type of organization is known as General register based CPU
Organization. In this type of organization, computer uses two or three address fields in their
instruction format. Each address field may specify a general register or a memory word. If many
CPU registers are available for heavily used variables and intermediate results, we can avoid
memory references much of the time, thus vastly increasing program execution speed, and
reducing program size.
For example:
MULT R1, R2, R3
This is an instruction of an arithmetic multiplication written in assembly language. It uses three
address fields R1, R2 and R3. The meaning of this instruction is
R1 <-- R2 * R3
This instruction also can be written using only two address fields as:
MULT R1, R2
In this instruction, the destination register is the same as one of the source registers. This means
the operation
R1 <-- R1 * R2
The use of large number of registers results in short program with limited instructions.
Some examples of General register based CPU Organization are IBM 360 and PDP- 11.
The advantages of General register based CPU organization –
 Efficiency of CPU increases as there are large number of registers are used in
 this organization.
 Less memory space is used to store the program since the instructions are written in
compact way.
The disadvantages of General register based CPU organization –
 Care should be taken to avoid unnecessary usage of registers. Thus, compilers need to be
more intelligent in this aspect.
 Since large number of registers are used, thus extra cost is required in this organization.
General register CPU organisation of two type:
1. Register-memory reference architecture (CPU with less register)– In this organisation
Source 1 is always required in register, source 2 can be present either in register or in
memory.Here two address instruction format is the compatible instruction format.
2. Register-register reference architecture(CPU with more register)– In this organisation ALU
operations are performed only on a register data. So operands are required in the register.
After manipulation result is also placed in register. Here three address instruction format is
the compatible instruction format.

Generally CPU has seven general registers. Register organization show how registers are selected
and how data flow between register and ALU. A decoder is used to select a particular register.
The output of each register is connected to two multiplexers to form the two buses A and B. The
selection lines in each multiplexer select the input data for the particular bus.
The A and B buses form the two inputs of an ALU. The operation select lines decide the micro
operation to be performed by ALU. The result of the micro operation is available at the output
bus. The output bus connected to the inputs of all registers, thus by selecting a destination
register it is possible to store the result in it.

A bus organization for seven CPU register

 EXAMPLE:

• To perform the operation R3 = R1+R2 We have to provide following binary selection

variable to the select inputs.

1. SEL A : 001 -To place the contents of R1 into bus A.

2. SEL B : 010 - to place the contents of R2 into bus B

3. SEL OPR : 10010 – to perform the arithmetic addition A+B

4. SEL REG or SEL D : 011 – to place the result available on output bus in R3.

Register and multiplexer input selection code

SEL-D or
Binary code SELA SELB SEL-REG

000 Input Input ---

001 R1 R1 R1

010 R2 R2 R2

011 R3 R3 R3

100 R4 R4 R4

101 R5 R5 R5

110 R6 R6 R6

111 R7 R7 R7
 Operation with symbol

Operation selection
code Operation symbol

0000 Transfer A TSFA

0001 Increment A INC A

0010 A+B ADD

0011 A-B SUB

0100 Decrement A DEC

0101 A AND B AND

0110 A OR B OR

0111 A XOR B XOR

1000 Complement A COMA

1001 Shift right A SHR

1010 Shift left A SHL

 What is CONTROL WORD?

• The combined value of a binary selection inputs specifies the control word.

• It consist of four fields SELA,SELB,and SELD or SELREG contains three bit each and
SELOPR field contains four bits thus the total bits in the control word are 13-bits.

SELREG OR
SEL A SELB SELD SELOPR

FORMAT OF CONTROL WORD

1. The three bits of SELA select a source registers of the ‘a’ input of the ALU.

2. The three bits of SELB select a source registers of the ‘b’ input of the ALU.

3. The three bits of SELED or SELREG select a destination register using the decoder.

4. The four bits of SELOPR select the operation to be performed by ALU.

CONTROL WORD FOR OPERATION R2 = R1+R3

SEL- D
OR SEL -
SEL A SEL B SEL- REG OPR

001 011 010 0010

Note: Control words for all micro operation are stored in the control memory

Example:

SEL
D
OR
SEL
SEL.A SEL.B REG SELOPR CONTROL WORD
MICROOPERATION
R2 = R1+R3 R1 R3 R2 ADD 001 011 010 0010
 Addressing Modes

Addressing modes specifies the way, the effective address of an operand is represented in the
instruction. Some addressing mode efficiently allows referring to a large range of area like a
linear array of addresses and list of addresses. Addressing mode describes
a flexible and efficient way to define complex effective address.

Generally, the programs are written in a high-level language, as it is a convenient way to define
the variables and operations that the programmer needs to perform on the variables. Later, this
program is compiled to generate the machine code. The machine code has low-level instructions.

The low-level instruction has opcode and operands. Addressing mode has nothing to do with
the opcode part. It focuses on presenting the operand’s address in the instructions.

We have the list below showing the various kind of addressing modes:

Types of Addressing Modes

1. Register Addressing Mode

2. Direct Addressing Mode
3. Immediate Addressing Mode
4. Register Indirect Addressing Mode
5. Index Addressing Mode
6. Auto Increment Mode
7. Auto Decrement Mode
8. Relative Addressing Mode

Before discussing the addressing modes, we must know about the term “effective address”.

Effective Address (EA):

Effective address is the address of the exact memory location where the value of the
operand is present.

Let us discuss all the addressing modes along with the example for better understanding.

1. Register Addressing Mode

Every instruction includes operands; the operands can be a memory location, a processor register
or an I/O device. The instruction which uses processor registers to represent operands is the
instruction in register addressing mode.
Here, the effective address is a register where the value of the operand is present.

EA=R

Below we have two instructions as our examples for register addressing mode.

Add R4, R3

Load R3, R2

In the examples above, the Add instruction uses registers to represent both of its operands.
Similarly, the Load instruction also uses registers to represent both of its operands. So, the
instruction above uses register addressing mode to describe the address of the operand. Below,
we have a figure showing the Add instruction in the example above.

Advantage: In the register addressing mode there are no memory references as the value to be
operated is present in the register.
Disadvantage: Registers have limited address space. So, it has a limit on the size of value that
can be stored.

2. Direct Addressing Mode

The direct addressing mode is also known as Absolute Addressing mode. Here, the instruction
contains the address of the location in memory where the value of the operand is stored.

Here, the effective address is the address of memory location.

EA = A

For example, observe the examples below:

Add R2, A

Store R2, B

The Add instruction includes the memory location A which has the value to be added to the
content of register R2. Similarly, the Store instruction has the address of memory location B
where the content of register R2 will be stored. Below we have a figure showing the direct
addressing of the operand A in the Add instruction of the example above.

Advantage: Direct addressing mode is the simplest of all addressing mode.

Disadvantage: Direct addressing mode provides a limited address space.

3. Immediate Addressing Mode

In immediate addressing mode, the value of the operand is explicitly mentioned in the
instruction. Here, effective address is not required as the operand is explicitly defined in
instruction.

Let us see the example of immediate addressing mode:

Add R2, #100

Store R2, 100H

The Add instruction, adds 100 to R2’s content . The # sign in front of the value indicates the
immediate value to be operated. If a value does not have # sign in front of it then it is the address
of a memory location.

The next instruction Store considers the immediate value 100H as address as it does not have #
sign in front of it. The Store instruction stores the content of R2 at memory location 100H. In the
figure below we have shown the Store instruction of the above examples.

Advantage: In the immediate addressing mode the memory reference is not required as the value
is explicitly present in the instruction

Disadvantage: The instruction format provides a limited size for the operand. So, the immediate
addressing mode has limited space for immediate value.

4. Register Indirect Addressing mode

A processor register is used to hold the address of a memory location where the operand is
placed. This addressing mode allows executing the same set of instructions for the different
memory location. This can be done by incrementing the content of register thereby pointing the
new location each time.

In higher-level language, it is referred to as pointers. The indirect mode is denoted by placing the
register inside the parenthesis.
Here the effective address is the content of memory location present in the register.
EA=(R)

Now, for example:

Load R3, (R2) // Load R2, A

The Load instruction above will load the value present at the memory location contained by
register R2 in the register R3. The figure below shows how the register R3 gets loaded with the
value stored in the memory location held by register R2.

Advantage: In the register indirect addressing mode the same set of instructions can be used
multiple times.

Disadvantage: In the register indirect addressing mode the number of memory reference is
more.

5. Index Addressing Mode

Index addressing mode is helpful when the instructions in the program are accessing the array
or the large range of memory addresses. In this mode, the effective address is generated
by adding a constant to the register’s content. The content of the register does not change.

The symbolic representation of index addressing mode is denoted as:

X(R)

And the effective address is denoted by

EA = X + (R)

For example, consider the instruction below:

Load R2, A

Load R3, (R2)

Load R4, 4(R2)

Load R5, 8(R2)

Load R6, 12(R2)

The above instructions will load the register R3, R4, R5, R6 with the contents, present at the
successive memory addresses from memory location A correspondingly.
Advantage: The index addressing mode provides flexibility to specify memory locations.

Disadvantage: The index addressing mode is complex to implement.

6. Auto Increment Addressing Mode

In auto-increment addressing mode once the content of the register is accessed by the instruction
the register’s content is incremented to refer the next operand.

Symbolically it is represented as below:

(R)+

Here, the effective address is content of the register as it is enclosed by parenthesis. The content
of register which is referring to a memory location is incremented so that it could point the next
memory location where the next operand is stored.

7. Auto Decrement Addressing Mode

It is just opposite of auto-increment mode. In auto decrement mode the content of the register
is decremented initially and then the decremented content of the register is used as effective
address.

Symbolically it is presented as:

-(R)

The auto-increment and decrement mode help to implement the stack structure.

8. Relative Addressing Mode

In the content above we have discussed the index addressing mode. There we were adding a
constant to the register content to refer the next operand address. In some computer instead of a
register, the program counter is used.

The symbolic representation of relative address mode is

X(PC)

The effective address for it would be:

EA = X + (PC)

As here the operand addresses are found relative to the program counter. That’s why it is referred
to as relative address mode.

Advantage: Relative addressing mode doesn’t require memory references.

Disadvantage: Relative addressing mode doesn’t have any disadvantage as such.

Advantages of Addressing Modes

1. To give programmers to facilities such as Pointers, counters for loop controls, indexing of
data and program relocation.
2. To reduce the number bits in the addressing field of the Instruction.

Addressing modes example