01/05/2021 Unit Test 5 (Module 6: Pipelining & Vector Processing)

Unit Test 5 (Module 6: Pipelining & Vector

Processing)
Total points 9/10

10 marks

The respondent's email (20se08ce002@ppsu.ac.in) was recorded on submission of this

form.

0 of 0 points

Enrollment No *

20SE08CE002

Student Name *

Krima Modi

Unit Test 5 (Module 6: Pipelining & Vector Processing) 9 of 10 points

CISC stands for * 1/1

Complex Instruction Set Computer

Common Instruction Set Counter

Complex Instruction Set Counter

None of the above

https://docs.google.com/forms/d/e/1FAIpQLSfK2ff01GHX4PQdZ7vcZT8sgwMJFfyAXDIIN4nLvFsTKXSbBg/viewscore?viewscore=AE0zAgAP-Bq… 1/4
01/05/2021 Unit Test 5 (Module 6: Pipelining & Vector Processing)

Pipeline help * 1/1

Throughput of entire workload

Latency of single task

Reduced speedup

None of the above

The amount of processing that can be accomplished during a given 1/1

interval of time is *

Speed up

Throughput

Clock speed

None of the above

Van Neumann architecture is ________________ type of system according 1/1

to Flynn’s taxonomy *

SISD

MISD

SIMD

MIMD

https://docs.google.com/forms/d/e/1FAIpQLSfK2ff01GHX4PQdZ7vcZT8sgwMJFfyAXDIIN4nLvFsTKXSbBg/viewscore?viewscore=AE0zAgAP-Bq… 2/4
01/05/2021 Unit Test 5 (Module 6: Pipelining & Vector Processing)

RISC stands for * ···/1

Reduced Instruction set Counter

Register Input Status Computer

Reduced Instruction Set Computer

Random Instruction Set Computer

No correct answers

A pipeline is like____________________ * 1/1

House pipeline

Automobile assembly line

A gas line

Both A and C

______________ processing is a technique of decomposing a sequential 1/1

process into sub operation , with each sub process being executed in
special dedicated segments *

Parallel

Vector

Pipeline

Array

https://docs.google.com/forms/d/e/1FAIpQLSfK2ff01GHX4PQdZ7vcZT8sgwMJFfyAXDIIN4nLvFsTKXSbBg/viewscore?viewscore=AE0zAgAP-Bq… 3/4
01/05/2021 Unit Test 5 (Module 6: Pipelining & Vector Processing)

Pipelining implemetation is easy in a system which have * 1/1

More addressing mode

Instruction of same size with few formats

Multiple instruction size and formats

Both A & B

The situation where data operands not available due to resource 1/1
contention is called *

Data hazard

Control Hazard

Structural Hazard

None of the above

Hazards which causes due to branch and other instruction that changes 1/1
the PC and make the fetch of next instruction to be delayed is known as *

Data Hazard

Control Hazards

Structure Hazard

None of the above

This form was created inside of P P Savani University.

 Forms

https://docs.google.com/forms/d/e/1FAIpQLSfK2ff01GHX4PQdZ7vcZT8sgwMJFfyAXDIIN4nLvFsTKXSbBg/viewscore?viewscore=AE0zAgAP-Bq… 4/4