DEPARTMENT OF ELECTRONICS AND

COMMUNICATION ENGINEERING

2018 REGULATION

18ECE001JL-VLSI DESIGN
LABORATORY

B.EECE-IIIYEAR-VISEMESTER
ACADEMICYEAR 2020-2021

1
 M.KUMARASAMY COLLEGE OF ENGINEERING

(Autonomous)

KARUR – 639 113

CERTIFICATE

Register Number: 18BEC4152

Certified that this is the Bonafide record of work done by Selvan / Selvi ___SHANMATHI M___

of the Sixth Semester B.E. – Electronics and Communication Engineering branch during the

Academic year 2020 - 2021 in the 18ECE001JL - VLSI Design Laboratory

Staff in-charge Head of the Department

Submitted for the End Semester Practical Examination on ……………

Internal Examiner External Examiner

INDEXED PAGE
2
EXPN DATE NAMEOFTHEEXPERIMENTS PAGE MARKS SIGN
O NO

1 08.02.2021 Verilog HDL based design and simulation of 07

combinational circuits(4-bitmin)

2 15.02.2021 Verilog HDL based design and simulation of 10

sequential circuits

3 22.02.2021 Verilog HDL based design and simulation of 13

state machine

4 01.03.2021 Synthesis, P&R and post P&R simulation of 4 16

Bit Serial Adder

5 08.03.2021 Synthesis, P&R and post P&R simulation of 4 20

Bit Parallel Adder/Subtractor

6 22.03.2021 Design and Synthesis of 4Bit Multiplier using 23

Simulator

7 27.03.2021 Basic Logic gates using LT-Spice Tool 27

Design and simulation of a simple five
8 29.03.2021 transistor differential amplifier using-spice 32

9 12.04.2021 Study of real time clock and demonstrate its 35

working on the FPGA board

10 19.04.2021 Study of Testing of 8-BitALU on FPGA 47

Board

Vision and Mission of the Institute

3
Vision
To emerge as a leader among the top institutions in the field of technical education

Mission
M1: Produce smart technocrats with empirical knowledge who can surmount the global challenges.
M2: Create a diverse, fully-engaged, learner-centric campus environment to provide quality education to
the students.
M3: Maintain mutually beneficial partnerships with our alumni, industry and professional associations

Vision and Mission of the Department

Vision
To empower the Electronics and Communication Engineering students with emerging technologies,
professionalism, innovative research and social responsibility.

Mission
M1: Attain the academic excellence through innovative teaching learning process, research areas &
laboratories and Consultancy projects.
M2: Inculcate the students in problem solving and lifelong learning ability.
M3: Provide entrepreneurial skills and leadership qualities.
M4: Render the technical knowledge and industrial skills of faculties.

Program Educational Objectives (PEO’s)

PEO1: Graduates will have a successful career in academia or industry associated with electronics and
communication engineering.
PEO2: Graduates will provide feasible solutions for the challenging problems through comprehensive
research and innovation in the allied areas of electronics and communication engineering.
PEO3: Graduates will contribute to the social needs through lifelong learning, practicing professional
ethics and leadership quality.

Program Outcomes (PO’s)

4
 PO1: Engineering knowledge: Apply the knowledge of mathematics, science, engineering fundamentals,
and an engineering specialization to the solution of complex engineering problems.
PO2: Problem analysis: Identify, formulate, review research literature, and analyze complex engineering
problems reaching substantiated conclusions using first principles of mathematics, natural sciences, and
engineering sciences.
PO3: Design/development of solutions: Design solutions for complex engineering problems and design
system components or processes that meet the specified needs with appropriate consideration for the public
health and safety, and the cultural, societal, and environmental considerations.
PO4: Conduct investigations of complex problems: Use research-based knowledge and research methods
including design of experiments, analysis and interpretation of data, and synthesis of the information to
provide valid conclusions.
PO5: Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modeling to complex engineering activities with an
understanding of the limitations.
PO6: The engineer and society: Apply reasoning informed by the contextual knowledge to assess societal,
health, safety, legal and cultural issues and the consequent responsibilities relevant to the professional
engineering practice.
PO7: Environment and sustainability: Understand the impact of the professional engineering solutions in
societal and environmental contexts, and demonstrate the knowledge of, and need for sustainable
development.
PO8: Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms of
the engineering practice.
PO9: Individual and team work: Function effectively as an individual, and as a member or leader in
diverse teams, and in multidisciplinary settings.
PO10: Communication: Communicate effectively on complex engineering activities with the engineering
community and with society at large, such as, being able to comprehend and write effective reports and
design documentation, make effective presentations, and give and receive clear instructions.
PO11: Project management and finance: Demonstrate knowledge and understanding of the engineering
and management principles and apply these to one’s own work, as a member and leader in a team, to
manage projects and in multidisciplinary environments.
PO12: Life-long learning: Recognize the need for, and have the preparation and ability to engage in
independent and life-long learning in the broadest context of technological change.

Program Specific Outcomes (PSO’s)

5
PSO1: Applying knowledge in various areas, like Electronics, Communications, Signal processing, VLSI,
Embedded systems etc., in the design and implementation of Engineering application.
PSO2: Able to solve complex problems in Electronics and Communication Engineering with analytical
and managerial skills either independently or in team using latest hardware and software tools to fulfil the
industrial expectations.

6
 EX.NO:1 Verilog HDL based design and simulation of combinational circuits (4-bit min)

1(a):Design and Simulation of Full Adder

AIM:
To design and verify the Full Adder using Verilog.

SOFTWARE REQUIRED:

ModelSim6.2c
THEORY:
A fulladder is a logical circuit that performs an addition operation on three one-bit binary
numbers. The fulladder produces a sum of the three inputs and carry value.

PROCEDURE:
1. Open new file in Verilog source editor
2. Type the Verilog coding for the circuit in the new file.
3. Save the file.
4. Compile and Simulate the Program.
5. Add the selected signal to the waveform window.
6. Force the input signals values and verify the output signal values

VERILOGCODING:
module fa(s,co,a,b,ci);
output s,co;
input a,b,ci;
xor u1(s,a,b,ci);
and1 u2(n1,a,b);
and1 u3(n2,b,ci);
and1 u4(n3,a,ci);
or u5(co,n1,n2,n3);
endmodule

SIMULATION RESULTS:

7
 1(b):Design and Simulation of Encoder

AIM:
To design and verify the Encoder using Verilog.

SOFTWARE REQUIRED:
ModelSim6.2c
THEORY:
An encoder is a device, circuit, transducer, software program, algorithm or person that converts
information from one format or code to another, for the purposes of standardization, speed or
compression.
PROCEDURE:
1. Open new file in Verilog source editor
2. Type the Verilog coding for the circuit in the new file.
3. Save the file.
4. Compile and Simulate the Program.
5. Add the selected signal to the waveform window.
6. Force the input signals values and verify the output signal values
VERILOGCODING:

module encoder 83(o,i);

output [2:0]o;
input[7:0]i;
wire x,y,k,l,m;
or u1 (x,i[5],i[4]);
or u2(y,i[7],i[6]);
or u3(o[2],x,y);
or u4(k,i[3],i[2]);
or u5(o[1],y,k);
or u6(l,i[7],i[5]);
or u7(m,i[3],i[1]);
or u8(o[0],l,m);
endmodule

SIMULATION RESULTS:

8
RESULT:

Thebasiccombinationalcircuitswasdesigned andsimulatedusing ModelsimSoftware

9
 EX.NO:2VerilogHDLbaseddesignandsimulationofsequentialcircuits

AIM:
To design and verify the 4bit serial adder using Verilog.

SOFTWAREREQUIRED:

ModelSim6.2c

THEORY:
The serial binary adder or bit-serial adder is a digital circuit that performs binary addition bit
bybit. The serial full adder has three single-bit inputs for the numbers to be added and the carry
in.There aretwosingle-bitoutputs forthesumandcarryout.

PROCEDURE:
1. Open new file in Verilog source editor
2. Type the Verilog coding for the circuit in the new file.
3. Save the file.
4. Compile and Simulate the Program.
5. Add the selected signal to the waveform window.
6. Force the input signals values and verify the output signal values

VERILOGCODING:

module serial(sum,cout,a,b,clk);
input [3:0]a,b;
input clk;
wire [3:0]x,z;
output [3:0] sum;
output cout;
wires, cin;
fa k(s,cout,x[0],z[0],cin);
dff q(cin,cout,clk);
sipom(sum,s,clk);
10
shift g(x,a,clk);
shift h(z,b,clk);
endmodule

module shift(y,d,clk);
input [3:0]d;
input clk;
output[3:0]y;
reg [3:0] y;
initial begin assign y=d;
end
always @(posedgeclk)
begin
assign y=y>>1;
end
endmodule

module sipo(y,s,clk);
inputs;
input clk; output [3:0]y;
reg [3:0]y;
always @(posedgeclk)
begin
assign y={s,y[3:1]};
end
endmodule

module fa(s,cout,a,b,cin);inputa,b,cin;
output s,cout;
assign {cout,s}=a+b+cin;endmodule

module dff(q,d,clk);inputd,clk;
outputq;regq;initial beginq=1'b0;
end
always@(posedgeclk)begin
q=d;end
endmodule

11
SIMULATIONRESULTS:

RESULT:

The4-bitserialadder wasdesignedandsimulatedusing ModelsimSoftware

12
 EX.NO:3Verilog HDL Based Design Entry and Simulation State Machine
(Moore Machine)
AIM:
To design Verilog HDL Based Design Entry and Simulation State Machine (Moore
Machine)

SOFTWAREREQUIRED:
ModelSim6.2c

PROCEDURE:
1. Open new file in Verilog source editor
2. Type the Verilog coding for the circuit in the new file.
3. Save the file.
4. Compile and Simulate the Program.
5. Add the selected signal to the waveform window.
6. Force the input signals values and verify the output signal values

MOOREMACHINE:

VERILOGCODING:

module moore( clk, rst, inp,

outp);inputclk,rst,inp;
outputoutp;reg
[1:0]
state;regoutp;
always @( posedge clk, posedge rst
)begin
if(rst)
state <=
2'b00;else
begin
case(state)

13
 2'b00:
begin
if( inp ) state <=
2'b01;elsestate<=2'b10
;end

2'b01:
begin
if( inp ) state <=
2'b11;elsestate<=2'b10
;end
2'b10:
begin
if( inp ) state <=
2'b01;elsestate<=2'b11
;end
2'b11:
begin
if( inp ) state <=
2'b01;elsestate<=2'b10
;end
endcase
end
end
always @(posedge clk, posedge
rst)begin
if( rst
)outp<=0;
else if( state == 2'b11
)outp<=1;
else outp <=
0;end
endmodule

RTLSCHEMATIC:

14
TECHNOLOGICALSCHEMATIC:

OUTPUTWAVEFORM:

RESULT:

Thusthefinitestatemachine(mooremachine)hasbeensimulatedandverifiedandimplemented.

15
 EX.NO:4 Synthesis, P&R and post P&Rsimulation of 4Bit Serial Adder
AIM:
To design and verify the 4bit serialadder using Verilog.

SOFTWAREREQUIRED:

ModelSim6.2c

THEORY:
The serial binary adder or bit-serial adder is a digital circuit that performs binary addition bit
bybit. Theserial full adder has three single-bit inputs for the numbers to be added and the carry
in.There aretwosingle-bitoutputs forthesumandcarryout.

PROCEDURE:
1. Open new file in Verilog source editor
2. Type the Verilog coding for the circuit in the new file.
3. Save the file.
4. Compile and Simulate the Program.
5. Add the selected signal to the waveform window.
6. Force the input signals values and verify the output signal values

VERILOGCODING:

module
serial(sum,cout,a,b,clk);input[3:
0]a,b;
inputclk;wire[
3:0]x,z;
output [3:0]
sum;outputcout;
wires,cin;
fa
k(s,cout,x[0],z[0],cin);df
f
q(cin,cout,clk);sipom(su
m,s,clk);
16
shiftg(x,a,clk);
shift
h(z,b,clk);end
module

17
module
shift(y,d,clk);input[3:
0]d;
inputclk;

output[3:0] y;
reg [3:0]
y;initial
beginassign
y=d;end
always@(posedgeclk)b
egin
assign
y=y>>1;end
endmodule

module
sipo(y,s,clk);inputs;
inputclk;output
[3:0]y;
reg [3:0]y;
always@(posedgeclk)b
egin
assign
y={s,y[3:1]};end
endmodule

module
fa(s,cout,a,b,cin);inputa,b
,cin;
output s,cout;
assign
{cout,s}=a+b+cin;endmodule

module
dff(q,d,clk);inputd,c
lk;
outputq;reg
q;initial
beginq=1'b
0;
end
always@(posedgeclk)b
egin
q=d;
end
endmodule

18
SIMULATIONRESULTS:

RESULT:

The4bitserialadderwasdesignedandsimulatedusingModelsimSoftware

19
 EX.NO:5 DesignandSimulationof4bitparalleladder/subtractor

AIM:
Todesignandverifythe 4bit4bitparalleladder/subtractor

SOFTWAREREQUIRED:
ModelSim6.2c

THEORY:
Parallel Adder :A single full adder performs the addition of two one bit numbers and an
inputcarry. But a Parallel Adder is a digital circuit capable of finding the arithmetic sum of two
binarynumbers that is greater than one bit in length by operating on corresponding pairs of bits
inparallel. It consists of full adders connected in a chain where the output carry from each
fulladder is connected to the carry input of the next higher order full adder in the chain. A n
bitparallel adder requires n full adders to perform the operation. So for the two-
bitnumber,two adders are needed while for four bit number, four adders are needed and so on.
Paralleladders normally incorporate carry lookahead logic to ensure that carry propagation
betweensubsequent stages of addition does not limit addition speed.A Parallel Subtractor is a
digitalcircuit capable of finding the arithmetic difference of two binary numbers that is greater
than onebitin length by operating on corresponding pairs of bits in parallel. The parallel
subtractor
canbedesignedinseveralwaysincludingcombinationofhalfandfullsubtractors,allfullsubtractorsorall
fulladders withsubtrahendcomplementinput.

PROCEDURE:
1. OpennewfileinVerilogsourceeditor
2. TypetheVerilogcodingforthecircuitinthenewfile.
3. Savethefile.
4. CompileandSimulatetheProgram.
5. Addtheselectedsignalto thewaveformwindow.
6. Forcetheinputsignalsvaluesandverifytheoutputsignalvalues

VERILOGCODING:

module ripple_carry_adder_subtractor(S, C, V, A, B,
Op);output[3:0]S;
outputC;outp
utV;input[3:0
]A;
input[3:0]B;
input Op;
wire C0;
wire C1;
wire C2;
wire C3;
wire B0;
wire B1;
wire B2;
20
wire B3;

21
 xor(B0,B[0],Op);
xor(B1,B[1],Op);
xor(B2,B[2],Op);
xor(B3,B[3],Op);
xor(C,C3,Op);
xor(V,C3,C2);

full_adder fa0(S[0], C0, A[0], B0,

Opfull_adderfa1(S[1],C1,A[1],B1,C0);
full_adderfa2(S[2],C2,A[2],B2,C1);
full_adderfa3(S[3],C3,A[3],B3,C2);

module full_adder(S, Cout, A, B,

Cin);outputS;
output
Cout;inputA
;inputB;inpu
tCin;wirew1
;wirew2;wir
ew3;wirew4
;
xor(w1, A, B);
xor(S,Cin,w1);
and(w2,A, B);
and(w3,A,Cin);
and(w4,B,Cin);
or(Cout, w2, w3,
w4);endmodule

SIMULATIONRESULTS:

RESULT:

The4bitadder/subtractorwasdesignedandsimulatedusingModelsimSoftware

22
 EX.NO:6 DesignandSimulationof4bitmultiplier

AIM:
Todesignandverifythe4bit4bitmultiplier
SOFTWAREREQUIRED:
ModelSim6.2c
THEORY:
A binary multiplieris a combinational logic circuitused in digital systems to perform
themultiplication of two binary numbers. These are most commonly used in various
applicationsespeciallyinthefieldofdigitalsignalprocessingtoperformthevariousalgorithms.

PROCEDURE:
1. OpennewfileinVerilogsourceeditor
2. TypetheVerilogcodingforthecircuitinthenewfile.
3. Savethefile.
4. CompileandSimulatetheProgram.
5. Addtheselectedsignalto thewaveformwindow.
6. Forcetheinputsignalsvaluesandverifytheoutputsignalvalues

VERILOGCODING:

module
array4x4(a,b,p);input[3:
0]a,b;
output[7:0]p;
wire[39:0]w;
anda1(w[0],a[0],b[0]);
anda2(w[1],a[1],b[0]);
anda3(w[2],a[2],b[0]);
anda4(w[3],a[3],b[0]);

anda5(w[4],a[0],b[1]);
anda6(w[5],a[1],b[1]);
23
anda7(w[6],a[2],b[1]);

24
anda8(w[7],a[3],b[1]);
anda9(w[8],a[0],b[2]);
anda10(w[9],a[1],b[2]);
anda11(w[10],a[2],b[2]);
anda12(w[11],a[3],b[2]);
anda13(w[12],a[0],b[3]);
anda14(w[13],a[1],b[3]);
anda15(w[14],a[2],b[3]);
anda16(w[15],a[3],b[3]);
assignp[0]=w[0];
fulladdera17(1'b0,w[1],w[4],w[16],w[17]);
fulladdera18(1'b0,w[2],w[5],w[18],w[19]);
fulladdera19(1'b0,w[3],w[6],w[20],w[21]);
fulladdera20(w[8],w[17],w[18],w[22],w[23]);
fulladdera21(w[9],w[19],w[20],w[24],w[25]);
fulladdera22(w[10],w[7],w[21],w[26],w[27]);
fulladdera23(w[12],w[23],w[24],w[28],w[29]);

fulladdera24(w[13],w[25],w[26],w[30],w[31]);
fulladdera25(w[14],w[11],w[27],w[32],w[33]);
fulladdera26(1'b0,w[29],w[30],w[34],w[35]);
fulladdera27(w[31],w[32],w[35],w[36],w[37]);
fulladder
a28(w[15],w[33],w[37],w[38],w[39]);assignp[1
]=w[16];
assign
p[2]=w[22];assign
p[3]=w[28];assign
p[4]=w[34];assign
p[5]=w[36];assign
p[6]=w[38];assign
p[7]=w[39];endmo
dule

FULLADDER
module
fulladder(a,b,c,s,ca);inputa,b
,c;
outputs,ca;assign
s=(a^b^c);
assign
ca=((a&b)|(b&c)|(c&a));endmo
dule

25
SIMULATIONRESULTS:

RESULT:

The4bitmultiplierwasdesignedandsimulatedusingModelsimSoftware.

26
 EX.NO:7BasicgatesusingLT-SPICEtool

AIM:
TodesignandverifytheBasicgatesusingSPICE

SOFTWAREREQUIRED:
LT-SPICE XVII

PROCEDURE:
1. OpenaFile →NewSchematic(Ctrl+N)
2. Click the Component Option
3. Select the required component paste it schematic window
4. Savethefile
5. OpenSimulate and Click Run Option and Select the input and output waves
6. Verifytheinputandoutputgraphs

27
 NAND GATE

DIAGRAM:

SIMULATIONRESULTS:

28
 NORGATE

DIAGRAM:

29
Aa

SIMULATIONRESULTS:

30
RESULT:

ThusthebasicCMOSgateswasdesignedandverifiedusingLT-SPICE.

31
EX.NO :8 Design andSimulation ofSimpleFiveTransistorDifferentialAmplifier

AIM:
TodesignandverifythesimplefivetransistordifferentialamplifierusingSPICE
andsimulatePre synthesisand postsynthesislayout.

SOFTWAREREQUIRED:
LT-SPICE XVII

PROCEDURE:
1. Opena File →NewSchematic(Ctrl+N)
2. Click the Component Option
3. Select the required component paste it schematic window
4. Savethefile
5. OpenSimulate and Click Run Option and Select the input and output waves
6. Verifytheinputandoutputgraphs

32
DIFFERENTIAL AMPLIFIER USING FIVE TRANSISTER

33
RESULT:

Thus, the simple five transistor differential amplifier was

simulatedandverifiedsuccessfully.

34
 EX.NO:9StudyofrealtimeclockanddemonstrateitsworkingontheFPGAboard

AIM:
To designa realtime clock and demonstrate itsworkingonthe FPGAboard.

SOFTWAREREQUIRED:
XilinxISE
Spartan3EFPGAKit

THEORY:
A clock that keeps track of the time even when the computer is turned off. Real-
timeclocks run on a special battery that is not connected to the normal power supply. In
contrast,clocks that are not real-time do not function when the computer is off. Although using a
RTC wehave the following benefits: Low power consumption, Frees the main system for time-
criticaltasks,sometimesmore accuratethanothermethods.

PROCEDURE:

1. OpennewVerilog sourceeditor inXilinxISEtool

2. TypetheVerilogcodingfor8-BitALUinthenewfile
3. Savethefile.
4. Assignthe I/O Signaltothe FPGApackage pins
5. SynthesistheVerilogCode.
6. Placeand RoutetheDesignbyclick onImplementDesign
7. Generatethebitfile
8. ConfigurethebitfileonSpartan3E FPGAandverifytheresult

VERILOGCODING:

module
new_code(clk,y,sel);inputclk
;
output
[7:0]y;output
[3:0]sel;reg[7:0
]y;
reg[3:0]sel;integer
w,i,f,j,k,n;reg[1:0]
state,stat;
parameter
state0=2’b00;parameter
state1=2’b01;parameter
state2=2’b10;parameter
state3=2’b11;initialbegi
n
35
w=0;i=0; f=0;j=0;k=0;n=0;
state=state0;
stat=state0;end

36
always@(posedgeclk)beginif(
i500000)begin
if(w == 100)begin
f = f+1; //—-increment of each data for each
devicew= 0;
end
else if (w < 100)
begini=0;
w =w+1;
state = stat; //—-moving to each device for each
countend
if (state == state0) begin //—unit
stateif(f==0)begin
y= 8'b11000000;
sel = 4'b1000 ; //—-selecting first
devicestat=state1;
end
if(f== 1)begin
y = 8'b11111001; //-/–data to be
displaysel=4'b1000;
stat =
state1;end
if(f== 2)begin
y = 8'b10100100; // —-code for selecting the segments in each
displaysel=4'b1000;
stat =
state1;end
if(f==3)beginy=8
'b10110000;
sel = 4'b1000
;stat=state1;en
d
if(f==4)beginy=8
'b10011001;
sel = 4'b1000
;stat=
state1;end
if(f==5)beginy=8
'b10010010;
sel = 4'b1000
;stat=state1;en
d
if(f==6)beginy=8
'b10000010;

37
sel=4'b1000;

38
stat =
state1;end
if(f==7)beginy=8
'b11111000;
sel = 4'b1000
;stat=state1;en
d
if(f==8)beginy=8
'b10000000;
sel = 4'b1000
;stat=state1;en
d
if(f== 9)begin
y= 8'b10010000;
sel = 4'b1000
;stat=state1;en
d
if(f==10)begin
y= 8'b10011000;
sel = 4'b1000
;stat=state1;
j=j+
1;f=0;
end
end
else if (state == state1)
beginif(j==0)begin
y= 8'b11000000;
sel = 4'b0100
;stat=state2;en
d
if(j==1)beginy=8
'b11111001;
sel = 4'b0100
;stat=state2;en
d
if(j==2)beginy=8
'b10100100;
sel = 4'b0100
;stat=state2;en
d
if(j==3)beginy=8
'b10110000;
sel = 4'b0100

39
;stat=state2;

40
end
if(j==4)beginy=8
'b10011001;
sel = 4'b0100
;stat=state2;en
d
if(j==5)beginy=8
'b10010010;
sel = 4'b0100
;stat=state2;en
d
if(j==6)beginy=8
'b10000010;
sel = 4'b0100
;stat=state2;
j=0;
k=k+
1;end
end
else if (state == state2)
beginif(k==0)begin
y= 8'b01000000;
sel = 4'b0010
;stat=state3;en
d
if (k == 1)
beginy=8'b01111
001;
sel = 4'b0010
;stat=state3;en
d
if (k == 2)
beginy=8'b00100
100;
sel = 4'b0010
;stat=state3;en
d
if (k == 3)
beginy=8'b00110
000;
sel = 4'b0010
;stat=state3;en
d
if (k == 4)

41
beginy=8'b00011
001;
sel = 4'b0010
;stat=state3;en
d

42
if (k == 5)
beginy=8'b00010
010;
sel = 4'b0010
;stat=state3;en
d
if (k == 6)
beginy=8'b00000
010;
sel = 4'b0010
;stat=state3;en
d
if (k == 7)
beginy=8'b01111
000;
sel = 4'b0010
;stat=state3;en
d
if (k == 8)
beginy=8'b00000
000;
sel = 4'b0010
;stat=state3;en
d
if(k==9)beginy=8
'b00011000;
sel=4'b0010;stat=
state3;endif (k ==
10)
beginy=8'b00010
000;
sel = 4'b0010
;stat=state3;k=
0;
n=n+1;
endend
if (state == state3)
beginif(n==0)begin
y= 8'b11000000;
sel = 4'b0001
;stat=state0;en
d
if (n == 1)
beginy=8'b11111

43
001;
sel = 4'b0001
;stat=state0;en
d
if (n == 2)
beginy=8'b10100
100;

44
sel = 4'b0001
;stat=
state0;end
if (n == 3)
beginy=8'b10110
000;
sel = 4'b0001
;stat=state0;en
d
if (n == 4)
beginy=8'b10011
001;
sel = 4'b0001
;stat=state0;en
d
if (n == 5)
beginy=8'b10010
010;
sel = 4'b0001
;stat=state0;en
d
if (n == 6)
beginy=8'b10000
010;
sel = 4'b0001
;stat=state0;
n=0;
end
end
end
end
endmodule

SIMULATIONRESULTS:

45
RESULT:

ThustheRealTimeClockwasdesignedandimplementedusingFPGA.

46
 EX.NO:10 Study of8 bit ALUonFPGAboard

AIM:

Todesignandverifythe8bitALUonFPGAboard

SOFTWAREREQUIRED:
XilinxISE
Spartan3EFPGAKit

THEORY:
Anarithmeticlogicunit(ALU)isadigitalcircuitusedtoperformarithmeticandlogicoperations. It
represents the fundamental building block of the central processing unit (CPU) of
acomputer.ModernCPUscontainverypowerfulandcomplexALUs.

PROCEDURE:

1. OpennewVerilog sourceeditor inXilinxISEtool

2. TypetheVerilogcodingfor8-BitALUinthenewfile
3. Savethefile.
4. Assignthe I/OSignaltothe FPGApackagepins
5. SynthesistheVerilogCode.
6. Placeand RoutetheDesignbyclick onImplementDesign
7. Generatethebitfile
8. ConfigurethebitfileonSpartan3E FPGAandverifytheresult

VERILOGCODING:
module
alu(input[7:0]A,
B,
input[3:0]ALU_Sel
output [7:0]
ALU_Out,outputCarry

47
Out);
reg[7:0]ALU_Result;

48
wire [8:0]tmp;

assign ALU_Out =
ALU_Result;assign tmp =
{1'b0,A} +
{1'b0,B};assignCarryOut=tmp[8];
always@(*)be
gincase(ALU_
Sel)
4'b0000://Addition
ALU_Result = A + B
;4'b0001://Subtraction
ALU_Result = A - B
;4'b0010: // Multiplication
ALU_Result = A *
B;4'b0011://Division
ALU_Result =
A/B;4'b0100://Logicalshiftl
eft
ALU_Result =
A<<1;4'b0101: // Logical
shift
rightALU_Result=A>>1;
4'b0110://Rotateleft
ALU_Result ={A[6:0],A[7]};
4'b0111://Rotateright
ALU_Result ={A[0],A[7:1]};
4'b1000: //Logical
andALU_Result=A&B;
4'b1001: //Logicalor
ALU_Result = A |
B;4'b1010: //Logicalxor
ALU_Result = A ^
B;4'b1011: //Logicalnor
ALU_Result = ~(A |
B);4'b1100: //Logical nand
ALU_Result =
~(A&B);4'b1101://Logicalxnor
ALU_Result = ~(A ^
B);4'b1110://

49
Greatercomparison
ALU_Result =(A>B)?8'd1:8'd0;
4'b1111://EqualcomparisonALU_Result=
(A==B)?8'd1:8'd0;
default:ALU_Result= A+B;

50
endcaseen
dendmodul
e

SIMULATIONRESULTS:

RESULT:

The 8 bit ALU was designed and simulated using Xilinx Software and implemented in
Spartan3Ekit.

51