18ECL48 Lab Manual

ANALOG CIRCUITS LAB 18ECL48
ANALOG CIRCUITS LABORATORY (18ECL48)
Subject Code : 18ECL48 I.A. Marks : 40

Hours/Week : 03 Exam Hours : 03
Total Hours : 36 Exam Marks : 60
VTU SYLLABUS
PART A : HARDWARE EXPERIMENTS
1 Design and setup the Common Source JFET/MOSFET amplifier and plot the frequency
response
2 Design and set up the BJT common emitter voltage amplifier with and without feedback and
determine the gain- bandwidth product, input and output impedances.
3 Design and set-up BJT/FET i) Colpitts Oscillator, and ii) Crystal Oscillator
4 Design active second order Butterworth low pass and high pass filters.
5 Design Adder, Integrator and Differentiator circuits using Op-Amp
6 Test a comparator circuit and design a Schmitt trigger for the given UTP and LTP values and
obtain the hysteresis.
7 Design 4 bit R – 2R Op-Amp Digital to Analog Converter (i) using 4 bit binary input from
toggle switches.
8 Design Monostable and a stable Multivibrator using 555 Timer.
and (ii) by generating digital inputs using mod-16 counter.
PART-B : Simulation using EDA software (EDWinXP, PSpice, MultiSim, Proteus,
CircuitLab or any other equivalent tool can be used)
9 RC Phase shift oscillator and Hartley oscillator.
10 Narrow Band-pass Filter and Narrow band-reject filter.
11 Precision Half and full wave rectifier.
12 Monostable and A stable Multivibrator using 555 Timer.
DEPT. OF ECE, ATMECE, MYSURU

EXPERIMENT NO: 01
DESIGN AND SETUP THE COMMON SOURCE JFET/MOSFET AMPLIFIER AND

PLOT THE FREQUENCY RESPONSE
AIM: To design and setup the common source JFET/MOSFET amplifier and plot the
frequency response
OBJECTIVE: To design the common source JFET/MOSFET amplifier and analyze

waveforms and to plot the frequency response.
CIRCUIT DIAGRAM:
XSC1
VDD
12V Ext Trig
+
R1 Rd _
B
82kΩ 1.5kΩ +
A
_ + _
Cc2
0.47µF Q1 0.47µF
Cc1
BFW10
V1
0.2 Vrms
1kHz
R2_DRB
0° Rs Cs
820Ω 100µF
POTENTIOMETER
Figure 1.1: Common Source FET Amplifier
OPERATION:
The circuit diagram of FET amplifier is shown in Figure 1.1. The source of FET is made
common to input and output side, hence the name common source amplifier. Since the current
flowing through the gate terminal of FET is 0, voltage divider circuit is employed to bias the
transistor. The FET is biased to have Q point in the middle of the linear region to get
maximum output swing.

DESIGN
Selection of FET:
Select BFW10 or BFW11. BFW10 is a N-channel JFET VHF/UHF amplifier. The B means
silicon, F means Transistor - high frequency, low power which is a bit random as BF can
mean a high frequency bipolar transistor (BJT) or FET. The W10 part is the manufacturer's
designation. W is used to indicate that it is used for commercial or industrial purpose and 10 is
the sequential number
DC bias conditions:
VDD= 12V, VGS=-1V, VRS=20% of VDD=2.4V

VRD=VDS=45% of VDD= 5.4V
For FET choose Idss=8mA
Vp=-4v,Vgs=-1.8v.
Id= Idss [1-Vgs/4]2
Id=8x10-3[1- (-1.81)/4]2
Id=2.4mA
Applying KVL to the outer loop
Vdd=Id(Rd+Rs)+Vds
Rd+Rs=Vdd-Vds/Id
12-6/2.4m=2.5x103
Rd+Rs=2.1kΩ.
Choose Rd=1.5kΩ and Rs=820Ω.
Design of R1 and R2 :
Let Vdd*R2/R1+R2= VGS+VRS

R2/R1+R2= VGS+ Id+ Rs/ Vdd
R2/R1+R2=-1.81+(2.4x10-3)x820/10
R2/R1+R2=0.15
R2=0.15 R1+0.15 R2
R2/R1=0.15/0.85
R2/R1=0.176
R2=0.176 R1

Use a large value for R1 to ensure zero gate current.So take standard value of resistors as
R1=82k Ω and R2~10K to15k Ω (DRB)
Design of bypass capacitor CS
Take XCS= Rs/10 at 150 Hz to bypass this frequency.
Then XCS< 100Ω
So, CS ≥ 1/2πf*820= 100µF use CS=100 µF
Assume coupling capacitors CC1=0.47µF and CC2 =0.47µF
PROCEDURE:
1. Test the components and build the circuit as per the circuit diagram shown in Figure 1.1.
2. The voltage from drain to soure should be approximately half of the DC supply voltage
(To Check Biasing condition)
3. Apply the input voltage 0.2Vp-p and 1K Hz sinusoidal signal using signal generator.
4. Observe the output voltage on the CRO, which should be the amplified version of input
voltage. Also observe the phase reversal of the output signal compared to input signal.
TO OBTAIN FREQUENCY RESPONSE:
1. Vary the frequency of the input from 20Hz to 3MHz range, note down the frequency
of the signal and corresponding output voltage.
2. Plot the frequency versus gain in dB and calculate BW.
OBSERVATION:
Peak to Peak input voltage Vi =_____
Table 1.1:Tabular Column of Common Source JFET/MOSFET Amplifier.
Frequency Peak to peak output

Gain A = Vo/Vi Gain in dB = 20 Log10 (A)
in Hz voltage Vo
100Hz
200Hz
...
...
FL = ____________
FH = ____________
BW = FH – FL = ________________
Input impedance Zi = _________
Output impedance Zo = ________

EXPECTED OUTPUT:
0.2V
0.8V
Figure 1.2: Expected output and frequency response graph
RESULT: Common Source FET amplifier was designed and an experiment was conducted
to find the following parameters.
Peak Gain in dB = ______________
Bandwidth = __________________
OUTCOME:
Students are able to understand the characteristics of JFET and able to calculate the drain
resistance and mutual conductance and amplification factor.

EXPERIMENT NO: 02
DESIGN AND SET UP THE BJT COMMON EMITTER VOLTAGE AMPLIFIER WITH
AND WITHOUT FEEDBACK AND DETERMINE THE GAIN- BANDWIDTH
PRODUCT, INPUT AND OUTPUT IMPEDANCES.
AIM: To design and set up the BJT common emitter amplifier using voltage divider bias
with and without feedback and to determine the gain bandwidth product from its frequency
response and its input and output responses.
OBJECTIVE:
Design and study the performance common emitter amplifier using voltage divider bias with
and without feedback.
CIRCUIT DIAGRAM:
XSC1
VCC
12V Ext T rig
+
_
RC A B
2.2kΩ + _ + _
C2
R1
47kΩ 0.47µF
C1
Vi Q1SL100
V1
0.47µF
0.2 Vrms R2 2N2222
100 Hz 8.1kΩ
CE
0° C3
RE 47µF
560Ω
Figure 2.1: BJT Common Emitter Amplifier without feedback
DESIGN: (With and without Feedback)
VCC=12V, β (Gain)=145, Let Ic(Collector current) =2mA

The amplifier gives good stabilization for both leakage and current gain when,
VRE=10% of VCC
VCE=50% of VCC

To determine VCE
VCE=VCC/2=6V
To find RE
VRE=IERE and IC=IE
RE=VRE/IC =1.2/2mA
RE=600Ω.
Choose RE=560Ω
To find RC
Apply KVL to output circuit
VCC=ICRC+VCE+IERE
RC=VCC-VCE-ICRE/IC
RC=12-6-1.2/2m
RC=2.4KΩ
Choose RC=2.2KΩ
To find R1 and R2
From Approximation analysis(Voltage divider bias )
R2≤βRE/10
R2≤560*145/10
R2=8.12KΩ
WKT, VBE=VB-VE
VB=VBE+VE
VB=0.7+1.2
VB=1.9V
VB(R1+R2)=VCC*R2
R1=43.05KΩ
Choose R1=47KΩ
Choose C1=C2=0.47µF, CE=47µF

CIRCUIT DIAGRAM:
XSC1
VCC
12V Ext T rig
+
_
RC A B
2.2kΩ + _ + _
Cc2
R1
47kΩ 0.47µF
Cc1
Q1
SL100
V1
0.47µF
0.2 Vrms R2
100 Hz 8.1kΩ
0°
RE
560Ω
Figure 2.2: BJT Common Emitter Amplifier with feedback
Figure 2.3: Experimental setup to measure Input Impedance
Figure 2.4: Experimental setup to measure Output Impedance

OPERATION:
Amplifier is an electronic device which magnifies the input signal applied to it. Amplifier
circuits are used in almost all the communication systems. The circuit diagram of BJT
common emitter amplifier using voltage divider bias without feedback is shown in Figure 2a.
The voltage divider bias circuit offers more stable operating point.
PROCEDURE:
1. Test the components and build the circuit as per the circuit diagram shown in Figure
2.1.
2. The voltage from collector to ground should be approximately half of the DC supply
voltage.
3. Apply the input voltage to 40mVp-p and 1000 Hz using signal generator.
4. Observe the output voltage on the CRO, which should be the amplified version of
input voltage. Also observe the phase reversal of the output signal compared to input
signal.
TO OBTAIN FREQUENCY RESPONSE
1. Varying the frequency of the input from 20Hz to 3MHz range, note down the
frequency of the signal and corresponding output voltage
2. Note the reading in tabular column
3. Plot the frequency versus gain in dB and calculate BW
TO MEASURE INPUT IMPEDANCE
1. Connect the DRB in series with input as shown in figure 2.3.

2. Set the DRB to minimum value (0ω).
3. Increase the resistance of DRB till the output voltage reduces to half of its initial value
4. The resistance of DRB at which the output voltage reduces to half of its initial value is
the input impedance of the amplifier
TO MEASURE OUTPUT IMPEDANCE
1. Connect the DRB as shown in Figure 2.4.

2. Set the DRB to maximum value.

3. Decrease the resistance of DRB till the output voltage reduces to half of its initial
value.
4. The resistance of DRB at which the output voltage reduces to half of its initial value is
the output impedance of the amplifier.
5. Repeat the above steps for amplifier with feedback for the circuit shown in Figure 2b.
OBSERVATION:
1. Amplifier without feedback

Peak to Peak input voltage Vi = _________________
Table 2.1: Tabular Column of Common Emitter Amplifier without feedback.
Frequency
Peak to peak output
in Gain A = Vo/Vi Gain in dB = 20 Log10 (A)
voltage Vo
Hz
100Hz
200Hz
...
...
FL = ____________
FH = ____________
BW = FH – FL = ________________
Input impedance Zi = _________

Output impedance Zo = ________
2. Amplifier with feedback

Peak to Peak input voltage Vi = _________________
Table 2.2: Tabular Column of Common Emitter Amplifier with feedback.
Frequency Peak to peak output

Gain A = Vo/Vi Gain in dB = 20 Log10 (A)
in Hz voltage Vo
100Hz
200Hz
...
...

FL = ____________
FH = ____________
BW = FH – FL = ________________
Input impedance Zif = _________
Output impedance Zof = ________
RESULT: The circuit of voltage divider common emitter BJT amplifier with and without
feedback was designed and frequency response of the amplifier was found.
Maximum Gain of amplifier without feedback = _______________
Bandwidth of amplifier without feedback = _________________
Maximum Gain of amplifier with feedback = _______________
Bandwidth of amplifier with feedback = _________________
Gain Bandwidth product of amplifier without feedback = _________
Gain Bandwidth product of amplifier with feedback = _________
OUTCOME:
 Students understand the application of Voltage divider bias.
 Students understand how to increase the frequency and plot the graph to find out the
gain bandwidth product from its frequency response graph.

EXPERIMENT: 03
DESIGN AND SET-UP BJT/FET I) COLPITTS OSCILLATOR, AND II)

CRYSTAL OSCILLATOR
(I) COLPITTS OSCILLATOR

AIM:
To design and set up Colpitts oscillator using BJT and to determine its frequency of
oscillation.
OBJECTIVE:
To study and design the Colpitts oscillator using BJT.
CIRCUIT DIAGRAM:
Figure 3.1: Colpitts Oscillator Circuit
OPERATION:
Colpitt oscillator consists of a tank circuit made of an inductor connected in parallel to two
series connected capacitors. The feedback signal is tapped at a point connecting two
capacitors. The transistor amplifier introduces 1800 phase shift which is then compensated by
the tank circuit which introduces a further 1800 phase shift. Frequency can be adjusted by
varying the inductor. The frequency of oscillations is given by
F=1/(2*π* sqrt(Ceq* L))

Where Ceq = C1C2/(C1 + C2) and M is mutual inductance of the coils.
Design:
VCC=12V, β=145, Let Ic=2mA

VRE=10% of VCC
VCE=50% of VCC
To determine VCE
VCE=VCC/2=6V
To find RE
VRE=IERE and IC=IE
RE=VRE/IC =1.2/2mA
RE=600Ω.
Choose RE=560Ω
To find RC
VCC=ICRC+VCE+IERE
RC=VCC-VCE-ICRE/IC
RC=12-6-1.2/2m
RC=2.4KΩ
Choose RC=2.2KΩ
To find R1 and R2
R2≤βRE/10
R2≤560*145/10
R2=8.12KΩ
WKT, VBE=VB-VE
VB=VBE+VE

VB=0.7+1.2
VB=1.9V
VB(R1+R2)=VCC*R2
R1=43.05KΩ
Choose R1=47KΩ
Tank circuit Design

F0=1/2πL1C
Choose f0=100KHz and L1=3.5mH
Ceq=0.723nF
Select C3=1nF and C4=2nF
Assume Cc1= CC2=0.47µF and CE=47µF
Procedure:
1. Test the components and build the circuit as per the circuit diagram shown in Figure
3.1.
2. Check the working of amplifier using signal generator and oscilloscope.
3. Connect the feedback network to the amplifier circuit.
4. Observe the output voltage on the CRO. Use potentiometer if oscillations are not
triggered.
OBSERVATION:
Frequency of oscillations = _____________
RESULT: Colpitt oscillator was designed and tested. The frequency of oscillations
_______________
OUTCOME:
 It helps the students to learn the basic working of LC circuits.

 On completion of the experiment the student understands why LC oscillators are used
for high frequency range.

(II) CRYSTAL OSCILLATOR
AIM:
To design and set-up the crystal oscillator and determine the frequency of oscillation.
OBJECTIVE:
To study and design the crystal oscillator using BJT.
CIRCUIT DIAGRAM:
Figure 3.2: Crystal Oscillator Circuit
OPERATION:
The circuit of crystal oscillator is shown in Figure 3.2. A voltage divider biased transistor
circuit provides adequate amplification. Crystal exhibits a property that when mechanical
stress is applied across one set of its faces, a difference of potential develops across the
opposite faces. This property is called piezoelectric effect. Similarly, a voltage applied across
one set of faces of the crystal causes mechanical distortion in the crystal shape. Every crystal
has its own resonant frequency of oscillation and is very precise.
Crystal can be electrically represented as an inductor connected in parallel with
capacitor. Thus a tank circuit can be formed using crystal. This tank circuit connected in the

feedback path of an amplifier satisfies Barkhausen criteria of oscillations i.e., the loop gain of
the circuit is 0 and total phase shift through the loop is 360 0 or 00.
The advantage of crystal oscillator is that due to precise resonant frequency of crystal,
the oscillations are very stable. Crystal do not wear out very easily and hence can operate for a
long time.
Design:

VRE=10% of VCC
VCE=50% of VCC
To determine VCE
VCE=VCC/2=6V
To find RE
VRE=IERE and IC=IE
RE=VRE/IC =1.2/2mA
RE=600Ω.
Choose RE=560Ω
To find RC
VCC=ICRC+VCE+IERE
RC=VCC-VCE-ICRE/IC
RC=12-6-1.2/2m
RC=2.4KΩ
Choose RC=2.2KΩ
To find R1 and R2
R2≤βRE/10
R2≤560*145/10
R2=8.12KΩ
WKT, VBE=VB-VE
VB=VBE+VE
VB=0.7+1.2
VB=1.9V
VB(R1+R2)=VCC*R2
R1=43.05KΩ
Choose R1=47KΩ
Choose CC1=Cc2=0.47µF, CE=47µF
Tank circuit Design:

Consider the crystal (X1) frequency as mentioned in the given component.
Choose C3=C4=22pF
PROCEDURE:
1. Test the components and build the amplifier circuit as per the circuit diagram shown in
Figure 3.2.
2. The voltage from collector to ground should be approximately half of the DC supply
voltage.
3. Check whether the amplifier circuit is working properly using signal generator and
oscilloscope.
4. Connect the feedback circuit which involves crystal to the amplifier and observe the
waveforms on CRO.
OBSERVATIONS:
Frequency of Oscillations = ______________________ Hz.
RESULT:
The crystal oscillator circuit was designed and successfully tested. The frequency of
oscillations is _______________

OUTCOME:
 It helps students to learn the design basic amplifiers and to use a crystal of given
frequency.
 The student will understand the functioning of each component in the circuit and thus
gains the required basic knowledge

EXPERIMENT NO: 04
DESIGN ACTIVE SECOND ORDER BUTTERWORTH LOW PASS AND HIGH PASS
FILTERS.
AIM:
i) To design a Second Order Butterworth Active Low Pass Filter (LPF) for a given cutoff
frequency fH = 1 kHz (<10 KHz), draw the frequency response and verify the roll-off factor.
ii) To design a Second Order Butterworth Active High Pass Filter (HPF) for a given cutoff
frequency fL = 1 kHz (10 KHz), draw the frequency response and verify the Roll-off factor
OBJECTIVE:
To enable students to get practical experience in design, assembly, testing and evaluation of
active second order Butterworth low pass and high pass filters.
CIRCUIT DIAGRAM OF ACTIVE LPF:
R1 R2
1kΩ 1kΩ
V1 XSC1
12 V
Ext T rig
+
4 U1 _
A B
+ _ + _
2
XFG1 C1 C2 741 6
3
0.01µF 0.01µF 7 1 5
R4
R3 7.5kΩ
7.5kΩ
V2
12 V
Figure 4.1: Circuit Diagram of active Low Pass Filter

OPERATION:
Filter is a frequency selective circuit that passes a specified band of frequencies & attenuates
signals of frequencies outside this band. Filters may be classified in a number of ways.
1. Analog or Digital
2. Passive or Active
3. Audio (AF) or Radio-frequency (RF)

Analog Filters are designed to process analog signals, while digital filters process analog
signals using digital techniques. Depending on the type of elements used in their construction,
filters may be classified as passive or Active. Active filters, on the other hand, employ
Transistors or Op-amps in addition to the resistors and capacitors. The type of element used
dictates the operating frequency range of the filter. RC filters are commonly used for audio or
low frequency operation, whereas LC or Crystal filters are employed at RF or High
frequencies. Crystals provide more stable operation at higher frequencies because of their high
Q value (Figure of Merit).The most commonly used filters are a)Low Pass Filter,b)High Pass
Filter,c) Band Pass Filter d) Band Reject Filter e)All Pass Filter.
Each of these filters uses an op-amp as the active element and resistors and capacitors
as the passive elements. A Low Pass filter has a constant gain from 0 Hz to a high cut-off
frequency fH. Therefore, the bandwidth is also fH. At fH the gain is down by 3 dB; after that (f
 fH) it decreases with the increase in the input frequency. The frequencies between 0 Hz and
fH are known as the pass band frequencies, where as the range of frequencies, those beyond fH,
that are attenuated includes the stop band frequencies. A High pass filter has the stop band 0
<f < fL and a pass band f > fL .fL is the low cutoff frequency, and f is the operating frequency.
High Pass filters are often formed by inter changing the frequency determining resistors and
capacitor in the low pass filter. i.e., a first order high pass filter is formed from first order low
pass filter by interchanging components R and C. Similarly, a second order high pass filter is
obtained from second order low pass filter if R and C are interchanged and so on.
Model Plot:
Figure 4.2:Frequency plot active Low pass filter

DESIGN:
Op-amp supply voltage V1=-12V and V2 =+12V; Cut-off Frequency, fH = 2 kHz

Gain AF =1.586
For Second order Low Pass Butterworth Filter response, the voltage gain magnitude equation
is
V0 Af
=
Vin 1  (f / fH)4
Where AF = 1 + RF/ R1 = Pass Band Gain of the filter.
f= Frequency of input Signal.
fH=1/2R2R3C2C3 = High Cut-off frequency.
Given high cut off frequency fH. = 2 kHz
To simplify the design calculation, Set R3=R4=R and C1=C2=C.
 fH =1/2RC
Choose C=0.01µF
 R = 1/2fHC  7.9k (Standard value 7.5k)
For the given value of AF , Find RF by assuming the value of R1 ,using the equation
AF = 1 + RF/ R1;
Let R1 =1k and RF=R2=1kΩ
PROCEDURE:
1. Connect the circuit as shown in Figure 4.1.

2. Make C2 Ground.
3. Set V in = 2V p-p in the Function generator.
4. Check the output at pin no. 6 i.e. verifies the low pass filter action by varying frequency.
5. Also check the maximum constant output voltage (approximately equal to input voltage).
6. Connect the op- Amp and remaining connections.
7. By varying the frequency (100Hz to 10 kHz) in the function generator, note down the
peak-to-peak voltage of the output waveform in the oscilloscope.
8. Also check the maximum constant output voltage (approximately equal to 1.5 times of
input voltage).
9. Plot the frequency response in the Semi-log sheet.
10. Draw -3dB line and Find the Cutoff frequency and Roll off factor from the plot.
11. Roll-off rate: In the transition band, the rate at which the gain falls (or increases in case of
HPF) is the Roll-off rate. Choose two points in this band such that the frequencies are in the
ratio 1:10, find the corresponding gains and the difference between them. This gives the Roll-
off rate expressed as _______ dB/decade.
12. From 700 Hz to 1.5 KHz take output in steps of 100Hz.

Vin = _______Volts p-p
Table 4.1: Tabular Column of Low pass filter
Normalized
Sl. V out gain (NG) Gain (dB) =
Freq (Hz) Gain=Vo/Vin
No. (Volts) 20log10(NG)
Normalized gain = Gain / Gain(max)
Result of LPF:
Cut off frequency (Theoretical) = 2 kHz

Cut off frequency (Practical) =
Roll off Factor (Theoretical) = -40 dB/decade
Roll off Factor (Practical) =
CIRCUIT DIAGRAM OF ACTIVE HPF:
R1 R2
1kΩ 1kΩ
V1 XSC1
12 V
Ext Trig
+
4 U1 _
A B
+ _ + _
2
XFG1 C1 C2 741 6
3
0.01µF 0.01µF 7 1 5
R4
R3 7.5kΩ
7.5kΩ
V2
12 V
Figure 4.3: Circuit Diagram of active HPF

MODEL PLOT:
Figure 4.4:Frequency response active High pass filter
DESIGN:
Op-amp supply voltage V1= -12V and V2 =+12V; Cut-off Frequency, fH = 2 kHz
Gain AF =1.586. For Second order Low Pass Butterworth Filter response, the voltage gain
magnitude equation is
V0 Af
=
Vin 1  (f / fH)4
Where AF = 1 + RF/ R1 = Pass Band Gain of the filter.
f= Frequency of input Signal.
fH=1/2R2R3C2C3 = High Cut-off frequency.
Given Low cut off frequency fH. = 2 kHz
To simplify the design calculation, Set R3=R4=R and C1=C2=C.
 fH =1/2RC
Choose C=0.01µF
 R = 1/2fHC  7.9k (Standard value 7.5k)
For the given value of AF , Find RF by assuming the value of R1 ,using the equation
AF = 1 + RF/ R1;
Let R1 =1k and RF=R2=1kΩ
PROCEDURE:
1. Connect the circuit as shown in the Figure 4.3.

2. Make C2 Ground.
3. Set Vin = 2Vp-p in the function generator.

4. Check the output at pin no.6 of opamp i.e. verify the high pass filter action by varying
frequency.
5. Also check the maximum constant output voltage (approximately equal to input voltage).
6. Connect the op- Amp and remaining connections.
7. By varying the frequency (100Hz to 10 kHz) in the function generator, note down the
peak-to-peak voltage of the output waveform in the oscilloscope.
8. Also check the maximum constant output voltage (approximately equal to 1.5 times of
input voltage).
9. Plot the frequency response in the given semi log sheet.
10. Find the cutoff frequency and Roll off factor from the plot.
11. From 700 Hz to 1.5 KHz take output in steps of 100Hz
Table 4.2: Tabular Column of High pass filter

Vin = _________ VP-P
Normalized
Gain= Gain (dB) =
Sl. No. Freq (Hz) Vout (V) gain
Vo/Vin 20 log10(NG)
(NG)
RESULT OF HPF:
Cut off frequency (Theoretical) =2 kHz

Cut off frequency (Practical) =
Roll off Factor (Theoretical) = +40 dB/decade
Roll off Factor (Practical) =
OUTCOME:
Following are outcomes of second order active low/high pass filter.

 It helps students to learn the design of filters which are the basic building blocks in
any communication system and will understand various terminologies used therein.
 LPF are used in the transmitter circuits for band limiting the base band signals and at
the receiver end to demodulate and get back the original base band data.

EXPERIMENT NO: 05
Design Adder, Integrator and Differentiator circuits using Op-Amp
AIM: To design adder, integrator and differentiator circuits.
OBJECTIVE:
This experiment enables students to design, demonstrate and analyze adder, integrator and
differentiator using Op-Amp.
CIRCUIT DIAGRAM :
Rf 10kΩ
XSC1
V4
12 V Ext Trig
+
4 U1 _
A B
+ _ + _
2
741 6
R2 R1
3
10kΩ 10kΩ
7 1 5
V1 V2 V3
1V 2V 12 V
Figure 5.1: Circuit diagram of an Adder
THEORY:
Adder: The Summing Amplifier is another type of operational amplifier circuit configuration
that is used to combine the voltages present on two or more inputs into a single output voltage. In
the inverting operational amplifier it has a single input voltage, (Vin) applied to the inverting
input terminal. If we add more input resistors to the input, each equal in value to the original
input resistor, (Rin) we end up with another operational amplifier circuit called a Summing
Amplifier.

DESIGN:
Let V 3= +12V and V4= -12V
V0=(I Rf)=- [I1+I2] Rf
If R1=R2=R then
V0=-Rf//R(V1+V2)
If Rf=R then
V0=-(V1+V2)
Therefore choose R1=R2=Rf=10KΩ
V1=1V and V2=2V
Note: V 1 and V 2 are Reference voltages and can be set accordingly.
PROCEDURE FOR INTEGRATOR:
1. Connections are made as per the integrator circuit diagram shown in fig 5.1.
2. Apply Vref voltages to V1 and V2 and note the output.
3. Note down the input and output waveforms.
EXPECTED OUTCOME:
1V
V1 t(s)
2V
V2 t(s)
V0 t(s)
3V
Figure 5.2: Output of an Adder

Integrator: Integrator circuit as its name implies, performs the mathematical operation of
integration, that is the output is the integration of the given input signal voltage. The integrator
can be constructed from basic inverting amplifier when feedback resistor Rf is replaced by
capacitance. The minus sign indicates a 1800 phase shift of the output waveform Vo with respect
to the input signal.
V0=-1/RCf
CIRCUIT DIAGRAM :
C1
0.01µF
XFG1 XSC1
V2
2V Ext T rig
+
4 U1 _
A B
R + _ + _
2
15kΩ 741 6
3
7 1 5
V1
12 V
Figure 5.3: Circuit diagram of an Integrator
DESIGN:
Design of integrator to integrate at cut-off frequency(f)= 1 KHz.
Let V 1= +12V and V2= -12V
Assume C1 = 0.01µf
f=1/2πRC
R= 15KΩ
PROCEDURE FOR INTEGRATOR:
4. Connections are made as per the integrator circuit diagram shown in fig 5.3.
5. Apply square wave of amplitude , 1 KHz to the input of integrator Circuit.

EXPECTED WAVEFORM:
1V(in)p-p
1V(o)p-p
Figure 5.4: Output of an Integrator
DIFFERENTIATOR:
Differentiator circuit as its name implies, performs the mathematical operation of differentiation,
that is the output is the derivative of the given input signal voltage. The differentiator can be
constructed from basic inverting amplifier when input resistor R is replaced by capacitance. The
minus sign indicates a 1800 phase shift of the output waveform Vo with respect to the input
signal.
V0=-Rf C dVin/dt
CIRCUIT DIAGRAM :
R1
15kΩ
XSC1
XFG1 V2
2V Ext T rig
+
4 U1 _
C1 R
A B
+ _ + _
2
0.01µF 15kΩ 741 6

3
7 1 5
V1
12 V
Figure 5.5: Circuit diagram of Differentiator

DESIGN:
Let V 1= +12V and V2= -12V
Design of integrator to integrate at cut-off frequency(f) =1 KHz.
Assume C1 = 0.01µf,
f=1/2πRC
R=R1= 15KΩ
PROCEDURE FOR DIFFERENTIATOR:
1. Connections are made as per the circuit diagram shown in Figure 5.5.
2. Apply square wave of amplitude 1Vp-p, 1 KHz to the input of differentiator circuit.
EXPECTED WAVEFORM:
1V(in)p-p
1V(o)p-p
Figure 5.6: Output of Differentiator

RESULT:
The adder, integrator and differentiator circuits are designed and waveforms observed.
OUTCOME:
This experiment enables students to gain hands-on experience in building adder, integrator and
differentiator using Op-Amp for a given specification using the basic building blocks.

EXPERIMENT NO: 06
Test a comparator circuit and design a Schmitt trigger for the given UTP
and LTP values and obtain the hysteresis.
AIM:
Test a comparator circuit and design a Schmitt trigger for the given UTP and LTP values and
obtain the hysteresis.
OBJECTIVE:
To study the design of a Schmitt trigger to convert any regular or irregular shaped input
waveform into a square wave output voltage.
CIRCUIT DIAGRAM:
C2
0.47µF R1
XSC1
20kΩ
Ext T rig
+
V2 _
12 V A B XBP1
+ _ + _
XFG1 IN OUT
7 1 5 U1
3
0.47µF
C1 6
R3 741
2
10kΩ
4 R2
R4 1kΩ
10kΩ
V1
12 V
Figure 6.1: Circuit diagram of Schmitt trigger.

THEORY:
Figure 6.1 shows an inverting comparator with positive feedback this circuit convert an
irregular shaped waveform to a square wave or pulse the circuit is known as Schmitt trigger for
squaring circuit figure shows the positive feedback comparator with signal is applied at negative
input the input voltage v i triggers the output voltage we not every time it exceeds certain voltage
levels called the upper threshold voltage and lower threshold voltage as shown in figure as shown
in the figure these threshold voltage are derived using potential divider are 1 - R2 the voltage
across R1 is fed back to the non inverting input of the opamp the voltage across R1 depends on
the value and polarity of the output voltage be not when we not is equal to plus 20 at the voltage
across R1 is called upper threshold voltage and is given as formula on the other and when we not
is equal to minus 20 at the voltage across R1 is called as the lower threshold voltage and is given
by formula the comparator with positive feedback is said to exist is terraces a dead band
condition that is when the input of the comparator exceed b u t its output switches from plus visa
2 - Visat and revert back to its original state plus we start when the input goes below vlt as shown
in figure the hysteresis voltage is equal to difference between b u t and vlt
Let Vref=3.33V,
Assume UTP=4V, LTP=2V,
assume, Vsat=10V
R2=90K, R1=10K~100K,
PROCEDURE:
1. Rig up the inverting Schmitt trigger circuit using op-amp 741 as shown in the Figure 6.1.
2. Apply a sinusoidal input signal and set the input signal amplitude to about 6V (5 to 6V)
and adjusts the input frequency to a suitable value. (say from 100Hz to 2KHz).
3. Obtain the input signal and o/p signal at pin no 6, waveforms on the CRO and display
them.
4. Note down the UTL(upper threshold limit) corresponding to the UTP(upper threshold
peak) from the input signal at which the output voltage falls abruptly from +Vsat to –Vsat
on CRO. UTL should be 4V.

5. Note down LTL(Lower threshold limit) corresponding to the LTP(Lower threshold Peak)
from the input signal wave form at ehich the output voltage increses abruptly from –Vsat
to + Vsat using CRO. LTL should be 2V.
EXPECTED WAVEFORM:
V0 (v)
t(s)
Figure 6.2: Output waveform of Schmitt trigger
Figure 6.3: Hysteresis curve
RESULT:
Comparator circuit for Schmitt trigger is designed for the given UTP and LTP values and
hysteresis curve is obtained.
OUTCOME:
Students are able to understand the design of comparator circuit and how it can be used as
Schmitt trigger to convert any signal(waveform) to square waveform.

EXPERIMENT NO: 07
Design 4 bit R – 2R Op-Amp Digital to Analog Converter (i) using 4 bit binary input from
toggle switches and (ii) by generating digital inputs using mod-16 counter.
AIM: To Design and test R-2R DAC using Op-amp
OBJECTIVE:
To Understand the implementation of 4-bit R – 2R Op-Amp Digital to Analog Converter (using
4-bit binary input from toggle switches and by generating digital inputs using mod-16 counter.
CIRCUIT DIAGRAM:
Figure 7.1: Circuit diagram of R-2R DAC

THEORY:
DAC converts digital input signal to a proportional analog output. For driving analog devices
like CRT, XY recorder etc the signal required should be in analog form. If the signal available is
in digital form, it should be first converted into analog form, before feeding it to analog devices,
by using DACs. D3 to D0 can be either Vref or 0V.
Design:
Take opamp µA741 with voltage levels +VCC =±12V

Resolution= Vref / (2n -1) where n is number of digital inputs to the DAC.
In this circuit number of digital inputs (n=4)
If Vref is 5V (from trainer kit) then resolution = 0.33V

Choose R = 5kΩ Hence 2R = 10KΩ
Accuracy is a comparison of actual output voltage with expected output

Accuracy = Vofs / (2n -1) x 2
Where,
Vo (fs) = D (decimal value of digital input) x resolution (The output full scale voltage)
Vo=(23D3+22D2+2D1+20D0) Vref/2n*2/3
PROCEDURE:
1. Connect the circuit diagram as shown in Figure 7.1. observe the O/P DC voltage with
multimeter.
2. Connect the circuit with op-Amp.
3. Apply different combinations of digital inputs.
4. Observe the o/p DC voltage-using multimeter.
5. Measure the Step size and resolution.
EXPECTED WAVEFORM: -
Analog O/P Signal Staircase output
V
1000
0100
1100
0010
0000
Digital Input
Figure 7.2: staircase waveform of an R-2R DAC

TABULAR COLUMN:
Table 7.1: Tabular column of R-2R DAC
S.No Decimal Binary Equivalent Theoretical Analog Practical Analog

Number D3 D2 D1 D0 o/p o/p
1 0 0 0 0 0 0
2 1 0 0 0 1 0.20833
16 15 1 1 1 1 3.125
Result: R-2R DAC using op-Amp is tested and designed.
OUTCOME:
This experiment enables students to,

 Differentiate between Digital to Analog Converter and Analog to Digital Converter.
 Understand the difference between uniform and non-uniform quantization.
 Analyze staircase waveform for 4-bit R – 2R Op-Amp
 Calculate resolution for above Digital to Analog Converter

EXPERIMENT NO: 08
DESIGN MONOSTABLE AND A STABLE MULTIVIBRATOR USING 555 TIMER.
AIM:
(a) To design and implement an Astable Multivibrator using 555 timer to generate a square
wave of given Duty cycle and frequency
(b) Design Monostable Multivibrator for given pulse width w
OBJECTIVE:
To enable students to design, demonstrate and analyse Monostable and Astable Multivibrator
using 555 Timer for various duty cycles.
CIRCUIT DIAGRAM :
0.1µF
Figure 8.1: Circuit diagram of Asymmetrical Astable Multivibrator

THEORY
A 555 timer is a monolithic timing circuit that can produce accurate and highly stable time delays
or oscillations, some of the applications of 555 are square wave generator, Astable and
MonoStable Multivibrator.
Astable Multivibrator is a free running oscillator has two quasi stable state in one state o/p
voltage remains low for a time interval of Toff and then switches over to other state in which the
o/p remains high for an interval of Ton the time interval Ton and Toff are determined by the
external resistors a capacitor and it does not require an external trigger, when the power is
switched on the timing capacitor begins to charge towards 2/3 Vcc through R A & RB, when the
capacitor voltage has reached this value, the upper comparator of the timer triggers the flip flop
in it and the capacitor begins to discharge through RB when the capacitor voltage reaches 1/3
Vcc the lower comparator is triggered and another cycle begins, the charging and discharging
cycle repeats between 2/3 Vcc and 1/3Vcc for the charging and discharging periods t 1and t2
respectively. Since the capacitor charges through RA and RB and discharges through RB only the
charge and discharge are not equal as a consequence the output is not a symmetrical square wave
and the multivibrator is called an asymmetric astable multivibrator.
DESIGN:
(i). A square wave of given Duty cycle and frequency
Use 555 timer and its voltage(VCC) is +5V.

For unsymmetrical square wave Let Duty cycle >50%
TON = 0.693(RA+ RB)C for charging time
TOFF =0.693 RBC for discharging time
(60%) Duty cycle = TON = TON

TON  TOFF T
TOFF = T- TON
Assume C= 0.1µF TOFF =0.693 RBC TON = 0.693(RA+RB) C
If f= 2KHz then RA=1.433=1.5kΩ and RB=2.886KΩ

Similarly for D<50% Ton<Toff
TOFF = 0.693(RA+ RB)C for charging time

TON =0.693 RAC for discharging time
Assume C for given f and determine R A and RB
EXPECTED OUTPUT WAVEFORM:

Upper threshold voltage
=2/3*Vcc
Vc at pin 6
Lower threshold
Voltage =Vcc/3
Vout at Toff
pin 3
t
Ton
Figure 8.2: Output of Asymmetrical Astable Multivibrator
PROCEDURE:
1. For Asymmetric connections are made as shown in the Figure 8.1.

2. Switch on the DC power supply unit.
3. Observe the wave form on CRO at pin 3 and measure the o/p pulse amplitude.
4. Observe the wave form on CRO at pin 6 and measure Vc max and Vc min.
5. Verify that Vc max=2/3Vcc and Vc min=1/3 Vcc
6. Calculate the duty cycle D, o/p frequency and verify with specified value.
7. For symmetric Connections are made as shown in the circuit diagram 8.2.
8. Vary DRB until we will get Symmetric wave form (Ton = Toff).
9. Repeat steps 3 to 6.

(B) MONOSTABLE MULTIVIBRATOR:

Mono Stable Multivibrator has a stable state and a quasi-stable state, the output of it is normally
low and it corresponds to reset of the flip flop in the timer, on the application of external negative
trigger pulse at pin 2 the circuit is triggered and the flip flop in the timer is set which in turn
releases the short across C and pushes the output high, At the same time the voltage across C
rises exponentially with the time constant RAC and remains in this state for a period R AC even if
it is triggered again during this interval, When the voltage across the capacitor reaches 2/3 Vcc,
the threshold comparator resets the flip flop in the timer which discharges C and the output is
driven low the circuit will remain in this state until the application of the next trigger pulse
CIRCUIT DIAGRAM:
Figure 8.3: Circuit diagram of Monostable Multivibrator
Design:
Given Pulse width W= 0.5ms
We know that W=1.1*RA*C
Assume RA=4.7kΩ and calculate C.

For Differentiator circuit,

Choose RtCt <<W
i.e. RtCt < W/10 (assume Rt=1k & find Ct)
Ct=0.01µF
Duty cycle D=W/T where T=1/f (f = Adjust trigger pulse input frequency to 1KHz)
Procedure:
1. Connections are made as shown in the Figure 8.3.

3. Observe the waveform on CRO at point A which gives positive and negative spikes.
4. Observe the waveform on CRO at point B which gives only negative spikes of amplitude
approximately 2/3 VCC.
5. Observe the wave form on CRO at pin 3 and measure the o/p pulse width and amplitude.
6. Vary the DCB value and note down different widths of the pulse.
7. Observe the wave form on CRO at pin 6 and observe charging and discharging.
Expected Output Waveform:
Figure 8.4: Output of Monostable Multivibrator

RESULT:
Thus, a Monostable circuit has been designed, constructed, and the output waveforms verified.
OUTCOME:
 Gain hands-on experience in building Monostable and Astable Multivibrator using 555
Timer.
 They also understand the principles and features of multivibrators and they will be in a
position to differentiate between various types of multivibrators.

PART-B
Simulation using EDA software (EDWinXP, PSpice, MultiSim, Proteus,

CircuitLab or any other equivalent tool can be used)

EXPERIMENT: 09
RC PHASE SHIFT OSCILLATOR AND HARTLEY OSCILLATOR
RC PHASE SHIFT OSCILLATOR

AIM:
To design and set up the RC Phase shift Oscillator using FET and calculate the frequency of
output waveform.
OBJECTIVE:
 Design the Study the performance of Audio oscillators.
 Test the Phase shift oscillator.
CIRCUIT DIAGRAM:
Figure 9.1: Circuit diagram of RC Phase Shift Oscillator
THEORY:
An oscillator is a device which produces sustained periodic signals. If the oscillator produces
sinusoidal oscillations, then it is called as sinusoidal oscillator. An oscillator circuit is made of
two parts: an amplifier and a feedback network. The output of amplifier drives feedback

network and output of feedback network in turn drives amplifier creating a loop. The
oscillations are sustained if the circuit satisfies Barkhausen criteria.
The Barkhausen criteria states that, the oscillations are sustained if and only if loop gain |Aβ| is
unity and total phase shift in the loop is 00 or 3600. A is the gain of amplifier and β is the gain of
feedback network. In a RC phase shift oscillator, three RC sections are used in the feedback
network. The MOSFET amplifier introduces 1800 phase shift of its own, to satisfy the
Barkhausen criteria, the three RC sections must together insert another 180 0 phase shift to the
feedback signal. Thus, each RC section is expected to insert 60 0 phase shift. Also the loop gain
Aβ is slightly kept greater than unity to compensate for any loss in the feedback signal. For
MOSFET based RC phase shift oscillator, the gain of the amplifier should be atleast 29 for obtain
sustained oscillations. The frequency of oscillations is given by
F=1/2*π*R*C*sqrt(n)
Where n=No of stages
RC phase shift oscillators produce stable sustained oscillations in audio frequency range.
DESIGN:
Given, fo = 500Hz; Assume C1=C2=C3 = 0.1µF

fo = 1/(2π√6 RC),
R2=R3 = 1KΩ
R1>R2
R2=1.9KΩ
Av= − Rf / R1, Av > -29, ie, Rf/ R1 > 29
Rf = 50 KΩ
PROCEDURE:
1. Open NI Multisim software. Go to place components.
2. Place all the components to an attribute area and Connect the circuit diagram as shown in Figure
9.1.
3. Connect all the components using wire and check the working of the circuit.
4. Using RUN command run the simulation.
5. Check whether the amplifier circuit is working properly using signal generator and oscilloscope.

6. Observe the output voltage by clicking on the CRO.

7. Record the output waveform and readings.
EXPECTED WAVEFORMS:
60 Degree phase shift
V0(v)
t(s)
Figure 9.2: RC Phase Shift Oscillator with 60 Degree phase shift
V0(v)
t(s)
V0(v)

t(s)
CALCULATION:
Find t(time period) from the obtained waveform.
Calculate frequency using the formula f=1/t.
OBSERVATIONS:
Frequency of Oscillations = ______________________ Hz.
RESULT:
The RC phase shift oscillator circuit was designed and successfully tested. The frequency of
oscillations is _______________.
OUTCOME:
 It helps the students to learn the basic working of audio oscillators.

 On completion of the experiment the student understands the reason behind using RC circuits
for audio frequencies

HARTLEY OSCILLATOR
AIM:
To design and set up Hartley oscillator using BJT and to determine its frequency of oscillation.
OBJECTIVE:
Design and study the performance of Hartley oscillators.
CIRCUIT DIAGRAM:
VCC
12V
SL100
Figure 9.5: Hartley Oscillator Circuit
Design:


VRE=10% of VCC
VCE=50% of VCC
To determine VCE
VCE=VCC/2=6V
To find RE
VRE=IERE and IC=IE
RE=VRE/IC =1.2/2mA
RE=600Ω.
Choose RE=560Ω
To find RC
VCC=ICRC+VCE+IERE
RC=VCC-VCE-ICRE/IC
RC=12-6-1.2/2m
RC=2.4KΩ
Choose RC=2.2KΩ
To find R1 and R2
R2≤βRE/10
R2≤560*145/10
R2=8.12KΩ
WKT, VBE=VB-VE
VB=VBE+VE
VB=0.7+1.2

VB=1.9V
VB(R1+R2)=VCC*R2
R1=43.05KΩ
Choose R1=47KΩ
Tank circuit Design
F0=1/2πL1C
Choose f0=100KHz and C=1nF
Leq=2.5mH
choose L1=1mH and L2=2mH
Assume Cc1= CC2=0.47µF and CE=0.01µF
THEORY:
Hartley oscillator consists of a tank circuit made of a capacitor connected in parallel to two series
connected inductors. The feedback signal is tapped at a point connecting two inductors. The
transistor amplifier introduces 1800 phase shift which is then compensated by the tank circuit
which introduces a further 1800 phase shift.
Frequency can be adjusted by varying the capacitor. It can produce oscillations with
constant gain over a large frequency range. The inductors can be replaced by a tapped coil as
well. The frequency of oscillations is given by
F=1/(2*π* sqrt(Leq* C))
Where Leq = L1 + L2 + M and M is mutual inductance of the coils.
PROCEDURE:
2. As per the required circuit diagram place all the components to an attribute area.
5. Check whether the amplifier circuit is working properly using signal generator and oscilloscope.
Observation:
Frequency of oscillations = _____________

Result:
Figure 9.6: Waveform of Hartley Oscillator
Hartley oscillator was designed and tested. The frequency of oscillations was _______________

EXPERIMENT: 10
Narrow Band-pass Filter and Narrow band-reject filter.
AIM: To design and simulate Bandpass and Band reject filter using an Op-Amp.
OBJECTIVE:
To Study and simulate Bandpass and Band reject filter using an Op-Amp.
CIRCUIT DIAGRAM OF NARROW BAND-PASS FILTER:
Figure 10.1: Circuit diagram of Narrow Band-pass Filter
OPERATION:
Band Pass Filters can be used to isolate or filter out certain frequencies that lie within a particular
band or range of frequencies. The cut-off frequency or ƒc point in a simple RC passive filter can be
accurately controlled using just a single resistor in series with a non-polarized capacitor, and
depending upon which way around they are connected, we have seen that either a Low Pass or a High
Pass filter is obtained.
One simple use for these types of passive filters is in audio amplifier applications or circuits such as
in loudspeaker crossover filters or pre-amplifier tone controls. Sometimes it is necessary to only pass
a certain range of frequencies that do not begin at 0Hz, (DC) or end at some upper high frequency
point but are within a certain range or band of frequencies, either narrow or wide.

PROCEDURE:
5. Check whether the circuit is working properly using signal generator and oscilloscope.
Expected Output Waveforms:
Figure 10.2: Waveform of Narrow Band-pass Filter
CIRCUIT DIAGRAM OF BAND-REJECT FILTER:

Figure 10.3: Circuit diagram of Band-reject Filter

Figure 10.4: Waveform of Narrow Band-pass Filter

RESULT:
The Bandpass and Band reject filter using an Op-Amp is successfully simulated.
OUTCOME:
 Student learns the basic principle Bandpass and Band reject filter using an Op-Amp.

EXPERIMENT: 11
PRECISION HALF WAVE AND FULLWAVE RECTIFIERS
AIM: To design and simulate the half wave and full wave rectifiers with and without filters and
to determine ripple factor and rectifier efficiency
OBJECTIVE:
To Study the concept of half wave and full wave rectification
HALF WAVE RECTIFIER:

CIRCUIT DIAGRAM:

Figure 11.1: Circuit diagram of Half Wave Rectifier
OPERATION:
The working of full wave rectifier can be explained using circuit diagram shown in Figure 1.
During the positive half cycle of the input waveform, the diode D1 is forward biased and diode
D2 is reverse biased. The conventional current takes the path abcd. During the negative half
cycle, the diode D1 is reverse biased and diode D2 is forward biased. The conventional current
takes the path efbcd. During both the half cycles, the conventional current flows in the direction
of c to d through the load resistance RL, setting up pulsating DC and corresponding pulsating DC
voltage waveform across the load.
A capacitor connected in parallel across the load to filter out the ripples in the output
waveform. When the voltage across load is more than the voltage across the capacitor, the
capacitor quickly charges to the new voltage level. Whenever the voltage across the load is less
than the voltage across the capacitor, the capacitor slowly discharges through the load
establishing a triangular waveform with small ripple. Using appropriate value of capacitor
ensures smallest possible ripple in the output DC voltage.
One of the important parameters to be measured in a rectifier is percentage regulation. This
figure tells how well the rectifier behaves when the value of load resistance changes. Ideally,
there should be no change in the DC voltage delivered by the rectifier when load changes. V dc(no-
load) is the average voltage delivered by rectifier when no current flows through the load(No
current flows through the load if and only if the load has infinite resistance or in other word, open

circuit). Vdc(rated-load) is the average voltage delivered by rectifier to the load for which the rectifier
is designed.
Design:
Choose R1=10kΩ and R2=1kΩ
FULLWAVE RECTIFIER:
CIRCUIT DIAGRAM:
Figure 11.2: Circuit diagram of Full Wave Rectifier
OPERATION:
The operation of bridge rectifier can be explained using the circuit shown in Figure 5.
During positive half cycle of input waveform, diodes D2 and D3 are forward biased and diodes
D1 and D4 are reverse biased. The conventional current flows along a-D2-b-load-c-d-D3-e.
During negative half cycle, diodes D1 and D4 are forward biased and diodes D2 and D3 are
reverse biased. The conventional current flows along e-D4-b-load-c-d-D1-a. Thus during both the
half cycles, the current flows from b to c through the load establishing pulsating DC current
through the load and pulsating DC voltage across the load.
DESIGN:

The operation of the positive full wave rectifier is expressed as

V0=|Vi|
and that of the negative rectifier as
V0=-|Vi|
CASE 1 : Vi > 0 : When Vi > 0, inverting side of Al will force its output to swing negative, thus
forward biasing D1 and reverse biasing D2.
Figure 11.3: Equivalent circuit
From equivalent circuit, the output voltage can be given as

V0=(-R/R)- (R/R)Vi=Vi
V0=(-2/3)Vi
CASE 2 : Vi < 0 : When Vi < 0, negative, the output voltage of Al swings to positive, making
diode D1 reverse biased and diode D2 forward biased.
Figure 11.4: Equivalent circuit

Let the output voltage of op-amp Al be V. Since the differential input to A2 is. zero, the inverting
input terminal is also at voltage V, as shown in the Figure 11.4
Applying KCL at node ‘a’ we have
Vi/R+V/2R+V/R=0
3V/2R=-Vi/R
Figure:11.6: Equivalent circuit
To find Vo in terms of V we concentrate on the equivalent circuit of A2, as shown in the Figure
11.5.
V0=(1+R/2R)V
V0=(2R+R/2R)V=3V/2
Substituting value of V in above equation
V0=3/2(-2Vi/3)=-Vi
Hence for Vi < 0 the output is positive.
PROCEDURE:
5. Check whether the circuit is working properly using signal generator and oscilloscope.

Figure 11.3: Output waveform of Half wave rectifier
Figure 11.4: Output waveform of Full wave rectifier
RESULT:
The Half wave and Full wave rectifiers with and without capacitor filters were designed and
successfully set up. The rectifier efficiency and ripple factor was calculated for the same.
Rectifier Efficiency
OUTCOME:
 Student learns the basic principle of Rectification – Half wave, Full wave and Bridge
rectifiers are studied.
 Students understand the need for filters, ripple factor, regulation and efficiency.
EXPERIMENT NO: 12
MONOSTABLE AND A STABLE MULTIVIBRATOR USING 555 TIMER.
AIM:
(a) To design and implement an Astable Multivibrator using 555 timer to generate a square wave
of given Duty cycle and frequency
(b) Design Monostable Multivibrator for given pulse width w
OBJECTIVE:
This experiment enables students to design, demonstrate and analyse Monostable and Astable
Multivibrator using 555 Timer for various duty cycles.
CIRCUIT DIAGRAM :
Figure 12.1: Circuit diagram of Astable Multivibrator
THEORY
A 555 timer is a monolithic timing circuit that can produce accurate and highly stable time
delays or oscillations, some of the applications of 555 are square wave generator, Astable and
MonoStable Multivibrator.
Astable Multivibrator is a free running oscillator has two quasi stable state in one state o/p
voltage remains low for a time interval of Toff and then switches over to other state in which
the o/p remains high for an interval of Ton the time interval Ton and Toff are determined by the
external resistors a capacitor and it does not require an external trigger, when the power is
switched on the timing capacitor begins to charge towards 2/3 Vcc through R A & RB, when the
capacitor voltage has reached this value, the upper comparator of the timer triggers the flip
flop in it and the capacitor begins to discharge through RB when the capacitor voltage reaches
1/3 Vcc the lower comparator is triggered and another cycle begins, the charging and
discharging cycle repeats between 2/3 Vcc and 1/3Vcc for the charging and discharging periods
t1and t2 respectively. Since the capacitor charges through RA and RB and discharges through RB
only the charge and discharge are not equal as a consequence the output is not a symmetrical
square wave and the multivibrator is called an asymmetric astable multivibrator.
DESIGN:
(i). A square wave of given Duty cycle and frequency
For unsymmetrical square wave Let Duty cycle >50%

TON = 0.693(RA+ RB)C for charging time
TOFF =0.693 RBC for discharging time
(60%) Duty cycle = TON = TON

TON  TOFF T
TOFF = T- TON
Assume C= 0.1µF TOFF =0.693 RBC TON = 0.693(RA+RB) C
If f= 2KHz then RA=1.433=1.5kΩ and RB=2.886KΩ
Similarly for D<50% Ton<Toff
TOFF = 0.693(RA+ RB)C for charging time
TON =0.693 RAC for discharging time
Assume C for given f and determine R A and RB
EXPECTED OUTPUT WAVEFORM:
Upper threshold voltage
=2/3*Vcc
Vc at pin 6
Lower threshold
Voltage =Vcc/3
Vout at Toff
pin 3
t
Ton

Figure 12.2: Output waveform of Astable Multivibrator.

PROCEDURE:
1. For Asymmetric connections are made as shown in the circuit diagram I.

3. Observe the wave form on CRO at pin 3 and measure the o/p pulse amplitude
4. Observe the wave form on CRO at pin 6 and measure Vcmax and Vc min
5. Verify that Vcmax=2/3Vcc and Vc min=1/3 Vcc
6. Calculate the duty cycle D, o/p frequency and verify with specified value.
7. For symmetric Connections are made as shown in the circuit diagram II.
8. Vary DRB until we will get Symmetric wave form (Ton = Toff).
9. Repeat steps 3 to 6.
RESULT:
Thus the Astable Multivibrator designed, constructed and waveforms are observed.
(B) MONOSTABLE MULTIVIBRATOR:

MonoStable Multivibrator has a stable state and a quasi stable state, the output of it is normally
low and it corresponds to reset of the flip flop in the timer, on the application of external negative
trigger pulse at pin 2 the circuit is triggered and the flip flop in the timer is set which in turn
releases the short across C and pushes the output high, At the same time the voltage across C
rises exponentially with the time constant R AC and remains in this state for a period R AC even if
it is triggered again during this interval, When the voltage across the capacitor reaches 2/3 Vcc,

the threshold comparator resets the flip flop in the timer which discharges C and the output is
driven low the circuit will remain in this state until the application of the next trigger pulse
CIRCUIT DIAGRAM:
Figure 12.3: Circuit diagram of Monostable Multivibrator
Design:
Given Pulse width W= 0.5ms
We know that W=1.1*RA*C
Assume RA=10k and calculate C
For Differentiator circuit,
Choose RtCt <<W
i.e. RtCt < W/10 (assume Rt=1k & find Ct)
Duty cycle D=W/T where T=1/f (f = Adjust trigger pulse input frequency to 1KHz)
PROCEDURE:
1. Connections are made as shown in the circuit diagram.

2. Switch on the DC power supply unitObserve the waveform on CRO at point A which
gives positive and negative spikes.

3. Observe the waveform on CRO at point B which gives only negative spikes of amplitude
approximately 2/3 VCC.
4. Observe the wave form on CRO at pin 3 and measure the o/p pulse width and amplitude.
5. Vary the DCB value and note down different widths of the pulse.
6. Observe the wave form on CRO at pin 6 and observe charging and discharging.
Expected Output Waveform:

Figure 12.4: Output waveform of Monostable Multivibrator.
RESULT:
Thus a Monostable circuit has been designed, constructed, and the output waveforms verified.
OUTCOME:
 Gain hands-on experience in building Monostable and Astable Multivibrator using 555
Timer.
 They also understand the principles and features of multivibrators and they will be in a
position to differentiate between various types of multivibrators.

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ANALOG CIRCUITS LAB 18ECL48

ANALOG CIRCUITS LABORATORY (18ECL48)

Subject Code : 18ECL48 I.A. Marks : 40

PART A : HARDWARE EXPERIMENTS

10 Narrow Band-pass Filter and Narrow band-reject filter.

11 Precision Half and full wave rectifier.

12 Monostable and A stable Multivibrator using 555 Timer.

DEPT. OF ECE, ATMECE, MYSURU

DESIGN AND SETUP THE COMMON SOURCE JFET/MOSFET AMPLIFIER AND

OBJECTIVE: To design the common source JFET/MOSFET amplifier and analyze

Figure 1.1: Common Source FET Amplifier

DEPT. OF ECE, ATMECE, MYSURU

VDD= 12V, VGS=-1V, VRS=20% of VDD=2.4V

Let Vdd*R2/R1+R2= VGS+VRS

DEPT. OF ECE, ATMECE, MYSURU

TO OBTAIN FREQUENCY RESPONSE:

Peak to Peak input voltage Vi =_____

Table 1.1:Tabular Column of Common Source JFET/MOSFET Amplifier.

Frequency Peak to peak output

DEPT. OF ECE, ATMECE, MYSURU

Figure 1.2: Expected output and frequency response graph

DEPT. OF ECE, ATMECE, MYSURU

Figure 2.1: BJT Common Emitter Amplifier without feedback

DESIGN: (With and without Feedback)

VCC=12V, β (Gain)=145, Let Ic(Collector current) =2mA

DEPT. OF ECE, ATMECE, MYSURU

DEPT. OF ECE, ATMECE, MYSURU

Figure 2.2: BJT Common Emitter Amplifier with feedback

Figure 2.3: Experimental setup to measure Input Impedance

Figure 2.4: Experimental setup to measure Output Impedance

DEPT. OF ECE, ATMECE, MYSURU

TO OBTAIN FREQUENCY RESPONSE

TO MEASURE INPUT IMPEDANCE

1. Connect the DRB in series with input as shown in figure 2.3.

TO MEASURE OUTPUT IMPEDANCE

1. Connect the DRB as shown in Figure 2.4.

DEPT. OF ECE, ATMECE, MYSURU

1. Amplifier without feedback

Table 2.1: Tabular Column of Common Emitter Amplifier without feedback.

Input impedance Zi = _________

2. Amplifier with feedback

Table 2.2: Tabular Column of Common Emitter Amplifier with feedback.

Frequency Peak to peak output

DEPT. OF ECE, ATMECE, MYSURU

Maximum Gain of amplifier without feedback = _______________

Bandwidth of amplifier without feedback = _________________

Maximum Gain of amplifier with feedback = _______________

Bandwidth of amplifier with feedback = _________________

Gain Bandwidth product of amplifier without feedback = _________

Gain Bandwidth product of amplifier with feedback = _________

DEPT. OF ECE, ATMECE, MYSURU

DESIGN AND SET-UP BJT/FET I) COLPITTS OSCILLATOR, AND II)

(I) COLPITTS OSCILLATOR

Figure 3.1: Colpitts Oscillator Circuit

DEPT. OF ECE, ATMECE, MYSURU

Where Ceq = C1C2/(C1 + C2) and M is mutual inductance of the coils.

VCC=12V, β=145, Let Ic=2mA

DEPT. OF ECE, ATMECE, MYSURU

Tank circuit Design

Frequency of oscillations = _____________

 It helps the students to learn the basic working of LC circuits.

DEPT. OF ECE, ATMECE, MYSURU