Wafer Deposition/Metallization and Back Grind, Process-Induced Warpage Simulation
Scott Irving and Yong Liu
Technology CAD Department
Fairchild Semiconductor Corporation, Mail Stop 35-2E
82 Running Hill Rd, South Portland, Maine, 04106
Email: sirving@fairchildsemi.com, Tel: 207-775-8508
Abstract
During deposition/metallization processes, metal interconnects
and dielectric films are layered on top of the wafer. Wafer
warpage appears due to the mismatch in thermal expansion
coefficients of the various deposited materials, as well as
intrinsic stresses. Large warpage is one of the root causes of
failures occurring during backside grind process and
subsequent processes. Wafers are routinely thinned by
backside grind prior to dicing to aid the sawing operation,
improve heat transfer, or reduce Rdson, and to allow the final
assembled package thickness to be minimized. As the wafer
thickness is decreased during backside grind the wafer
progressively become less able to support its own weight and
to resist the stresses generated by front side dielectric and
metal deposition. Therefore, modeling the wafer warpage
during the dielectric and metal deposition process and the
backside grind is important to achieve optimal wafer and die
yield. A FEA approach is developed to simulate both wafer
deposition and backside grind processes. During the
deposition processes, the multi-layer thin film depositions are
modeling with different temperatures by non-linear finite
element in both geometry and materials is presented. The
residual warpage and stress results from the deposition phases
are used as the initial warpage and stress for the backside
grind process. Advanced element death and birth techniques
are used to simulate the deposition/metallization process and
grind process layer by layer.
Introduction
During back end processing a sequence of depositions and
etches are used to build up the interconnect layers and the
final passivation layer. At minimum this involves one metal
layer and one dielectric layer per level of interconnect, with
one to six levels of interconnect being common in the
industry.
The dielectric and metal layers are thin films deposited by
vapor deposition or sputtering techniques. The conductive
metal layers may consist of one or more thin films, (typically
TiW, TiN, Al(Cu), W, Cu, etc.) The insulating dieletric layer
typically consists of oxides (TEOS, BPTEOS, PSG, SOG,
etc,) , nitride (Si3N4), oxynitride (SiON), etc. Each thin film
has unique material properties associated with it. The intrinsic
stress of each material will vary with the deposition process,
and thermal history that occurs after deposition.
Typically a large portion (30-70%) of the deposited metal
layers are removed during patterning. For the dielectric layers
the proportion us much smaller. For the dielectric layers the
patterning is for the contact, via or bond pad openings.
With the exception of passivation, the dielectric layers will
often have the in-die areas refilled with tungstan plugs, or the
metal from the next conductive layer. All films above silicon
are normally removed from the saw street region of the
wafers. Given the above, the dielectric layers can usually be
assumed to be continuous, except for the saw street. For the
conductive layers others have estimated that the stress relief
due to patterning is proportional to the area removed.[1,2].
The backside grinding of wafers is a common operation
done for a number of reasons. The final wafer thickness is set
either by our ability to mechanically handle the wafer without
breakage or for high voltage vertical devices by the need to
support deep depletion regions. In vertical devices thinning
the wafer improves the Rdson that can be achieved. For all
types of devices wafer thinning improves the transfer of heat
from the front device side of the wafer to the backside for
dissipation by the paddle, the package substrate or other
portions of the package capable of efficient conduction. The
drawback of wafer thinning is an increase in wafer warpage
and fragility.
Stress Models
The stress and strain in a thin film layer results either from
the deposition process or due to CTE mismatch. The stress
from deposition, known as the intrinsic stress, is due to the
non-equilibrium growth of the film microstructure [2].
Intrinsic stress begins at the start of the deposition, at
temperature and will vary as a result of changing process
conditions or subsequent process steps including anneals.
The stress due to CTE mismatch is the well known thermo
mechanical phonomenon. The total stress in the film is given
by
σ t = σ int + σ th (1)
Where σ t is the total stress, σ int is the intrinsic stress and
σ th is the thermo mechanical stress due to CTE mismatch. In
this study we did not include the intrinsic stress, earlier
internal studies showed the intrinsic stress to be small
compared to other sources.
Further we can relate the stress in a film to the wafer
warpage using Stoney's formula [3], knowing only the
materials properties of the substrate and the thickness of the
deposited film.
Es t s2
σt = (κ i − κ e ) (2)
6(1 − υ s )t f
Where σt is the biaxial film stress, t s and t f are the thicknes
Table 2 Layer thicknesses
of the substrate and film respectively, υ s is poisson's ratio for Layer Material Thickness
the substrate, E s is Young's modulus, and κ i and κ e are the Substrate Si 670
final and initial value of the wafer curvature (1/bending ILD 1 LTO/BPSG 0.5 um
radius). Metal 1 TiW 0.18 um
Euler beam theory gives the load limit of a sample as: Metal 2 Al(Cu) 5.0 um
Passivation SiOn 1.2
σ p bh 2
Plim = (3)
1 .5 L Figure 1 below shows the temperature history used in the
where σ p is the chip strength, L, b and h are the span, width, simulation. Dwell times at temperature were not included as
no time dependant materials properties or effects of anneals
and thickness of the sample respectively, and Plim is the load were simulated.
limit. 450

Modeling wafer warpage and backside grind is technically

challenging because of the scale differences between wafer
400

size and the thinness of the deposited films. Backside grind 350

presents similar issues because of the relative thinness of the 300

layers removed.

Temp (C)
250

In order to handle the wide variety of materials and

conditions easily the models presented were built using the
200

parameterization features of the FEM software (Ansys). With 150

the parameterized code available any number of variations can 100

be run easily. This includes the ability to change the number 50

of deposited films and the associated materials parameters, the
wafer diameter, and backside grind thickness'. 0
0 1 2 3 4 5 6 7 8 9 10

load step

Figure 1 Deposition temperature load history

Thin Film Deposition
We start the modeling at the first deposited dielectric The deposition of layers is done using the element birth
layer. The grown oxides and other films have a relatively mechanism within Ansys.
insignificant effect on wafer warpage and stress. Table 1 Figure 2 shows the incremental warpage due to each
below lists the material parameters used in this study. Ideally
the study would use parameters extracted from the wafer fab 90

process itself but these were unavailable so values from the 80

vendors were used.

70

Table 1 Deposited materials parameters 60

Warp (microns)

Material Modulus CTE (ppm/C) Poisson ratio 50

(Mpa)
40
Silicon 169.5e3 3.2 0.23
ILD 1 70.0e3 4 0.25 30

TiW 117.0e3 10.2 0.25

20
Al(Cu) 70.0e3 10 0.35
10
SiON 115.0e3 2.92 0.25
0
1 2 3 4

The system simulated in this study was a single conductor Thin film layers

made up of a TiW barrier layer and Al(Cu). The layer

thicknesses are given in table 2 below. We could not account
for the wafer patterning in this study as it increases the
complexity of the simulation beyond normal computational
limits.
Figure 2 Warpage vs. deposition Step
sequential deposition. The extremely thick aluminum
deposition is responsible for the majority of the deformation
as can be seen in the increase from step 2 to step 3. The final
warpage is displayed in figure 3. The black circle shows the
measured final wafer warpage. Given the amount of patterning
for these wafers the difference is reasonable. If a patterning
step was included we would expect to see a decrease in
warpage at the time of the etch.

Silicon
Fine
20 um

Coarse
537 um

Figure 4 Grind scheme for 4 mil wafer

Table 4 Uncalibrated backside grind results

4 mil 8 mil
Figure 3 Wafer warpage from deposition Warpage 2639 um 687 um
Max Stress 239.0 Mpa 243.6 Mpa

Backside grind Due to the geometries involved the elements used have a
The backside grind process uses the initial wafer stresses large aspect ratio. The results converged, however with a
from the previous steps. During the backside grind process the negative Jacobian during the solution process. As a result the
frontside of the wafer is protected with a film, the wafer is values in the above table should not be taken as being
loaded onto a vacuum chuck, and a two step grind process is predictive, they are valid for a relative comparison between
used to thin the wafer. We examined two cases with the different films or backside grind thickness'. The result shows
simulation, with final wafer thicknesses of 113 um and 226 the stress to be independent of backside grind thickness and
um. the ratio between the grind thickness' to be 3.84.
The steps in the backside grind process model are:
1. Apply vacuum chuck
2. Heat to process temperature
3. Coarse grind
4. Fine grind
5. Cool down
6. Remove wafer from chuck

Table 3 shows the process parameters used for simulation

in this paper. The same is shown schematically in figure 4.

Table 3 Backside grind process parameters

Parameter Thin Thick
Initial thickness 670 um 670 um
Grind force 6 lbs 6 lbs
Grind temp 60 C 60 C
Coarse grind Tk 537 um 424 um
Fine grind 20 um 20 um
Final thicknes 4 mil (113 um) 8 mil (226 um)

Figure 5 Wafer after grind to 4 mils

 In order to derive a predictive model, a smaller geometry
was constructed that allows a reduced aspect ratio. The new
model used a 13.6 x 6.3 mm sample size as shown below in
figure 6, constructed to comply with ASTM Industrial
Standard , E 855. This allows comparison to the results of Wu
et al. [4].
The reduced model results in the same maximum stresses
as were found in the quarter model above.
Table 5 Calibrated backside grind results
4 mil 8 mil
Sample warpage 87 um 63.4 um
Normalized warpage 478 um 124 um
Max Stress 239.4 Mpa 243.8 Mpa
Table 5 shows the results of the new model that uses the
smaller sample size. This new model does not have the same
problem as before with negative Jacobians appearing in the
solution. The ratio between the 4 mil and 8 mil backside grind
samples is 3.85 which is similar to the result in the larger
uncalibrated model.
Figure 6 Reduced model
It confirms the experimental results of Wu et al. [4], that
the stress is independent of the size of the wafer or sample.
This result makes sense, that the films and grind processes
include a given amount of stress that is independent of the
sample size. The stress in turn induces a warpage that could be
expressed as a radius of curvature that is independent of
sample size. This is important for future work that will try to
model the effects of backside grind and stress on die damage,
but will need to be modeled as smaller samples to be practical.
Wu et al. [4] show that average tensile yield strength for a
wafer is approximately 240Mpa. They also showed a
variability in the post backside grind die strength of about
40%, with the weakest areas being 30% weaker than the
average. This weakness occurred on machines produced by
several vendors, although in differing patterns. Therefore in
the weak areas of the wafer the yield strength will be reduced
to about 161 Mpa.
Using equation 3 above allows us to calculate the load
limits that can be placed on a wafer of different backside grind
thicknesses.
P4 mil = 0.635 N
P8 mil = 2.54 N
Based on the load limits a 8 mil thick wafer can withstand
4 times the load of a 4 mil wafer before it is damaged.
Conclusions
In this work the layer deposition process is modeled and
the resultant stresses and warpage is determined.
The backside grind process is modeled and the difference
in warpage and stress between 4 and 8 mil final wafer
thicknesses were compared. The 4 mil back grind results in a
warpage increase of 3.85 times.
When compared to the work of Wu et al. [4] and van
Silfhout et al. [2] the parameterized models developed show
reasonable agreement.
Future work should include the use of the modeled wafer
for crack propagation studies. Current experimental setups are
restricted to relatively large die due to physical constraints of
the equipment. The use of FEA models will allow us to extend
the studies to smaller die sizes and die with different aspect
ratios.
The models discussed here need to be extended to include
the effects of backside metal deposition and patterning. The
results of these models will provide the initial stress state for
further die cracking studies.
Ultimately the goal is to build a parameterized system that
can be used by process engineers, without strong FEA
knowledge, to examine and optimize both deposition and
backside grind processes.
Acknowledgments
We would like to thank our collegues at Fairchild
Semiconductor who shared their knowledge of wafer
deposition and backside grind processes.
References
1. Shen, Y.L., et al.,"Stresses, Warpages, and Shape Changes
Arising from patterned lineson Silicon Wafers", J. Appl.
Phys., Vol 80, 1996, pp. 1388-1398
2. van Silfhout, R.B.R., et al., "Prediction of Back-End
Process-induced wafer Warpage and Experimental
Verification", Proc 2002 Electronic Components and
Technology Conference, San Diego, CA, May. 2002, pp.
1182-1187.
3. Stoney, G. G., "The tension of Metallic films Deposited
by Electrolysis", Proc. Roy. Soc. London A Math., 82,
1909, pp172-175
4. Wu, E., et al., "Influence of Grinding Process on
Semiconductor Chip Strength", Proc 2002 Electronic
Components and Technology Conference, San Diego,
CA, May. 2002, pp. 1617-1621.