ARM COLLEGE OF ENGINEERING AND TECHNOLOGY

SATTAMANGALAM, MARAIMALAI NAGAR, CHENNAI, TAMIL NADU. PIN-603 209.

ARMCET
(Approved by AICTE & Affiliated to Anna University)

DEPARTMENT OF ELECCTRONICS AND COMMUNICATION

ENGINEERING

EC8661 - VLSI DESIGN LABORATORY

2019-2020

Name of the Student :

Registration Number :

Year of Study :

Semester :

1
 ARM COLLEGE OF ENGINEERING AND TECHNOLOGY
SATTAMANGALAM, MARAIMALAI NAGAR, CHENNAI, TAMIL NADU. PIN-603 209.

ARMCET
(Approved by AICTE & Affiliated to Anna University)

BONAFIDE CERTIFICATE

Reg. No.

Certified that this is a Bonafide Record of Practical Work done by

Mr. /Ms ……………………………………………………………………………………………...
of B.E/ B.Tech ………………………………………………………………………………….
of ……… Semester in ……………………………………………………………………………….
during the academic year…………………

Signature of Lab-In charge Signature of Head of Dept.

Submitted for the practical Examination held on: …./…./…….

Internal Examiner External Examiner

 EC8661 VLSI Design Laboratory
LIST OF EXPERIMENTS

S.NO DATE EXPERIMENT NAME PAGE. SIGNATURE

NO
Design an Adder (Min 8 Bit) using HDL.

1 Simulate it using Xilinx/Altera Software

and implement by Xilinx/AlteraFPGA

Design a Multiplier (4 Bit Min) using HDL.

2 Simulate it using Xilinx/Altera Software and
implement by Xilinx/AlteraFPGA
Design an ALU using HDL. Simulate it using
3 Xilinx/Altera Software and implement by
Xilinx/AlteraFPGA
4 Design a Universal Shift Register using
HDL. Simulate it using Xilinx/Altera
Software and implement by
Xilinx/AlteraFPGA
5 Design Finite State Machine (Moore/Mealy)
using HDL. Simulate it using Xilinx/Altera
Software and implement by
Xilinx/AlteraFPGA
6 Design Memories using HDL. Simulate it
using Xilinx/Altera Software and implement
by Xilinx/AlteraFPGA
7 Design and simulate a CMOS inverter using
digitalflow
8 Design and simulate a CMOS Basic Gates
&Flip-Flops
9 Design and simulate a 4-bit synchronous
counter using aFlip-Flops
S.NO DATE EXPERIMENT NAME PAGE. SIGNATURE
NO
10 Design and Simulate a CMOS Inverting
Amplifier.

Design and Simulate basic Common Source,

11
Common Gate and Common Drain
Amplifiers. Analyze the input impedance,
output impedance, gain and bandwidth for
experiments 10 and 11 by performing
SchematicSimulations.

Design and simulate simple 5 transistor

differential amplifier. Analyze Gain,
12
Bandwidth and CMRR by performing
SchematicSimulations.

13 Study of Verilog HDL and Spartan 3E FPGA

board
Expt. No::01 Date:

DESIGN OF ADDER CIRCUITS

AIM:
To design and implement 8 bit adders circuits using Verilog HDL and simulate,
Synthesize and implement in FPGA hardware.

APPARATUS REQUIRED:

 PC with Windows xp.

 XILINX software.
 Spartan 3E FPGA Kit.

THEORY:

8- Bit Addition (Ripple Carry Adder)

The n-bit adder built from n number of one –bit full adders is known as ripple carry adder
because of the carry is computed. The addition is not complete until n-1th adder has computed its
Sn-1 output; that results depends upon ci input, n and so on down the line, so the critical delay path
goes from the 0-bit inputs up through ci’s to the n-1 bit.(We can find the critical path through the n-
bit adder without knowing the exact logic in the full adder because the delay through the n-bit
adder without knowing the exact logic in the full adder because the delay through the n-bit carry
chain is so much longer than the delay from a and b to s). The ripple-carry adder is area efficient
and easy to design but it is when n is large. It can also be called as cascaded full adder.

PROCEDURE:

1. Start Xilinx ISE 13.1, click on “CREATE A NEW PROJECT” and then click on Next.
2. Select you’re working directory, give the name of the project, then click on “NEXT”.
3. Select the device family (Spartan 3E), Device (XC3S250E), package (PQ208), Speed grade
(4), Synthesis tool (XST [VHDL/VERILOG]), simulator (ISim) and preferred language
(Verilog) from the available device list, and then click “NEXT” and click FINISH.
4. Write the HDL code and be careful to give the entity name the same as project name. After
writing the code save the file and click on “SynthesisXST”.
5. If the HDL code is error free a green check mark will be shown on the synthesis XST.
6. Select simulation then double click on “Simulate Behavioral Model” (here we can change
the level of abstraction. i.e. structural/behavioral/dataflow/switch level)
7. If there is zero error a new window will be shown. Apply the desired input as 1’s and 0’s
and check whether the outputs are correct or not in the output waveform.
 8. In the design window change into implementation and click on “Synthesis XST”. If the
HDL code is error free a green check mark will be shown on the Synthesize – XST.
9. Note down the Device Utilization Summary (Number of Slices , Number of LUTs and
Number of bonded IOBs)
10. Double Click the View RTL Schematic in the process window and RTL Schematic view of
your HDL code.
11. Double Click View Technology Schematic in the process window and View the
Technology Schematic view of your HDL code.
12. In User Constraints, double click I/O Pin Planning (Plan Ahead) –Post synthesize. Plan
Ahead window is opened.
13. Give the input ports and output port 9n the Plan Ahead tool and save the configuration and
close the Plan Ahead window.
14. Double Click the Implementation Design and green check mark will be shown on the
Implementation Icon.
15. In the Design window, change into Post – Route Simulation and by double clicking the
Post-Place & Route Check Syntax and if code is error free a green check mark will be
shown on the Post-Place & Route Check Syntax.
16. Double Click Simulate Post-Place & Route Model and analyze the output waveform.
17. In the design window change into Implementation and process window under
implementation – Place & Route, double click the View/Edit Routed Design (FPGA
Editor), now we can see the routed design of our circuit.
18. A BIT file will be generating by double clicking the Generate Programming File.
19. The BIT file is loaded in the FPGA processor through JTAG or USB cable and the output
can be verified using the hardware kit.
20. MCS file is created and loaded into the PROM for verification.

8-Bit Addition (Ripple Carry Adder)

Logic Diagram:
Programs:

Addition using Dataflow modeling

moduleaddition8bit(a,b,oup);
input [7:0]a;
input [7:0]b;
output [8:0] oup;
assign oup = a + b;
endmodule

Ripple Carry Adder using Structural Modelling

moduleripplecarry_adder(a,b,oup);
input [7:0] a,b;
output [8:0] oup;

wire [6:0]c;
parameter cin=1'b0;

// instantiating 1b-ti full adders

fulladder f1(c[0],oup[0],a[0],b[0],cin);
fulladder f2(c[1],oup[1],a[1],b[1],c[0]);
fulladder f3(c[2],oup[2],a[2],b[2],c[1]);
fulladder f4(c[3],oup[3],a[3],b[3],c[2]);
fulladder f5(c[4],oup[4],a[4],b[4],c[3]);
fulladder f6(c[5],oup[5],a[5],b[5],c[4]);
fulladder f7(c[6],oup[6],a[6],b[6],c[5]);
fulladder f8(oup[8],oup[7], a[7],b[7],c[6]);
endmodule

Full Adder using Dataflow

Modellingmodule fulladder(cout,sum,
in1,in2,cin); output cout;
output sum;
input in1,in2,cin;
assign {cout,sum}= in1 + in2 + cin;
endmodule
OUTPUT WAVEFORM:

RESULT:
The 8-bit Adder was designed and implemented in hardware.
Expt.No: 02 Date:

DESIGN OF MULTIPLIER CIRCUITS

AIM:

To design and implement 4 bit multiplier circuits using Verilog HDL and simulate, synthesize and
implement in FPGA hardware.

APPARATUS REQUIRED:

 PC with Windows XP.

 XILINX software.
 Spartan 3E FPGA Kit.

THEORY:

4- BitMultiplier
Binary multiplication can be accomplished by several approaches. The approach presented
here is realized entirely with combinational circuits. Such a circuit is called an array multiplier. The
term array is used to describe the multiplier because the multiplier is organized as an array
structure. Each row, called a partial product, is formed by a bit-by- bit multiplication of each
operand.
For example, a partial product is formed when each bit of operand ‘a’ is multiplied by b0,
resulting in a3b0, a2b0,a1b0, a0b0. The binary multiplication table is identical to the AND truth
table.
Each product bit {o(x)}, is formed by adding partial product columns. The product
equations, including the carry-in {c(x)}, from column c(x-1), are (the plus sign indicates addition
not OR). Each product term, p(x), is formed by AND gates and collection of product terms needed
for the multiplier. By adding appropriate p term outputs, the multiplier output equations are
realized, as shown in figure.

PROCEDURE:

1. Start Xilinx ISE 13.1, click on “CREATE A NEW PROJECT” and then click on Next.
2. Select you’re working directory, give the name of the project, then click on “NEXT”.
3. Select the device family (Spartan 3E), Device (XC3S250E), package (PQ208), Speed grade
(4), Synthesis tool (XST [VHDL/VERILOG]), simulator (ISim) and preferred language
(Verilog) from the available device list, and then click “NEXT” and click FINISH.
4. Write the HDL code and be careful to give the entity name the same as project name. After
writing the code save the file and click on “Synthesis XST”.
5. If the HDL code is error free a green check mark will be shown on the synthesis XST.
 6. Select simulation then double click on “Simulate Behavioral Model” (here we can change
the level of abstraction. i.e. structural/behavioral/dataflow/switch level)
7. If there is zero error a new window will be shown. Apply the desired input as 1’s and 0’s
and check whether the outputs are correct or not in the output waveform.
8. In the design window change into implementation and click on “Synthesis XST”. If the
HDL code is error free a green check mark will be shown on the Synthesize – XST.
9. Note down the Device Utilization Summary (Number of Slices , Number of LUTs and
Number of bonded IOBs)
10. Double Click the View RTL Schematic in the process window and RTL Schematic view of
your HDL code.
11. Double Click View Technology Schematic in the process window and View the
Technology Schematic view of your HDL code.
12. In User Constraints, double click I/O Pin Planning (Plan Ahead) –Post synthesize. Plan
Ahead window is opened.
13. Give the input ports and output port 9n the Plan Ahead tool and save the configuration and
close the Plan Ahead window.
14. Double Click the Implementation Design and green check mark will be shown on the
Implementation Icon.
15. In the Design window, change into Post – Route Simulation and by double clicking the
Post-Place & Route Check Syntax and if code is error free a green check mark will be
shown on the Post-Place & Route Check Syntax.
16. Double Click Simulate Post-Place & Route Model and analyze the output waveform.
17. In the design window change into Implementation and process window under
implementation – Place & Route, double click the View/Edit Routed Design (FPGA
Editor), now we can see the routed design of our circuit.
18. A BIT file will be generating by double clicking the Generate Programming File.
19. The BIT file is loaded in the FPGA processor through JTAG or USB cable and the output
can be verified using the hardware kit.
20. MCS file is created and loaded into the PROM for verification.

4-Bit Multiplier

4 X 4 Array Multiplier:

a3 a2
a1 a0
b3 b2 b1
b0a3b0 a2b0 a1b0
a0b0
a3b1 a2b1a1b1 a0b1
a3b2 a2b2 a1b2a0b2
a3b3 a2b3 a1b3a0b3
o7 o6 o5 o4 o3 o2 o1
a0b0 = p0 a1b2 = p8
a1b0 = p1 a0b3 = p9
a0b1 = p2 a3b1 = p10
a2b0 = p3 a2b2 = p11
a1b1 = p4 a1b3 = p12
a0b2 = p5 a3b2 = p13
a3b0 = p6 a2b3 = p14
a2b1 = p7 a3b3 = p15

Logic Diagram:

P14 P13 P11,P10 P2P1 P0

P15 P7 P6 P4 P3

FA FA HA HA HA

P12 P8
FA FA FA

P9

FA FA FA HA

O7 O6 O5 O4 O3 O2 O1 O0

Programs:

Multiplier using Dataflow Modelling

module mult4bit(a,b,op);
input [3:0] a;
input [3:0] b;
output [7:0]op;
assign op= a * b;
endmodule
OUTPUT WAVEFORM:

RESULT:
The 4-bit Multiplier was designed and implemented in hardware.
 Expt.No: 03 Date:

DESIGN ENTRY AND SIMULATION OF ALU

AIM:
To design and implement Arithmetic Logic Unit using Verilog HDL and simulate,
synthesize and implement in FPGA hardware.

APPARATUS REQUIRED:

 PC with Windows XP.

 XILINX software.
 Spartan 3E FPGA Kit.

THEORY:

Arithmetic Logic Unit (ALU) is the fundamental building block of the processor, which is
responsible for carrying out the arithmetic and logic functions. ALU comprises of combinatorial
logic that implements arithmetic operations such as Addition, Subtraction and Multiplication, and
logic operations such as AND, OR, NOT. The ALU gets operands from the register file or memory.
The ALU reads two input operands In A and In B. The operation to perform on these input
operands is selected using the control input Opcode. The ALU performs the selected operation on
the input operands In A and In B and produces the output, Out. The ALU also updates different flag
signals after performing the selected function. Note that the ALU is purely combinatorial logic and
contains no registers or latches.
The arithmetic functions are much more complex to implement than the logic functions.
The performance of the ALU depends upon the architecture of each structural components of the
ALU. The ALU is divided into an arithmetic section and a logical section.

The Arithmetic Unit compromises of three functions. They are:

 Addition
 Subtraction
 Multiplication
The Logical Unit compromises of five functions. They are:
 Bitwise AND
 Bitwise OR
 Bitwise NAND
 Bitwise NOR
 Bitwise XOR
]

PROCEDURE:

1. Start Xilinx ISE 13.1, click on “CREATE A NEW PROJECT” and then click on Next.
2. Select you’re working directory, give the name of the project, and then click on “NEXT”.
3. Select the device family (Spartan 3E), Device (XC3S250E), package (PQ208), Speed grade
(4), Synthesis tool (XST [VHDL/VERILOG]), simulator (ISim) and preferred language
(Verilog) from the available device list, and then click “NEXT” and click FINISH.
4. Write the HDL code and be careful to give the entity name the same as project name. After
writing the code save the file and click on “Synthesis XST”.
5. If the HDL code is error free a green check mark will be shown on the synthesis XST.
6. Select simulation then double click on “Simulate Behavioral Model” (here we can change
the level of abstraction. i.e. structural/behavioral/dataflow/switch level)
7. If there is zero error a new window will be shown. Apply the desired input as 1’s and 0’s
and check whether the outputs are correct or not in the output waveform.
8. In the design window change into implementation and click on “Synthesis XST”. If the
HDL code is error free a green check mark will be shown on the Synthesize – XST.
9. Note down the Device Utilization Summary (Number of Slices , Number of LUTs and
Number of bonded IOBs)
10. Double Click the View RTL Schematic in the process window and RTL Schematic view of
your HDL code.
11. Double Click View Technology Schematic in the process window and View the
Technology Schematic view of your HDL code.
12. In User Constraints, double click I/O Pin Planning (Plan Ahead) –Post synthesize. Plan
Ahead window is opened.
13. Give the input ports and output port 9n the Plan Ahead tool and save the configuration and
close the Plan Ahead window.
14. Double Click the Implementation Design and green check mark will be shown on the
Implementation Icon.
15. In the Design window, change into Post – Route Simulation and by double clicking the
Post-Place & Route Check Syntax and if code is error free a green check mark will be
shown on the Post-Place & Route Check Syntax.
16. Double Click Simulate Post-Place & Route Model and analyze the output waveform.
17. In the design window change into Implementation and process window under
implementation – Place & Route, double click the View/Edit Routed Design (FPGA
Editor), now we can see the routed design of our circuit.
18. A BIT file will be generating by double clicking the Generate Programming File.
19. The BIT file is loaded in the FPGA processor through JTAG or USB cable and the output
can be verified using the hardware kit.
20. MCS file is created and loaded into the PROM for verification.
Programs:

ALU using Behaviour modeling

`timescale 1ns / 1ps

modulealu (op,a,b,opcode);

outputreg[15:0]op; //output of alu

input[7:0] a,b; //inputs toalu
input[3:0]opcode; //control signal for differentoperation

always @(*)
begin
case (opcode)

4'b0000 : begin op = a + b; $display("Addition operation"); end 4'b0001 :

begin op = a - b; $display("Subtraction operation"); end 4'b0010 : begin op
= a * b; $display("Multiplication operation"); end 4'b0011 : begin op = a /
b; $display("Division operation"); end

4'b0100 : begin op = a % b; $display("Modulo Division operation");end

4'b0101 : begin op = a & b; $display("Bit-wise AND operation"); end

4'b0110 : begin op = a | b; $display("Bit-wise OR operation"); end 4'b0111 :

begin op = a && b; $display("Logical AND operation"); end 4'b1000 : begin

op = a || b; $display("Logical OR operation"); end 4'b1001 : begin op = a ^ b;
$display("Bit-wise XOR operation"); end 4'b1010 : begin op = ~ a;
$display("Bit-wise Invert operation"); end 4'b1011 : begin op = ! a;
$display("Logical Invert operation"); end 4'b1100 : begin op = a >> 1;
$display("Right Shift operation"); end 4'b1101 : begin op = a << 1 ;
$display("Left Shift operation"); end 4'b1110 : begin op = a + 1;
$display("Increment operation"); end 4'b1111 : begin op = a - 1;
$display("Decrement operation"); end default:op =8'bXXXXXXXX;
endcase
end

endmodule
OUTPUT WAVEFORM:

RESULT:
The Arithmetic Logic Unit was designed and implemented in hardware.
ExptNo: 04 Date:

DESIGN OF UNIVERSAL SHIFT REGISTER

AIM:
To design and implement the Universal Shift Register using Verilog HDL and
simulate, synthesize and implement in FPGA hardware.

APPARATUS REQUIRED:

 PC with Windows XP.

 Xilinx software.
 Spartan 3E FPGA Kit.

THEORY:
A Universal shift register is a register which has both the right shift and left shift with
parallel load capabilities. Universal shift registers are used as memory elements in computers. A
Unidirectional shift register is capable of shifting in only one direction. A bidirectional shift
register is capable of shifting in both the directions. The Universal shift register is a combination
design of bidirectional shift register and a unidirectional shift register with parallel load provision.

it universal shift register

A n-bit universal shift register consists of n flip-flops and n 4×1 multiplexers. All the n
multiplexers share the same select lines (S1 and S0)to select the mode in which the shift register
operates. The select inputs select the suitable input for the flip-flops.
 S1 S0 REGISTER OPERATION

0 0 No changes

0 1 Shift right

1 0 Shift left

1 1 Parallel load

PROCEDURE:

1. Start Xilinx ISE 13.1, click on “CREATE A NEW PROJECT” and then click on Next.
2. Select you’re working directory, give the name of the project, then click on “NEXT”.
3. Select the device family (Spartan 3E), Device (XC3S250E), package (PQ208), Speed grade
(4), Synthesis tool (XST [VHDL/VERILOG]), simulator (ISim) and preferred language
(Verilog) from the available device list, and then click “NEXT” and click FINISH.
4. Write the HDL code and be careful to give the entity name the same as project name. After
writing the code save the file and click on “Synthesis XST”.
 5. If the HDL code is error free a green check mark will be shown on the synthesis XST.
6. Select simulation then double click on “Simulate Behavioral Model” (here we can change
the level of abstraction. i.e. structural/behavioral/dataflow/switch level)
7. If there is zero error a new window will be shown. Apply the desired input as 1’s and 0’s
and check whether the outputs are correct or not in the output waveform.
8. In the design window change into implementation and click on “Synthesis XST”. If the
HDL code is error free a green check mark will be shown on the Synthesize – XST.
9. Note down the Device Utilization Summary (Number of Slices , Number of LUTs and
Number of bonded IOBs)
10. Double Click the View RTL Schematic in the process window and RTL Schematic view of
your HDL code.
11. Double Click View Technology Schematic in the process window and View the
Technology Schematic view of your HDL code.
12. In User Constraints, double click I/O Pin Planning (Plan Ahead) –Post synthesize. Plan
Ahead window is opened.
13. Give the input ports and output port 9n the Plan Ahead tool and save the configuration and
close the Plan Ahead window.
14. Double Click the Implementation Design and green check mark will be shown on the
Implementation Icon.
15. In the Design window, change into Post – Route Simulation and by double clicking the
Post-Place & Route Check Syntax and if code is error free a green check mark will be
shown on the Post-Place & Route Check Syntax.
16. Double Click Simulate Post-Place & Route Model and analyze the output waveform.
17. In the design window change into Implementation and process window under
implementation – Place & Route, double click the View/Edit Routed Design (FPGA
Editor), now we can see the routed design of our circuit.
18. A BIT file will be generating by double clicking the Generate Programming File.
19. The BIT file is loaded in the FPGA processor through JTAG or USB cable and the output
can be verified using the hardware kit.
20. MCS file is created and loaded into the PROM for verification.

Programs:

Universal Shift Register using Behaviour modeling

`timescale 1ns / 1ps

moduleuniversal_shift(a,s,clk,p);
input [3:0]a;
input [1:0]s;
input clk;
outputreg [3:0]p;
 initial p<=4'b0110;

always@(posedgeclk)
begin
case (s)
2'b00:
begin
p[3]<=p[3]; p[2]<=p[2];
p[1]<=p[1]; p[0]<=p[0];
end
2'b01:
begin
p[3]<=p[0]; p[2]<=p[3];
p[1]<=p[2]; p[0]<=p[1];
end
2'b10:
begin
p[0]<=p[3]; p[1]<=p[0];
p[2]<=p[1]; p[3]<=p[2];
end
2'b11:
begin
p[0]<=a[0]; p[1]<=a[1];
p[2]<=a[2]; p[3]<=a[3];
end
endcase
end
endmodule

OUTPUT WAVE FORM:

RESULT:
The Universal Shift Register was designed and implemented in hardware.
ExptNo: 05 Date:

DESIGN OF FINITE STATE MACHINE

AIM:
To design and implement Finite State Machine model using Verilog HDL and
simulate, synthesize and implement in FPGA hardware.

APPARATUS REQUIRED:

 PC with Windows XP.

 XILINX software.
 Spartan 3E FPGA Kit.

PROCEDURE:

1. Start Xilinx ISE 13.1, click on “CREATE A NEW PROJECT” and then click on Next.
2. Select you’re working directory, give the name of the project, and then click on “NEXT”.
3. Select the device family (Spartan 3E), Device (XC3S250E), package (PQ208), Speed grade
(4), Synthesis tool (XST [VHDL/VERILOG]), simulator (ISim) and preferred language
(Verilog) from the available device list, and then click “NEXT” and click FINISH.
4. Write the HDL code and be careful to give the entity name the same as project name. After
writing the code save the file and click on “Synthesis XST”.
5. If the HDL code is error free a green check mark will be shown on the synthesis XST.
6. Select simulation then double click on “Simulate Behavioral Model” (here we can change
the level of abstraction. i.e. structural/behavioral/dataflow/switch level)
7. If there is zero error a new window will be shown. Apply the desired input as 1’s and 0’s
and check whether the outputs are correct or not in the output waveform.
8. In the design window change into implementation and click on “Synthesis XST”. If the
HDL code is error free a green check mark will be shown on the Synthesize – XST.
9. Note down the Device Utilization Summary (Number of Slices , Number of LUTs and
Number of bonded IOBs)
10. Double Click the View RTL Schematic in the process window and RTL Schematic view of
your HDL code.
11. Double Click View Technology Schematic in the process window and View the
Technology Schematic view of your HDL code.
12. In User Constraints, double click I/O Pin Planning (Plan Ahead) –Post synthesize. Plan
Ahead window is opened.
13. Give the input ports and output port 9n the Plan Ahead tool and save the configuration and
close the Plan Ahead window.
 14. Double Click the Implementation Design and green check mark will be shown on the
Implementation Icon.
15. In the Design window, change into Post – Route Simulation and by double clicking the
Post-Place & Route Check Syntax and if code is error free a green check mark will be
shown on the Post-Place & Route Check Syntax.
16. Double Click Simulate Post-Place & Route Model and analyze the output waveform.
17. In the design window change into Implementation and process window under
implementation – Place & Route, double click the View/Edit Routed Design (FPGA
Editor), now we can see the routed design of our circuit.
18. A BIT file will be generate by double clicking the Generate Programming File.
19. The BIT file is loaded in the FPGA processor through JTAG or USB cable and the output
can be verified using the hardware kit.
20. MCS file is created and loaded into the PROM for verification.

State Diagram

Programs:

FSM Design using Behavioral Modelling

module m1011(clk, rst, inp, outp);

inputclk, rst, inp;

outputoutp;

reg[1:0] state; regoutp;

always@( posedgeclk, rst )
begin
if( rst )
state<= 2'b00;
else
begin
 case( {state,inp} )
3'b000: begin
state<= 2'b00;
outp<= 0;
end
3'b001: begin
state <= 2'b01;
outp<= 0;
end
3'b010: begin
state <= 2'b10;
outp<= 0;
end
3'b011: begin
state <= 2'b01;
outp<= 0;
end
3'b100: begin
state <= 2'b00;
outp<= 0;
end
3'b101: begin
state <= 2'b11;
outp<= 0;
end
3'b110: begin
state <= 2'b10;
outp<= 0;
end
3'b111: begin
state <= 2'b01;
outp<= 1;
end

endcase
end
endendmod
ule
OUTPUT WAVEFORM:

RESULT:
The Finite State machine was designed and implemented in hardware.
ExptNo: 06 Date:

DESIGN OF MEMORIES

AIM:

To design and implement Memory Circuit using Verilog HDL and simulate, synthesize and
implement in FPGA hardware.

APPARATUS REQUIRED:

 PC with Windows XP.

 XILINX software.
 Spartan 3E FPGA Kit.

PROCEDURE:

1. Start Xilinx ISE 13.1, click on “CREATE A NEW PROJECT” and then click on Next.
2. Select you’re working directory, give the name of the project, then click on “NEXT”.
3. Select the device family (Spartan 3E), Device (XC3S250E), package (PQ208), Speed grade
(4), Synthesis tool (XST [VHDL/VERILOG]), simulator (ISim) and preferred language
(Verilog) from the available device list, and then click “NEXT” and click FINISH.
4. Write the HDL code and be careful to give the entity name the same as project name. After
writing the code save the file and click on “Synthesis XST”.
5. If the HDL code is error free a green check mark will be shown on the synthesis XST.
6. Select simulation then double click on “Simulate Behavioral Model” (here we can change
the level of abstraction. i.e. structural/behavioral/dataflow/switch level)
7. If there is zero error a new window will be shown. Apply the desired input as 1’s and 0’s
and check whether the outputs are correct or not in the output waveform.
8. In the design window change into implementation and click on “Synthesis XST”. If the
HDL code is error free a green check mark will be shown on the Synthesize – XST.
9. Note down the Device Utilization Summary (Number of Slices , Number of LUTs and
Number of bonded IOBs)
10. Double Click the View RTL Schematic in the process window and RTL Schematic view of
your HDL code.
11. Double Click View Technology Schematic in the process window and View the
Technology Schematic view of your HDL code.
12. In User Constraints, double click I/O Pin Planning (Plan Ahead) –Post synthesize. Plan
Ahead window is opened.
 13. Give the input ports and output port 9n the Plan Ahead tool and save the configuration and
close the Plan Ahead window.
14. Double Click the Implementation Design and green check mark will be shown on the
Implementation Icon.
15. In the Design window, change into Post – Route Simulation and by double clicking the
Post-Place & Route Check Syntax and if code is error free a green check mark will be
shown on the Post-Place & Route Check Syntax.
16. Double Click Simulate Post-Place & Route Model and analyze the output waveform.
17. In the design window change into Implementation and process window under
implementation – Place & Route, double click the View/Edit Routed Design (FPGA
Editor), now we can see the routed design of our circuit.
18. A BIT file will be generating by double clicking the Generate Programming File.
19. The BIT file is loaded in the FPGA processor through JTAG or USB cable and the output
can be verified using the hardware kit.
20. MCS file is created and loaded into the PROM for verification.

Programs:

moduleraminfr (clk, we, a, di, do);

inputclk;
input we;
input [4:0]a;
input [3:0]di;
output [3:0] do;
reg [3:0] ram[31:0];

always @(posedgeclk) begin

if (we)
ram[a] <= di;
end
assign do = ram[a];
endmodule
OUTPUT WAVEFORM:

RESULT:
The Memory was designed and implemented in hardware.
ExptNo: 07 Date:

DESIGN OF CMOS INVERTER

AIM:
To design and simulate the CMOS inverter and observe the DC and transient
responses and to create the layout of CMOS inverter and extract the parasitic values using cadence
tool.

APPARATUS REQUIRED:
1. Personal Computer with Windows xp
2. Tanner/Cadence EDA

PROCEDURES:
Schematic Entry:
Creating a new library:
1. In the library manager, execute File - New library. The new library form appears.
2. In the new library form, type ‘my design lib’ in the name section.
3. In the field of directory section, verify that the path to the library is set to
~/Database / Cadence- analog – lab –bl3 and click ok.
4. In the next ‘technology file for new library form select option attach to an existing tech
file and click ok.
5. In the ‘attach design library to technology file’ form, select gpdk180 form the cyclic field
and click ok.
6. After creating a new library you can verify it from the library manager.
7. If you right click on the ‘my design lib’ and select properties, you wil find that
gpdk180 library is attached as tech lib to ‘my design lib’.
Creating a schematic cell view:
8. In the CIW or library manager, execute file – new – cell view.
9. Setup the new file form as follows, Do not edit the library path file and the above might
be different from the path shown in your form.
10. Click ok when done the above setting. A black schematic window for the inverter design
appears.
Adding components to schematic:
11. In the inverter schematic window, click the instance fixed menu icon to display the add
instance form.
12. Click on the browse button. This opens up a library browser from which you can select
components and the symbol view.
13. After you complete the add instance form move your cursor to the schematic
window and click left to place a component.
14. This is a table of components for building the inverter schematic.
15. After entering components, click cancel in the add instance form or press ESC with your
cursor in the schematic window.
Adding pins to schematic:
16. Click the pin fixed menu icon in the schematic window. You can execute create pin or
press ‘p’.
LIBRARY NAME CELL NAME PROPERTIES/COMMENTS
gpdk180 PMOS For M0 : model name PMOS1, W = wp, L =180n
gpdk180 NMOS For M1 : model name NMOS1, W = 2u, L =180n
17. Add pin form appears. Type the following in the ADD pin form in the next order leaving
space between the pin.
PIN NAMES DIRECTION
Vin Input
Vout output
18. Select cancel and then the schematic window enter window file or press the f bind key.
Adding wires to schematic:
19. Click the wire (narrow) icon in the schematic window.
20. In the schematic window click on a pin of one of your components as the first point for
your wiring. A diamond shape appears over the starting point of this wire.
21. Follow the prompts at the bottom of design window and click left on the
destination point for your wire. A wire is routed between the source and
destination points.
22. Complete the wiring as shown in the figure and when done wiring press ECS key in the
schematic window to cancel wiring.
Saving the design:
23. Click the check and save icon in the schematic editor window observe CIW output for any
errors.
Building the inverter test design:
Creating the inverter test cell view:
24. In the CIW or library manager, execute file – new – cell view.
25. Setup the new file as shown below.
26. Click ok when done. A blank schematic window for the inverter test design
appears.
27. Using the components list and properties/ comments in this table build the
28. inverter test schematic.

LIBRARY NAME CELL VIEW NAME PROPERTIES/COMMENTS

My design lib Inverter Symbol
Analog lib Vpulse V1 = 0, v2 = 1, td = 0, tr=tf=1ns,
ton = 10ns, T= 20ns
Analog lib Vdc, gnd Vdc = 1.8v

29. Add the above components using create – instance or by pressing I.

 30. Click the wire (narrow) icon and wire your schematic.
31. Click create wire name or press c to name the i/p (vin) and output wires as in below
schematic.
32. Click on the check and save icon to save the design.
Analog simulation with spectra:
Starting the simulation environment:
33. In the inverter-test schematic window execute launch – ADEL. The variable
virtuoso analog design environment (ADE) simulation window appears.
Choosing a simulator:
34. In the simulation window (ADE) execute setup – simulator / directory /host.
35. In the choosing simulator form, set the simulator field to specra and click ok.
36. In the simulation window (ADE) execute the setup model libraries. To
complete, move the cursor and click ok.
Choosing Analysis:
37. Click the choose- Analysis icon in the simulation window(ADE).
38. The choosing analysis form appears.
39. To Setup the transient analysis.
a. In the analysis section select tron.
b. Set the stop time as200ns
c. Click at the moderate or enabled button and the bottom and then click apply.
40. To set for DC analysis
a. In the analysis section select DC.
b. Turn on save DC operating point.
c. Turn on the component parameters.
d. Double click the select V pulse source.
e. Select the DC voltage in the select window parameter and click in the form start and
stop voltages are 0 to1.8.
f. Select the enable button and click apply and then click ok.

Setting deign variables:

41. Click on the edit variable icon and its corresponding form appears.
42. Click copy from at the bottom of the form. The design is scanned. All variables formed in
the design are listed.In the few moments the wp variable name wp and enter.
Value (ixpr) 2u
43. Click change and notice the update and then click ok or cancel (in the editing design
variable window)
Selecting o/p’s for plotting:
44. Execute the o/p’s to be plotted -select on s schematic in the simulation window.
45. Follow the prompt at the bottom. Click on the o/p net vout input vin of the
inverter. Press esc with the cursor after selecting.
Running the simulation:
46. Execute the simulation Net list and run in the simulation window to start the
simulation on the icon. This will create the net list as well as run the simulation.
47. When the simulation finishes the transient DC plots automatically with the log file.
Creating layout view of inverter:
48. From the inverter schematic window menu execute Launch – layout XL. A startup option
form appears.
49. Select create new option. This gives a new cell view form.
50. Check the cell name (inverter). View name (Layout).
51. Click ok from the new cell view form. LSW and a black layout window appear along
with schematic window.
Adding components to layout:
52. Execute connecting Generate – All from source or click the icon in the layout editor
window. Generate the layout form appears. Click ok which imports the schematic
components into the layout window automatically.
53. Rearrange the components with in PR – Boundary as shown.
54. To rotate a component select the component and execute Edit – Properties. Now select
the degree of rotation from the property edit form.
55. Move a component, select the component and execute edit – Move command.
Making connection:
56. Execute connectivity – Nets – show/hide selected incomplete Nets or click the icon in the
layout menu.
57. Move the mouse pointer over the device and click LMB to get the connectivity
information which shows the guide lines for the interconnections of the components.
58. From the layout window, execute create – shape – path / create wire or create – shape –
rectangle and select the appropriate layers from the LSW window and vi as for making the
interconnections.

Creating contacts/vias:
Execute create-via to place different contacts.
Connection Contact Type
For metal 1 – Polyconnection Metal 1 –Poly
For metal 1 – psubstrate connection Metal 1 – psub
For metal 1 – nwell connection Metal 1 - nwell
Saving the design:
Save your design by selecting file – save to save the layout and layout appears.

Running a DRC:
59. Open the inverter layout form the CIW or library manager if you have closed that. Press
shift –f in the layout to display all the levels.
 60. Select As sura – Run DRC from layout window. The DRC form appears. The library and
cellname are taken from the current design window, but rule file maybe missing.
61. Select the technology as gpdk180. This automatically loads the rule file.
62. Click ok to start DRC.
63. A progress form will appear. You can click on the watch log file to see the log file.
64. When DRC finishes a dialog box asking you if you want to view your DRC results, and
click yes to view results of the run.
65. If there any DRC results in the design view layer window (VLW) and error layer
window (ELW) appears. Also the errors highlight in the design itself.
66. Click view – summary in the ELW to find the details of error.
67. You can refer to the run file for info, correct all the DRC error and the Re-run the DRC.
68. If there are no errors in the layout then a dialog bo appears with no DRC errors found
written in it, click on close to terminate the DRC run.

Running LVS:
69. Select Assura – Run LVS from the layout window. The Assura – Run – LVS form
appears. It will automatically load both the schematic and layout view of the cell and
click ok.
70. The LVS begins and a progress form appears.
71. If the schematic and layout matches completely, you will get form displaying
schematic and layout match.
72. If the schematic and layout do not matches, a form informs that the LVS completed
successfully and asks if you want to see the results of this sum.
73. Click yes in the form.
74. In the LVS dialog box you can find the details of mismatches and you need to correct
all those mismatches and Re-Run the LVS.
75. In the filtering tab of the form enter power nets as vdd! , vss! And enter ground nets
asgnd!
76. Click ok in the assura parasitic extraction form when done. The RCX progress form
appears, in the progress form click watch log file to see the output log file.
77. When RCX completes, a dialog box appears, informs you that Assura RCX run
completed successfully.
78. You can open the av-extracted view from the library manager and view the
parasitic.
 Circuit Diagram:

SIMULATION OUTPUT:

RESULT:

The CMOS inverter Schematic and symbol was created and DC and Transient analysis were
done. Manual layout was drawn and parasitic extraction was done.
ExptNo: 08 Date:

DESIGN OF CMOS BASIC GATES & FLIP-FLOPS

AIM:
To design and simulate the CMOS basic gates and D Flip-Flop and observe the DC
and transient responses and to create the layout of them and extract the parasitic values using cadence
EDA tool.
APPARATUS REQUIRED:
1. Personal Computer with Windows xp
2. Tanner/Cadence EDA
PROCEDURES:
Schematic Entry:
Creating a new library:
1. In the library manager, execute File - New library. The new library form appears.
2. In the new library form, type ‘my design lib’ in the name section.
3. In the field of directory section, verify that the path to the library is set to
~/Database / Cadence- analog – lab –bl3 and click ok.
4. In the next ‘technology file for new library form select option attach to an existing tech
file and click ok.
5. In the ‘attach design library to technology file’ form, select gpdk180 form the cyclic field
and click ok.
6. After creating a new library you can verify it from the library manager.
7. If you right click on the ‘my design lib’ and select properties, you will find that
gpdk180 library is attached as tech lib to ‘my design lib’.
Creating a schematic cell view:
8. In the CIW or library manager, execute file – new – cell view.
9. Setup the new file form as follows, Do not edit the library path file and the above might
be different from the path shown in your form.
10. Click ok when done the above setting. A black schematic window for the inverter design
appears.
Adding components to schematic:
11. In the inverter schematic window, click the instance fixed menu icon to display the add
instance form.
12. Click on the browse button. This opens up a library browser from which you can select
components and the symbol view.
13. After you complete the add instance form move your cursor to the schematic
window and click left to place a component.
14. This is a table of components for building the inverter schematic.
15. After entering components, click cancel in the add instance form or press ESC with your
cursor in the schematic window.
Adding pins to schematic:
16. Click the pin fixed menu icon in the schematic window. You can execute create pin or
press ‘p’.
LIBRARY NAME CELL NAME PROPERTIES/COMMENTS
gpdk180 PMOS For M0 : model name PMOS1, W = wp, L =180n
gpdk180 NMOS For M1 : model name NMOS1, W = 2u, L =180n
17. Add pin form appears. Type the following in the ADD pin form in the next order leaving
space between the pin.
PIN NAMES DIRECTION
Vin Input
Vout output
18. Select cancel and then the schematic window enter window file or press the f bind key.
Adding wires to schematic:
19. Click the wire (narrow) icon in the schematic window.
20. In the schematic window click on a pin of one of your components as the first point for
your wiring. A diamond shape appears over the starting point of this wire.
21. Follow the prompts at the bottom of design window and click left on the
destination point for your wire. A wire is routed between the source and
destination points.
22. Complete the wiring as shown in the figure and when done wiring press ECS key in the
schematic window to cancel wiring.
Saving the design:
23. Click the check and save icon in the schematic editor window observe CIW output for any
errors.
Building the inverter test design:
Creating the inverter test cell view:
24. In the CIW or library manager, execute file – new – cell view.
25. Setup the new file as shown below.
26. Click ok when done. A blank schematic window for the inverter test design
appears.
27. Using the components list and properties/ comments in this table build the inverter test
schematic.

LIBRARY NAME CELL VIEW NAME PROPERTIES/COMMENTS

My design lib Inverter Symbol
Analog lib Vpulse V1 = 0, v2 = 1, td = 0, tr=tf=1ns,
ton = 10ns, T= 20ns
Analog lib Vdc, gnd Vdc = 1.8v

28. Add the above components using create – instance or by pressing I.

 29. Click the wire (narrow) icon and wire your schematic.
30. Click create wire name or press c to name the i/p (vin) and output wires as in
31. below schematic.
32. Click on the check and save icon to save the design.
Analog simulation with spectra:
Starting the simulation environment:
33. In the inverter-test schematic window execute launch – ADEL. The variable
virtuoso analog design environment (ADE) simulation window appears.
Choosing a simulator:
34. In the simulation window (ADE) execute setup – simulator / directory /host.
35. In the choosing simulator form, set the simulator field to specra and click ok.
36. In the simulation window (ADE) execute the setup model libraries. To
complete, move the cursor and click ok.
Choosing Analysis:
37. Click the choose- Analysis icon in the simulation window (ADE).
38. The choosing analysis form appears.
39. To Setup the transient analysis.
a. In the analysis section select tron.
b. Set the stop time as200ns
c. Click at the moderate or enabled button and the bottom and then click apply.
40. To set for DC analysis
a. In the analysis section select DC.
b. Turn on save DC operating point.
c. Turn on the component parameters.
d. Double click the select V pulse source.
e. Select the DC voltage in the select window parameter and click in the form start and
stop voltages are 0 to1.8.
f. Select the enable button and click apply and then click ok.

Setting deign variables:

41. Click on the edit variable icon and its corresponding form appears.
42. Click copy from at the bottom of the form. The design is scanned. All variables formed in
the design are listed.In the few moments the wp variable name wp and enter.
Value (ixpr) 2u
43. Click change and notice the update and then click ok or cancel (in the
44. editing design variable window)
Selecting o/p’s for plotting:
45. Execute the o/p’s to be plotted -select on s schematic in the simulation window.
46. Follow the prompt at the bottom. Click on the o/p net vout input vin of the
inverter. Press esc with the cursor after selecting.
Running the simulation:
47. Execute the simulation Net list and run in the simulation window to start the
simulation on the icon. This will create the net list as well as run the simulation.
48. When the simulation finishes the transient DC plots automatically with the log file.
Creating layout view of inverter:
49. From the inverter schematic window menu execute Launch – layout XL. A startup option
form appears.
50. Select create new option. This gives a new cell view form.
51. Check the cell name (inverter). View name(Layout).
52. Click ok from the new cell view form. LSW and a black layout window appears along
with schematic window.
Adding components to layout:
53. Execute connecting Generate – All from source or click the icon in the layout editor
window. Generate the layout form appears. Click ok which imports the schematic
components into the layout window automatically.
54. Rearrange the components with in PR – Boundary as shown.
55. To rotate a component select the component and execute Edit – Properties. Now select
the degree of rotation from the property edit form.
56. Move a component, select the component and execute edit – Move command.
Making connection:
57. Execute connectivity – Nets – show/hide selected incomplete Nets or click the icon in the
layout menu.
58. Move the mouse pointer over the device and click LMB to get the connectivity
information which shows the guide lines for the interconnections of the components.
59. From the layout window, execute create – shape – path / create wire or create – shape –
rectangle and select the appropriate layers from the LSW window and vias for making the
interconnections.

Creating contacts/vias:
Execute create-via to place different contacts.
Connection Contact Type
For metal 1 – Polyconnection Metal 1 –Poly
For metal 1 – psubstrate connection Metal 1 – psub
For metal 1 – nwell connection Metal 1 - nwell

Saving the design:

Save your design by selecting file – save to save the layout and layout appears.
Running a DRC:
60. Open the inverter layout form the CIW or library manager if you have closed that. Press
shift –f in the layout to display all the levels.
61. Select Assura – Run DRC from layout window. The DRC form appears. The library and
cell name are taken from the current design window, but rule file maybe missing.
62. Select the technology as gpdk180. This automatically loads the rule
63. file.
64. Click ok to start DRC.
65. A progress form will appear. You can click on the watch log file to see the log
66. file.
67. When DRC finishes a dialog box asking you if you want to view your DRC results, and
click yes to view results of the run.
68. If there any DRC results in the design view layer window (VLW) and error layer
window (ELW) appears. Also the errors highlight in the design itself.
69. Click view – summary in the ELW to find the details of error.
70. You can refer to the run file for info, correct all the DRC error and the Re-run the DRC.
71. If there are no errors in the layout then a dialog bo appears with no DRC errors found
written in it, click on close to terminate the DRC run.

Running LVS:
72. Select Assura – Run LVS from the layout window. The Assura – Run – LVS form
appears. It will automatically load both the schematic and layout view of the cell and
click ok.
73. The LVS begins and a progress form appears.
74. If the schematic and layout matches completely, you will get form displaying
schematic and layout match.
75. If the schematic and layout do not matches, a form informs that the LVScompleted
successfully and asks if you want to see the results of thissum.
76. Click yes in the form.
77. In the LVS dialog box you can find the details of mismatches and you need to correct
all those mismatches and Re-Run the LVS.
78. In the filtering tab of the form enter power nets as vdd! , vss! And enter ground nets
asgnd!
79. Click ok in the assura parasitic extraction form when done. The RCX progress form
appears, in the progress form click watch log file to see the output log file.
80. When RCX completes, a dialog box appears, informs you that Assura RCX run
completed successfully.
81. You can open the av-extracted view from the library manager and view the
parasitic.
 Circuit Diagram:

CMOS LOGIC – NAND Gate CMOS LOGIC – NOR Gate

CMOS Negative Edge Triggered Flip-Flop

SIMULATION OUTPUT:

RESULT:

The 2 input NAND and NOR gates and Negative Edge D Flip Flop Schematics and symbols
were created and DC and Transient analysis were done. Manual layout was drawn and parasitic
extraction was done.
ExptNo: 09 Date:

DESIGN OF 4-BIT SYNCHRONOUS COUNTER USING FLIP-FLOP

AIM:
To design, simulate and synthesize the 4-bit synchronous counter circuit and
generate the automatic layout and simulate through post layout extraction using Cadence tool.

APPARATUS REQUIRED:

1. Personal Computer with Windows xp

2. Tanner/Cadence tool

PROCEDURES:

1. Write a verilog program (file name.v) for counter circuit and save it and close.
2. Simulate through the nc sim command and give the inputs and check the output through
the simvision window.
3. Synthesize and elaborate the verilog program.
4. Create a constraint file (filename.g) and read the file.
5. Synthesize the circuit and note down the power, timing parameters.
6. Create a net file (filename_net.v) and the hdl net file.
7. Open the encounter tool for automatic layout genearation.
8. Import the filename_net.v and select the *.leffile.
9. Create the power and ground nets.
10. Create the *.view file
11. Specify the floor plan structure and define the core utilization area.
12. Create power rings and nets (VDD and VSS) and select the ring configuration for metal
layers.
13. Create the power stripes and specify the number of sets to be used.
14. Route the design and Place the standard cells.
15. Do the Pre-CTS, clock synthesize, post-CTS and extract RC operations.
16. Create the *.gdsfile.
 PROGRAM:

Up Counter Design using Behavioral

Modellingmodule
counter_up_down(out,clk,reset,control); output
[3:0]out;
inputclk, reset,control;
reg [3:0] out;
always @(negedgeclk or posedge reset)
if(reset)
out<=4'b0000;
else
out<=out+1;
endmodule

OUTPUT:

RESULT:
The counter circuit was designed, simulated and synthesized and generated the automatic
layout and simulate through post layout extraction using Cadence tool.
ExptNo: 10 Date:
DESIGN OF CMOS INVERTING AMPLIFIER
AIM:
To design and simulate the simple CMOS inverting amplifier and observe the DC
and transient responses, calculate CMRR.
APPARATUS REQUIRED:
1. Personal Computer with Windows xp
2. Tanner/Cadence tool
PROCEDURES:
Schematic Entry:
Creating a new library:
1. In the library manager, execute File - New library. The new library form appears.
2. In the new library form, type ‘my design lib’ in the name section.
3. In the field of directory section, verify that the path to the library is set to
~/Database / Cadence- analog – lab –bl3 and click ok.
4. In the next ‘technology file for new library form select option attach to an existing tech
file and click ok.
5. In the ‘attach design library to technology file’ form, select gpdk180 form the cyclic field
and click ok.
6. After creating a new library you can verify it from the library manager.
7. If you right click on the ‘my design lib’ and select properties, you will find that
gpdk180 library is attached as tech lib to ‘my design lib’.
Creating a schematic cell view:
8. In the CIW or library manager, execute file – new – cell view.
9. Setup the new file form as follows, Do not edit the library path file and the above might
be different from the path shown in your form.
10. Click ok when done the above setting. A black schematic window for the inverter design
appears.
Adding components to schematic:
11. In the inverter schematic window, click the instance fixed menu icon to display the add
instance form.
12. Click on the browse button. This opens up a library browser from which you can select
components and the symbol view.
13. After you complete the add instance form move your cursor to the schematic
window and click left to place a component.
14. This is a table of components for building the inverter schematic.
15. After entering components, click cancel in the add instance form or press ESC with your
cursor in the schematic window.
Adding pins to schematic:
16. Click the pin fixed menu icon in the schematic window. You can execute create pin or
press ‘p’.
 LIBRARY NAME CELL NAME PROPERTIES/COMMENTS
gpdk180 PMOS For M0 : model name PMOS1, W = wp, L =180n
gpdk180 NMOS For M1 : model name NMOS1, W = 2u, L =180n
17. Add pin form appears. Type the following in the ADD pin form in the nextorder leaving
space between the pin.
PIN NAMES DIRECTION
Vin Input
Vout output
18. Select cancel and then the schematic window enter window file or press the f bind key.
Adding wires to schematic:
19. Click the wire (narrow) icon in the schematic window.
20. In the schematic window click on a pin of one of your components as the first point for
your wiring. A diamond shape appears over the starting point of this wire.
21. Follow the prompts at the bottom of design window and click left on the
destination point for your wire. A wire is routed between the source and
destination points.
22. Complete the wiring as shown in the figure and when done wiring press ECS key in the
schematic window to cancel wiring.
Saving the design:
23. Click the check and save icon in the schematic editor window observe CIW output for any
errors.
Building the inverter test design:
Creating the inverter test cell view:
24. In the CIW or library manager, execute file – new – cell view.
25. Setup the new file as shown below.
26. Click ok when done. A blank schematic window for the inverter test design
appears.
27. Using the components list and properties/ comments in this table build the inverter test
schematic.

LIBRARY NAME CELL VIEW NAME PROPERTIES/COMMENTS

My design lib Inverter Symbol
Define pulse specification as AC
Magnitude= 1; DC Voltage= 0; Offset
Analog lib Vsin Voltage= 0; Amplitude= 5m;
Frequency= 1K
Analog lib Vdc, gnd vdd=2.5 ; vss= -2.5

28. Add the above components using create – instance or by pressing I.

29. Click the wire (narrow) icon and wire your schematic.
 30. Click create wire name or press c to name the i/p (vin) and output wires as in below
schematic.
31. Click on the check and save icon to save the design.
Analog simulation with spectra:
Starting the simulation environment:
32. In the inverter-test schematic window execute launch – ADEL. The variable
virtuoso analog design environment (ADE) simulation window appears.
Choosing a simulator:
33. In the simulation window (ADE) execute setup – simulator / directory /host.
34. In the choosing simulator form, set the simulator field to specra and click ok.
35. In the simulation window (ADE) execute the setup model libraries. To
complete, move the cursor and click ok.
Choosing Analysis:
36. Click the choose- Analysis icon in the simulation window(ADE).
37. The choosing analysis form appears.
38. To Setup the transient analysis.
a. In the analysis section select tron.
b. Set the stop time as200ns
c. Click at the moderate or enabled button and the bottom and then click apply.
39. To set for DC analysis
a. In the analysis section select DC.
b. Turn on save DC operating point.
c. Turn on the component parameters.
d. Double click the select V pulse source.
e. Select the DC voltage in the select window parameter and click in the form start and
stop voltages are 0 to1.8.
f. Select the enable button and click apply and then click ok.
Setting deign variables:
40. Click on the edit variable icon and its corresponding form appears.
41. Click copy from at the bottom of the form. The design is scanned. All variables formed in
the design are listed.In the few moments the wp variable name wp and enter.
Value (ixpr) 2u
42. Click change and notice the update and then click ok or cancel (in the editing design
variable window)
Selecting o/p’s for plotting:
43. Execute the o/p’s to be plotted -select on s schematic in the simulation window.
44. Follow the prompt at the bottom. Click on the o/p net vout input vin of the
inverter. Press esc with the cursor after selecting.
 Running the simulation:
45. Execute the simulation Net list and run in the simulation window to start the
simulation on the icon. This will create the net list as well as run the simulation.
46. When the simulation finishes the transient DC plots automatically with the log file.

Schematic Diagram

SIMULATION OUTPUT:

RESULT:
The simple CMOS inverting Amplifier Schematic and symbol was created, DC and Transient
analysis were done, and CMRR was obtained from the results.
ExptNo: 11 Date:
DESIGN OF DIFFERENTIAL AMPLIFIER

AIM:
To design and simulate the simple Differential amplifier and observe the DC and
transient responses, calculate CMRR and to create the layout of CMOS inverter and
extract the parasitic values using cadence tool.

APPARATUS REQUIRED:

1. Personal Computer with Windows xp

2. Tanner/Cadence tool

PROCEDURES:

Schematic Entry:

Creating a new library:

1. In the library manager, execute File - New library. The new library form appears.
2. In the new library form, type ‘my design lib’ in the name section.
3. In the field of directory section, verify that the path to the library is set to
~/Database / Cadence- analog – lab –bl3 and click ok.
4. In the next ‘technology file for new library form select option attach to an existing tech
file and click ok.
5. In the ‘attach design library to technology file’ form, select gpdk180 form the cyclic field
and click ok.
6. After creating a new library you can verify it from the library manager.
7. If you right click on the ‘my design lib’ and select properties, you will find that
gpdk180 library is attached as tech lib to ‘my design lib’.

Creating a schematic cell view:

8. In the CIW or library manager, execute file – new – cell view.

9. Setup the new file form as follows, Do not edit the library path file and the above might
be different from the path shown in your form.
10. Click ok when done the above setting. A black schematic window for the inverter design
appears.

Adding components to schematic:

11. In the inverter schematic window, click the instance fixed menu icon to display the add
instance form.
 12. Click on the browse button. This opens up a library browser from which you can select
components and the symbol view.
13. After you complete the add instance form move your cursor to the schematic

LIBRARY NAME CELL NAME PROPERTIES/COMMENTS

For M0 : model name PMOS1,
gpdk180 PMOS
W = wp, L =180n
gpdk180 NMOS For M1 : model name NMOS1,
W = 2u, L =180n
window and click left to place a component.
14. This is a table of components for building the inverter schematic.

15. After entering components, click cancel in the add instance form or press ESC with your
cursor in the schematic window.

Adding pins to schematic:

16. Click the pin fixed menu icon in the schematic window. You can execute create pin or
press ‘p’.
17. Add pin form appears. Type the following in the ADD pin form in the next order leaving
space between the pin.

PIN NAMES DIRECTION

Vin Input
Vout output

18. Select cancel and then the schematic window enter window file or press the f bind key.

Adding wires to schematic:

19. Click the wire (narrow) icon in the schematic window.

20. In the schematic window click on a pin of one of your components as the first point for
your wiring. A diamond shape appears over the starting point of this wire.
21. Follow the prompts at the bottom of design window and click left on the
destination point for your wire. A wire is routed between the source and
destination points.
22. Complete the wiring as shown in the figure and when done wiring press ECS key in the
schematic window to cancel wiring.

Saving the design:

Click the check and save icon in the schematic editor window observe CIW output for any
errors.
Building the inverter test design: Creating
the inverter test cell view:

23. In the CIW or library manager, execute file – new – cell view.
24. Setup the new file as shown below.
25. Click ok when done. A blank schematic window for the inverter test design
appears.
26. Using the components list and properties/ comments in this table build the inverter test
schematic.

CELL VIEW
LIBRARY NAME PROPERTIES/COMMENTS
NAME
My design lib Inverter Symbol
V1 = 0, v2 = 1, td = 0,
Analog lib Vpulse tr=tf=1ns, ton = 10ns, T=
20ns
Analog lib Vdc, gnd Vdc = 1.8v

27. Add the above components using create – instance or by pressing I.

28. Click the wire (narrow) icon and wire your schematic.
29. Click create wire name or press c to name the i/p (vin) and output wires as in below
schematic.
30. Click on the check and save icon to save the design.

Analog simulation with spectra: Starting

the simulation environment:

31. In the inverter-test schematic window execute launch – ADEL. The variable
virtuoso analog design environment (ADE) simulation window appears.

Choosing a simulator:

32. In the simulation window (ADE) execute setup – simulator / directory /host.
33. In the choosing simulator form, set the simulator field to spectra and click ok.
34. In the simulation window (ADE) execute the setup model libraries. To
complete, move the cursor and click ok.

Choosing Analysis:

35. Click the choose- Analysis icon in the simulation window(ADE).

36. The choosing analysis form appears.
37. To Setup the transient analysis.
a. In the analysis section select tron.
b. Set the stop time as200ns
 c. Click at the moderate or enabled button and the bottom and then click apply.
38. To set for DC analysis
a. In the analysis section select DC.
b. Turn on save DC operating point.
c. Turn on the component parameters.
d. Double click the select V pulse source.
e. Select the DC voltage in the select window parameter and click in the form start and
stop voltages are 0 to1.8.
f. Select the enable button and click apply and then click ok.

Setting deigns variables:

39. Click on the edit variable icon and its corresponding form appears.
40. Click copy from at the bottom of the form. The design is scanned. All variables formed in
the design are listed.In the few moments the wp variable name wp and enter.
Value (ixpr) 2u
41. Click change and notice the update and then click ok or cancel (in the editing design
variable window)

Selecting o/p’s for plotting:

42. Execute the o/p’s to be plotted -select on s schematic in the simulation window.
43. Follow the prompt at the bottom. Click on the o/p net vout input vin of the
inverter. Press esc with the cursor after selecting.

Running the simulation:

44. Execute the simulation Net list and run in the simulation window to start the
simulation on the icon. This will create the net list as well as run the simulation.
45. When the simulation finishes the transient DC plots automatically with the log file.
 Schematic Diagram

OUTPUT WAVEFORM:

RESULT:
The simple Differential Amplifier Schematic and symbol was created and DC and
Transient analysis were done.
ExptNo: 12 Date:

DESIGN OF COMMON SOURCE, COMMON GATE AND COMMON

DRAINAMPLIFIERS

AIM:
To design and simulate the simple Differential amplifier and observe the DC and
transient responses, calculate CMRR and to create the layout of CMOS inverter and extract the
parasitic values using cadence tool.

APPARATUS REQUIRED:

1. Personal Computer with Windows xp

2. Tanner/Cadence tool

PROCEDURES:

Schematic Entry:

Creating a new library:

1. In the library manager, execute File - New library. The new library form appears.
2. In the new library form, type ‘my design lib’ in the name section.
3. In the field of directory section, verify that the path to the library is set to
~/Database / Cadence- analog – lab –bl3 and click ok.
4. In the next ‘technology file for new library form select option attach to an existing tech
file and clickok.
5. In the ‘attach design library to technology file’ form, select gpdk180 form the cyclic field
and clickok.
6. After creating a new library you can verify it from the library manager.
7. If you right click on the ‘my design lib’ and select properties, you will find that
gpdk180 library is attached as tech lib to ‘my design lib’.

Creating a schematic cell view:

8. In the CIW or library manager, execute file – new – cell view.

9. Setup the new file form as follows, Do not edit the library path file and the above might
be different from the path shown in your form.
10. Click ok when done the above setting. A black schematic window for the inverter design
appears.

Adding components to schematic:

11. In the inverter schematic window, click the instance fixed menu icon to display the add
instance form.
 12. Click on the browse button. This opens up a library browser from which you can select
components and the symbol view.
13. After you complete the add instance form move your cursor to the schematic

LIBRARY NAME CELL NAME PROPERTIES/COMMENTS

For M0 : model name PMOS1,
gpdk180 PMOS
W = wp, L =180n
gpdk180 NMOS For M1 : model name NMOS1,
W = 2u, L =180n
window and click left to place a component.
14. This is a table of components for building the inverterschematic.

15. After entering components, click cancel in the add instance form or press ESC with your
cursor in the schematic window.

Adding pins to schematic:

16. Click the pin fixed menu icon in the schematic window. You can execute create pin or
press ‘p’.
17. Add pin form appears. Type the following in the ADD pin form in the next order leaving
space between the pin.

PIN NAMES DIRECTION

Vin Input
Vout Output

18. Select cancel and then the schematic window enter window file or press the f bind key.

Adding wires to schematic:

19. Click the wire (narrow) icon in the schematic window.

20. In the schematic window click on a pin of one of your components as the first point for
your wiring. A diamond shape appears over the starting point of this wire.
21. Follow the prompts at the bottom of design window and click left on the
destination point for your wire. A wire is routed between the source and
destination points.
22. Complete the wiring as shown in the figure and when done wiring press ECS key in the
schematic window to cancel wiring.

Saving the design:

Click the check and save icon in the schematic editor window observe CIW output for any
errors.

Building the inverter test design:

Creating the inverter test cell view:

23. In the CIW or library manager, execute file – new – cell view.
24. Setup the new file as shown below.
25. Click ok when done. A blank schematic window for the inverter test design
appears.
26. Using the components list and properties/ comments in this table build the inverter test
schematic.

CELL VIEW
LIBRARY NAME PROPERTIES/COMMENTS
NAME
My design lib Inverter Symbol
V1 = 0, v2 = 1, td = 0,
Analog lib Vpulse tr=tf=1ns, ton = 10ns, T=
20ns
Analog lib Vdc, gnd Vdc = 1.8v

27. Add the above components using create – instance or by pressing I.

28. Click the wire (narrow) icon and wire your schematic.
29. Click create wire name or press c to name the i/p (vin) and output wires as in below
schematic.
30. Click on the check and save icon to save the design.

Analog simulation with spectra: Starting

the simulation environment:

31. In the inverter-test schematic window execute launch – ADEL. The variable
virtuoso analog design environment (ADE) simulation window appears.

Choosing a simulator:

32. In the simulation window (ADE) execute setup – simulator / directory /host.
33. In the choosing simulator form, set the simulator field to spectra and click ok.
34. In the simulation window (ADE) execute the setup model libraries. To
complete, move the cursor and click ok.

Choosing Analysis:

35. Click the choose- Analysis icon in the simulation window(ADE).

36. The choosing analysis form appears.
37. To Setup the transient analysis.
a. In the analysis section select tron.
b. Set the stop time as200ns
c. Click at the moderate or enabled button and the bottom and then click apply.
 38. To set for DC analysis
a. In the analysis section select DC.
b. Turn on save DC operating point.
c. Turn on the component parameters.
d. Double click the select V pulse source.
e. Select the DC voltage in the select window parameter and click in the form start and
stop voltages are 0 to1.8.
f. Select the enable button and click apply and then click ok.

Setting deign variables:

39. Click on the edit variable icon and its corresponding form appears.
40. Click copy from at the bottom of the form. The design is scanned. All variables formed in
the design are listed.In the few moments the wp variable name wp and enter.
Value (ixpr) 2u
41. Click change and notice the update and then click ok or cancel (in the editing design
variable window)

Selecting o/p’s for plotting:

42. Execute the o/p’s to be plotted -select on s schematic in the simulation window.
43. Follow the prompt at the bottom. Click on the o/p net vout input vin of the
inverter. Press esc with the cursor after selecting.

Running the simulation:

44. Execute the simulation Net list and run in the simulation window to start the
simulation on the icon. This will create the net list as well as run the simulation.
45. When the simulation finishes the transient DC plots automatically with the log file.
Schematic Diagram

Common Source Amplifier Common Drain Amplifier

OUTPUT:

RESULT:
The common source, common gate and common drain amplifiers Schematic and symbol was
created and DC and Transient analysis were done.
Expt.No: 13 Date:

STUDY OF VERILOG HDL AND SPARTAN-3E FPGA BOARD

AIM:

To study Verilog HDL, Spartan-3E FPGA board and the related software.

SOFTWARE USED:
Xilinx software.

DEVICE USED:
Spartan-3E FPGA 250S

THEORY:

INTRODUCTION TO VERILOG HDL:

Verilog HDL is one of the Hardware Description Languages (HDL) used to describe a
digital system. VHDL is the other one. Verilog HDL allows a hardware designer to describe
designs at a high level of abstraction such as an the architectural or behavioral level as a set of
modules. Modules can either be specified behaviorally or structurally (for a combination of two). A
behavioral specification defines the behavior of a digital system (module) using traditional
programming language constructs. E.g. if assignment statements. A structural specification
expresses the behavior of a digital system (module) as a hierarchical interconnection of sub
modules. At the bottom of the hierarchy the components must be primitives or specified
behaviorally. Verilog provides the following gate level primitives:

And/nand - logical AND/NAND

or/nor - logical OR/NOR xor/xnor
- logical XOR/XNOR
buf/not - buffer/inverter
bufif0/notif0- tristate with low enable
bufif1/notif1- tristate with high enable

The structure of a module is the following:

Module <module name> (<port list>);

<(declares)>
<module items>
End module.

The <module name> is an identifier that uniquely names the module. The <port list> is a list of
input, in-out and output ports which are used to connect to other modules. The
<declares> section specifies data objects as registers, memories and wires as well as procedural
constructs such as functions and tasks. The <module items> may be initial constructs, always
constructs, continuous assignments or instances of modules.

OPERATORS:

Bitwise operators: ~(not), &(and), |(or) and ^(xor)

Arithmetic: +, -, *, /
Unary reduction: &, &&, |, ~|, ^, ~ ^
Logical: !, &&, ||
Equality: ==, != (0,1)
Identity: ===, !== (0,1,x,z)
Relational: <,>,<=,>=
Logical shift : <<, >>
Conditional: ?:
Concatenate: {}
Replicate: {{}}

DESIGN FLOW:

DESIGN ENTRY: The designed circuit is specified either by means of a schematic

diagram or by using a hardware description language, such as Verilog or VHDL.

SYNTHESIS: The entered design is synthesized into a circuit that consists of the logic elements
(LE’s) provided in the FPGA board.

FUNCTIONAL SIMULATION: The synthesized circuit is tested to verify it’s functional

correctness. This simulation does not take into account any timing issues. A test bench is HDL code
that allows you to provide a repeatable set of stimuli with clock and input date for
error checking, file input and output and conditional testing.

FITTING: The CAD filter told determines the placement of LE’s defined in the net list into the
LE’s in the actual FPGA chip. It also chooses routing wires in the chip to make the required
connections between specific LE’s.

TIMING ANALYSIS: Propagation delays along the various paths in the fitted circuit are analyzed
to provide an indication of the expected performance of the circuit.

TIMING SIMULATION: The fitted circuit is tested to verify both its functional correctness and
timing.
PROGRAMMING AND CONFIGURATION: The designed circuit is implemented in a physical
FPGA chip by programming the configuration switches that configure the LE’s and established the
required wiring connections.

Fig. Flow chart of VLSI design flow

PROCEDURE OF XILINX SOFTWARE:

1. Start Xilinx ISE 13.1, click on “CREATE A NEW PROJECT” and then click on Next.
2. Select you’re working directory, give the name of the project, then click on “NEXT”.
3. Select the device family (Spartan 3E), Device (XC3S250E), package (PQ208), Speed grade
(4), Synthesis tool (XST [VHDL/VERILOG]), simulator (ISim) and preferred language
(Verilog) from the available device list, and then click “NEXT” and click FINISH.
4. Write the HDL code and be careful to give the entity name the same as project name. After
writing the code save the file and click on “Synthesis XST”.
5. If the HDL code is error free a green check mark will be shown on the synthesis XST.
6. Select simulation then double click on “Simulate Behavioral Model” (here we can change
the level of abstraction. i.e. structural/behavioral/dataflow/switch level)
7. If there is zero error a new window will be shown. Apply the desired input as 1’s and 0’s
and check whether the outputs are correct or not in the output waveform.
8. In the design window change into implementation and click on “Synthesis XST”. If the
HDL code is error free a green check mark will be shown on the Synthesize – XST.
9. Note down the Device Utilization Summary (Number of Slices , Number of LUTs and
Number of bonded IOBs)
10. Double Click the View RTL Schematic in the process window and RTL Schematic view of
your HDL code.
11. Double Click View Technology Schematic in the process window and View the
Technology Schematic view of your HDL code.
12. In User Constraints, double click I/O Pin Planning (Plan Ahead) –Post synthesize. Plan
Ahead window is opened.
13. Give the input ports and output port 9n the Plan Ahead tool and save the configuration and
close the Plan Ahead window.
14. Double Click the Implementation Design and green check mark will be shown on the
Implementation Icon.
15. In the Design window, change into Post – Route Simulation and by double clicking the
Post-Place & Route Check Syntax and if code is error free a green check mark will be
shown on the Post-Place & Route Check Syntax.
16. Double Click Simulate Post-Place & Route Model and analyze the output waveform.
17. In the design window change into Implementation and process window under
implementation – Place & Route, double click the View/Edit Routed Design (FPGA
Editor), now we can see the routed design of our circuit.
18. A BIT file will be generate by double clicking the Generate Programming File.
19. The BIT file is loaded in the FPGA processor through JTAG or USB cable and the output
can be verified using the hardware kit.
20. MCS file is created and loaded into the PROM for verification.
RESULT:
The verilog modeling methodology and Spartan 3E FPGA board were studied.