IEEE Std 1800™-2017

(Revision of
IEEE Std 1800-2012)

Errata to
IEEE Standard for SystemVerilog—
Unified Hardware Design,
Specification, and Verification
Language

STANDARDS
Developed by the
Design Automation Standards Committee
of the
IEEE Computer Society
and the
IEEE Standards Association Corporate Advisory Group

Correction Sheet
9 April 2020

Copyright 2020 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved.
Published 9 April 2020. Printed in the United States of America.

This correction sheet may be freely reproduced and distributed in order to maintain the utility and currency of the underlying
Standard. This correction sheet may not be sold, licensed or otherwise distributed for any commercial purposes whatsoever.
The content of this correction sheet may not be modified.
In the List of tables section on pages 27-30, please insert and sort the following table numbers
into the existing list:
Table 4-1—PLI callbacks…………………………………………………………………………………………......68
Table 5-1—Specifying special characters in sting literals………………………………………………….………...77
Table 6-1—Built-in net types……………………………………………………………………………….………...87
Table 7-1—Value read from a nonexistent array entry………………………………………………………..…….149
Table 8-1—Comparison of pointer and handle types……………………………………………………………......173
Table 9-1—fork-join control options…………………………………………………………………….....………..211
Table 10-1—Legal left-hand forms in assignment statements……………………………………………..………..232
Table 11-1—Operators and data types……………………………………………………………………………....256
Table 16-1—Operator precedence and associativity……………………………………………………….………..390
Table 18-1—Unordered constraint c legal value probability……………………………………………….……….519
Table 19-1—Instance-specific coverage options………………………………………………………………….....578
Table 20-1—Diagnostics for $finish………………………………………………………………………….……..592
Table 21-1—Escape sequences for printing special characters……………………………………………………...625
Table 22-1—IEEE 1364-1995 reserved keywords…………………………………………………………………..691
Table-23-1—Net types resulting from dissimilar port connections…………………………………….…………...718
Table 26-1—Scoping rules for package importation…………………………………………………….…………..782
Table 28-1—Built-in gates and switches……………………………………………………………….…………....799
Table 29-1—UDP table symbols……………………………………………………………………….……………831
Table 30-1—List of valid operators in state-dependent path delay expression……………………………………...844
Table 31-1—$setup arguments………………………………………………………………………..……………..866
Table 32-1—Mapping of SDF delay constructs to SystemVerilog declarations…………………..………………...893
Table 34-1—protect pragma keywords……………………………………………………………….……………...920
Table 36-1—VPI routines for simulation-related callbacks………………………………………….……………....959
Table 37-1—Part-select parent expressions………………………………………………………….……………..1036
Table 38-1—Return error constraints for vpi_chk_error()…………………………………………….……………1053
Table 40-1—Coverage control return values……………………………………………………………………….1122

9 April 2020 STD22888E

IEEE Std 1800™-2017