Computer System Architecture

The following is the structure of the modern general computer system.

The general purpose computer system contains a CPU and number of device
controllers and those are connected to common bus and share memory. Here
each device controller is incharge of specific devices i.e., disk controller is
incharge of disks etc., Here, CPU and device controllers can execute concurrently
and they competing for memory cycles to provide a memory accessing in order, a
memory controller is placed, whose job is to synchronize the access to memory.

1 R.SHIVA SHANKAR,
ASSISTANT PROFESSOR, DEPARTMENT OF CSE,
SRKREC.
Boot Strap Program:
When the computer is switched on, it requires running an initial program
known as Boot Strap Program. It initializes all the computer registers, device
controllers, memory contents. This program knows how to load the OS into the
memory.

Interrupt:
The operating system starts to execute the first process in the memory and
it waits an event to occur. The occurrence of an event is generally signaled by
interrupt either from Hardware or Software.

Hardware may trigger interrupt at any time to CPU by using some bus.

Software may trigger interrupt by executing a special operation known as

System Call or Monitor Call.

There are different ways to give the trigger. For example, an I/O device
completes its operation or division by zero or invalid memory access etc.,

When the CPU is interrupted, it stops its current task and immediately
transfers control to fixed location. The fixed location contains starting address of
interrupt service routine, the routine executes. After the interruption, CPU
comes back to the location where it stops execution.

Interrupts are important part of the system architecture. Each computer

has its own interrupt handling mechanism, but several functions are common.
The straight forward method is to transfer control to a table. That table contains
each device member, its service routine address and it is known as Interrupt
Vector Table. Whenever an interrupt occurs, searching is done in this table to
find the service routine.

2 R.SHIVA SHANKAR,
ASSISTANT PROFESSOR, DEPARTMENT OF CSE,
SRKREC.
I/O Structure:

In general purpose computer system consists of a CPU and some device

controllers connected through a common bus. Each device controller is incharge
of specific type of devices. The device controller contains a local storage buffer
and a set of special purpose registers. The device controller is responsible for
moving the data between the device and the device controller varies from one
controller to another controller.

For example, the size of buffer in device controller corresponding to disk is

equal to a multiple of 512. Here 512 is smallest addressable partition in the disk,
called Sector.

While starting the I/O operation, CPU loads the appropriate registers
within the device controllers.

The device controller then examines the contents of the registers and
determines action there the controller transfers the data from the disk to the
local buffer. After the completion, controller generates a signal to CPU. That
signal is called Interrupt.

Once an I/O is started, two actions are possible. In the case, once I/O is
started, after the completion of I/O, control returns to user process. This is
known as Synchronous. The other possibility is Asynchronous. Here, control
returns to the user process without waiting for an I/O complete. These are
explained in the following diagram.

3 R.SHIVA SHANKAR,
ASSISTANT PROFESSOR, DEPARTMENT OF CSE,
SRKREC.
Device Status Table:

The better way of I/O is to start the I/O and then continue to processing
Operating System or Other programming code. Here, a system call is needed to
allow the user program to wait for I/O completion. Here, the operating system
maintains a table known as Device Status Table. Each table entry is the device
name and its status (idle or busy). If a device is busy with request, the type of
request and other parameters are stored in the entry for that device. This is also
called waiting queue. The following is the device status table.

4 R.SHIVA SHANKAR,
ASSISTANT PROFESSOR, DEPARTMENT OF CSE,
SRKREC.
 Whenever an I/O operation is needed by a process, CPU checks in the
device status table for corresponding device. If it is idle, I/O starts the status
changes busy, control transfers execute another process. If CPU needs an I/O
device and finds that it is busy. It simply adds the information about request in
the waiting queue of that device in the device status table. The device is going to
serve for the processes which in the waiting queue. This method improves the
utilization of I/O devices. Here, the important point is, while I/O is taking place
control transfers to execute other processes.

5 R.SHIVA SHANKAR,
ASSISTANT PROFESSOR, DEPARTMENT OF CSE,
SRKREC.
Storage Structure:

The following is the hierarchy of various storage devices of the general

purpose computer system.

At the higher level high speed, expensive, low capacity storage devices.

At the lower level low speed, less expensive, high capacity storage devices.

In this hierarchy, we have both volatile and non-volatile devices. All the
devices above Electronic devices (Main Memory, Cache Memory, Registers) are
volatile i.e., they loss the information when the power is off.

6 R.SHIVA SHANKAR,
ASSISTANT PROFESSOR, DEPARTMENT OF CSE,
SRKREC.
 All the devices below the Electronic devices (Magnetic disk, Optical disk,
Magnetic Tape) are non-volatile i.e., they do not loss the information when the
power is off.

In the normal operation, the electronic disk stores its data in the large
DRAM array which is volatile. But most electronic disks contain a magnetic hard
disk in it and a battery is also placed for the back up power. So, whenever power
is off, the electronic disk copies information from DRAM array to magnetic hard
disk, which is not volatile by using the battery.

The design of computer memory system, we place as much expensive

memory as necessary and it must associate with inexpensive high capacity
memory.

Caching:

Cache memory is very expensive, low capacity, high speed memory placed
in between CPU and main memory. The information which is frequently needed
is to be placed in cache memory. Whenever information needed to CPU, it first
checks whether it is present in the cache memory or not. If it is there, CPU uses
that information. Otherwise, the information is accessed from the main memory.
The information is also copied into main memory. So that, if it CPU needs that
information again, it takes information from cache memory. The cache memory
always contains updated information and this is copied into main memory, when
it removed from cache memory. Generally we use the FIFO, RR algorithms to
remove from cache.

Cache Main

Memory Memory
CPU

7 R.SHIVA SHANKAR,
ASSISTANT PROFESSOR, DEPARTMENT OF CSE,
SRKREC.
 Suppose if the CPU requested process is not present in the main memory,
it takes from the disk and copied into main memory and the remaining process is
same as above.

We observe that the user program may located in different storage devices
and the higher level must contain the updated version. While designing the
memory system, care must be taken. So that whenever a program is accessed, we
should get only the latest version.

Coherency and Consistency:

In the storage hierarchy system, same data may appear at several levels.
For example, consider a variable „A‟ in file „B‟. Suppose A is to be incremented by
1 (one). Initially the file is stored on the disk, inorder to execute this instruction
the block of the file „B‟ is copied into main memory followed by a copy to cache
memory and then a copy to registers is done, then increment operation is
performed i.e., the updated value of A is in register only. After that any
instruction which needs A will be taken from register. While it is removed from
registers, it is copied into cache memory, later it is copied into main memory and
on to the disk. Here whenever CPU needs information, it should be taken from
higher level device. So, we may not get any problem.

Consider a multitasking system, CPU switches among the various

processes. If several processes wants to access A and modify A, care must be
taken. So that all the accesses must be done from higher storage devices.

The situation becomes more complicated in the multiprocessor

environment. Each CPU has its own cache memory and registers. In such
environment, the copy of A may exists in several cache memories and these may

8 R.SHIVA SHANKAR,
ASSISTANT PROFESSOR, DEPARTMENT OF CSE,
SRKREC.
be different. Here, various CPUs can execute concurrently. So, care must be
taken because one modification of A will reflect all other registers and cache
memory in which A resides. This is known as Cache Coherency.

In the distributed environment, the situation is more complex because

several copies of file kept at several systems. So, care must be taken because the
updating of one file at one location will reflect at all other locations.

Hardware Protection:

Operating System improves the system utilization. We can share the

system resources among several programs. So, if one program executing its I/O,
CPU switches to another program. This type of sharing will improve the
utilization and will increase the problems. When the system runs without
sharing, any error in the program can cause to effect only that program.
Otherwise, when the system runs with sharing, many processors will effect with
error in one processor. Sometimes, in multiprogramming environment, any
erroneous program can modify the operating system program or some other
process. So, we need some protection for this type of error. Protection must be
required for the I/O devices and operating system and also to the CPU.

Dual Mode Operation:

We have to protect the operating system and user programs. Protection is

needed for all the shared resources. To ensure the proper operation the computer
is going to run in two modes. They are

a) User mode
b) Monitor mode ( Supervisor mode / System mode / Privileged mode )

9 R.SHIVA SHANKAR,
ASSISTANT PROFESSOR, DEPARTMENT OF CSE,
SRKREC.
 A bit called mode bit is added to computer hardware. It is „0‟ for the
monitor mode and „1‟ for the user mode. By using the mode bit, we can
distinguish between task performed by operating system and task performed by
the user. Initially at the system boot time, we are in monitor mode. After the
operating system is loaded, the computer switches to user mode to execute the
user processes. Whenever the user program performs an illegal operation, a trap
(signal) occurs and the system switches to monitor mode i.e., the operating
system takes over the control.

10 R.SHIVA SHANKAR,
ASSISTANT PROFESSOR, DEPARTMENT OF CSE,
SRKREC.
Memory Protection:

We have to provide protection to memory for the operating system,

interrupt vector, and interrupt service routine, device status table and some user
programs from other programs in the multiprogramming environment. This
protection can be achieved by the hardware. The following is one way by using
base register always holds the starting address of the current instruction (job)
and limit register holds the maximum memory.

Consider the following example.

Here, the protection is provided by the CPU hardware. Compare every

address generated by current process using base register and limit register. If it
is in the allotted address space of the current process, accessing is done.
Otherwise, a trap occurs and operating system takes control over the system.

11 R.SHIVA SHANKAR,
ASSISTANT PROFESSOR, DEPARTMENT OF CSE,
SRKREC.
 This is shown in the following diagram.

CPU Protection:

We must prevent the user program from getting struck infinitely and do
not release processor for any other program. Here, user program get struck in
infinite loop and processor is not released. We can protect our processor from this
type of problems by using a timer.

A timer is set to interrupt the computer after a specific period of time.

Here, the time may be fixed or variable.

The variable timer is ranging from 1 millisecond to 1024 milliseconds (if it

is a 10-bit counter). A variable timer is implemented with a clock and a counter.
Initially, the operating system counter and every time the clock moves, the
counter is decrements by „1‟. Whenever the counter reaches „0‟, an interrupt
occurs.

For example, suppose we have a 10-bit counter and we 1 millisecond clock,

then the timer is allowed an interrupt from 1 millisecond to 1024 milliseconds.

12 R.SHIVA SHANKAR,
ASSISTANT PROFESSOR, DEPARTMENT OF CSE,
SRKREC.
 In this way, timer can prevent a user program to run for along period of
time. Generally a controller is set to the vale which is equal to the maximum
allowed time for the process.

One more use of timer is to implement time sharing. Here, timer is set to a
value „N‟, which is known as “Time Slice”. For each every N seconds, interrupt
occurs i.e., each user is allowed to execute N seconds and for every N seconds,
operating system takes over the control and it is going to make various tasks
over the control and it is going to make various tasks such as resetting the
values of N, setting the various registers, buffers with the values currently
executing program and selects another process to switch. This switching is
known as “Context Switch”. After switching, the above cycle repeats.

By using timer, we can calculate the current time i.e., a timer interrupt
informs passage of time. We calculate the time with reference to some initial
time and number of interrupts, time interval of the interrupt.

Suppose we have initial time 9 AM (9: 00: 00) and we have an interrupt for
every 1 second. Therefore we have totally 1427 interrupts, then the time interval
is 9: 23: 47 AM (1427 / 60 = 23 minutes and 47 seconds).

I/O Protection:

To prevent the user program from performing illegal I/O operations, we

have to define all the I/O instructions as privileged. Every privileged instruction
must be executed in monitor mode.

As all the I/O instructions are privileged, they are executed only by the
operating system. Whenever an I/O instruction occurs, the user must ask the
operating system to execute this instruction on behalf of user. Such a request is
known as System Call or Monitor Call or Operating System function Call.

Whenever a system call occurs, a trap to specific location is happened.

This location is taken from interrupt vector table. When a system call is
executed, control passes to the interrupt service routine in the operating system.
13 R.SHIVA SHANKAR,
ASSISTANT PROFESSOR, DEPARTMENT OF CSE,
SRKREC.
The address of this routine is stored in interrupt vector table. The execution of
this routine is done in monitor mode. After executing this instruction, the mode
bit again changed to user mode.

The following diagram shows the system call.

14 R.SHIVA SHANKAR,
ASSISTANT PROFESSOR, DEPARTMENT OF CSE,
SRKREC.