LAB-MANUAL

II Year III SEM EE

3EE10
Digital Electronics Lab

USB ENGG/EE DEPART.

 DEPARTMENT OF ELECTRICAL ENGINEERING

SYLLABUS
DIGITAL ELECTORNICS LAB

1.To verify the truth tables of basic logic gates:AND, OR, NOR, NAND, NOR. Also
to verify the truth table of Ex-OR, Ex-NOR (For 2 inputs ).

2.To verify the truth table of OR, AND, NOR, realized using NAND & NOR gates.

3. To realize an SOP and POS expression..

4. To realize Half adder/ Subtractor & Full Adder/ Subtractor using NAND & NOR
gates and to verify their truth tables.

5. To realize a 4-bit ripple adder/ Subtractor using basic Half adder/ Subtractor &
basicFull Adder/ Subtractor.

6. To verify the truth table of 4-to-1 multiplexer and 1-to-4 demultiplexer. Realize the
multiplexer using basic gates only. Also to construct and 8-to-1 multiplexer and 1- to- 8
demultiplexer using blocks of 4-to-1 multiplexer and 1-to-4 demultiplexer

7.To study Binary to gray and gray to binary converter .Also verify the truth table for all
possible combinations.

8. Using basic logic gates, realize the R-S, J-K and D-flip flops with and without clock
signal and verify their truth table

9. Construct a divide by 2,4 & 8 asynchronous counter. Construct a 4-bit binary

counter and ring counter for a particular output pattern using D flip flop.

10. Perform input/output operations on parallel in/Parallel out and Serial in/Serial out
registers using clock. Also exercise loading only one of multiple values into the
register using multiplexer.

USB ENGG/EE DEPART.

 DO’S AND DON’T’S

DO’S
 Maintain strict discipline.
 Proper handling of apparatus must be done.
 Before switching on the power supply get it checked by the lecturer.
 Switch off your mobile.
 Be a keen observer while performing the experiment

DON’TS
 Do not touch or attempt to touch the mains power directly with bare hands.
 Do not manipulate the experiment results.
 Do not overcrowd the tables.
 Do not tamper with equipments.
 Do not leave the lab without prior permission from the teacher.

USB ENGG/EE DEPART.

 INSTRUCTIONS TO THE STUDENTS

GENERAL INSTRUCTIONS

 Maintain separate observation copy for each laboratory.

 Observations or readings should be taken only in the observation copy.
 Get the readings counter signed by the faculty after the completion of the
experiment.
 Maintain Index column in the observation copy and get the signature of the
faculty before leaving the lab.

BEFORE ENTERING THE LAB

 The previous experiment should have been written in the practical file, without
which the students will not be allowed to enter the lab.
 The students should have written the experiment in the observation copy that
they are supposed to perform in the lab.
 The experiment written in the observation copy should have aim, apparatus
required, circuit diagram/algorithm, blank observation table (if any), formula
(if any), programme (if any), model graph (if any) and space for result.

WHEN WORKING IN THE LAB

 Necessary equipments/apparatus should be taken only from the lab assistant

by making an issuing slip, which would contain name of the experiment,
names of batch members and apparatus or components required.
 Never switch on the power supply before getting the permission from the
faculty.

USB ENGG/EE DEPART.

BEFORE LEAVING THE LAB

 The equipments/components should be returned back to the lab assistant in

good condition after the completion of the experiment.
 The students should get the signature from the faculty in the observation copy.
 They should also check whether their file is checked and counter signed in the
index.

USB ENGG/EE DEPART.

LAB PLAN-

DATE/EXP. No. 1 2 3 4 5 6 7 8 9 10

G1 G2 G3 G4 G5
G5 G1 G2 G3 G4
G4 G5 G1 G2 G3
G3 G4 G5 G1 G2
G2 G3 G4 G5 G1
G1 G2 G3 G4 G5
G5 G1 G2 G3 G4
G4 G5 G1 G2 G3
G3 G4 G5 G1 G2
G2 G3 G4 G5 G1

USB ENGG/EE DEPART.

 LIST OF EXPERIMENTS

1.To verify the truth tables of basic logic gates:AND, OR, NOR, NAND, NOR. Also
to verify the truth table of Ex-OR, Ex-NOR (For 2 inputs ).

2.To verify the truth table of OR, AND, NOR, realized using NAND & NOR gates.

3. To realize an SOP and POS expression..

4. To realize Half adder/ Subtractor & Full Adder/ Subtractor using NAND & NOR
gates and to verify their truth tables.

5. To realize a 4-bit ripple adder/ Subtractor using basic Half adder/ Subtractor &
basicFull Adder/ Subtractor.

6. To verify the truth table of 4-to-1 multiplexer and 1-to-4 demultiplexer. Realize the
multiplexer using basic gates only. Also to construct and 8-to-1 multiplexer and 1- to- 8
demultiplexer using blocks of 4-to-1 multiplexer and 1-to-4 demultiplexer

7.To study Binary to gray and gray to binary converter .Also verify the truth table for all
possible combinations.

8. Using basic logic gates, realize the R-S, J-K and D-flip flops with and without clock
signal and verify their truth table

9. Construct a divide by 2,4 & 8 asynchronous counter. Construct a 4-bit binary

counter and ring counter for a particular output pattern using D flip flop.

10. Perform input/output operations on parallel in/Parallel out and Serial in/Serial out
registers using clock. Also exercise loading only one of multiple values into the
register using multiplexer.

USB ENGG/EE DEPART.

EXP. NAME OF THE EXPERIMENT PAGE
NO NO

USB ENGG/EE DEPART.

 Introduction to the Breadboard

The breadboard consists of two terminal strips and two bus strips (often
broken in the centre). Each bus strip has two rows of contacts. Each of the
two rows of contacts is a node. That is, each contact along a row on a bus
strip is connected together (inside the breadboard). Bus strips are used
primarily for power supply connections, but are also used for any node
requiring a large number of connections. Each terminal strip has 60 rows
and 5 columns of contacts on each side of the centre gap. Each row of 5
contacts is a node.

You will build your circuits on the terminal strips by inserting the leads of
circuit components into the contact receptacles and making connections with
22-26 gauge wire. There are wire cutter/strippers and a spool of wire in the
lab. It is a good practice to wire +5V and 0V power supply connections to
separate bus strips.

Fig 1. The breadboard. The lines indicate connected holes.

USB ENGG/EE DEPART.

The 5V supply MUST NOT BE EXCEEDED since this will damage the
ICs (Integrated circuits) used during the experiments. Incorrect connection of
power to the ICs could result in them exploding or becoming very hot -
with the possible serious injury occurring to the people working on the
experiment! Ensure that the power supply polarity and all components
and connections are correct before switching on power.

Building the Circuit:

Throughout these experiments we will use TTL chips to build circuits. The
steps for wiring a circuit should be completed in the order described below:

1. Turn the power (Trainer Kit) off before you build anything!
2. Make sure the power is off before you build anything!
3. Connect the +5V and ground (GND) leads of the power supply to
the power and ground bus strips on your breadboard.
4. Plug the chips you will be using into the breadboard. Point all the
chips in the same direction with pin 1 at the upper-left corner.
(Pin 1 is often identified by a dot or a notch next to it on the chip
package)
5. Connect +5V and GND pins of each chip to the power and
ground bus strips on the breadboard.
6. Select a connection on your schematic and place a piece of hook-up
wire between corresponding pins of the chips on your breadboard. It
is better to make the short connections before the longer ones. Mark
each connection
on your schematic as you go, so as not to try to make the same

USB ENGG/EE DEPART.

 connection again at a later stage.
7. Get one of your group members to check the connections, before
you turn the power on.
8. If an error is made and is not spotted before you turn the power on.
Turn the power off immediately before you begin to rewire the
circuit.

Common Causes of Problems:

1. Not connecting the ground and/or power pins for all chips.
2. Not turning on the power supply before checking the operation of
the circuit.
3. Leaving out wires.
4. Plugging wires into the wrong holes.
5. Driving a single gate input with the outputs of two or more gates
6. Modifying the circuit with the power on

USB ENGG/EE DEPART.

 EXPERIMENT

Objective:
To study the working of 5v DC Power supply.

Tools Required: Connecting Wires, Multimeter, Step-down transformer,

capacitors, LED Diode etc.

Circuit Diagram:

Stepdown Transformer :
It is used to step down the voltage of A.C. Signal. Here we are
using 9v step down transformers. It converts 230v A.C. signal into 9v A.C.
signal.
Bridge Rectifier :
It converts A.C. signal into D.C. signal. It is full wave Rectifier.
Here it converts 9v A.C. signal to 9v D.C. signal.

Capacitors :
After rectification, we don‟t get the perfect D.C. signal; there is
some ripple in it. To avoid this kind of ripple, we use capacitors. It works as a
Filter.
LED DIODE :
We can connect a LED Diode at the output to check whether the
circuit is getting the power or not. LED turns on when the circuit gets power.
Conclusion:
We get 5v D.C. voltage across the output which can be used as a 5v
D.C. power supply.

USB ENGG/EE DEPART.

 EXPERIMEMT No.-1
OBJECT: To investigate AND, OR, NOT, Exclusive OR (EX-OR),
Exclusive NOR (EX-NOR), NAND and NOR Gate operation

APPARATUS REQUIRED:

S.No. Apparatus Specification Quantity

1. Integrated chips AND gate -7408 1
(IC) NOT gate-7404 1
OR gate-7432 1
NAND gate-7400 1
NOR gate-7402 1
EX-Or gate-7486 1
EX-NOR gate-74266 1
2. Connecting wires - -
3. Digital trainer kit - 1

THEORY:

2 Input AND Gate : AND gate is physical realization of the logical multiplication.
Output of AND gate will be1 only when all the inputs are 1. If the inputs are A & B
then AND gate output is given as:
Y=A.B
AND = NAND + NOT or NAND = AND + NOT

7408 IC

Symbol Truth Table

USB ENGG/EE DEPART.

2 Input NOT gate : It is also called not gate IC and is also called MUX inverter as there
are 6 not gates in it. If we give input „0‟ then we get „1‟ as output and vise versa.
1.

7404 IC

2 Input OR gate : OR gate is physical realization of the logical Addition. Output of OR

gate will be1 if any of the input signal is 1. If the inputs are A & B of a OR gate then output
is given as:
Y = A+B

OR=NOR+NOT or NOR=OR+NOT

7432 IC

USB ENGG/EE DEPART.

2 Input NAND Gate : In this IC there are four nand gates. Pin no 7 is grounded and 14 is
connected to power supply. Input pins are (1,2), (4,5),(9,10),(12,13) and output of these nand
gates is taken across pin 3,6,8 and 12 respectively.

7400IC
2 Input NOR Gate : It is also called quad-2 input nor gate IC. In this IC nor gate input is
given from (2,3),(5,6),(8,9),(11,12) and output pins are 1,4,10 and 14 respectively.

7402 IC

USB ENGG/EE DEPART.

2 Input EX-OR Gate : In this IC there are four nand gates. Pin no 7 is grounded and 14 is
connected to power supply. Input pins are (1,2), (4,5),(9,10),(12,13) and output of these nand
gates is taken across pin 3,6,8 and 12 respectively.

74

74 7486 IC

7. 2 Input EX-NOR Gate : : It is also called quad-2 input nor gate IC. In this IC nor gate
input is given from (2,3),(5,6),(8,9),(11,12) and output pins are 1,4,10 and 14 respectively.

74286 IC Symbol and Truth table

PROCEDURE:

USB ENGG/EE DEPART.

 1. IC testing mode is mode 1 of system, selected at power ON and hardware result. This
mode can also be selected from other modes by pressing “IC Test Key”.
2. On selection of this mode by default self diagnostic RAM test message is displayed
followed by prompt “IC no….??” If at power on self-diagnostic test fails. System is
waiting for number of IC to be tested.
3. At this stage TEST SOCKET is potential free. User IC should be tested in test socket
properly.
4. While inserting IC under test in test socket, care should be taken to align bottom edge
of IC under test with bottom edge of test socket.

PRECAUTION:

1. IC should be inserted carefully.

2. Handle the IC carefully.

RESULT:

Various IC‟s have been tested successfully using IC tester.

DISCUSSION:

Any IC condition can be tested as well as IC no. can be found out by means of IC tester.

USB ENGG/EE DEPART.

Viva Quiz:

1. Define logic gates with example?

2. Which logic gates are known as universal logic gates?

3. Draw the pin diagram of IC7400.

4. Draw the pin diagram of IC7402.

5. Draw the pin diagram of IC7404.

6. Draw the pin diagram of IC7408.

7. Draw the pin diagram of IC7432.

8. Draw the pin diagram of IC74266.

9. Which logical operations is represented by the + sign in Boolean algebra?

10. Define truth table.

11. Explain Boolean expression for digital networks.

12. What is the Boolean expression for 2-input AND gate.

13. What is the Boolean expression for 2-input OR gate.

14. What does the small bubble on the output of the NAND gate logic symbol mean?

15. What is the difference between a 7400 and a 7411 IC?

USB ENGG/EE DEPART.

 EXPERIMEMT No.-2

OBJECT: - : To verify the truth table of AND, OR, NOT, Ex-OR, Ex-NOR realized using
NAND and NOR gates

APPARATUS REQUIRED:

S.No. Apparatus Specification Quantity

1. Integrated chips NAND gate-7400 1
(IC) NOR gate-7402 1
NOT gate-7404 1
2. Connecting wires - -
3. Digital trainer kit - 1

THEORY:

NAND GATE:
NAND gate is complemented AND gate. Output of NAND gate will be 1 if anyone of the
input is a zero and will be zero only when all the inputs ,re 1. If the inputs are A & B of a
NAND gate then output is given as:
Y = (A. B)’
NOR GATE:
NOR gate is complemented OR gate. Output of NOR gate will be 1 only when all inputs are
zero and will be zero if any input represents a 1. If the inputs are A & B of a NOR gate then
output is given as:
Y= (A+B)’

Implementing Inverter using NAND Gate

The figure shows two ways in which a NAND Gate can be used as an inverter
(NOT Gate):
1. All NAND input pins connect to the input signal A gives an output A‟
2. One NAND Gate input pin is connected to the input signal A while all other input
pins are connected to logic 1.The output will be A‟
A Y

0v 5v
A A‟
5v 0v

USB ENGG/EE DEPART.

Implementing AND Gate using NAND Gate
An AND Gate can be realized by NAND Gate with its output complemented by
a NAND Gate inverter. A B Y

A (AB)‟ Y=A.B 0v 0v 0v
B 0v 5v 0v
5v 0v 0v
5v 5v 5v

Implementing OR Gate using NAND Gate

An OR Gate can be realized by NAND Gate with all its inputs complemented
by a NAND Gate inverter.

A B Y
A A‟
0v 0v 0v
(A‟B‟)‟= A+B 0v 5v 5v

B B’ 5v 0v 5v

5v 5v 5v

Implementing EX-NOR Gate using NAND Gate

(A.(AB)’)’

A
B Y=(AB+A’B’)
A B Y
(B.(AB)’)’ 0v 0v 5v

0v 5v 0v
Implementing EX-OR Gate using NAND Gate
5v 0v 0v
USB ENGG/EE DEPART.
5v 5v 5v
 (A.(AB)’)’

A (AB)’
B Y=AB’+A’B

(B.(AB)’)’ A B Y

0v 0v 0v

0v 5v 5v

5v 0v 5v

5v 5v 0v

Implementing Inverter using NOR Gate

The figure shows two ways in which a NOR Gate can be used as an inverter
(NOT Gate):
1. All NOR input pins connect to the input signal A gives an output A‟
2. One NOR Gate input pin is connected to the input signal A while all other input pins
are connected to logic 0.The output will be A‟
Implementing OR Gate using NOR Gate
An OR Gate is realized by NOR Gate with its output complemented by a NOR
Gate inverter.

Implementing AND Gate using NOR Gate

An AND Gate is realized by NOR Gate with all its inputs complemented by a
NOR Gate inverter.

USB ENGG/EE DEPART.

Implementing Ex-OR Gate using NOR GATE

Implementing Ex-NOR Gate using NOR GATE

USB ENGG/EE DEPART.

Procedure:

1. Plug the chips you will be using into the bread-board with pin1 at the upper-
left corner (Pin 1 is identified by a dot or notch next to it on the chip
package).

2. Connect +5v and Gnd pins of each chip to the power and ground bus strips on
the bread-board.

3. Make the connections as per the pin diagram.

4. Switch on VCC and apply various combinations of input according to the

truth table.

5. Note down the output readings for different combinations of inputs where
5v indicates logic 1 and 0v indicates logic 0.

6. Repeat steps 1 to 4 for NOT, AND, OR, EX – OR & EX-NOR.

Precautions:
1. All the connections should be made properly.

2. IC should not be reversed.

Result: The basic logic gates are successfully constructed using NAND
and NOR gates this verifies that they are Universal Gates.

CONCLUSION:
The NAND and NOR Gate is a UNIVERSAL Gate which can implement any
Boolean function without using any other gate.

USB ENGG/EE DEPART.

Viva Quiz:
1. Explain truth table for NAND gate?

2. Explain truth table for NOR gate?

3. Explain truth table for AND gate?

4. Explain truth table for Ex-OR gate?

5. Explain truth table for OR gate?

6. Realise NAND gate using NOR gates.

7. Realise NOR gate using NAND gates.

8. When is the output of an exclusive-OR gate is HIGH?

9. How many input combinations would a truth table have for a six-input AND gate?

10. The term "hex inverter" refers to?

11. Implement Ex-OR gate using NAND Gate?

12. Implement Ex-OR gate using NOR Gate?

13. Implement Ex-NOR gate using NAND Gate?

14. Implement Ex-NOR gate using NAND Gate?

15. Why NAND & NOR gate are called as universal logic gates?

USB ENGG/EE DEPART.

 EXPERIMENT NO.-3
OBJECT: To realize an SOP and POS expression.

APPARATUS REQUIRED:

S.No. Name of the apparatus Specification Quantity

1. Integrated chips(IC) 74151,74138,7400, 5
74163,7805
2. Connecting wires - -
3. Digital trainer kit - 1

THEORY:

1 . SOP : It is often the case that the canonical minterm form can be simplified to an
equivalent SoP form. This simplified form would still consist of a sum of product terms.
Y = A+B
Y = A(B+B‟)+B(A+A‟)
Y = AB + AB‟ + BA +BA‟
Y = AB + AB‟ + A‟B

OBSERVATION TABLE:

A B A‟ B‟ AB AB‟ A‟B Y=AB+AB‟+A‟B

0 0 1 1 0 0 0 0
0 1 1 0 0 0 1 1
1 0 0 1 0 1 0 1
1 1 0 0 1 0 0 1

(2) POS : A standard POS form is product of sum . and one which a no. of sum terms, each
one of which contains all the variables og the function either in complemented and non
complemented form are multiplied together .
Y = A.B
Y = (A+B.B‟)B(A.A‟)
Y = (A+B)(A+B‟)(A+B)(A‟+B)
Y = (A+B)(A+B‟)(A‟+B)

USB ENGG/EE DEPART.

OBSERVATION TABLE:

A B A‟ B‟ A+B A+B‟ A‟+B Y=(A+B)(A+B‟)(A‟+B)

0 0 1 1 0 1 1 0
0 1 1 0 1 0 1 0
1 0 0 1 1 1 0 0
1 1 0 0 1 1 1 1

VIVA QUESTIONS

1 1. Convert the following SOP expression to an equivalent POS expression.

.

2. Determine the values of A, B, C, and D that make the sum term equal to zero.
3. Derive the Boolean expression for the logic circuit shown below:

4. From the truth table below, determine the standard SOP expression.

5. The systematic reduction of logic circuits is accomplished by ?

6. For the SOP expression , how many 1s are in the truth table's output
column?
7. A truth table for the SOP expression has how many input combinations?
8. How many gates would be required to implement the following Boolean expression before
simplification? XY + X(X + Z) + Y(X + Z)
9. Determine the values of A, B, C, and D that make the product term equal to 1.
USB ENGG/EE DEPART.
 10. How many gates would be required to implement the following Boolean expression after
simplification? XY + X(X + Z) + Y(X + Z)

PROCEDURE:

1.Insert the IC on bread-board.

2.Make pin no 7 grounded and connect pin no 14 to power supply.
3.Now provide inputs as specified in circuit diagram.
4.Take output across respective pins.
5.Any operation such as and, or, half adder etc. can be performed using these IC‟s.

PRECAUTIONS:

1.Insert IC on bread-board tightly.

2.Don‟t forget to ground pin no. 7.
3.Hold the IC properly.

RESULT:

Study SOP and POS expression has been done using IC 7400 ,7402,7404,7408,7432S

DISCUSSION:

Using these IC‟s we can realize other combinational circuits easily. Since NAND and NOR are
universal gates so we generally use IC 7400 and 7402.

USB ENGG/EE DEPART.

Viva Quiz:
1. What is SOP?

2. What is difference between decoder and encoder?

3. What is POS?

4. What are different code and their application.

5. What are Code Converter?

6. Using 3:8 decoder and associated logic ,implement a full adder.

7. What is the role of encoder in communication?

8. What is the difference between decoder and demux?

9. What is the advantage of using an encoder?

10. What is Priority Encoder?

11. What is the necessity for Sequence Generation?

12. How many minimum number of Flip flop a modulus-12 ring counter requires?

13. How many clock pulse will be required to completely load serially a 5-bit shift register?

14. Differentiate between Serial and Parallel data.

15. What are the advantage of Synchronous Counter?

USB ENGG/EE DEPART.

 EXPERIMENT NO.-4

OBJECT: - To Study & realize half and full adder.

i. Using Basic Gates.
ii. Using only NAND Gates.

APPARATUS REQUIRED:

S.No. Apparatus Specification Quantity

1. Integrated chips (IC) NAND gate-7400 1
AND gate-7408 1
OR gate-7432 1
X-OR gate-7486 etc. 1

2. Connecting wires & -

Power supply -
3. Digital trainer kit - 1
4. Multi meter - 1

THEORY:

HAFF-ADDER:
The simplest combinational circuit which performs the arithmetic addition of two binary
digits is called HAFF-ADDER. A half adder adds two one-bit binary numbers A and B. It
has two outputs, S and C (the value theoretically carried on to the next addition); the final
sum is 2C + S.

Fig. 1.1 Haff-adder logic diagam

From the truth table, the logic expression for the Sum output can be written as a Sum of
Product expression by summing up the input combinations for which the sum is equal to 1.

USB ENGG/EE DEPART.

 In the truth table, the sum output is 1when AB=01 and AB=10. Therefore, the
expression for sum is

Now, this expression can be simplified as

Similarly, the logic expression for Carry output can be expressed as a Sum of Product
expression by summing up the input combination for which the carry is equal to 1. In the
truth table ,the carry is 1 when AB=11. Therefore,
C = AB

FULL-ADDER:
A Full-Adder is a combinational circuit that performs the arithmetic sum of three input bits
and produces a sum output and a carry.

Fig.1.2 Full-Adder logic diagram

From the truth table , the logic expression for S can be written by summing up the input
combination for which the sum output is 1 as:

= BCin + ACin + AB

USB ENGG/EE DEPART.

CIRCUIT DIAGRAM :-

USB ENGG/EE DEPART.

OBSERVATION TABLE:
HALF ADDER

Input Output
A B S(Sum) C(Carry)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

FULL ADDER

Input Output
A B Cin S(Sum) Cout(Carry)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

USB ENGG/EE DEPART.

PROCEDURE:-

1. Verify the gates.

2. Make the connections as per the circuit diagram.
3. Make pin no 7 grounded and connect pin no 14 to power supply.
4. Switch on Vcc and apply various combination of input according to the truth table.
5. Note down the output readings for half/full adder sum/difference and the carry/borrow
bit for different combination of inputs.

PRECAUTIONS:

1. Insert IC on bread-board tightly.

2. Don‟t forget to ground pin no. 7.
3. Hold the IC properly.

RESULT:

Study and Realization of Half-Adder & Full-Adder circuits have been done using IC‟s 7400
,7408,7432 etc.

DISCUSSION:

Using these IC‟s we can realize Full & Half Adder & other combinational circuits easily.
Since NAND is universal gate so we generally use IC 7400 .

USB ENGG/EE DEPART.

Viva Quiz:
1. What is a half-subtractor?

2. Explain the half-adder.

3. Draw the logic circuit for half adder?

4. Explain the full adder?

5. Draw the logic circuit for full adder?

6. Define a full-subtractor.

7. Draw the logic circuit for full subtractor?

8. Draw the logic circuit for half subtractor?

9. What is the major difference between half-adders and full-adders?

10. The binary subtraction 0 – 1 =?

11. One way to make a four-bit adder perform subtraction is by ?

12. Which logic circuit provides a HIGH output for both inputs HIGH or both inputs

LOW?

13. Which logic circuit provides a HIGH output if one input or the other input, but not

both, is HIGH?

14. Implement the expression AB + CDE using NAND logic?

15. Implement the expression using NAND logic?

USB ENGG/EE DEPART.

 EXPERIMENT NO.-5

OBJECT: - To realize a 4-bit ripple adder/ Subtractor using basic Half adder/ Subtractor &
basicFull Adder/ Subtractor.

APPARATUS REQUIRED:

S.No. Apparatus Specification Quantity

1. Integrated chips (IC) 4 Bit Full adder-7483 1
NOT gate-7404 etc. 1

2. Connecting wires & -

Power supply -
3. Digital trainer kit - 1
4. Multi meter - 1

THEORY:

4-BIT PARALLEL ADDER: The ripple carry adder is constructed by cascading full
adders (FA) blocks in series. One full adder is responsible for the addition of two binary
digits at any stage of the ripple carry. The carryout of one stage is fed directly to the carry-in
of the next stage. A number of full adders may be added to the ripple carry adder or ripple
carry adders of different sizes may be cascaded in order to accommodate binary vector strings
of larger sizes. For an n-bit parallel adder, it requires n computational elements (FA). Figure
shows an example of a parallel adder: a 4-bit ripple-carry adder. It is composed of four full
adders. The augends bits of x are added to the addend bits of y respectfully of their binary
position. Each bit addition creates a sum and a carry out. The carry out is then transmitted to
the carry in of the next higher-order bit. The final result creates a sum of four bits plus a carry
out (c4).

USB ENGG/EE DEPART.

 Figure : Parallel Adder: 4-bit Ripple-Carry Adder Block Diagram

Pin Diagram :

ADDER:

USB ENGG/EE DEPART.

OBSERVATION TABLE:

X3 X2 X1 X0 Y3 Y2 Y1 YO C4 S3 S2 S1 S0
0 0 0 1 0 0 1 0 0 0 0 1 1
0 1 0 1 1 0 1 1 1 1 0 0 0
1 0 1 0 1 0 1 0 1 0 1 0 0
1 1 1 1 1 1 1 1 1 1 1 1 0
0 1 1 1 0 0 1 1 0 1 0 1 0

SUBTRACTOR:

OBSERVATION TABLE:

X3 X2 X1 X0 Y3 Y2 Y1 YO C4 S3 S2 S1 S0
0 0 1 0 0 0 0 1 1 0 0 0 1
0 1 0 1 0 0 1 1 1 0 0 1 0
0 0 1 1 0 1 0 1 0 1 1 1 0
1 0 1 0 0 1 1 0 1 0 1 0 0
1 0 0 0 1 1 1 1 0 1 0 0 1

PROCEDURE:-

1. Verify the gates.

2. Make the connections as per the circuit diagram.
3. Make pin no 12 grounded and connect pin no 5 to power supply.
4. Switch on Vcc and apply various combination of input according to the truth
table.
5. Note down the output readings for adder and subtractor and the sum and carry bit
for different combination of inputs.

USB ENGG/EE DEPART.

PRECAUTIONS:

1. Insert IC on bread-board tightly.

2. Don‟t forget to ground pin no. 12.
3. Hold the IC properly.

RESULT:

Study and Realization of a 4-bit ripple adder/ Subtractor using basic Half adder/ Subtractor
& basicFull Adder/ Subtractor

DISCUSSION:

Using these IC‟s we can realize a 4-bit ripple adder/ Subtractor using basic Half adder/
Subtractor & basicFull Adder/ Subtractor .

USB ENGG/EE DEPART.

Viva Quiz:

1. A full subtracter circuit have how many inputs and outputs?

2. How many 3-line-to-8-line decoders are required for a 1-of-32 decoder?

3. Convert BCD 0001 0010 0110 to binary.

4. How many data select lines are required for selecting eight inputs?

5. Which statements accurately represents the BEST methods of logic circuit

simplification?

6. Which gate is best used as a basic comparator?

7. The inverter can be produced with how many NAND gates?

8. How is a J-K flip-flop made to toggle?

9. On a master-slave flip-flop, when is the master enabled?

10. When the output will be a LOW for any case one or more inputs are zero?

11. Solve the network in the figure given below for X.

12. What type of logic circuit is represented by the figure shown below?

13. How many outputs would two 8-line-to-3-line encoders, expanded to a 16-line-to-

4-line encoder, have?

14. If a 3-input NOR gate has eight input possibilities, how many of those possibilities

will result in a HIGH output?

15. Draw the truth table of full adder?

USB ENGG/EE DEPART.

 EXPERIMENT NO.-6

OBJECT: - To verify the truth table of 4-to-1 multiplexer and 1-to-4

demultiplexer. Realize the multiplexer using basic gates only. Also to construct
and 8-to-1 multiplexer and 1-to-8 demultiplexer using blocks of 4-to-1
multiplexer and 1-to-4 demultiplexer.

APPARATUS REQUIRED:

S.No. Name of the apparatus Specification Quantity

1. Integrated chips(IC) 74151,74138,7400, 5
74163,7805
2. Connecting wires - -
3. Digital trainer kit - 1

THEORY:

MULTIPLEXERS:

Multiplexer is a digital circuit, which has many inputs and single output. The function of

Multiplexer is to select one of the input lines and connect it to the output. It is also known

as data selector. Selection of desired input is done by means of selection lines. Generally

there are 2N input lines and N select lines whose bit combinations determine which input

is to be selected. It acts like a digitally controlled switch. The select input is controlled by

the select inputs applied.

DEMULTIPLEXER:

Demultiplexer is digital circuit, which has one input line and many output lines. It is used
to send a single input on one of the output lines and thus performs reverse operation of the
multiplexer. It has one input and N outputs. The select input code determines to which
output line the data input will be transmitted. In other words, demultiplexer takes one input
data source and selectively distributes it to 1 of N output channels. The number of select
lines is „S‟ where,
N = 2^S.

USB ENGG/EE DEPART.

CIRCUIT DIAGRAM:

USB ENGG/EE DEPART.

OBSERVATION TABLE:

8-to-1 Multiplexer:

INPUTS OUTPUTS
S2 S1 S0
0 0 0 D0
0 0 1 D1
0 1 0 D2
0 1 1 D3
1 0 0 D4
1 0 1 D5
1 1 0 D6
1 1 1 D7

USB ENGG/EE DEPART.

1-to-8 Demultiplexer:

Data input Select inputs Outputs

S2 S1 S0 Y Y Y Y Y Y Y Y
7 6 5 4 3 2 1 0
D 0 0 0 0 0 0 0 0 0 0 D
D 0 0 1 0 0 0 0 0 0 D 0
D 0 1 0 0 0 0 0 0 D 0 0
D 0 1 1 0 0 0 0 D 0 0 0
D 1 0 0 0 0 0 D 0 0 0 0
D 1 0 1 0 0 D 0 0 0 0 0
D 1 1 0 0 D 0 0 0 0 0 0
D 1 1 1 D 0 0 0 0 0 0 0

PROCEDURE:

1. Make connections as per the circuit diagram.

2. Provide input through input lines and obtain the multiplexed output.
3. Note the corresponding output.
4. Repeat the same process for demultiplexer.

PRECAUTIONS:

1. All connections must be tight.

2. Check power supply circuit and other factors according to requirement.

RESULT:

Study of 8-channel digital multiplexer and demultiplexer has been done successfully.

DISCUSSION:

Multiplexer and demultiplexers have wide application in digital communication. In case of

multiplexing several signals can be transmitted through a common communication channel.

USB ENGG/EE DEPART.

Viva Quiz:
1. Define multiplexer.

2. Draw the logic diagram of a 2x1 multiplexer using logic gates?

3. What is a demultiplexer?

4. State the difference between multiplexer and encoder.

5. If there are 16 inputs to a multiplexer, the how many select lines are used?

6. Give the names of some multiplexer ICs.

7. Give the names of some demultiplexer ICs.

8. Why there is need of multiplexing?

9. One Application of a multiplexer is to facilitate what ?

10. The primary use for Gray code is?

11. How decoder can be used as demultiplexer?

12. What is the difference between decoder and demux?

13. What is the advantage of using an encoder?

14. Explain the difference between multiple access and multiplexing?

15. Draw the demultiplexer block diagram?

USB ENGG/EE DEPART.

 EXPERIMENT No.-7

-
OBJECT: Study of Binary to Gray and gray to binary code converter and also verify the truth
table for all the possible combinations.

APPARATUS REQUIRED:

S.No. Name of apparatus Specification Quantity

1. Integrated chips 7486 -

2. Patch Chords - -

3. Digital trainer kit - 1

THEORY:
BINARY CODE:
Digital systems use signals that have two distinct values and circuit elements that have two stable
states i. e. 0 or 1. Binary code is a positional weighted code having 1,2,4,8,…… from LSB to
MSB.

GRAY CODE: The gray code belongs to a class of codes called minimum change codes, in
which only one bit in the group changes when moving from one step to the next. The gray code is
non weighted code. Therefore, these are also called as unit distance code.

BINARY TO GRAY CONVERSION:

1. The first bit (MSB) of gray code will be same as the first bit of binary number, so it will be
noted as it is.
2. Now the second bit of gray code will be the XOR of the first and second bit of the binary
number.
3. Similarly, the third bit of gray code will be XOR of second and third digit of binary number
and thus the sequence will go on.
4. Hence, for the 4 bit number we will have

USB ENGG/EE DEPART.

 Fig. 5.1 Binary to gray code converter

GRAY TO BINARY CONVERSION:

1. The first bit of binary code (MSB) will be same as first bit of gray code.
2. The second bit of binary code is obtained by XORing the second bit of the gray code and the
previous noted bit of binary code, i.e. nth bit of binary = nth bit of gray (n+1)th bit of binary
3. Similarly, the next bits are obtained by repeating the step 2 and thus sequence will go on.
4. Hence for a four bit gray code the binary bits will be

USB ENGG/EE DEPART.

CIRCUIT DIAGRAM:

USB ENGG/EE DEPART.

PROCEDURE:

1. Make connections as per the circuit diagram.

2. Give binary input to the circuit and you will get the equivalent gray output.
3. Note the output.
4. Repeat the process with different inputs.

PRECAUTIONS:

1. Connections must be tight and clear.

2. Leads must be carefully pushed in ports.
3. Output should be recorded correctly.
4. Switch off when equipment is not used.

RESULT:
Binary to gray and gray to binary code conversion has been done successfully.

DISCUSSION:
Gray code is that in which only one bit in the code group change when going from one no to the
next. The experiment is implemented by Ex-OR gate IC-7486 and conversion requires four Ex-
OR gates i.e. one Ex-OR gate IC.

Viva Quiz:

USB ENGG/EE DEPART.

 EXPERIMENT NO.-8

OBJECT: - Using basic logic gates, realize the R-S, J-K and D-flip flops with and without
clock signal and verify their truth table .

APPARATUS REQUIRED:

S.No. Name of the apparatus Specification Quantity

1. Integrated chips(IC) 7400, 2

2. Connecting wires - -
3. Digital trainer kit - 1

THEORY: (1) RS Flip-Flop :

 A RS-flipflop is the simplest possible memory element.

 It is constructed by feeding the outputs of two NOR gates back to the other NOR
gates input.
 The inputs R and S are referred to as the Reset and Set inputs, respectively.
 To understand the operation of the RS-flipflop (or RS-latch) consider the following
scenarios:
o S=1 and R=0: The output of the bottom NOR gate is equal to zero, Q'=0.
o Hence both inputs to the top NOR gate are equal to one, thus, Q=1.
o Hence, the input combination S=1 and R=0 leads to the flipflop being set to
Q=1.
o S=0 and R=1: Similar to the arguments above, the outputs become Q=0 and
Q'=1.
o We say that the flipflop is reset.
o S=0 and R=0: Assume the flipflop is set (Q=0 and Q'=1), then the output of
the top NOR gate remains at Q=1 and the bottom NOR gate stays at Q'=0.
o Similarly, when the flipflop is in a reset state (Q=1 and Q'=0), it will remain
there with this input combination.
o Therefore, with inputs S=0 and R=0, the flipflop remains in its state.
o S=1 and R=1: This input combination must be avoided.

USB ENGG/EE DEPART.

  We can summarize the operation of the RS-flipflop by the following truth table.
 Note, the output Q' is simply the inverse of Q.
 An RS flipflop can also be constructed from NAND gates.

CIRCUIT DIAGRAM:

Figure : RS Flip-Flop composed of two NOR Gates.

OBSERVATION TABLE:

R S Q Q' Comment
0 0 Q Q' Hold state
0 1 1 0 Set
1 0 0 1 Reset
1 1 ? ? Avoid

THEORY:
(2) JK Flip-Flop : The JK flip-flop augments the behavior of the SR flip-flop (J=Set,
K=Reset) by interpreting the S = R = 1 condition as a "flip" or toggle command. Specifically,
the combination J = 1, K = 0 is a command to set the flip-flop; the combination J = 0, K = 1 is
a command to reset the flip-flop; and the combination J = K = 1 is a command to toggle the
flip-flop, i.e., change its output to the logical complement of its current value. Setting J = K =
0 does NOT result in a D flip-flop, but rather, will hold the current state. To synthesize a D
flip-flop, simply set K equal to the complement of J. The JK flip-flop is therefore a universal
flip-flop, because it can be configured to work as an SR flip-flop, a D flip-flop, or a T flip-
flop.

USB ENGG/EE DEPART.

CIRCUIT DIAGRAM:

Figure : JK Flip-Flop
OBSERVATION TABLE:

(3) D Flip-Flop : The operations of a D flip-flop is much more simpler. It has only one
input addition to the clock. It is very useful when a single data bit (0 or 1) is to be stored.
If there is a HIGH on the D input when a clock pulse is applied, the flip-flop SETs and stores
a 1.
If there is a LOW on the D input when a clock pulse is applied, the flip-flop RESETs and
stores a 0.
The truth table below summarize the operations of the positive edge-triggered D flip-flop.

CIRCUIT DIAGRAM:

Figure : D Flip-Flop

USB ENGG/EE DEPART.

OBSERVATION TABLE:

D Q Comments
0 1 REST (store 0)
1 0 SET (store 1)

PROCEDURE:

5. Make connections as per the circuit diagram.

6. Provide input through input lines and obtain the Flip flop output.
7. Note the corresponding output.
8. Repeat the same process for flip flop

PRECAUTIONS:

3. All connections must be tight.

4. Check power supply circuit and other factors according to requirement.

RESULT:

Study of R-S, J-K and D-flip flops. has been done successfully.

DISCUSSION:

Flip flop have wide application in digital communication. The Flip flop has been used in
digital communication as a memory element .

USB ENGG/EE DEPART.

Viva Quiz:

1. What is a flip flop?

2. Define latch.

3. Explain difference between a latch and flip flop.

4. What do you mean by triggering?

5. How many types of triggering are there?

6. Explain difference between level and edge triggering.

7. Draw the truth table of SR flip flop?

8. Explain the truth table of D flip flop?

9. Draw the truth table of JK flip flop?

10. Implement JK flip flop using NAND gate?

11. Implement SR flip flop using NAND gate?

12. What is toggle? Which flip flop uses this phenomenon?

13. Implement D flip flop using NAND gate?

14. What is race around condition? How it is removed?

15. Why the flip flops are used?

USB ENGG/EE DEPART.

 EXPERIMENT NO.-9

OBJECT: - Construct a divide by 2,4 & 8 asynchronous counter. Construct a 4-bit

binary counter and ring counter for a particular output pattern using D flip flop.

APPARATUS REQUIRED:

S.No. Apparatus Specification Quantity

1. 4 J-K flip-flops 7473 2
4 AND logic gates 7408 1

2. Connecting wires - -
3. Digital trainer kit - 1
Theory – : A Binary ripple counter consists of a series connection of complementing flip-
flop (T or JK) ,with the output of each flip flop connected to the CP input of the next higher
order flip flop. The flip flop holding the least significant bit receives the incoming count
pluses. The diagram of a 4 bit binary ripple counter is shown in above figure . all J & K
inputs are equal to 1. The small circle in the CP input indicates that the flip flop complement
during a negative-going transition or when the output to which it is connected goes from 1 to
0. To understand the operation of the binary counter , refers to its count sequence given in
below table

Count sequence for a binary ripple counter

count sequence condition for complimenting flip-flop
A4 A3 A2 A1
0 0 0 0 compliment A1
0 0 0 1 compliment A1 A1 will go from 1 to 0 and compliment A2
0 0 1 0 compliment A1
0 0 1 1 compliment A1 A1 will go from 1 to 0 and compliment A2
A2 will go from 1 to 0 and compliment A3
0 1 0 0 compliment A1
0 1 0 1 compliment A1 A1 will go from 1 to 0 and compliment A2
0 1 1 0 compliment A1
0 1 1 1 compliment A1 A1 will go from 1 to 0 and compliment A2
A2 will go from 1 to 0 and compliment A3
A3 will go from 1 to 0 and compliment A4

1 0 0 0

USB ENGG/EE DEPART.

It obvious that the lowest – order bit A1 must be complemented with each count pulse .
Every time A1 goes from 1to 0, it complement A2 . Every time A2 goes from 1 to 0, it
complement A3, and so on . for example take the transition from count 0111 to 1000.The
arrows in the table emphasize the transition in this case . A1 is complemented with the count
pulse. Since A1 goes from 1 to 0 , it trigger A2 and complements it . As a result A2 goes
from 1 to 0. Which in turn complement A3 . A3 now goes from 1 to 0 , which complements
A4 . The output transition of A4 , if connected to a next stages , will not trigger the next flip
flop since it goes from 0 to 1. The flip flop change one at a time in rapid succession , and the
signal propagates through the counter in ripple fashion . ripple counters are sometimes called
asynchronous counters.

A binary counter with a reverse count is called a binary down – counter. In a down-
counter, the binary count is decremented by 1 with every input pulse . The count of a 4-bit
down counter , the binary count starts from binary 15 and continuous to binary counts
14,12,12,.....,0 and then back to 15 . the circuit figure (given above).
A list of the count sequence of a count- down binary counter shows that the lowest-order bit
must be complemented with every count pulse. Any other bit in the sequence is
complemented with if its previous lower-order bit goes from 0 to 1. Therefore ,the diagram
of binary down – counter look the same as in fig (given above) provided all flip- flop trigger
on the positive edge of the pulse.(The small circles in the CP in puts must be absent). If
negative-edge-triggered flip-flop are used, then the CP input of each flip-flop must be
connected to the Q‟ output of the previous flip-flop. Then when Q goes from 0 to 1, Q‟ will
go from 1 to 0 and complement the next flip-flop as required.

Circuit Diagram –

USB ENGG/EE DEPART.

Precautions –:
1. Connection must be tight.
2. Do not touch the wire while taking observation.
3. After the experiment switch OFF the power supply.

Result –: Here we have studied the construction of 2,4 & 8 asynchronous counter, 4 bit
binary counter and ring counter for a particular output pattern using D flip flop.

USB ENGG/EE DEPART.

Viva Questions –

1. Define counter.

2. Explain the synchronous counter?

3. Explain the asynchronous counter?

4. How does the ring counter works?

5. How many Flip-Flops are required for mod–16 counter?

6. Explain the working of a three bit binary ripple counter.

7. Draw the counting sequence of three bit binary ripple counter?

8. Explain the Mod-5 Synchronous Counter?

9. What is a Johnson Counter?

10. Draw the logic diagram of 3-Bit Binary Ripple Counter?

11. Differentiate between Serial and Parallel data.

12. What is the terminal count of a modulus-11 binary counter?

13. Why the Synchronous counters eliminate the delay problems encountered with

asynchronous counters?

14. In a seven-segment, for what purpose does common-anode LED display is designed

for?

15. To operate correctly, starting a ring counter requires?

USB ENGG/EE DEPART.

 EXPERIMEMT No.-10

OBJECT: - Perform input/output operations on parallel in/Parallel out and Serial

in/Serial out registers using clock

THEORY: The Shift Register :

The Shift Register is another type of sequential logic circuit that is used for the storage or
transfer of data in the form of binary numbers and then "shifts" the data out once every clock
cycle, hence the name "shift register". It basically consists of several single bit "D-Type Data
Latches", one for each bit (0 or 1) connected together in a serial or daisy-chain arrangement
so that the output from one data latch becomes the input of the next latch and so on. The data
bits may be fed in or out of the register serially, i.e. one after the other from either the left or
the right direction, or in parallel, i.e. all together.

The Shift Register is used for data storage or data movement and are used in calculators or
computers to store data such as two binary numbers before they are added together, or to
convert the data from either a serial to parallel or parallel to serial formatGenerally, shift
registers operate in one of four different modes with the basic movement of data through a
shift register being:

1. Serial-in to Parallel-out (SIPO) - The register is loaded with serial data, one bit at a
time, with the stored data being available in parallel form.
2. Serial-in to Serial-out (SISO) - The data is shifted serially "IN" and "OUT" of the
register, one bit at a time in either a left or right direction under clock control.
3. Parallel-in to Serial-out (PISO) - The parallel data is loaded into the register
simultaneously and is shifted out of the register serially one bit at a time under clock
control.
4. Parallel-in to Parallel-out (PIPO) - the parallel data is loaded simultaneously into the
register, and transferred together to their respective outputs by the same clock pulse.
5. The effect of data movement from left to right through a shift register can be
presented graphically as

6.
USB ENGG/EE DEPART.
Also, the directional movement of the data through a shift register can be either to
the left, (left shifting) to the right, (right shifting) left-in but right-out, (rotation) or both
left and right shifting within the same register thereby making it bidirectional. In this
tutorial it is assumed that all the data shifts to the right, (right shifting).

Serial-in to Parallel-out (SIPO)

4-bit Serial-in to Parallel-out Shift Register

The operation is as follows. Lets assume that all the flip-flops (FFAto FFD) have just been
RESET (CLEAR input) and that all the outputs QAto QD are at logic level "0" i.e, no parallel
data output. If a logic "1" is connected to the DATA input pin of FFA then on the first clock
pulse the output of FFA and therefore the resulting Q A will be set HIGH to logic "1" with all
the other outputs still remaining LOW at logic "0". Assume now that the DATA input pin of
FFA has returned LOW again to logic "0" giving us one data pulse or 0-1-0.

The second clock pulse will change the output of FFA to logic "0" and the output of FFB and
QB HIGH to logic "1" as its inputD has the logic "1" level on it from Q A. The logic "1" has
now moved or been "shifted" one place along the register to the right as it is now at Q A.
When the third clock pulse arrives this logic "1" value moves to the output of FFC(Q C) and so
on until the arrival of the fifth clock pulse which sets all the outputs Q A to QD back again to
logic level "0" because the input to FFA has remained constant at logic level "0".

The effect of each clock pulse is to shift the data contents of each stage one place to the right,
and this is shown in the following table until the complete data value of 0-0-0-1 is stored in
the register. This data value can now be read directly from the outputs of Q A to QD. Then the
data has been converted from a serial data input signal to a parallel data output. The truth
table and following waveforms show the propagation of the logic "1" through the register
from left to right as follows.

USB ENGG/EE DEPART.

Basic Movement of Data through a Shift Register

Clock Pulse No QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 0 0 1 0
4 0 0 0 1
5 0 0 0 0

RESULT: Perform input/output operations on parallel in/Parallel out and Serial

in/Serial out registers using clock
Viva Questions
1. What is the shift register?

2. What type of input and output does a shift register can have?

3. Define circular shift register.

4. Explain different types of shift registers?

5. Can a shift register be used as a counter? If yes, explain how?

6. Explain how a shift register can be used as a ring counter giving the wave forms at the

output of the flip flops.

7. List out some applications of Shift Register.

8. Describe the operation of parallel in parallel out (PIPO) shift register.

9. Draw SISO logic diagram?

10. Draw SIPO logic diagram?

11. Draw PISO logic diagram?

12. Draw PIPO logic diagram?

13. What is a linear feedback shift register?

14. Which flip flop is used for realizing the shift register

USB ENGG/EE DEPART.