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Model Name : VILE1 & VILE2


File Name : NM-A043, NM-A044
BOM P/N:

A A

VILE1:

VILE2:

B B

M/B Schematics Document


Intel Ivy Bridge Processor with DDRIII + Panther Point PCH
GPU nVIDIA N14M-GL / N14P-GV2

2012-11-07
REV:0.1
C C

D D

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Security Classification
4

LC Future Center Secret Data


Size Document Number
Title
Cover Page
5
Rev
A B C D E

nVIDIA N14M-GL
DDR3*4
VRAM 256M*16/
128M*16/64M*16 Intel
1
nVIDIA N14P-GV2 Memory Bus 1

DDR3*4 PCI-E X8 Ivy Bridge Dual Channel


VRAM 256M*16/ 1.5V DDR3 1600MHz
DDR3-SO-DIMM X2
rPGA 989 Socket Page 11~12
128M*16/64M*16 Page 24~32
37.5mm * 37.5mm

HDMI Connector Page 4~10


HDMI DC-IN dongle
Page 34 FDI x8
DMI x4
(UMA) 100MHz 2Channel Speaker
100MHz Page 35
5GB/s
CRT Connector 2.7GT/s
RGB Digital MIC
Page 33 HD Audio Audio Codec
Page 35
Intel CX20671-21Z CODEC
LVDS
2
LVDS Connector
Page 32
Panther Point USB3+DP Page 35 Audio combo Jack 2

Page 35
PCI-E FCBGA 989
Card Reader 25mm*25mm USB 2.0
cable CMOS Camera Page 32
Realtek RTS5229 HM76
SPI ROM USB 3.0
Page 36 SPI
BIOS 8M+4M SATA
Page 13 Page 13~21
Realtek Page 39
RTL8111F(Giga) cable
Sub-Board
Page 40 LPC BUS Finger Printer
UPEK TCS5DA6C0 Page 40

RJ45 CONN EC TPM


ENE KBC9012 Page 40
3
Page 40 USB PORT 3.0 x 2 3

Page 41 Page 37
Sub-Board
Track Point G-Sensor
Page 39 Page 36 SATA3.0 HDD CONN Page 36

PCI Express USB(BT)


Click Pad Int.KBD Thermal Sensor SATA ODD CONN Page 36
Mini card Page 39 Page 39 Fintek F75303M Page 39
Slot 1 Page 38 PCI-E(WLAN) m-SATA CONN Page 38
WLAN/WiMAX/BT

PCI Express USB

Mini card SATA


4 Slot 2 Page 38
4

WWAN/mSATA

SIM Card Security Classification LC Future Center Secret Data Title


Issued Date 2012/07/01 Deciphered Date 2014/07/01 Block Diagram
Page 38 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 2 of 59

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A B C D E
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Voltage Rails
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

+5VS Full ON HIGH HIGH HIGH HIGH ON ON ON ON


+3VS
power S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
plane +1.5VS
+VCCP S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
A +5VALW +CPU_CORE A
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+B +1.5V +VGA_CORE
+3VM
+3VALW +VCC_GFXCORE_AXG
+1.05VM
+1.8VS
State +0.75VS
+1.05VS BOARD ID Table
Board ID PCB Revision
0 0.1
1 0.2
S0
O O O O O 2
M3 Supported
3
S3 O 4
O O O X M3 Supported
5
S5 S4/AC O 6
O O X X M3 Supported
7
S5 S4/ Battery only
X X X X
B B
S5 S4/AC & Battery
don't exist
X X X X
USB Port Table BOM Structure Table
3 External BTO Item BOM Structure
USB 2.0 Port USB Port Connector ME@
EC SM Bus1 address EC SM Bus2 address 0 USB 3.0 Port (Left Side) 45 LEVEL 45@
UHCI0
1 Unpop @
Device Address Device Address
Smart Battery Thermal Sensor Fintek F75303M1001_101xb
2 USB 3.0 Port (Left Side) NVidia DIS@
0001 011X b UHCI1
3 USB 3.0 Port
EHCI1
4 Touch Panel PCH AUX Power +3V_PCH@
USB3.0 UHCI2
5 Intel UMA UMA@
PCH SM Bus address 6 VRAM Option X76@
UHCI3
7 Intel SBA SBA@
Device Address
DDR DIMM0
8 Intel AOAC AOAC@
1001 000Xb UHCI4
DDR DIMM2 1001 010Xb
9 USB Port (Right Side) TPM TPM@
10 Mini Card(WLAN/BT) GPU N14M-GL N14MGL@
EHCI2 UHCI5
11 FPR GPU N14P-GV2 N14PGV2@
C
12 Mini Card(WWAN) SIM Card Slot 3G@ C
UHCI6
13 Camera Touch Panel Touch@
Finger Print Board FP@
SMBUS Control Table SSD SSD@
ZZZ5
WLAN Thermal
SOURCE VGA BATT KE9012 SODIMM WWAN Sensor PCH
SMB_EC_CK1
SMB_EC_DA1
KB9012
+3VALW
X V
+3VALW
X X X X X DA PCB
DA80000TG00
SMB_EC_CK2
SMB_EC_DA2
KB9012
+3VALW
X X X X X X V
+3VS
NM-A043
SMBCLK
SMBDATA
PCH
+3VALW
X X X V
+3VS
V
+3VS
X X
SML0CLK
X X X X X X X
B2 B3
PCH
SML0DATA +3VALW 1
1

SML1CLK
SML1DATA
PCH
+3VALW
V
+3VS
X V
+3VS
X X V
+3VS
X 46J_BARCODE_16X7
@
UUID_BARCODE_16X7
@
D D

Security Classification LC Future Center Secret Data Title


Issued Date 2012/07/01 Deciphered Date 2014/07/01 Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 3 of 59

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A A
JCPU1A ME@
J22 PEG_COMP R1 1 2 24.9_0402_1% +1.05VS PEG_ICOMPI and RCOMPO signals should be shorted and routed
PEG_ICOMPI J21
PEG_ICOMPO with - max length = 500 mils - typical impedance = 43 mohms
15 DMI_CRX_PTX_N0 B27 H22 PEG_ICOMPO signals should be routed with - max length = 500 mils
B25 DMI_RX#[0] PEG_RCOMPO
15 DMI_CRX_PTX_N1 DMI_RX#[1] - typical impedance = 14.5 mohms
15 DMI_CRX_PTX_N2 A25
DMI_RX#[2] PCIE_CRX_GTX_N[0..7] 22
15 DMI_CRX_PTX_N3 B24 K33 PCIE_CRX_GTX_N0
DMI_RX#[3] PEG_RX#[0] M35 PCIE_CRX_GTX_N1
B28 PEG_RX#[1] L34 PCIE_CRX_GTX_N2
15 DMI_CRX_PTX_P0 DMI_RX[0] PEG_RX#[2]
B26 J35 PCIE_CRX_GTX_N3
15 DMI_CRX_PTX_P1 DMI_RX[1] PEG_RX#[3]
15 DMI_CRX_PTX_P2 A24 J32 PCIE_CRX_GTX_N4

DMI
B23 DMI_RX[2] PEG_RX#[4] H34 PCIE_CRX_GTX_N5
15 DMI_CRX_PTX_P3 DMI_RX[3] PEG_RX#[5] H31 PCIE_CRX_GTX_N6
G21 PEG_RX#[6] G33 PCIE_CRX_GTX_N7
15 DMI_CTX_PRX_N0 DMI_TX#[0] PEG_RX#[7]
E22 G30
15 DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8]
F21 F35 PEG Static Lane Reversal - CFG2 is for the 16x
15 DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9]
D21 E34
15 DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10] E32
G22 PEG_RX#[11] D33 1: Normal Operation; Lane # definition matches
15
15
15
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
D22
F20
DMI_TX[0]
DMI_TX[1]
PEG_RX#[12]
PEG_RX#[13]
D31
B33
CFG2 * socket pin map definition

PCI EXPRESS* - GRAPHICS


C21 DMI_TX[2] PEG_RX#[14] C32
15 DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15]
PCIE_CRX_GTX_P[0..7] 22 0:Lane Reversed
J33 PCIE_CRX_GTX_P0
PEG_RX[0] L35 PCIE_CRX_GTX_P1
PEG_RX[1] K34 PCIE_CRX_GTX_P2
A21 PEG_RX[2] H35 PCIE_CRX_GTX_P3
15 FDI_CTX_PRX_N0 FDI0_TX#[0] PEG_RX[3]
H19 H32 PCIE_CRX_GTX_P4
15 FDI_CTX_PRX_N1 FDI0_TX#[1] PEG_RX[4]
E19 G34 PCIE_CRX_GTX_P5
15 FDI_CTX_PRX_N2 FDI0_TX#[2] PEG_RX[5]
F18 G31 PCIE_CRX_GTX_P6
15 FDI_CTX_PRX_N3 FDI0_TX#[3] PEG_RX[6]

Intel(R) FDI
B21 F33 PCIE_CRX_GTX_P7
15 FDI_CTX_PRX_N4 FDI1_TX#[0] PEG_RX[7]
C20 F30
15 FDI_CTX_PRX_N5 FDI1_TX#[1] PEG_RX[8]
D18 E35
15 FDI_CTX_PRX_N6 FDI1_TX#[2] PEG_RX[9]
E17 E33
B 15 FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10] B
F32
PEG_RX[11] D34
A22 PEG_RX[12] E31
15 FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13]
G19 C33
15 FDI_CTX_PRX_P1 FDI0_TX[1] PEG_RX[14]
E20 B32
15 FDI_CTX_PRX_P2 FDI0_TX[2] PEG_RX[15]
G18
15 FDI_CTX_PRX_P3 FDI0_TX[3] PCIE_CTX_GRX_N[0..7] 22
B20 M29 PCIE_CTX_GRX_C_N0 C1 1 2 DIS@ 0.22U_0402_10V6K PCIE_CTX_GRX_N0
15 FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0]
C19 M32 PCIE_CTX_GRX_C_N1 C2 1 2 DIS@ 0.22U_0402_10V6K PCIE_CTX_GRX_N1
15 FDI_CTX_PRX_P5 FDI1_TX[1] PEG_TX#[1]
D19 M31 PCIE_CTX_GRX_C_N2 C3 1 2 DIS@ 0.22U_0402_10V6K PCIE_CTX_GRX_N2
15 FDI_CTX_PRX_P6 FDI1_TX[2] PEG_TX#[2]
F17 L32 PCIE_CTX_GRX_C_N3 C4 1 2 DIS@ 0.22U_0402_10V6K PCIE_CTX_GRX_N3
15 FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3] L29 PCIE_CTX_GRX_C_N4 C5 1 2 DIS@ 0.22U_0402_10V6K PCIE_CTX_GRX_N4
J18 PEG_TX#[4] K31 PCIE_CTX_GRX_C_N5 C6 1 2 DIS@ 0.22U_0402_10V6K PCIE_CTX_GRX_N5
15 FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5]
15 FDI_FSYNC1 J17 K28 PCIE_CTX_GRX_C_N6 C7 1 2 DIS@ 0.22U_0402_10V6K PCIE_CTX_GRX_N6
FDI1_FSYNC PEG_TX#[6] J30 PCIE_CTX_GRX_C_N7 C8 1 2 DIS@ 0.22U_0402_10V6K PCIE_CTX_GRX_N7
H20 PEG_TX#[7] J28
15 FDI_INT FDI_INT PEG_TX#[8] H29
J19 PEG_TX#[9] G27
15 FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10]
15 FDI_LSYNC1 H17 E29
FDI1_LSYNC PEG_TX#[11] F27
PEG_TX#[12] D28
+1.05VS PEG_TX#[13] F26
PEG_TX#[14] E25
R2 1 2 24.9_0402_1% EDP_COMP A18 PEG_TX#[15]
eDP_COMPIO PCIE_CTX_GRX_P[0..7] 22
A17 M28 PCIE_CTX_GRX_C_P0 C17 1 2 DIS@ 0.22U_0402_10V6K PCIE_CTX_GRX_P0
R3 1 @ 2 10K_0402_5% B16 eDP_ICOMPO PEG_TX[0] M33 PCIE_CTX_GRX_C_P1 C18 1 2 DIS@ 0.22U_0402_10V6K PCIE_CTX_GRX_P1
eDP_HPD# PEG_TX[1] M30 PCIE_CTX_GRX_C_P2 C19 1 2 DIS@ 0.22U_0402_10V6K PCIE_CTX_GRX_P2
PEG_TX[2] L31 PCIE_CTX_GRX_C_P3 C20 1 2 DIS@ 0.22U_0402_10V6K PCIE_CTX_GRX_P3
C15 PEG_TX[3] L28 PCIE_CTX_GRX_C_P4 C21 1 2 DIS@ 0.22U_0402_10V6K PCIE_CTX_GRX_P4
D15 eDP_AUX PEG_TX[4] K30 PCIE_CTX_GRX_C_P5 C22 1 2 DIS@ 0.22U_0402_10V6K PCIE_CTX_GRX_P5
eDP_AUX# PEG_TX[5] K27 PCIE_CTX_GRX_C_P6 C23 1 2 DIS@ 0.22U_0402_10V6K PCIE_CTX_GRX_P6
eDP
PEG_TX[6] J29 PCIE_CTX_GRX_C_P7 C24 1 2 DIS@ 0.22U_0402_10V6K PCIE_CTX_GRX_P7
C17 PEG_TX[7] J27
eDP_COMPIO and ICOMPO signals eDP_TX[0] PEG_TX[8]
F16 H28
should be shorted near balls C16 eDP_TX[1] PEG_TX[9] G28
G15 eDP_TX[2] PEG_TX[10] E28
C and routed with typical eDP_TX[3] PEG_TX[11]
C
F28
impedance <25 mohms C18 PEG_TX[12] D27
E16 eDP_TX#[0] PEG_TX[13] E26
D16 eDP_TX#[1] PEG_TX[14] D25
F15 eDP_TX#[2] PEG_TX[15]
eDP_TX#[3]

TYCO_2013620-2_IVY BRIDGE

Nvidia support PCIE Gen2

D D

Security Classification LC Future Center Secret Data Title


Issued Date 2012/07/01 Deciphered Date 2014/07/01 PROCESSOR(1/7) DMI,FDI,PEG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 4 of 59

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JCPU1B

A28 CLK_CPU_DMI_R R355 1 2 0_0402_5%


BCLK CLK_CPU_DMI 14
C26 A27 CLK_CPU_DMI#_R R354 1 2 0_0402_5%

MISC

CLOCKS
18 H_SNB_IVB# PROC_SELECT# BCLK# CLK_CPU_DMI# 14
A A
R306 1 @ 2 10K_0402_5% AN34
SKTOCC# A16 R297 1 2 1K_0402_5%
DPLL_REF_CLK A15 R321 1 2 1K_0402_5%
DPLL_REF_CLK# +1.05VS

H_CATERR# AL33
CATERR#

+1.05VS

THERMAL
H_PECI AN33 R8
18,41 H_PECI PECI SM_DRAMRST# H_DRAMRST# 6
Processor Pullups

DDR3
MISC
R2811 2 62_0402_5% H_PROCHOT# H_PROCHOT# R298 1 2 56_0402_5% H_PROCHOT#_R AL32 AK1 SM_RCOMP0 R20 1 2 140_0402_1%
41 H_PROCHOT# PROCHOT# SM_RCOMP[0] A5 SM_RCOMP1 R236 1 2 25.5_.402_1%
SM_RCOMP[1] A4 SM_RCOMP2 R312 1 2 200_0402_1%
SM_RCOMP[2]
DDR3 Compensation Signals
H_THRMTRIP# AN32
18 H_THRMTRIP# THERMTRIP#

P+ AP29 XDP_PRDY# PU/PD for JTAG signals


PRDY# AP27
P+ XDP_PREQ#
PREQ# +1.05VS
P+ AR26 XDP_TCK R326 1 2 51_0402_5%
TCK AR27 R238 1 2 51_0402_5%
P+ XDP_TMS

PWR MANAGEMENT
TMS

JTAG & BPM


H_PM_SYNC AM34 P+ AP30 XDP_TRST# R323 1 2 51_0402_5%
15 H_PM_SYNC PM_SYNC TRST#
P+ AR28 XDP_TDI R296 1 2 51_0402_5%
TDI AP26 XDP_TDO R299 1 2 51_0402_5%
R240 1 2 0_0402_5% H_CPUPWRGD_R AP33 TDO
18,5 H_CPUPWRGD UNCOREPWRGOOD +3VS
R324 1 2 10K_0402_5%
C75 @
@1 2 220P_0402_50V7K R327 1 2 1K_0402_5%
B B
AL35 XDP_DBRESET#_C R267 1 2 0_0402_5%
DBR# XDP_DBRESET# 15
PM_SYS_PWRGD_BUF R322 1 2 130_0402_5% PM_DRAM_PWRGD_R V8
SM_DRAMPWROK
AT28 XDP_BPM#0
BPM#[0] AR29 XDP_BPM#1
BPM#[1] AR30 XDP_BPM#2
BUF_CPU_RST# AR33 BPM#[2] AT30 XDP_BPM#3
RESET# BPM#[3] AP32
P+ BPM#[4]
XDP_BPM#4
AR31 XDP_BPM#5
BPM#[5] AT31 XDP_BPM#6
BPM#[6] AR32 XDP_BPM#7
BPM#[7]

TYCO_2013620-2_IVY BRIDGE
ME@

C C

+3VS +3VALW +1.5V_CPU_VDDQ +3VS +1.05VS

1 Buffered reset to CPU 1


1

1
C74 C73
0.1U_0402_16V4Z R331 0.1U_0402_16V4Z R320
200_0402_5% 75_0402_5%
2 2
2

2
5

R295 U12 R242


5

10K_0402_5% 74AHC1G09GW_TSSOP5 1 43_0402_1%


P

1 2 1 NC 4 BUFO_CPU_RST# 1 2 BUF_CPU_RST#
P

B 4 PM_SYS_PWRGD_BUF 2 Y
O 17 PCH_PLTRST# A
G

1
2 U7
15 PM_DRAM_PWRGD A
G

SN74LVC1G07DCKR_SC70-5 R44
3
1

0_0402_5%
3

R239 @
39_0402_5% For 26 Pin XDP Conn.

2
@
1 2

R237 1 @ 2 1K_0402_1%
18,5 H_CPUPWRGD
R301 1 @ 2 0_0402_5%
15,41 PBTN_OUT#
D Q13 R224 1 @ 2 1K_0402_1%
7 XDP_CFG0
2 2N7002K_SOT23-3 R325 1 @ 2 0_0402_5%
9 RUN_ON_CPU1.5VS3# 15 SYS_PWROK
G @ R194 1 @ 2 0_0402_5%
14 CLK_XDP_CLK
S R279 1 @ 2 0_0402_5%
14 CLK_XDP_CLK#
PLT_RST# R191 1 @ 2 1K_0402_1%
14,17,22,38,39,40,41,42 PLT_RST#
3

@
PM_DRAM_PWRGD R333 1 2 0_0402_5% PM_SYS_PWRGD_BUF

D D

Security Classification LC Future Center Secret Data Title


Issued Date 2012/07/01 Deciphered Date 2014/07/01 PROCESSOR(2/7) PM,XDP,CLK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 5 of 59

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JCPU1C ME@ JCPU1D ME@

AB6 AE2
11 DDR_A_D[0..63] SA_CLK[0] M_CLK_DDR0 11 12 DDR_B_D[0..63] SB_CLK[0] M_CLK_DDR2 12
A AA6 AD2 A
SA_CLK#[0] M_CLK_DDR#0 11 SB_CLK#[0] M_CLK_DDR#2 12
DDR_A_D0 C5 V9 DDR_B_D0 C9 R9
SA_DQ[0] SA_CKE[0] DDR_CKE0_DIMMA 11 SB_DQ[0] SB_CKE[0] DDR_CKE2_DIMMB 12
DDR_A_D1 D5 DDR_B_D1 A7
DDR_A_D2 D3 SA_DQ[1] DDR_B_D2 D10 SB_DQ[1]
DDR_A_D3 D2 SA_DQ[2] DDR_B_D3 C8 SB_DQ[2]
DDR_A_D4 D6 SA_DQ[3] AA5 DDR_B_D4 A9 SB_DQ[3] AE1
SA_DQ[4] SA_CLK[1] M_CLK_DDR1 11 SB_DQ[4] SB_CLK[1] M_CLK_DDR3 12
DDR_A_D5 C6 AB5 DDR_B_D5 A8 AD1
SA_DQ[5] SA_CLK#[1] M_CLK_DDR#1 11 SB_DQ[5] SB_CLK#[1] M_CLK_DDR#3 12
DDR_A_D6 C2 V10 DDR_B_D6 D9 R10
SA_DQ[6] SA_CKE[1] DDR_CKE1_DIMMA 11 SB_DQ[6] SB_CKE[1] DDR_CKE3_DIMMB 12
DDR_A_D7 C3 DDR_B_D7 D8
DDR_A_D8 F10 SA_DQ[7] DDR_B_D8 G4 SB_DQ[7]
DDR_A_D9 F8 SA_DQ[8] DDR_B_D9 F4 SB_DQ[8]
DDR_A_D10 G10 SA_DQ[9] AB4 DDR_B_D10 F1 SB_DQ[9] AB2
DDR_A_D11 G9 SA_DQ[10] RSVD_TP[1] AA4 DDR_B_D11 G1 SB_DQ[10] RSVD_TP[11] AA2
DDR_A_D12 F9 SA_DQ[11] RSVD_TP[2] W9 DDR_B_D12 G5 SB_DQ[11] RSVD_TP[12] T9
DDR_A_D13 F7 SA_DQ[12] RSVD_TP[3] DDR_B_D13 F5 SB_DQ[12] RSVD_TP[13]
DDR_A_D14 G8 SA_DQ[13] DDR_B_D14 F2 SB_DQ[13]
DDR_A_D15 G7 SA_DQ[14] DDR_B_D15 G2 SB_DQ[14]
DDR_A_D16 K4 SA_DQ[15] AB3 DDR_B_D16 J7 SB_DQ[15] AA1
DDR_A_D17 K5 SA_DQ[16] RSVD_TP[4] AA3 DDR_B_D17 J8 SB_DQ[16] RSVD_TP[14] AB1
DDR_A_D18 K1 SA_DQ[17] RSVD_TP[5] W10 DDR_B_D18 K10 SB_DQ[17] RSVD_TP[15] T10
DDR_A_D19 J1 SA_DQ[18] RSVD_TP[6] DDR_B_D19 K9 SB_DQ[18] RSVD_TP[16]
DDR_A_D20 J5 SA_DQ[19] DDR_B_D20 J9 SB_DQ[19]
DDR_A_D21 J4 SA_DQ[20] DDR_B_D21 J10 SB_DQ[20]
DDR_A_D22 J2 SA_DQ[21] AK3 DDR_B_D22 K8 SB_DQ[21] AD3
SA_DQ[22] SA_CS#[0] DDR_CS0_DIMMA# 11 SB_DQ[22] SB_CS#[0] DDR_CS2_DIMMB# 12
DDR_A_D23 K2 AL3 DDR_B_D23 K7 AE3
SA_DQ[23] SA_CS#[1] DDR_CS1_DIMMA# 11 SB_DQ[23] SB_CS#[1] DDR_CS3_DIMMB# 12
DDR_A_D24 M8 AG1 DDR_B_D24 M5 AD6
DDR_A_D25 N10 SA_DQ[24] RSVD_TP[7] AH1 DDR_B_D25 N4 SB_DQ[24] RSVD_TP[17] AE6
DDR_A_D26 N8 SA_DQ[25] RSVD_TP[8] DDR_B_D26 N2 SB_DQ[25] RSVD_TP[18]
DDR_A_D27 N7 SA_DQ[26] DDR_B_D27 N1 SB_DQ[26]
DDR_A_D28 M10 SA_DQ[27] DDR_B_D28 M4 SB_DQ[27]
DDR_A_D29 M9 SA_DQ[28] AH3 DDR_B_D29 N5 SB_DQ[28] AE4
SA_DQ[29] SA_ODT[0] M_ODT0 11 SB_DQ[29] SB_ODT[0] M_ODT2 12
DDR_A_D30 N9 AG3 DDR_B_D30 M2 AD4

DDR SYSTEM MEMORY B


SA_DQ[30] SA_ODT[1] M_ODT1 11 SB_DQ[30] SB_ODT[1] M_ODT3 12
M7 AG2 M1 AD5

DDR SYSTEM MEMORY A


DDR_A_D31 DDR_B_D31
DDR_A_D32 AG6 SA_DQ[31] RSVD_TP[9] AH2 DDR_B_D32 AM5 SB_DQ[31] RSVD_TP[19] AE5
DDR_A_D33 AG5 SA_DQ[32] RSVD_TP[10] DDR_B_D33 AM6 SB_DQ[32] RSVD_TP[20]
B
DDR_A_D34 AK6 SA_DQ[33] DDR_B_D34 AR3 SB_DQ[33] B
DDR_A_D35 AK5 SA_DQ[34] DDR_B_D35 AP3 SB_DQ[34]
DDR_A_D36 AH5 SA_DQ[35] DDR_B_D36 AN3 SB_DQ[35]
SA_DQ[36] DDR_A_DQS#[0..7] 11 SB_DQ[36] DDR_B_DQS#[0..7] 12
DDR_A_D37 AH6 C4 DDR_A_DQS#0 DDR_B_D37 AN2 D7 DDR_B_DQS#0
DDR_A_D38 AJ5 SA_DQ[37] SA_DQS#[0] G6 DDR_A_DQS#1 DDR_B_D38 AN1 SB_DQ[37] SB_DQS#[0] F3 DDR_B_DQS#1
DDR_A_D39 AJ6 SA_DQ[38] SA_DQS#[1] J3 DDR_A_DQS#2 DDR_B_D39 AP2 SB_DQ[38] SB_DQS#[1] K6 DDR_B_DQS#2
DDR_A_D40 AJ8 SA_DQ[39] SA_DQS#[2] M6 DDR_A_DQS#3 DDR_B_D40 AP5 SB_DQ[39] SB_DQS#[2] N3 DDR_B_DQS#3
DDR_A_D41 AK8 SA_DQ[40] SA_DQS#[3] AL6 DDR_A_DQS#4 DDR_B_D41 AN9 SB_DQ[40] SB_DQS#[3] AN5 DDR_B_DQS#4
DDR_A_D42 AJ9 SA_DQ[41] SA_DQS#[4] AM8 DDR_A_DQS#5 DDR_B_D42 AT5 SB_DQ[41] SB_DQS#[4] AP9 DDR_B_DQS#5
DDR_A_D43 AK9 SA_DQ[42] SA_DQS#[5] AR12 DDR_A_DQS#6 DDR_B_D43 AT6 SB_DQ[42] SB_DQS#[5] AK12 DDR_B_DQS#6
DDR_A_D44 AH8 SA_DQ[43] SA_DQS#[6] AM15 DDR_A_DQS#7 DDR_B_D44 AP6 SB_DQ[43] SB_DQS#[6] AP15 DDR_B_DQS#7
DDR_A_D45 AH9 SA_DQ[44] SA_DQS#[7] DDR_B_D45 AN8 SB_DQ[44] SB_DQS#[7]
DDR_A_D46 AL9 SA_DQ[45] DDR_B_D46 AR6 SB_DQ[45]
DDR_A_D47 AL8 SA_DQ[46] DDR_B_D47 AR5 SB_DQ[46]
DDR_A_D48 AP11 SA_DQ[47] DDR_B_D48 AR9 SB_DQ[47]
SA_DQ[48] DDR_A_DQS[0..7] 11 SB_DQ[48] DDR_B_DQS[0..7] 12
DDR_A_D49 AN11 D4 DDR_A_DQS0 DDR_B_D49 AJ11 C7 DDR_B_DQS0
DDR_A_D50 AL12 SA_DQ[49] SA_DQS[0] F6 DDR_A_DQS1 DDR_B_D50 AT8 SB_DQ[49] SB_DQS[0] G3 DDR_B_DQS1
DDR_A_D51 AM12 SA_DQ[50] SA_DQS[1] K3 DDR_A_DQS2 DDR_B_D51 AT9 SB_DQ[50] SB_DQS[1] J6 DDR_B_DQS2
DDR_A_D52 AM11 SA_DQ[51] SA_DQS[2] N6 DDR_A_DQS3 DDR_B_D52 AH11 SB_DQ[51] SB_DQS[2] M3 DDR_B_DQS3
DDR_A_D53 AL11 SA_DQ[52] SA_DQS[3] AL5 DDR_A_DQS4 DDR_B_D53 AR8 SB_DQ[52] SB_DQS[3] AN6 DDR_B_DQS4
DDR_A_D54 AP12 SA_DQ[53] SA_DQS[4] AM9 DDR_A_DQS5 DDR_B_D54 AJ12 SB_DQ[53] SB_DQS[4] AP8 DDR_B_DQS5
DDR_A_D55 AN12 SA_DQ[54] SA_DQS[5] AR11 DDR_A_DQS6 DDR_B_D55 AH12 SB_DQ[54] SB_DQS[5] AK11 DDR_B_DQS6
DDR_A_D56 AJ14 SA_DQ[55] SA_DQS[6] AM14 DDR_A_DQS7 DDR_B_D56 AT11 SB_DQ[55] SB_DQS[6] AP14 DDR_B_DQS7
DDR_A_D57 AH14 SA_DQ[56] SA_DQS[7] DDR_B_D57 AN14 SB_DQ[56] SB_DQS[7]
DDR_A_D58 AL15 SA_DQ[57] DDR_B_D58 AR14 SB_DQ[57]
DDR_A_D59 AK15 SA_DQ[58] DDR_B_D59 AT14 SB_DQ[58]
DDR_A_D60 AL14 SA_DQ[59] DDR_B_D60 AT12 SB_DQ[59]
SA_DQ[60] DDR_A_MA[0..15] 11 SB_DQ[60] DDR_B_MA[0..15] 12
DDR_A_D61 AK14 AD10 DDR_A_MA0 DDR_B_D61 AN15 AA8 DDR_B_MA0
DDR_A_D62 AJ15 SA_DQ[61] SA_MA[0] W1 DDR_A_MA1 DDR_B_D62 AR15 SB_DQ[61] SB_MA[0] T7 DDR_B_MA1
DDR_A_D63 AH15 SA_DQ[62] SA_MA[1] W2 DDR_A_MA2 DDR_B_D63 AT15 SB_DQ[62] SB_MA[1] R7 DDR_B_MA2
SA_DQ[63] SA_MA[2] W7 DDR_A_MA3 SB_DQ[63] SB_MA[2] T6 DDR_B_MA3
SA_MA[3] V3 DDR_A_MA4 SB_MA[3] T2 DDR_B_MA4
SA_MA[4] V2 DDR_A_MA5 SB_MA[4] T4 DDR_B_MA5
SA_MA[5] W3 DDR_A_MA6 SB_MA[5] T3 DDR_B_MA6
AE10 SA_MA[6] W6 DDR_A_MA7 AA9 SB_MA[6] R2 DDR_B_MA7
C C
11 DDR_A_BS0 SA_BS[0] SA_MA[7] 12 DDR_B_BS0 SB_BS[0] SB_MA[7]
AF10 V1 DDR_A_MA8 AA7 T5 DDR_B_MA8
11 DDR_A_BS1 SA_BS[1] SA_MA[8] 12 DDR_B_BS1 SB_BS[1] SB_MA[8]
V6 W5 DDR_A_MA9 R6 R3 DDR_B_MA9
11 DDR_A_BS2 SA_BS[2] SA_MA[9] 12 DDR_B_BS2 SB_BS[2] SB_MA[9]
AD8 DDR_A_MA10 AB7 DDR_B_MA10
SA_MA[10] V4 DDR_A_MA11 SB_MA[10] R1 DDR_B_MA11
SA_MA[11] W4 DDR_A_MA12 SB_MA[11] T1 DDR_B_MA12
AE8 SA_MA[12] AF8 DDR_A_MA13 AA10 SB_MA[12] AB10 DDR_B_MA13
11 DDR_A_CAS# SA_CAS# SA_MA[13] 12 DDR_B_CAS# SB_CAS# SB_MA[13]
AD9 V5 DDR_A_MA14 AB8 R5 DDR_B_MA14
11 DDR_A_RAS# SA_RAS# SA_MA[14] 12 DDR_B_RAS# SB_RAS# SB_MA[14]
AF9 V7 DDR_A_MA15 AB9 R4 DDR_B_MA15
11 DDR_A_WE# SA_WE# SA_MA[15] 12 DDR_B_WE# SB_WE# SB_MA[15]

TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE

+1.5V

R39 1 @ 2 0_0402_5%
1

R40
1K_0402_5% R41
1K_0402_5%
3
S

1 DDR3_DRAMRST#_R 1 2
5 H_DRAMRST# DDR3_DRAMRST# 11,12
2
1

D D
Q2
BSS138_NL_SOT23-3
G
2

R42
4.99K_0402_1%
2

R43 1 2 0_0402_5% DRAMRST_CNTRL


14 DRAMRST_CNTRL_PCH DRAMRST_CNTRL 9
1 Security Classification LC Future Center Secret Data Title
C36
0.047U_0402_16V4Z PROCESSOR(3/7) DDRIII
Issued Date 2012/07/01 Deciphered Date 2014/07/01
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 6 of 59

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CFG Straps for Processor


CFG2

1
A R45 A
1K_0402_1%
@

2
JCPU1E ME@
PEG Static Lane Reversal - CFG2 is for the 16x

AH27 1: Normal Operation; Lane # definition matches


5 XDP_CFG0 AK28
AK29 CFG[0]
CFG[1]
VCC_DIE_SENSE
VSS_DIE_SENSE
AH26 R173 1
T2
2 0_0402_5% CFG2 * socket pin map definition
CFG2 AL26
AL27 CFG[2]
CFG[3] 0:Lane Reversed
CFG4 AK26 L7
CFG5 AL29 CFG[4] RSVD28 AG7
AL30 CFG[5] RSVD29 AE7
CFG6 P+
CFG7 AM31 CFG[6] RSVD30 AK2
AM32 CFG[7] RSVD31 CFG4
AM30 CFG[8] W8

CFG
+CPU_CORE +VCC_GFXCORE_AXG AM28 CFG[9] RSVD32
CFG[10]

1
AM26
AN28 CFG[11] AT26
AN31 CFG[12] RSVD33 AM33 R50
CFG[13] RSVD34
1

AN26 AJ27 1K_0402_1%


R48 R46 AM27 CFG[14] RSVD35

2
49.9_0402_1% AK31 CFG[15]
49.9_0402_1% CFG[16]
AN29
CFG[17]
2

T8 Display Port Presence Strap


RSVD37 J16
B
VCC_AXG_VAL_SENSE AJ31 RSVD38 H16 B
R176 1 @ 2 100_0402_1% VSS_AXG_VAL_SENSE AH31 VAXG_VAL_SENSE RSVD39 G16
VSSAXG_VAL_SENSE RSVD40 1 : Disabled; No Physical Display Port
VCC_VAL_SENSE AJ33 CFG4
R179 1 @ 2 100_0402_1% VSS_VAL_SENSE AH33 VCC_VAL_SENSE attached to Embedded Display Port
VSS_VAL_SENSE
R47 1 2 49.9_0402_1% VSS_AXG_VAL_SENSE 0 : Enabled; An external Display Port device is
R49 1 2 49.9_0402_1% VSS_VAL_SENSE
AJ26
RSVD5 RSVD_NCTF1
AR35
AT34 * connected to the Embedded Display Port

RESERVED
RSVD_NCTF2 AT33
RSVD_NCTF3 AP35
RSVD_NCTF4 AR34
RSVD_NCTF5
CFG6
F25 CFG5
F24 RSVD8
RSVD9

1
F23
D24 RSVD10 B34 R51 R52
G25 RSVD11 RSVD_NCTF6 A33 1K_0402_1% 1K_0402_1%
G24 RSVD12 RSVD_NCTF7 A34 @
E23 RSVD13 RSVD_NCTF8 B35

2
D23 RSVD14 RSVD_NCTF9 C35
C30 RSVD15 RSVD_NCTF10
A31 RSVD16
B30 RSVD17
B29 RSVD18
D30 RSVD19 AJ32
B31 RSVD20 RSVD51 AK32
A30 RSVD21 RSVD52
RSVD22 PCIE Port Bifurcation Straps
C29
RSVD23
AN35 11: (Default) x16 - Device 1 functions 1 and 2 disabled
J20 BCLK_ITP AM35
B18 RSVD24 BCLK_ITP#
CFG[6:5] 10: x8, x8 - Device 1 function 1 enabled ; function 2
C
RSVD25
* disabled C
01: Reserved - (Device 1 function 1 disabled ; function
J15 AT2
RSVD27 RSVD_NCTF11 AT1 2 enabled)
RSVD_NCTF12 AR1
RSVD_NCTF13 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

B1
KEY CFG7

1
@ R53
TYCO_2013620-2_IVY BRIDGE 1K_0402_1%

2
PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB


CFG7 de assertion

0: PEG Wait for BIOS for training

D D

Security Classification LC Future Center Secret Data Title


Issued Date 2012/07/01 Deciphered Date 2014/07/01 PROCESSOR(4/7) RSVD,CFG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 7 of 59

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+CPU_CORE +1.05VS

JCPU1F POWER ME@

97A 8.5A
AG35
AG34 VCC1 AH13
AG33 VCC2 VCCIO1 AH10
A A
AG32 VCC3 VCCIO2 AG10
AG31 VCC4 VCCIO3 AC10
AG30 VCC5 VCCIO4 Y10
AG29 VCC6 VCCIO5 U10
AG28 VCC7 VCCIO6 P10
AG27 VCC8 VCCIO7 L10
AG26 VCC9 VCCIO8 J14
AF35 VCC10 VCCIO9 J13
AF34 VCC11 VCCIO10 J12
AF33 VCC12 VCCIO11 J11
AF32 VCC13 VCCIO12 H14
AF31 VCC14 VCCIO13 H12
AF30 VCC15 VCCIO14 H11
AF29 VCC16 VCCIO15 G14
AF28 VCC17 VCCIO16 G13
AF27 VCC18 VCCIO17 G12

PEG AND DDR


AF26 VCC19 VCCIO18 F14
AD35 VCC20 VCCIO19 F13
AD34 VCC21 VCCIO20 F12
AD33 VCC22 VCCIO21 F11
AD32 VCC23 VCCIO22 E14
AD31 VCC24 VCCIO23 E12
AD30 VCC25 VCCIO24
AD29 VCC26 E11
AD28 VCC27 VCCIO25 D14
AD27 VCC28 VCCIO26 D13
AD26 VCC29 VCCIO27 D12
AC35 VCC30 VCCIO28 D11
AC34 VCC31 VCCIO29 C14
AC33 VCC32 VCCIO30 C13
AC32 VCC33 VCCIO31 C12
AC31 VCC34 VCCIO32 C11
AC30 VCC35 VCCIO33 B14
AC29 VCC36 VCCIO34 B12
B
AC28 VCC37 VCCIO35 A14 B
AC27 VCC38 VCCIO36 A13
AC26 VCC39 VCCIO37 A12
AA35 VCC40 VCCIO38 A11
AA34 VCC41 VCCIO39
AA33 VCC42 J23
AA32 VCC43 VCCIO40
AA31 VCC44
AA30 VCC45
AA29 VCC46
AA28 VCC47
AA27 VCC48 +1.05VS +1.05VS
AA26 VCC49
Y35 VCC50

CORE SUPPLY
Y34 VCC51
Y33 VCC52
VCC53

1
Y32 1 1
Y31 VCC54 C37 R54 R55 C38
Y30 VCC55 0.1U_0402_16V4Z 130_0402_5% 75_0402_5% 0.1U_0402_16V4Z
Y29 VCC56
Y28 VCC57 2 2
Place the PU

2
Y27 VCC58
Y26 VCC59 resistors close to VR
V35 VCC60
V34 VCC61 AJ29 H_CPU_SVIDALRT# R56 1 2 43_0402_1%

SVID
VCC62 VIDALERT# VR_SVID_ALRT# 53
V33 AJ30 H_CPU_SVIDCLK R57 1 2 0_0402_5%
VCC63 VIDSCLK VR_SVID_CLK 53
V32 AJ28 H_CPU_SVIDDAT R58 1 2 0_0402_5%
VCC64 VIDSOUT VR_SVID_DAT 53
V31
V30 VCC65
V29 VCC66
V28 VCC67
V27 VCC68
V26 VCC69
U35 VCC70
U34 VCC71
C C
U33 VCC72
U32 VCC73
U31 VCC74
U30 VCC75
U29 VCC76
U28 VCC77 VSSSENSE_R R174 @
@1 2 100_0402_1% VCCSENSE_R
U27 VCC78
U26 VCC79
R35 VCC80 +CPU_CORE
R34 VCC81
R33 VCC82
VCC83

1
R32
R31 VCC84 R59
VCC85 Trace Impedance = 27 ~ 33 ohm Place the PU
R30 100_0402_1%
R29 VCC86 Trace Length Match < 25 mils resistors close to CPU
R28 VCC87
SENSE LINES

2
R27 VCC88 AJ35 VCCSENSE_R R60 1 2 0_0402_5%
VCC89 VCC_SENSE VCCSENSE 53
R26 AJ34 VSSSENSE_R R61 1 2 0_0402_5%
VCC90 VSS_SENSE VSSSENSE 53
P35
P34 VCC91 +1.05VS
VCC92

1
P33 R64 1 2 10_0402_1%
P32 VCC93 B10 VCCIO_SENSE R62
VCC94 VCCIO_SENSE VCCIO_SENSE 51
P31 A10 VSSIO_SENSE 100_0402_1%
P30 VCC95 VSS_SENSE_VCCIO
P29 VCC96

2
VCC97

1
P28
P27 VCC98 R63
P26 VCC99 10_0402_1%
VCC100 2

D D

TYCO_2013620-2_IVY BRIDGE

Security Classification LC Future Center Secret Data Title


Issued Date 2012/07/01 Deciphered Date 2014/07/01 PROCESSOR(5/7) PWR,BYPASS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 8 of 59

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M3 Support R67 1 @ 2 0_0402_5%

Q3 +VREF_DQ_DIMMA
BSS138_NL_SOT23-3

+VCC_GFXCORE_AXG 3

D
+V_DDR_REFA_R 1

1
2
R79

G
2
R65 1K_0402_1%
10_0402_1% @ DRAMRST_CNTRL

2
1
A A
VCC_AXG_SENSE 53
R73 1 @ 2 100_0402_1% R71 1 @ 2 0_0402_5%

+VCC_GFXCORE_AXG
JCPU1G
POWER ME@
VSS_AXG_SENSE 53
Q6
BSS138_NL_SOT23-3
+VREF_DQ_DIMMB

1
+V_SM_VREF should
33A 3

D
R66 have 10 mil trace width +V_DDR_REFB_R 1
AT24 AK35 10_0402_1%

SENSE
LINES
VAXG1 VAXG_SENSE

1
AT23 AK34
AT21 VAXG2 VSSAXG_SENSE +1.5V_CPU_VDDQ +1.5V R108

G
2

2
AT20 VAXG3 1K_0402_1%
AT18 VAXG4 @
VAXG5

1
AT17 DRAMRST_CNTRL 6

2
AR24 VAXG6 R68 @ R69
AR23 VAXG7 1K_0402_5% R70 1 @ 2 0_0402_5% 100_0402_5%
AR21 VAXG8
VAXG9 from 1PCS 2N7002 dual channel change to BSS138 2pCS
AR20

2
AR18 VAXG10 AL1 +V_SM_VREF_CNT 3 1 +V_SM_VREF
AR17 VAXG11 SM_VREF Q4
VAXG12

C39

0.1U_0402_16V4Z
AP24 AP2302GN-HF_SOT23-3

VREF
VAXG13

1
AP23 1 @
AP21 VAXG14 R72 @ R74 +1.5V_CPU_VDDQ +1.5V
AP20 VAXG15 B4 +V_DDR_REFA_R 1K_0402_5% 2 RUN_ON_CPU1.5VS3 100_0402_5%
AP18 VAXG16 SA_DIMM_VREFDQ D1 +V_DDR_REFB_R
AP17 VAXG17 SB_DIMM_VREFDQ 2 C47 1 2 0.1U_0402_10V7K

2
AN24 VAXG18
AN23 VAXG19
AN21 VAXG20 C53 1 2 0.1U_0402_10V7K
AN20 VAXG21 +1.5V
AN18 VAXG22 +1.5V_CPU_VDDQ
10A

DDR3 -1.5V RAILS


AN17 VAXG23 @ JP1 C54 1 2 0.1U_0402_10V7K
AM24 VAXG24 AF7 1 2
GRAPHICS
AM23 VAXG25 VDDQ1 AF4
VAXG26 VDDQ2

C40

10U_0603_6.3V6M

C41

10U_0603_6.3V6M

C42

10U_0603_6.3V6M

C43

10U_0603_6.3V6M

C44

10U_0603_6.3V6M

C45

10U_0603_6.3V6M

C46

330U_D2_2V_Y
AM21 AF1 1 PAD-OPEN 4x4m C55 1 2 0.1U_0402_10V7K
AM20 VAXG27 VDDQ3 AC7
B VAXG28 VDDQ4 1 1 1 1 1 1 B
AM18 AC4 +
AM17 VAXG29 VDDQ5 AC1
AL24 VAXG30 VDDQ6 Y7
AL23 VAXG31 VDDQ7 Y4 2 2 2 2 2 2 2
AL21 VAXG32 VDDQ8 Y1
AL20 VAXG33 VDDQ9 U7
AL18 VAXG34 VDDQ10 U4
AL17 VAXG35 VDDQ11 U1
AK24 VAXG36 VDDQ12 P7
AK23 VAXG37 VDDQ13 P4
AK21 VAXG38 VDDQ14 P1 +VCCSA
AK20 VAXG39 VDDQ15
AK18 VAXG40
AK17 VAXG41
AJ24 VAXG42
VAXG43

C48

10U_0603_6.3V6M

C49

10U_0603_6.3V6M

C50

10U_0603_6.3V6M

C51

10U_0603_6.3V6M

C52

330U_D2_2V_Y
AJ23 1
AJ21 VAXG44
VAXG45 1 1 1 1
AJ20 +
AJ18 VAXG46 6A
AJ17 VAXG47 M27 @ @
AH24 VAXG48 VCCSA1 M26 2 2 2 2 2
SA RAIL

AH23 VAXG49 VCCSA2 L26


AH21 VAXG50 VCCSA3 J26
AH20 VAXG51 VCCSA4 J25
AH18 VAXG52 VCCSA5 J24
AH17 VAXG53 VCCSA6 H26
VAXG54 VCCSA7 H25
VCCSA8

+1.5V_CPU_VDDQ Source
1.8V RAIL

+1.8VS_VCCPLL H23
+1.8VS VCCSA_SENSE +VCCSA_SENSE 50
C
1.5A R75 1 @ 2 0_0402_5% C
R76 1 2 0_0805_5% B6
A6 VCCPLL1 C22 +3VALW +VSB +1.5V +1.5V_CPU_VDDQ
MISC

VCCPLL2 VCCSA_VID[0] H_VCCSA_VID0 50


C56

10U_0603_6.3V6M

C57

1U_0402_6.3V6K

C58

1U_0402_6.3V6K

C59

330U_D2_2V_Y

1 A2 C24 @ J2
VCCPLL3 VCCSA_VID[1] H_VCCSA_VID1 50
1 1 1 1 2
+ +3VS
PAD-OPEN 4x4m
@ A19 H_VCCP_SEL R77 1 2 0_0402_5% R78 1 2 10K_0402_5% Q5
2 2 2 2 VCCIO_SEL AP4800BGM-HF_SO-8
IVY Bridge drives VCCIO_SEL low

1
TYCO_2013620-2_IVY BRIDGE 8 1

R82
VCCP_PWRCTRL:0 R80
100K_0402_5%
R81
82K_0402_1%
7
6
2
3

1
@ 5 1
C60
Sandy Bridge is NC for A19

2
0.1U_0402_10V6K

4
@
VCCP_PWRCTRL:1 R201 2

2
220_0402_5%
RUN_ON_CPU1.5VS3 1 2

1
Q11 15K_0402_5%

1
D R85 1
31,43,49,52 SUSP R83 1 2 0_0402_5% 2
G @ C61

1
S

1
2

0.047U_0603_25V7K
D

2
2N7002K_SOT23-3

330K_0402_5%
Q12 D 2 RUN_ON_CPU1.5VS3#
2 G
G S Q7

2N7002K_SOT23-3
31,41,43,49,51 SUSP# R86 1 @ 2 @ S 2N7002K_SOT23-3

3
3
0_0402_5%

D D

RUN_ON_CPU1.5VS3#
Vaxg 5 RUN_ON_CPU1.5VS3#

‧ Can connect to GND if motherboard only


supports external graphics and if GFX VR is not

‧ VAXG can be left floating in a common


stuffed in a common motherboard design,
Security Classification LC Future Center Secret Data Title

motherboard design (Gfx VR keeps VAXG from Issued Date 2012/07/01 Deciphered Date 2014/07/01 PROCESSOR(6/7) PWR
floating) if the VR is stuffed THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 9 of 59

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1 2 3 4 5

A A

JCPU1H ME@ JCPU1I ME@

AT35 AJ22
AT32 VSS1 VSS81 AJ19
AT29 VSS2 VSS82 AJ16 T35 F22
AT27 VSS3 VSS83 AJ13 T34 VSS161 VSS234 F19
AT25 VSS4 VSS84 AJ10 T33 VSS162 VSS235 E30
AT22 VSS5 VSS85 AJ7 T32 VSS163 VSS236 E27
AT19 VSS6 VSS86 AJ4 T31 VSS164 VSS237 E24
AT16 VSS7 VSS87 AJ3 T30 VSS165 VSS238 E21
AT13 VSS8 VSS88 AJ2 T29 VSS166 VSS239 E18
AT10 VSS9 VSS89 AJ1 T28 VSS167 VSS240 E15
AT7 VSS10 VSS90 AH35 T27 VSS168 VSS241 E13
AT4 VSS11 VSS91 AH34 T26 VSS169 VSS242 E10
AT3 VSS12 VSS92 AH32 P9 VSS170 VSS243 E9
AR25 VSS13 VSS93 AH30 P8 VSS171 VSS244 E8
AR22 VSS14 VSS94 AH29 P6 VSS172 VSS245 E7
AR19 VSS15 VSS95 AH28 P5 VSS173 VSS246 E6
AR16 VSS16 VSS96 AH25 P3 VSS174 VSS247 E5
AR13 VSS17 VSS98 AH22 P2 VSS175 VSS248 E4
AR10 VSS18 VSS99 AH19 N35 VSS176 VSS249 E3
AR7 VSS19 VSS100 AH16 N34 VSS177 VSS250 E2
AR4 VSS20 VSS101 AH7 N33 VSS178 VSS251 E1
AR2 VSS21 VSS102 AH4 N32 VSS179 VSS252 D35
AP34 VSS22 VSS103 AG9 N31 VSS180 VSS253 D32
AP31 VSS23 VSS104 AG8 N30 VSS181 VSS254 D29
AP28 VSS24 VSS105 AG4 N29 VSS182 VSS255 D26
AP25 VSS25 VSS106 AF6 N28 VSS183 VSS256 D20
AP22 VSS26 VSS107 AF5 N27 VSS184 VSS257 D17
AP19 VSS27 VSS108 AF3 N26 VSS185 VSS258 C34
AP16 VSS28 VSS109 AF2 M34 VSS186 VSS259 C31
AP13 VSS29 VSS110 AE35 L33 VSS187 VSS260 C28
B
AP10 VSS30 VSS111 AE34 L30 VSS188 VSS261 C27 B
AP7 VSS31 VSS112 AE33 L27 VSS189 VSS262 C25
AP4 VSS32 VSS113 AE32 L9 VSS190 VSS263 C23
AP1 VSS33 VSS114 AE31 L8 VSS191 VSS264 C10
AN30 VSS34 VSS115 AE30 L6 VSS192 VSS265 C1
AN27 VSS35 VSS116 AE29 L5 VSS193 VSS266 B22
AN25 VSS36 VSS117 AE28 L4 VSS194 VSS267 B19
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS118
VSS119
VSS120
AE27
AE26
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
AN16 AE9 L1 B13
AN13 VSS40 VSS121 AD7 K35 VSS198 VSS271 B11
AN10 VSS41 VSS122 AC9 K32 VSS199 VSS272 B9
AN7 VSS42 VSS123 AC8 K29 VSS200 VSS273 B8
AN4 VSS43 VSS124 AC6 K26 VSS201 VSS274 B7
AM29 VSS44 VSS125 AC5 J34 VSS202 VSS275 B5
AM25 VSS45 VSS126 AC3 J31 VSS203 VSS276 B3
AM22 VSS46 VSS127 AC2 H33 VSS204 VSS277 B2
AM19 VSS47 VSS128 AB35 H30 VSS205 VSS278 A35
AM16 VSS48 VSS129 AB34 H27 VSS206 VSS279 A32
AM13 VSS49 VSS130 AB33 H24 VSS207 VSS280 A29
AM10 VSS50 VSS131 AB32 H21 VSS208 VSS281 A26
AM7 VSS51 VSS132 AB31 H18 VSS209 VSS282 A23
AM4 VSS52 VSS133 AB30 H15 VSS210 VSS283 A20
AM3 VSS53 VSS134 AB29 H13 VSS211 VSS284 A3
AM2 VSS54 VSS135 AB28 H10 VSS212 VSS285
AM1 VSS55 VSS136 AB27 H9 VSS213
AL34 VSS56 VSS137 AB26 H8 VSS214
AL31 VSS57 VSS138 Y9 H7 VSS215
AL28 VSS58 VSS139 Y8 H6 VSS216
AL25 VSS59 VSS140 Y6 H5 VSS217
AL22 VSS60 VSS141 Y5 H4 VSS218
AL19 VSS61 VSS142 Y3 H3 VSS219
AL16 VSS62 VSS143 Y2 H2 VSS220
AL13 VSS63 VSS144 W35 H1 VSS221
AL10 VSS64 VSS145 W34 G35 VSS222
C C
AL7 VSS65 VSS146 W33 G32 VSS223
AL4 VSS66 VSS147 W32 G29 VSS224
AL2 VSS67 VSS148 W31 G26 VSS225
AK33 VSS68 VSS149 W30 G23 VSS226
AK30 VSS69 VSS150 W29 G20 VSS227
AK27 VSS70 VSS151 W28 G17 VSS228
AK25 VSS71 VSS152 W27 G11 VSS229
AK22 VSS72 VSS153 W26 F34 VSS230
AK19 VSS73 VSS154 U9 F31 VSS231
AK16 VSS74 VSS155 U8 F29 VSS232
AK13 VSS75 VSS156 U6 VSS233
AK10 VSS76 VSS157 U5
AK7 VSS77 VSS158 U3
AK4 VSS78 VSS159 U2
AJ25 VSS79 VSS160
VSS80

TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE

D D

Security Classification LC Future Center Secret Data Title


Issued Date 2012/07/01 Deciphered Date 2014/07/01 PROCESSOR(7/7) VSS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 10 of 59

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1 2 3 4 5
1 2 3 4 5

DDR_A_DQS#[0..7] 6

DDR_A_DQS[0..7] 6
+1.5V
DDR_A_D[0..63] 6

DDR_A_MA[0..15] 6

1
R2001
1K_0402_1%

+1.5V +1.5V

2
A JDIMM1 A
+VREF_DQ_DIMMA +VREF_DQ_DIMMA 1 2 Layout Note:
3 VREF_DQ VSS1 4 DDR_A_D4
VSS2 DQ4 Place near

C2001

2.2U_0603_6.3V6K

C2002

0.1U_0402_16V4Z
DDR_A_D0 5 6 DDR_A_D5
DQ0 DQ5

1
1 1 DDR_A_D1 7 8 JDIMM1
R2003 9 DQ1 VSS3 10 DDR_A_DQS#0
1K_0402_1% 11 VSS4 DQS#0 12 DDR_A_DQS0
13 DM0 DQS0 14 +1.5V For RF
2 2 DDR_A_D2 15 VSS5 VSS6 16 DDR_A_D6

2
DDR_A_D3 17 DQ2 DQ6 18 DDR_A_D7
19 DQ3 DQ7 20

47P_0402_50V8J
2200P_0402_50V7K
VSS7 VSS8

C2003

0.1U_0402_10V6K

C2004

0.1U_0402_10V6K

C2005

0.1U_0402_10V6K

C2006

0.1U_0402_10V6K
DDR_A_D8 21 22 DDR_A_D12 1
DQ8 DQ12

1
DDR_A_D9 23 24 DDR_A_D13

RFC1

RFC2
DQ9 DQ13 1 1 1 1
25 26 @ @
DDR_A_DQS#1 27 VSS9 VSS10 28

2
DDR_A_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST# 2
DQS1 RESET# DDR3_DRAMRST# 12,6 2 2 2 2
31 32
DDR_A_D10 33 VSS11 VSS12 34 DDR_A_D14
All VREF traces should 35 DQ10 DQ14 36
DDR_A_D11 DDR_A_D15
have 10 mil trace width 37 DQ11 DQ15 38
DDR_A_D16 39 VSS13 VSS14 40 DDR_A_D20
DDR_A_D17 41 DQ16 DQ20 42 DDR_A_D21
43 DQ17 DQ21 44
DDR_A_DQS#2 45 VSS15 VSS16 46 +1.5V
DDR_A_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_A_D22
DDR_A_D18 51 VSS18 DQ22 52 DDR_A_D23
DQ18 DQ23

C2007

10U_0603_6.3V6M

C2008

10U_0603_6.3V6M

C2009

10U_0603_6.3V6M

C2010

10U_0603_6.3V6M

C2011

10U_0603_6.3V6M

C2012

10U_0603_6.3V6M

C2013

10U_0603_6.3V6M

C2014

330U_D2_2V_Y
DDR_A_D19 53 54
55 DQ19 VSS19 56 DDR_A_D28
VSS20 DQ28 1 1 1 1 1 1 1 1
DDR_A_D24 57 58 DDR_A_D29
DDR_A_D25 59 DQ24 DQ29 60 +
61 DQ25 VSS21 62 DDR_A_DQS#3 @
63 VSS22 DQS#3 64 DDR_A_DQS3 2 2 2 2 2 2 2 @
65 DM3 DQS3 66 2
DDR_A_D26 67 VSS23 VSS24 68 DDR_A_D30
B
DDR_A_D27 69 DQ26 DQ30 70 DDR_A_D31 B
71 DQ27 DQ31 72
VSS25 VSS26

DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA
6 DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA 6
75 76
77 VDD1 VDD2 78 DDR_A_MA15
DDR_A_BS2 79 NC1 A15 80 DDR_A_MA14
6 DDR_A_BS2 BA2 A14
81 82
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
87 A9 A7 88
DDR_A_MA8 89 VDD5 VDD6 90 DDR_A_MA6
A8 A6 Layout Note:
DDR_A_MA5 91 92 DDR_A_MA4
93 A5 A4 94 Place near
DDR_A_MA3 95 VDD7 VDD8 96 DDR_A_MA2 JDIMM1.203,204
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
99 A1 A0 100
M_CLK_DDR0 101 VDD9 VDD10 102 M_CLK_DDR1
6 M_CLK_DDR0 CK0 CK1 M_CLK_DDR1 6
M_CLK_DDR#0 103 104 M_CLK_DDR#1
6 M_CLK_DDR#0 CK0# CK1# M_CLK_DDR#1 6 +1.5V
105 106
107 VDD11 VDD12 108 +0.75VS
DDR_A_MA10 DDR_A_BS1 DDR_A_BS1 6 For RF
DDR_A_BS0 109 A10/AP BA1 110 DDR_A_RAS#
6 DDR_A_BS0 BA0 RAS# DDR_A_RAS# 6
111 112
VDD13 VDD14

1
DDR_A_WE# 113 114 DDR_CS0_DIMMA#
6 DDR_A_WE# DDR_CS0_DIMMA# 6

47P_0402_50V8J
2200P_0402_50V7K
WE# S0#

C2017

1U_0402_6.3V6K

C2018

1U_0402_6.3V6K

C2019

1U_0402_6.3V6K

C2020

1U_0402_6.3V6K
6 DDR_A_CAS# DDR_A_CAS# 115 116 M_ODT0 M_ODT0 6 R2004 1
CAS# ODT0

1
117 118 1K_0402_1%

RFC3

RFC4
VDD15 VDD16 1 1 1 1
DDR_A_MA13 119 120 M_ODT1 M_ODT1 6 @ @
DDR_CS1_DIMMA# 121 A13 ODT1 122
6 DDR_CS1_DIMMA#

2
123 S1# NC2 124 2
125 VDD17 VDD18 126 +VREF_CA 2 2 2 2
127 NCTEST VREF_CA 128
VSS27 VSS28

C2015

2.2U_0603_6.3V6K

C2016

0.1U_0402_16V4Z
DDR_A_D32 129 130 DDR_A_D36
DDR_A_D33 131 DQ32 DQ36 132 DDR_A_D37
C 1 1 C
DQ33 DQ37

1
133 134
DDR_A_DQS#4 135 VSS29 VSS30 136 R2005
DDR_A_DQS4 137 DQS#4 DM4 138 1K_0402_1%
139 DQS4 VSS31 140 DDR_A_D38 2 2
DDR_A_D34 141 VSS32 DQ38 142 DDR_A_D39

2
DDR_A_D35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_A_D44
DDR_A_D40 147 VSS34 DQ44 148 DDR_A_D45
DDR_A_D41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_A_DQS#5
153 VSS36 DQS#5 154 DDR_A_DQS5
155 DM5 DQS5 156
DDR_A_D42 157 VSS37 VSS38 158 DDR_A_D46
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47
161 DQ43 DQ47 162
DDR_A_D48 163 VSS39 VSS40 164 DDR_A_D52
DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D53
167 DQ49 DQ53 168
DDR_A_DQS#6 169 VSS41 VSS42 170
DDR_A_DQS6 171 DQS#6 DM6 172
173 DQS6 VSS43 174 DDR_A_D54
DDR_A_D50 175 VSS44 DQ54 176 DDR_A_D55
DDR_A_D51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_A_D60
DDR_A_D56 181 VSS46 DQ60 182 DDR_A_D61
DDR_A_D57 183 DQ56 DQ61 184
185 DQ57 VSS47 186 DDR_A_DQS#7
187 VSS48 DQS#7 188 DDR_A_DQS7
189 DM7 DQS7 190
DDR_A_D58 191 VSS49 VSS50 192 DDR_A_D62
DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63
195 DQ59 DQ63 196
197 VSS51 VSS52 198
199 SA0 EVENT# 200 SMB_DATA_S3
D +3VS VDDSPD SDA SMB_DATA_S3 12,14,38,39 D
201 202 SMB_CLK_S3
SA1 SCL SMB_CLK_S3 12,14,38,39
203 204
+0.75VS VTT1 VTT2 +0.75VS
C2021

0.1U_0402_16V4Z

C2046

0.1U_0402_16V4Z

C2022

2.2U_0603_6.3V6K

R2006

10K_0402_5%

R2007

10K_0402_5%

205 206
G1 G2
1

<Address: 00> 1 1 1
LCN_DAN06-K4806-0102
ME@
DIMM_A Reserve H:4.0mm 2 2 2
Title
Security Classification LC Future Center Secret Data
2

Issued Date 2012/07/01 Deciphered Date 2014/07/01 DDRIII DIMMA


@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 11 of 59

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1 2 3 4 5
1 2 3 4 5

+1.5V DDR_B_DQS#[0..7] 6

DDR_B_DQS[0..7] 6

1
DDR_B_D[0..63] 6
R2008
1K_0402_1%
DDR_B_MA[0..15] 6

2
+1.5V +1.5V
JDIMM2
A +VREF_DQ_DIMMB 1 2 A
+VREF_DQ_DIMMB VREF_DQ VSS1
3 4 DDR_B_D4
VSS2 DQ4

C2024

2.2U_0603_6.3V6K

C2023

0.1U_0402_16V4Z
DDR_B_D0 5 6 DDR_B_D5
DDR_B_D1 7 DQ0 DQ5 8
1 1 DQ1 VSS3

1
9 10 DDR_B_DQS#0 Layout Note:
R2010 11 VSS4 DQS#0 12 DDR_B_DQS0
1K_0402_1% 13 DM0 DQS0 14 Place near
2 2 DDR_B_D2 15 VSS5 VSS6 16 DDR_B_D6 JDIMM2
DDR_B_D3 17 DQ2 DQ6 18 DDR_B_D7

2
19 DQ3 DQ7 20
DDR_B_D8 21 VSS7 VSS8 22 DDR_B_D12
23 DQ8 DQ12 24 +1.5V
DDR_B_D9 DDR_B_D13 For RF
25 DQ9 DQ13 26
DDR_B_DQS#1 27 VSS9 VSS10 28
DDR_B_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST# DDR3_DRAMRST# 11,6

47P_0402_50V8J
2200P_0402_50V7K
DQS1 RESET#

C2025

0.1U_0402_10V6K

C2026

0.1U_0402_10V6K

C2027

0.1U_0402_10V6K

C2028

0.1U_0402_10V6K
31 32 1
VSS11 VSS12

1
DDR_B_D10 33 34 DDR_B_D14

RFC5

RFC6
DQ10 DQ14 1 1 1 1
DDR_B_D11 35 36 DDR_B_D15 @ @
37 DQ11 DQ15 38

2
DDR_B_D16 39 VSS13 VSS14 40 DDR_B_D20 2
All VREF traces should DDR_B_D17 41 DQ16 DQ20 42 DDR_B_D21 2 2 2 2
have 10 mil trace width 43 DQ17 DQ21 44
DDR_B_DQS#2 45 VSS15 VSS16 46
DDR_B_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_B_D22
DDR_B_D18 51 VSS18 DQ22 52 DDR_B_D23
DDR_B_D19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_B_D28 +1.5V
DDR_B_D24 57 VSS20 DQ28 58 DDR_B_D29
DDR_B_D25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_B_DQS#3
VSS22 DQS#3

C2029

10U_0603_6.3V6M

C2030

10U_0603_6.3V6M

C2031

10U_0603_6.3V6M

C2032

10U_0603_6.3V6M

C2033

10U_0603_6.3V6M

C2034

10U_0603_6.3V6M

C2035

10U_0603_6.3V6M

C2036

330U_D2_2V_Y
63 64 DDR_B_DQS3
65 DM3 DQS3 66
VSS23 VSS24 1 1 1 1 1 1 1 1
DDR_B_D26 67 68 DDR_B_D30
DDR_B_D27 69 DQ26 DQ30 70 DDR_B_D31 +
B
71 DQ27 DQ31 72 @ B
VSS25 VSS26 2 2 2 2 2 2 2 @
2

6 DDR_CKE2_DIMMB DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB DDR_CKE3_DIMMB 6


75 CKE0 CKE1 76
77 VDD1 VDD2 78 DDR_B_MA15
DDR_B_BS2 79 NC1 A15 80 DDR_B_MA14
6 DDR_B_BS2 BA2 A14
81 82
DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
DDR_B_MA8 89 VDD5 VDD6 90 DDR_B_MA6
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
VDD7 VDD8 Layout Note:
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0 Place near
99 A1 A0 100 JDIMM2.203,204
M_CLK_DDR2 101 VDD9 VDD10 102 M_CLK_DDR3
6 M_CLK_DDR2 CK0 CK1 M_CLK_DDR3 6
6 M_CLK_DDR#2 M_CLK_DDR#2 103 104 M_CLK_DDR#3 M_CLK_DDR#3 6
105 CK0# CK1# 106 +1.5V
DDR_B_MA10 107 VDD11 VDD12 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 6
6 DDR_B_BS0 DDR_B_BS0 109 110 DDR_B_RAS# DDR_B_RAS# 6
BA0 RAS#

1
111 112
113 VDD13 VDD14 114 +0.75VS
6 DDR_B_WE# DDR_B_WE#
WE# S0#
DDR_CS2_DIMMB# DDR_CS2_DIMMB# 6 R2011 For RF
DDR_B_CAS# 115 116 M_ODT2 1K_0402_1%
6 DDR_B_CAS# CAS# ODT0 M_ODT2 6
117 118
DDR_B_MA13 119 VDD15 VDD16 120 M_ODT3 M_ODT3 6

47P_0402_50V8J
2200P_0402_50V7K
2
A13 ODT1

C2039

1U_0402_6.3V6K

C2040

1U_0402_6.3V6K

C2041

1U_0402_6.3V6K

C2042

1U_0402_6.3V6K

C2045

1U_0402_6.3V6K
6 DDR_CS3_DIMMB# DDR_CS3_DIMMB# 121 122 1
S1# NC2

1
123 124

RFC7

RFC8
VDD17 VDD18 1 1 1 1 1
125 126 +VREF_CB @ @ @
127 NCTEST VREF_CA 128

2
VSS27 VSS28 2

C2037

2.2U_0603_6.3V6K

C2038

0.1U_0402_16V4Z
DDR_B_D32 129 130 DDR_B_D36
DDR_B_D33 131 DQ32 DQ36 132 DDR_B_D37 2 2 2 2 2
DQ33 DQ37 1 1

1
C 133 134 C
DDR_B_DQS#4 135 VSS29 VSS30 136 R2012
DDR_B_DQS4 137 DQS#4 DM4 138 1K_0402_1%
139 DQS4 VSS31 140 DDR_B_D38 2 2
DDR_B_D34 141 VSS32 DQ38 142 DDR_B_D39

2
DDR_B_D35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_B_D44
DDR_B_D40 147 VSS34 DQ44 148 DDR_B_D45
DDR_B_D41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_B_DQS#5
153 VSS36 DQS#5 154 DDR_B_DQS5
155 DM5 DQS5 156
DDR_B_D42 157 VSS37 VSS38 158 DDR_B_D46
DDR_B_D43 159 DQ42 DQ46 160 DDR_B_D47
161 DQ43 DQ47 162
DDR_B_D48 163 VSS39 VSS40 164 DDR_B_D52
DDR_B_D49 165 DQ48 DQ52 166 DDR_B_D53
167 DQ49 DQ53 168
DDR_B_DQS#6 169 VSS41 VSS42 170
DDR_B_DQS6 171 DQS#6 DM6 172
+3VS +3VS 173 DQS6 VSS43 174 DDR_B_D54
DDR_B_D50 175 VSS44 DQ54 176 DDR_B_D55
DDR_B_D51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_B_D60
VSS46 DQ60
C2043

0.1U_0402_16V4Z

C2044

2.2U_0603_6.3V6K

DDR_B_D56 181 182 DDR_B_D61


DQ56 DQ61
1

1 1 DDR_B_D57 183 184


R2013 185 DQ57 VSS47 186 DDR_B_DQS#7
10K_0402_5% 187 VSS48 DQS#7 188 DDR_B_DQS7
189 DM7 DQS7 190
2 2 DDR_B_D58 191 VSS49 VSS50 192 DDR_B_D62
2

DDR_B_D59 193 DQ58 DQ62 194 DDR_B_D63


195 DQ59 DQ63 196
197 VSS51 VSS52 198
199 SA0 EVENT# 200 SMB_DATA_S3
VDDSPD SDA SMB_DATA_S3 11,14,38,39
201 202 SMB_CLK_S3
D SA1 SCL SMB_CLK_S3 11,14,38,39 D
+0.75VS 203 204 +0.75VS
VTT1 VTT2
1

205 206
R2014 G1 G2
10K_0402_5% LCN_DAN06-K4406-0102
ME@
2

Security Classification LC Future Center Secret Data Title


Issued Date 2012/07/01 Deciphered Date 2014/07/01 DDRIII DIMMB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 12 of 59

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1 2 3 4 5

PCH_RTCX1
W=20mils W=20mils
R87 1 2 10M_0402_5% PCH_RTCX2
+RTCVCC +RTCBATT
Y1
R106
1 2 1K_0402_5%
1 2
18P_0402_50V8J

32.768KHZ_12.5PF_CM31532768DZFT

1
1 1 1
C64 C179 CLRP1
C63 11/14 18P_0402_50V8J 1U_0402_6.3V6K SHORT PADS

2
2 2 2
CMOS
A A

SHORT PADS
JCMOS1
1 U3A

1
C62
+RTCVCC 1U_0402_6.3V6K PCH_RTCX1 A20 P+ C38 LPC_AD0
RTCX1 FWH0 / LAD0 LPC_AD0 38,40,41
@ P+ A38 LPC_AD1
LPC_AD1 38,40,41

2
2 FWH1 / LAD1

LPC
PCH_RTCX2 C20 P+ B37 LPC_AD2
+RTCVCC RTCX2 FWH2 / LAD2 LPC_AD2 38,40,41
P+ C37 LPC_AD3
FWH3 / LAD3 LPC_AD3 38,40,41
R88 1 2 20K_0402_5% PCH_RTCRST# D20
R90 1 2 1M_0402_5% SM_INTRUDER# RTCRST# D36 LPC_FRAME#
FWH4 / LFRAME# LPC_FRAME# 38,40,41
R89 1 2 20K_0402_5% PCH_SRTCRST# G22
R91 1 2 330K_0402_5% PCH_INTVRMEN SRTCRST# E36 +3VS
P+ LDRQ0#
SM_INTRUDER# K22 K36

RTC
1 INTRUDER# P+ LDRQ1# / GPIO23

1
SHORT PADS
JME1
C66 R92 1 2 10K_0402_5%
INTVRMEN
:Integrated
1U_0402_6.3V6K PCH_INTVRMEN C17 V5 SERIRQ
INTVRMEN SERIRQ SERIRQ 40,41
* LH: Integrated VRM enable @

2
2
VRM disable
AM3 SATA_DTX_C_PRX_N0
SATA0RXN SATA_DTX_C_PRX_N0 36
(INTVRMEN should always be pull high.) HDA_BIT_CLK N34 AM1 SATA_DTX_C_PRX_P0
HDA_BCLK SATA0RXP SATA_DTX_C_PRX_P0 36
AP7 SATA_PTX_C_DRX_N0 C67 1 2 0.01U_0402_16V7K SATA_PTX_DRX_N0 HDD

SATA 6G
SATA0TXN SATA_PTX_DRX_N0 36
HDA_SYNC L34 P- AP5 SATA_PTX_C_DRX_P0 C68 1 2 0.01U_0402_16V7K SATA_PTX_DRX_P0
HDA_SYNC SATA0TXP SATA_PTX_DRX_P0 36

ME HDA_SPKR T10 P- AM10 SATA_DTX_C_PRX_N1


+3VS 35 HDA_SPKR SPKR SATA1RXN SATA_DTX_C_PRX_N1 38
AM8 SATA_DTX_C_PRX_P1
SATA1RXP SATA_DTX_C_PRX_P1 38
HDA_RST# K34
HDA_RST# SATA1TXN
AP11 SATA_PTX_C_DRX_N1 C69 1 2 0.01U_0402_16V7K SATA_PTX_DRX_N1
SATA_PTX_DRX_N1 38 m-SATA
R93 1 @ 2 1K_0402_5% HDA_SPKR AP10 SATA_PTX_C_DRX_P1 C70 1 2 0.01U_0402_16V7K SATA_PTX_DRX_P1
SATA1TXP SATA_PTX_DRX_P1 38
HIGH= Enable ( No Reboot ) 35 HDA_SDIN0 HDA_SDIN0 E34 P- AD7 SATA_DTX_C_PRX_N2
HDA_SDIN0 SATA2RXN SATA_DTX_C_PRX_N2 36
LOW= Disable (Default) AD5 SATA_DTX_C_PRX_P2
* G34
HDA_SDIN1 P- SATA2RXP
SATA2TXN
AH5 SATA_PTX_C_DRX_N2 C71 1 2 0.01U_0402_16V7K SATA_PTX_DRX_N2
SATA_DTX_C_PRX_P2
SATA_PTX_DRX_N2 36
36
ODD
AH4 SATA_PTX_C_DRX_P2 C72 1 2 0.01U_0402_16V7K SATA_PTX_DRX_P2
SATA2TXP SATA_PTX_DRX_P2 36
C34 P-
HDA_SDIN2 AB8

IHDA
A34 SATA3RXN AB10
B HDA_SDIN3 P- SATA3RXP B
AF3
+3V_PCH SATA3TXN AF1
+3VS R94 1 2 0_0402_5% HDA_SDOUT A36 SATA3TXP
41 ME_FLASH HDA_SDO P-
R95 1 @ 2 1K_0402_5% HDA_SDOUT Y7

SATA
SATA4RXN Y5
R202 1 2 10K_0402_5% WLBT_OFF_5# WLBT_OFF_5# C36 SATA4RXP AD3
38 WLBT_OFF_5# HDA_DOCK_EN# / GPIO33 SATA4TXN AD1
R209 1 2 10K_0402_5% N32 SATA4TXP
9/27 +3V_PCH @ PCH_GPIO13
HDA_DOCK_RST# / GPIO13 Y3
HDA_SDO SATA5RXN Y1
SATA5RXP AB3
ME debug mode,this signal has a weak internal PD SATA5TXN
Low = Disabled (Default) R96 1 2 51_0402_5% PCH_JTAG_TCK J3 P- AB1
* High = Enabled [Flash Descriptor Security Overide]
JTAG_TCK SATA5TXP +1.05VS_PCH
PCH_JTAG_TMS H7 P+ Y11
JTAG_TMS SATAICOMPO

JTAG
PCH_JTAG_TDI K5 P+ Y10 SATA_COMP R97 1 2 37.4_0402_1% +1.05VS_VCC_SATA
JTAG_TDI SATAICOMPI
PCH_JTAG_TDO H1
JTAG_TDO AB12
+3V_PCH SATA3RCOMPO +1.05VS_SATA3
AB13 SATA3_COMP R98 1 2 49.9_0402_1%
R99 1 2 1K_0402_5% HDA_SYNC SATA3COMPI

This signal has a weak internal pull-down SPI_CLK_PCH_R T3 AH1 RBIAS_SATA3 R100 1 2 750_0402_1%
SPI_CLK SATA3RBIAS
SPI_SB_CS0# Y14
On Die PLL VR Select is supplied by SPI_CS0# +3VS
1.5V when sampled high SPI_SB_CS1# T1
* SPI_CS1#

SPI
P3 PCH_SATALED# R101 1 2 10K_0402_5%
1.8V when sampled low SATALED#
Prevent back drive issue.
Needs to be pulled High for Huron River platfrom SPI_SI V4 P- V14 PCH_GPIO21 R102 1 2 10K_0402_5%
SPI_MOSI SATA0GP / GPIO21
SPI_SO_R U3 P+ P+ P1 ODD_DET# R103 1 2 10K_0402_5%
SPI_MISO SATA1GP / GPIO19
ODD_DET# 36
C C
PANTHER-POINT_FCBGA989
R107
33_0402_5%
1 2 HDA_BIT_CLK +5VS
35 HDA_BITCLK_AUDIO

8MB+4MB SPI ROM FOR 5M ME(SBA)


2
G

R241
9/22
35 HDA_SYNC_AUDIO 1
33_0402_5%
2 HDA_SYNC_R 3 1 HDA_SYNC & Non-share ROM. +3VS_SPI

R110 1
@
2 0_0402_5%
+3VS +3VM
if not supply SBA function R110 mount , R112 @
S

Q8 if supply SBA function R110 @,R112 mount


1

R109 BSS138_NL_SOT23-3 R112 1 SBA@ 2 0_0402_5%


33_0402_5%
1 2 HDA_RST# R303
35 HDA_RST#_AUDIO
1M_0402_5% U6
U6 4M +3VS_SPI
SPI_SB_CS1# R336 1 2 0_0402_5% CS1# 1 8
2

R111 SPI_SO_R R343 1 2 33_0402_5% SPI_SO1 2 CS# VCC 7 SPI_HOLD#1


33_0402_5% SPI_WP#1 3 DO(IO1) HOLD#(IO3) 6 SPI_CLK1 R339 1 2 33_0402_5% SPI_CLK_PCH_R SPI_WP#1 R104 1 2 3.3K_0402_5%
1 2 HDA_SDOUT 4 WP#(IO2) CLK 5 SPI_SI1 R338 1 2 33_0402_5% SPI_SI
35 HDA_SDOUT_AUDIO GND DI(IO0) SPI_HOLD#1 R105 1 2 3.3K_0402_5%
W25Q16BVSSIG_SO8
SPI_WP# R334 1 2 3.3K_0402_5%
+3VS_SPI
C76 1 2 22P_0402_50V8J HDA_BITCLK_AUDIO SPI_HOLD# R335 1 2 3.3K_0402_5%
C191 1 2 0.1U_0402_16V4Z
C77 @1
@ 2 22P_0402_50V8J HDA_SDOUT_AUDIO SPI_CLK_PCH_R R119 1 @ 2 33_0402_5% C78 @1
@ 2 22P_0402_50V8J
U5
U5 8M
SPI_SB_CS0# R340 1 2 0_0402_5% CS# 1 8 Reserve for EMI please close to U3
SPI_SO_R R337 1 2 33_0402_5% SPI_SO_L 2 CS# VCC 7 SPI_HOLD# R342 33_0402_5%
SPI_WP# 3 DO HOLD# 6 SPI_CLK_PCH 1 2 SPI_CLK_PCH_R
4 WP# CLK 5 SPI_SI_R 1 2 SPI_SI SPI_CLK_PCH_R C84 1 2 22P_0402_50V8J
GND DI R341 33_0402_5%
+3V_PCH +3V_PCH +3V_PCH W25Q32BVSSIG_SO8 C85 1 2 22P_0402_50V8J
D 9/28 RF modify D
1

EON Reserve for RF please close to U5, U6


R120 @ R121 @ R122 @
200_0402_5% 200_0402_5% 200_0402_5% 8M:SA000046400 S IC FL 64M EN25Q64-104HIP SOP 8P
4M:SA00004LI00 S IC FL 32M EN25Q32B-104HIP SOP 8P
2

PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI


1

Security Classification LC Future Center Secret Data Title


R123 @ R124 @ R125 @
100_0402_1% 100_0402_1% 100_0402_1% PCH (1/9) SATA,HDA,SPI, LPC
Issued Date 2012/07/01 Deciphered Date 2014/07/01
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Saturday, November 03, 2012 Sheet 13 of 59

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+3V_PCH

PCH_SMBCLK R128 1 2 2.2K_0402_5%

PCH_SMBDATA R129 1 2 2.2K_0402_5%

U3B PCH_SML0CLK R130 1 2 2.2K_0402_5%

PCIE_PRX_DTX_N1 BG34 PCH_SML0DATA R131 1 2 2.2K_0402_5%


39 PCIE_PRX_DTX_N1 PERN1
PCIE_PRX_DTX_P1 BJ34 E12 PCH_GPIO11
39 PCIE_PRX_DTX_P1 PERP1 SMBALERT# / GPIO11
Card Reader C86 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N1 AV32 PCH_SML1CLK R126 1 2 2.2K_0402_5%
39 PCIE_PTX_C_DRX_N1 PETN1
C79 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P1 AU32 H14 PCH_SMBCLK
39 PCIE_PTX_C_DRX_P1 PETP1 SMBCLK PCH_SML1DATA R132 1 2 2.2K_0402_5%
PCIE_PRX_DTX_N2 BE34 C9 PCH_SMBDATA
38 PCIE_PRX_DTX_N2 PERN2 SMBDATA
PCIE_PRX_DTX_P2 BF34 PCH_HOT# R133 1 2 10K_0402_5%
38 PCIE_PRX_DTX_P2 PERP2
Wireless LAN C82 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N2 BB32
38 PCIE_PTX_C_DRX_N2 PETN2
A C83 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P2 AY32 PCH_GPIO11 R135 1 2 10K_0402_5% A
38 PCIE_PTX_C_DRX_P2 PETP2

SMBUS
A12 DRAMRST_CNTRL_PCH
SML0ALERT# / GPIO60 DRAMRST_CNTRL_PCH 6
BG36 DRAMRST_CNTRL_PCH R127 1 2 1K_0402_5%
BJ36 PERN3 C8 PCH_SML0CLK
AV34 PERP3 SML0CLK PCH_GPIO47 R138 1 2 10K_0402_5%
AU34 PETN3 G12 PCH_SML0DATA
PETP3 SML0DATA
PCIE_PRX_DTX_N4 BF36
42 PCIE_PRX_DTX_N4 PERN4
PCIE_PRX_DTX_P4 BE36
42 PCIE_PRX_DTX_P4 PERP4
PCIE LAN C80 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N4 AY34 C13 PCH_HOT#
42 PCIE_PTX_C_DRX_N4 PETN4 SML1ALERT# / PCHHOT# / GPIO74 +3VS
C81 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P4 BB34
42 PCIE_PTX_C_DRX_P4 PETP4 E14 PCH_SML1CLK
BG37 SML1CLK / GPIO58

PCI-E*
BH37 PERN5 M16 PCH_SML1DATA R136 2.2K_0402_5%
PERP5 SML1DATA / GPIO75

2
AY36 1 2 +3VS
BB36 PETN5
PETP5 PCH_SMBDATA 6 1 SMB_DATA_S3
SMB_DATA_S3 11,12,38,39
BJ38
BG38 PERN6 Q9A 2N7002KDWH_SOT363-6
AU36 PERP6 M7
P+/P-

Controller
AV36 PETN6 CL_CLK1 R137 2.2K_0402_5%
DDR, WALN, WWAN
PETP6

5
1 2 +3VS

Link
BG40 P+/P- T11
BJ40 PERN7 CL_DATA1 PCH_SMBCLK 3 4 SMB_CLK_S3
PERP7 SMB_CLK_S3 11,12,38,39
AY40
BB40 PETN7 P10 Q9B 2N7002KDWH_SOT363-6
PETP7 CL_RST1#
BE38
BC38 PERN8
AW38 PERP8
AY38 PETN8 +3VS
PETP8 DIS@
M10 PCH_GPIO47 R139 1 2 0_0402_5% Pull up at EC side.
PEG_A_CLKRQ# / GPIO47 GPU_CLKREQA 22
R147 1 2 0_0402_5% CLK_CARD# Y40 R140 1 @ 2 0_0402_5%
39 CLK_PCIE_CARD# CLKOUT_PCIE0N

2
Card Reader R149 1 2 0_0402_5% CLK_CARD Y39
B 39 CLK_PCIE_CARD CLKOUT_PCIE0P B
AB37 CLK_PCIE_VGA#_R DIS@ R144 1 2 0_0402_5%
CLKOUT_PEG_A_N CLK_PCIE_VGA# 22
CARD_CLKREQ# J2 AB38 CLK_PCIE_VGA_R DIS@ R151 1 2 0_0402_5% PCH_SML1DATA 6 1 EC_SMB_DA2

CLOCKS
39 CARD_CLKREQ# PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P CLK_PCIE_VGA 22 EC_SMB_DA2 22,39,41
Q10A 2N7002KDWH_SOT363-6
R141 1 2 0_0402_5% CLK_MINI1# AB49 AV22 CLK_CPU_DMI# EC, VGA, Theraml
38 CLK_PCIE_WLAN1# CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI# 5

5
R142 1 2 0_0402_5% CLK_MINI1 AB47 AU22 CLK_CPU_DMI
38 CLK_PCIE_WLAN1 CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI 5
Wireless LAN
38 WLAN_CLKREQ1# WLAN_CLKREQ1# M1 PCH_SML1CLK 3 4EC_SMB_CK2 EC_SMB_CK2 22,39,41
PCIECLKRQ1# / GPIO18 AM12
CLKOUT_DP_N AM13 Q10B 2N7002KDWH_SOT363-6
AA48 CLKOUT_DP_P
AA47 CLKOUT_PCIE2N
CLKOUT_PCIE2P BF18 CLK_BUF_CPU_DMI# R148 1 2 10K_0402_5%
PCH_GPIO20 V10 CLKIN_DMI_N BE18 CLK_BUF_CPU_DMI R150 1 2 10K_0402_5%
PCIECLKRQ2# / GPIO20 CLKIN_DMI_P

R145 1 2 0_0402_5% CLK_LAN# Y37 BJ30 CLKIN_DMI2# R152 1 2 10K_0402_5%


42 CLK_PCIE_LAN# CLKOUT_PCIE3N CLKIN_GND1_N
PCIE LAN R146 1 2 0_0402_5% CLK_LAN Y36 BG30 CLKIN_DMI2 R153 1 2 10K_0402_5%
42 CLK_PCIE_LAN CLKOUT_PCIE3P CLKIN_GND1_P R168 33_0402_5% C89 22P_0402_50V8J
42 LAN_CLKREQ# LAN_CLKREQ# A8 CLK_BUF_ICH_14M 1 @ 2 @ 1 2
PCIECLKRQ3# / GPIO25 G24 CLK_BUF_DREF_96M# R154 1 2 10K_0402_5%
CLKIN_DOT_96N E24 CLK_BUF_DREF_96M R155 1 2 10K_0402_5%
Y43 CLKIN_DOT_96P
+3VS Y45 CLKOUT_PCIE4N
CLKOUT_PCIE4P AK7 CLK_BUF_PCIE_SATA# R156 1 2 10K_0402_5%
R170 1 2 10K_0402_5% WLAN_CLKREQ1# PCH_GPIO26 L12 CLKIN_SATA_N AK5 CLK_BUF_PCIE_SATA R157 1 2 10K_0402_5%
PCIECLKRQ4# / GPIO26 CLKIN_SATA_P
R162 1 2 10K_0402_5% PCH_GPIO20 Reserve for EMI
V45 K45 CLK_BUF_ICH_14M R158 1 2 10K_0402_5%
V46 CLKOUT_PCIE5N REFCLK14IN
CLKOUT_PCIE5P
+3V_PCH PCH_GPIO44 L14 P+ H45 CLK_PCI_LPBACK XTAL25_IN
PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LPBACK 17
R177 1 2 10K_0402_5% CARD_CLKREQ# XTAL25_OUT R161 1 2 1M_0402_5%
C AB42 V47 XTAL25_IN C
R175 1 2 10K_0402_5% LAN_CLKREQ# AB40 CLKOUT_PEG_B_N XTAL25_IN V49 XTAL25_OUT Y2
CLKOUT_PEG_B_P XTAL25_OUT +1.05VS_PCH 25MHZ 12PF 20PPM X3G025000DC1H
R181 1 2 10K_0402_5% PCH_GPIO26 PCH_GPIO56 E6
PEG_B_CLKRQ# / GPIO56 +1.05VS_VCCDIFFCLKN 1 3
R182 1 2 10K_0402_5% PCH_GPIO44 Y47 XCLK_RCOMP R160 1 2 90.9_0402_1% 1 3
V40 XCLK_RCOMP GND GND
CLKOUT_PCIE6N 1 1
R159 1 2 10K_0402_5% PCH_GPIO56 V42
CLKOUT_PCIE6P C87 2 4 C88
R183 1 2 10K_0402_5% PCH_GPIO45 PCH_GPIO45 T13 15P_0402_50V8J 15P_0402_50V8J
PCIECLKRQ6# / GPIO45 2 2
11/14
R184 1 @ 2 10K_0402_5% ON_ODD_DET V38 P- K43
V37 CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64
FLEX CLOCKS

CLKOUT_PCIE7P F47
P- CLKOUTFLEX1 / GPIO65
ON_ODD_DET K12 P+
36 ON_ODD_DET PCIECLKRQ7# / GPIO46
P- H47 LAN_25M R163 1 @ 2 22_0402_5%
CLKOUTFLEX2 / GPIO66 PCH_LAN_25M 42
R164 1 2 0_0402_5% CLK_BCLK_ITP# AK14
5 CLK_XDP_CLK# CLKOUT_ITPXDP_N +3VS
R165 1 2 0_0402_5% CLK_BCLK_ITP AK13 P- K49 PCH_GPIO67
5 CLK_XDP_CLK CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67 PCH_GPIO67 18
+3VS

1
PANTHER-POINT_FCBGA989
R172
10K_0402_5%
@
U8

2
1 8
2 NC VCC 7
NC WP
ROM_WP 1
PLT_RST# 3 6 SMB_CLK_S3 C91
17,22,38,39,40,41,42,5 PLT_RST# PROT# SCL
4 5 SMB_DATA_S3 0.1U_0402_16V4Z
+3VS GND SDA
Touch@ PCA24S08D_SO8 2
EEPROM SA00004MK00
R143 2.2K_0402_5% EEPROM SA00004ML00
2

1 2 +3VS
D D
PCH_SML0DATA 6 1 SMB_DATA_TPanel
SMB_DATA_TPanel 40
Q2417A 2N7002KDWH_SOT363-6
Touch@
Touch@

R167 2.2K_0402_5%
Touch Panel
5

1 2 +3VS
Security Classification LC Future Center Secret Data Title
PCH_SML0CLK 3 4 SMB_CLK_TPanel SMB_CLK_TPanel 40
Q2417B 2N7002KDWH_SOT363-6
Issued Date 2012/07/01 Deciphered Date 2014/07/01 PCH (2/9) PCIE, SMBUS, CLK
Touch@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Saturday, November 03, 2012 Sheet 14 of 59

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U3C

4 DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0 FDI_CTX_PRX_N0 4


DMI_CTX_PRX_N1 BE20 DMI0RXN FDI_RXN0 AY14 FDI_CTX_PRX_N1
4 DMI_CTX_PRX_N1 DMI1RXN FDI_RXN1 FDI_CTX_PRX_N1 4
A DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2 A
4 DMI_CTX_PRX_N2 DMI2RXN FDI_RXN2 FDI_CTX_PRX_N2 4
4 DMI_CTX_PRX_N3 DMI_CTX_PRX_N3 BG20 BH13 FDI_CTX_PRX_N3 FDI_CTX_PRX_N3 4
DMI3RXN FDI_RXN3 BC12 FDI_CTX_PRX_N4
FDI_RXN4 FDI_CTX_PRX_N4 4
4 DMI_CTX_PRX_P0 DMI_CTX_PRX_P0 BE24 BJ12 FDI_CTX_PRX_N5 FDI_CTX_PRX_N5 4
DMI_CTX_PRX_P1 BC20 DMI0RXP FDI_RXN5 BG10 FDI_CTX_PRX_N6
4 DMI_CTX_PRX_P1 DMI1RXP FDI_RXN6 FDI_CTX_PRX_N6 4
DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7
4 DMI_CTX_PRX_P2 DMI2RXP FDI_RXN7 FDI_CTX_PRX_N7 4
4 DMI_CTX_PRX_P3 DMI_CTX_PRX_P3 BJ20
DMI3RXP BG14 FDI_CTX_PRX_P0
FDI_RXP0 FDI_CTX_PRX_P0 4
DMI_CRX_PTX_N0 AW24 BB14 FDI_CTX_PRX_P1 FDI_CTX_PRX_P1 4
4 DMI_CRX_PTX_N0 DMI0TXN FDI_RXP1
DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2 FDI_CTX_PRX_P2 4
4 DMI_CRX_PTX_N1 DMI1TXN FDI_RXP2
DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3
4 DMI_CRX_PTX_N2 DMI2TXN FDI_RXP3 FDI_CTX_PRX_P3 4
DMI_CRX_PTX_N3 AV18 BE12 FDI_CTX_PRX_P4 FDI_CTX_PRX_P4 4
4 DMI_CRX_PTX_N3 DMI3TXN FDI_RXP4

DMI
FDI
BG12 FDI_CTX_PRX_P5 FDI_CTX_PRX_P5 4
DMI_CRX_PTX_P0 AY24 FDI_RXP5 BJ10 FDI_CTX_PRX_P6
4 DMI_CRX_PTX_P0 DMI0TXP FDI_RXP6 FDI_CTX_PRX_P6 4
DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7 FDI_CTX_PRX_P7 4
4 DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7
DMI_CRX_PTX_P2 AY18
4 DMI_CRX_PTX_P2 DMI2TXP
DMI_CRX_PTX_P3 AU18
4 DMI_CRX_PTX_P3 DMI3TXP AW16 FDI_INT
FDI_INT FDI_INT 4
+1.05VS_PCH
BJ24 AV12 FDI_FSYNC0
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 4
+1.05VS_VCC_EXP
R186 1 2 49.9_0402_1% DMI_IRCOMP BG25 BC10 FDI_FSYNC1
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 4
R188 1 2 750_0402_1% RBIAS_CPY BH21 AV14 FDI_LSYNC0
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 4
4mil width and place BB10 FDI_LSYNC1
FDI_LSYNC1 FDI_LSYNC1 4
within 500mil of the PCH
+RTCVCC
A18 DSWODVREN
DSWVRMEN
DSWODVREN R185 1 2 330K_0402_5%

System Power Management


T8 SUSACK#_R C12 P+ E22 PCH_DPWROK_R R189 1 2 0_0402_5% PCH_RSMRST#_R
SUSACK# DPWROK R187 1 @ 2 330K_0402_5%

::
B B
R193 1 2 0_0402_5% XDP_DBRESET#_R K3 B9 WAKE# R914 1 2 0_0402_5%
PCIE_WAKE# 42 DSWODVREN - On Die DSW VR Enable
5 XDP_DBRESET# SYS_RESET# WAKE#
* H Enable
L Disable
SYS_PWROK P12 N3 PM_CLKRUN#
SYS_PWROK CLKRUN# / GPIO32 PM_CLKRUN# 40

41 PCH_PWROK PCH_PWROK R197 1 2 0_0402_5% PCH_POK_R L22 G8


R198 1 @ 2 0_0402_5% PWROK SUS_STAT# / GPIO61

R200 1 2 0_0402_5% APWROK L10 N14 SUSCLK +3V_PCH


41 PCH_APWROK APWROK SUSCLK / GPIO62 SUSCLK 41

T11 WAKE# R192 1 2 10K_0402_5%


PM_DRAM_PWRGD B13 D10 PM_SLP_S5#
5 PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# 41
PCH_GPIO29 R195 1 @ 2 10K_0402_5%
T12 +3VS
R203 1 2 0_0402_5% PCH_RSMRST#_R C21 H4 PM_SLP_S4#
41 EC_RSMRST# RSMRST# SLP_S4# PM_SLP_S4# 41

T13 PM_CLKRUN# R196 1 2 8.2K_0402_5%


SUSWARN# K16 F4 PM_SLP_S3#
SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# PM_SLP_S3# 41
R199 1 @ 2 10K_0402_5%

E20 P+ G10 PCH_SLPA#


41,5 PBTN_OUT# PWRBTN# SLP_A# PCH_SLPA# 41
EC team suggestion
T14 South Bridge side must have
D3 1 2 AC_PRESENT_R H20 P- G16 PM_SLP_SUS#_R pull-low 10K on this pin(GPIO32)
41,42,47 ACIN ACPRESENT / GPIO31 SLP_SUS#
RB751V-40_SOD323-2
Use CLKRUN# Requires a 8.2- k weak
T15 pull-up resistor to Vcc3_3S
PCH_GPIO72 E10 AP14
BATLOW# / GPIO72 P+
H_PM_SYNC
PMSYNCH H_PM_SYNC 5

RI# A10 K14 PCH_GPIO29


RI# SLP_LAN# / GPIO29
Can be left NC when
PANTHER-POINT_FCBGA989 IAMT is not support on
C the platfrom C

+3VS +3VS

R204 1 @ 2 200_0402_5% PM_DRAM_PWRGD U9

5
VCC
PCH_PWROK 1
+3V_PCH IN1 4 SYS_PWROK
OUT SYS_PWROK 5
2

GND
53 VGATE IN2
R305 1 2 200_0402_5% PM_DRAM_PWRGD

1
3

R205 1 2 10K_0402_5% SUSWARN# MC74VHC1G08DFT2G_SC70-5 R211


100K_0402_5%

2
D D
R207 1 2 10K_0402_5% PCH_GPIO72

R208 1 2 10K_0402_5% RI#

R210 1 2 10K_0402_5% PCH_RSMRST#_R

+3VALW Security Classification LC Future Center Secret Data Title


Issued Date 2012/07/01 Deciphered Date 2014/07/01 PCH (3/9) DMI,FDI,PM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
R206 1 2 200K_0402_5% AC_PRESENT_R Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Saturday, November 03, 2012 Sheet 15 of 59

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A A

100K_0402_5% 1 2 R253
U3D
R252 1 2 0_0402_5% PCH_ENBKL J47 P- AP43
41 ENBKL L_BKLTEN SDVO_TVCLKINN
M45 P- AP45
32 PCH_ENVDD L_VDD_EN SDVO_TVCLKINP
P45 P- AM42
32 PCH_PWM L_BKLTCTL SDVO_STALLN
P- AM40
T40 SDVO_STALLP
32 EDID_CLK L_DDC_CLK
K47 P- P- AP39
32 EDID_DATA L_DDC_DATA SDVO_INTN
P- AP40
2.2K_0402_5% 1 2 R212 CTRL_CLK T45 SDVO_INTP
+3VS L_CTRL_CLK
2.2K_0402_5% 1 2 R213 CTRL_DATA P39
L_CTRL_DATA
2.37K_0402_1% 1 2 R215 LVDS_IBG AF37 P38
LVD_IBG SDVO_CTRLCLK HDMICLK_NB 34
AF36 P- SDVO_CTRLDATA M39
LVD_VBG HDMIDAT_NB 34 +3VS
LVD_VREF AE48
0_0402_5% 1 2 R217 AE47 LVD_VREFH AT49
B LVD_VREFL DDPB_AUXN AT47 B
DDPB_AUXP AT40
DDPB_HPD PCH_DPB_HPD 34
AK39
32 LVDS_ACLK# LVDSA_CLK#

LVDS
AK40 AV42
32 LVDS_ACLK LVDSA_CLK DDPB_0N PCH_DPB_N0 34

1
AV40 HDMI D2
DDPB_0P PCH_DPB_P0 34
AN48 AV45 R2156 R2157
32 LVDS_A0# LVDSA_DATA#0 DDPB_1N PCH_DPB_N1 34
AM47 AV46 HDMI D1 2.2K_0402_5% 2.2K_0402_5%
32 LVDS_A1# LVDSA_DATA#1 DDPB_1P PCH_DPB_P1 34

Digital Display Interface


AK47 AU48
32 LVDS_A2# LVDSA_DATA#2 DDPB_2N PCH_DPB_N2 34
AJ48 AU47 HDMI D0
PCH_DPB_P2 34

2
LVDSA_DATA#3 DDPB_2P AV47
DDPB_3N PCH_DPB_N3 34
AN47 AV49 HDMI CLK DDPC_CTRLCLK
32 LVDS_A0 LVDSA_DATA0 DDPB_3P PCH_DPB_P3 34
AM49
32 LVDS_A1 LVDSA_DATA1
AK49
32 LVDS_A2 LVDSA_DATA2
AJ47 P46 DDPC_CTRLCLK DDPC_CTRLDATA
LVDSA_DATA3 DDPC_CTRLCLK P42
P- DDPC_CTRLDATA DDPC_CTRLDATA

AF40
32 LVDS_BCLK# LVDSB_CLK#
AF39 AP47
32 LVDS_BCLK LVDSB_CLK DDPC_AUXN DISP_AUXN_R 42
AP49
DDPC_AUXP DISP_AUXP_R 42
AH45 AT38 DISP_HPD 42
32 LVDS_B0# LVDSB_DATA#0 DDPC_HPD
AH47
32 LVDS_B1# LVDSB_DATA#1
AF49 AY47
32 LVDS_B2# LVDSB_DATA#2 DDPC_0N DISP_A0N_L 42
AF45 AY49
LVDSB_DATA#3 DDPC_0P DISP_A0P_L 42
AY43
DDPC_1N DISP_A1N_L 42
AH43 AY45
32 LVDS_B0 LVDSB_DATA0 DDPC_1P DISP_A1P_L 42
AH49 BA47
32 LVDS_B1 LVDSB_DATA1 DDPC_2N
AF47 BA48
32 LVDS_B2 LVDSB_DATA2 DDPC_2P
AF43 BB47
LVDSB_DATA3 DDPC_3N BB49
DDPC_3P

+3VS DAC_BLU N48 M43


33 DAC_BLU CRT_BLUE DDPD_CTRLCLK
DAC_GRN P49 P- DDPD_CTRLDATA M36
33 DAC_GRN CRT_GREEN
R218 1 2 2.2K_0402_5% CRT_DDC_CLK DAC_RED T49
33 DAC_RED CRT_RED
C C
R219 1 2 2.2K_0402_5% CRT_DDC_DATA AT45
DDPD_AUXN

CRT
CRT_DDC_CLK T39 AT43
33 CRT_DDC_CLK CRT_DDC_CLK DDPD_AUXP
CRT_DDC_DATA M40 BH41
33 CRT_DDC_DATA CRT_DDC_DATA DDPD_HPD
R220 1 2 150_0402_1% DAC_BLU BB43
CRT_HSYNC M47 DDPD_0N BB45
33 CRT_HSYNC CRT_HSYNC DDPD_0P
R221 1 2 150_0402_1% DAC_GRN CRT_VSYNC M49 BF44
33 CRT_VSYNC CRT_VSYNC DDPD_1N BE44
R222 1 2 150_0402_1% DAC_RED DDPD_1P BF42
1.05K_0402_0.5%
1.05K_0402_0.5%1 2 R223 CRT_IREF T43 DDPD_2N BE42
T42 DAC_IREF DDPD_2P BJ42
CRT_IRTN DDPD_3N BG42
DDPD_3P
PANTHER-POINT_FCBGA989

D D

Security Classification LC Future Center Secret Data Title


Issued Date 2012/07/01 Deciphered Date 2014/07/01 PCH (4/9) LVDS,CRT,DP,HDMI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Saturday, November 03, 2012 Sheet 16 of 59

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+3VS
U3E
R225 AY7
1 8 PCI_PIRQB# RSVD1 AV7
2 7 PCI_PIRQC# BG26 RSVD2 AU3
3 6 PCI_PIRQD# BJ26 TP1 RSVD3 BG4
4 5 PCI_PIRQA# BH25 TP2 RSVD4
BJ16 TP3 AT10
8.2K_8P4R_5% BG16 TP4 RSVD5 BC8
AH38 TP5 RSVD6
R228 AH37 TP6 AU2
1 8 PCH_GPIO52 AK43 TP7 RSVD7 AT4
2 7 PCH_GPIO5 AK45 TP8 RSVD8 AT3
3 6 PCH_GPIO51 C18 TP9 RSVD9 AT1
4 5 PCH_GPIO53 N30 TP10 RSVD10 AY3
TP11 RSVD11
A
8.2K_8P4R_5%
USB3.0 H3
AH12 TP12 RSVD12
AT5
AV3
A

AM4 TP13 RSVD13 AV1


R227 AM5 TP14 RSVD14 BB1
Port1 USB 3.0 TP15 RSVD15
1 8 ODD_DA# Y13 BA3
2 7 K24 TP16 RSVD16 BB5
3 6 PCH_GPIO2 L24 TP17 RSVD17 BB3
Port2 TP18 RSVD18
4 5 AB46 BB7
AB45 TP19 RSVD19 BE8
TP20 RSVD20

RSVD
8.2K_8P4R_5% Port3 USB 3.0 BD4
RSVD21 BF6
R230 1 2 8.2K_0402_5% PCH_GPIO55 RSVD22
Port4 USB 3.0+DP B21 AV5
R231 1 2 8.2K_0402_5% PCH_GPIO50 M20 TP21 RSVD23 AV10
AY16 TP22 RSVD24
R246 1 2 8.2K_0402_5% PCH_GPIO54 BG46 TP23 AT8
TP24 RSVD25
R357 1 2 8.2K_0402_5% PCH_GPIO4 AY5
RSVD26 BA2
BE28 RSVD27
37 USB3_RX0_N USB3Rn1
BC30 AT12
BE32 USB3Rn2 RSVD28 BF3
37 USB3_RX2_N USB3Rn3 RSVD29
BJ32
42 USB3_RX3_N USB3Rn4
R358 1 @ 2 8.2K_0402_5% PCH_GPIO4 BC28 PCH HM65 config not support USB port 6 & 7.
37 USB3_RX0_P USB3Rp1
BE30
R244 1 @ 2 8.2K_0402_5% PCH_GPIO54 BF32 USB3Rp2
37 USB3_RX2_P USB3Rp3
BG32 C24 USB20_N0
42 USB3_RX3_P USB3Rp4 USBP0N USB20_N0 37
R232 1 @ 2 8.2K_0402_5% PCH_GPIO50 37 USB3_TX0_N AV26 A24 USB20_P0 USB 3.0
USB3Tn1 USBP0P USB20_P0 37
BB26 C25
R234 1 @ 2 100K_0402_5% PCH_PLTRST# AU28 USB3Tn2 USBP1N B25
37 USB3_TX2_N USB3Tn3 USBP1P
AY30 C26 USB20_N2
42 USB3_TX3_N USB3Tn4 USBP2N USB20_N2 37
AU26 A26 USB20_P2 USB 3.0
37 USB3_TX0_P USB3Tp1 USBP2P USB20_P2 37
AY26 K28 USB20_N3
USB3Tp2 USBP3N USB20_N3 42
AV28 H28 USB20_P3 USB 3.0+DP
37 USB3_TX2_P USB3Tp3 USBP3P USB20_P3 42
AW30 E28 USB20_N4
B 42 USB3_TX3_P USB3Tp4 USBP4N USB20_N4 40 B
D28 USB20_P4
USBP4P C28
USB20_P4 40 Touch Panel
USBP5N A28
USBP5P C29
USBP6N B29
P- USBP6P
PCI_PIRQA# K40 N28
R243 1 @ 2 1K_0402_5% PCH_GPIO51 PCI_PIRQB# K38 PIRQA# USBP7N M28
PIRQB# USBP7P

PCI
PCI_PIRQC# H38 L30
PCI_PIRQD# G38 PIRQC# USBP8N K30
PIRQD# USBP8P G30 USB20_N9
USBP9N USB20_N9 39
DIS@ R254 1 2 0_0402_5% PCH_GPIO50 C46 E30 USB20_P9 USB 2.0
22 DGPU_HOLD_RST# REQ1# / GPIO50 USBP9P USB20_P9 39

USB
Boot BIOS Strap bit1 BBS1 DIS@ R348 1 2 0_0402_5% PCH_GPIO52 C44 C30 USB20_N10
52 NVDD_PWR_EN REQ2# / GPIO52 USBP10N USB20_N10 38
DIS@ R264 1 2 0_0402_5% PCH_GPIO54 E40 A30 USB20_P10 Mini Card(WLAN/BT)
22,31 DGPU_PWR_EN REQ3# / GPIO54 USBP10P USB20_P10 38
GPIO51 GPIO19 Boot BIOS L32 USB20_N11
USBP11N USB20_N11 40
PCH_GPIO51 D47 P+ K32 USB20_P11 FingerPrint
Destination PCH_GPIO53 E42 GNT1# / GPIO51 USBP11P G32 USB20_N12
USB20_P11 40
Bit11 Bit10 GNT2# / GPIO53 P+ USBP12N USB20_N12 38
PCH_GPIO54 R190 1 @ 2 0_0402_5% PCH_GPIO52 PCH_GPIO55 F46 P+ E32 USB20_P12 Mini Card(WWAN)
GNT3# / GPIO55 USBP12P USB20_P12 38
0 1 Reserved C32 USB20_N13
USBP13N USB20_N13 32
A32 USB20_P13 CMOS Camera (LVDS) OC[0..3] use for EHCI 1
USBP13P USB20_P13 32
1 0 PCI R332 1 2 0_0402_5% PCH_GPIO2 G42 OC[4..7] use for EHCI 2
38 BT_DET# PIRQE# / GPIO2
ODD_DA# G40
36 ODD_DA#
R356 1 2 0_0402_5% C42 PIRQF# / GPIO3 C33
Within 500 2mils22.6_0402_1%
R247 1 +3V_PCH
1 1 * SPI (Default) 31 DGPU_GC6_EN
@ PCH_GPIO4
PIRQG# / GPIO4 USBRBIAS#
USBRBIAS
PCH_GPIO5 D44
PIRQH# / GPIO5
0 0 LPC R233
B33 USB_OC0# 1 8
K10 USBRBIAS USB_OC1# 2 7
41 PCI_PME# PME# P+
USB_OC2# 3 6
PCH_PLTRST# C6 A14 USB_OC0# (To USB S/B) USB_OC3# 4 5
5 PCH_PLTRST# PLTRST# OC0# / GPIO59 USB_OC0# 39
K20 USB_OC1#
OC1# / GPIO40 USB_OC1# 37
R245 1 @ 2 1K_0402_5% PCH_GPIO55 B17 USB_OC2# 10K_8P4R_5%
R248 1 2 22_0402_5% CLK_PCI0 H49 OC2# / GPIO41 C16 USB_OC3#
14 CLK_PCI_LPBACK CLKOUT_PCI0 P- OC3# / GPIO42
R235
CLK_PCI_EC R249 1 2 22_0402_5% CLK_PCI1 H43 P- L16 USB_OC4# USB_OC4# 1 8
41 CLK_PCI_EC CLKOUT_PCI1 OC4# / GPIO43
R250 1 2 22_0402_5% CLK_PCI2 J48 P- A16 USB_OC5# USB_OC5# 2 7
38,40 CLK_PCI_DB CLKOUT_PCI2 OC5# / GPIO9
A16 swap overide Strap/Top-Block R350 1 2 22_0402_5% CLK_PCI3 K42 P- D14 USB_OC6# USB_OC6# 3 6
40 CLK_PCI_TPM CLKOUT_PCI3 OC6# / GPIO10
C Swap Override jumper TPM@ H40 P- C14 USB_OC7# USB_OC7# 4 5 C
CLKOUT_PCI4 OC7# / GPIO14
Low=A16 swap 10K_8P4R_5%
override/Top-Block PANTHER-POINT_FCBGA989
PCI_GNT3# Swap Override enabled
High=Default *

RF Boris Tsai suggests


10P_0402_50V8J 1 2 C119 CLK_PCI_TPM

10P_0402_50V8J @ 1 2 C92 CLK_PCI_LPBACK


R251 1 2 0_0402_5%

10P_0402_50V8J 1 2 C93 CLK_PCI_EC


+3VS
5

U11
PCH_PLTRST# 1
P

B 4
Y PLT_RST# 14,22,38,39,40,41,42,5
2
A
G

@ R255
3

TC7SH08FUF_SSOP5 100K_0402_5%
2

D D

Security Classification LC Future Center Secret Data Title


Issued Date 2012/07/01 Deciphered Date 2014/07/01 PCH (5/9) PCI, USB, NVRAM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Saturday, November 03, 2012 Sheet 17 of 59

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GPIO28
On-Die PLL Voltage Regulator
This signal has a weak internal pull up

* H
L
::On-Die voltage regulator enable
On-Die PLL Voltage Regulator disable

R265 1 @ 2 1K_0402_5% PCH_GPIO28

U3F +3VS

R274 1 @ 2 1K_0402_5% EC_SMI# PCH_GPIO0 T7 P+ C40 ODD_EN# ODD_EN# R256 1 2 8.2K_0402_5%


BMBUSY# / GPIO0 TACH4 / GPIO68 ODD_EN# 36
A R359 1 2 0_0402_5% PCH_GPIO1 A42 P+ P+ B41 PCH_GPIO69 R260 1 @ 2 8.2K_0402_5% A
39 FN_LED# TACH1 / GPIO1 TACH5 / GPIO69
R360 1 2 0_0402_5% PCH_GPIO6 H36 P+ P+ C41 PCH_GPIO70
39 F1_LED# TACH2 / GPIO6 TACH6 / GPIO70
EC_SCI# E38 P+ P+ A40 CMOS_ON# +3VS
41 EC_SCI# TACH3 / GPIO7 TACH7 / GPIO71 CMOS_ON# 32
EC_SMI# C10 P+ PCH_GPIO70 R258 2 1 10K_0402_5%
41 EC_SMI# GPIO8
PCH_GPIO12 C4 R262 1 @ 2 10K_0402_5%
LAN_PHY_PWR_CTRL / GPIO12
+3VS R178 1 2 0_0402_5% PCH_GPIO15 G2 P- P4
41 EC_WAKE# GPIO15 A20GATE GATEA20 41
R280 1 2 10K_0402_5% P- AU16 PCH_PECI_R R307 1 @ 2 0_0402_5% +3VS
PECI H_PECI 41,5
R282 1 @ 2 10K_0402_5% WLBT_OFF_51# For GC6 PCH_GPIO16 U2
SATA4GP / GPIO16 P5 KB_RST# CMOS_ON# R257 2 1 10K_0402_5%
RCIN# KB_RST# 41
D40

GPIO
DGPU_PWROK AY11 H_CPUPWRGD R263 1 @ 2 10K_0402_5%
+3V_PCH 31,52 DGPU_PWROK TACH0 / GPIO17 PROCPWRGD H_CPUPWRGD 5

CPU/MISC
R361 1 2 0_0402_5% PCH_GPIO22 T5 AY10 R278 1 2 390_0402_5% H_THRMTRIP#
39 F4_LED# SCLOCK / GPIO22 THRMTRIP# H_THRMTRIP# 5
R288 1 2 10K_0402_5%
VGA_THRMTRIP# 22 +3VS
R290 1 @ 2 10K_0402_5% PCH_GPIO24 PCH_GPIO24 E8 P+ T14
GPIO24 INIT3_3V#
INIT3_3V
R293 1 2 0_0402_5% PCH_GPIO27 E16 P+ P- AY1 DF_TVS GATEA20 R272 1 2 10K_0402_5%
38 mSATA_PCH GPIO27 DF_TVS
This signal has weak internal
+3VS PCH_GPIO28 P8 P+ KB_RST# R276 1 2 10K_0402_5%
GPIO28 AH8
PU, can't pull low
R285 1 @ 2 10K_0402_5% PCH_GPIO34 K1 TS_VSS1
R284 1 2 10K_0402_5% PCH_GPIO37 STP_PCI# / GPIO34 AK11
3G_DET# K4 TS_VSS2 +1.8VS
38 3G_DET# GPIO35 AH10
WLBT_OFF_51# V8 TS_VSS3
+3VS 38 WLBT_OFF_51# SATA2GP / GPIO36 P-
AK10 Intel schematic reviwe recommand.
TS_VSS4

1
PCH_GPIO37 M5 P-
SATA3GP / GPIO37 R226
R269 1 2 10K_0402_5% PCH_GPIO0 PCH_GPIO38 N2 P37 2.2K_0402_5%
B SLOAD / GPIO38 NC_1 B
R270 1 2 10K_0402_5% PCH_GPIO1 3G_OFF# M3
38 3G_OFF#

2
SDATAOUT0 / GPIO39
R266 1 2 10K_0402_5% PCH_GPIO6 GPS_OFF# V13 BG2 T18 DF_TVS R229 1 2 1K_0402_5% H_SNB_IVB# 5
38 GPS_OFF# SDATAOUT1 / GPIO48 VSS_NCTF_15
R344 1 2 10K_0402_5% EC_SCI# PCH_GPIO49 V3 BG48
T19
SATA5GP / GPIO49 / TEMP_ALERT# VSS_NCTF_16
DMI Termination Voltage
R275 1 2 10K_0402_5% PCH_GPIO16 PCH_GPIO57 D6 BH3 T20
GPIO57 VSS_NCTF_17
Set to Vcc when HIGH
R268 1 2 10K_0402_5% DGPU_PWROK BH47 T21 NV_CLE
VSS_NCTF_18
Set to Vss when LOW
R277 1 2 10K_0402_5% PCH_GPIO22 T22 A4 BJ4 T23
VSS_NCTF_1 VSS_NCTF_19
CLOSE TO THE BRANCHING POINT
R346 1 2 10K_0402_5% PCH_GPIO34 GPIO34 T24 A44 BJ44 T25
VSS_NCTF_2 VSS_NCTF_20
R283 1 2 10K_0402_5% 3G_DET# T26 A45 BJ45
T27
VSS_NCTF_3 VSS_NCTF_21

NCTF
R287 1 2 10K_0402_5% 3G_OFF# T28 A46 BJ46 T29
VSS_NCTF_4 VSS_NCTF_22
R289 1 2 10K_0402_5% GPS_OFF# T30 A5 BJ5 T31
VSS_NCTF_5 VSS_NCTF_23
R291 1 2 10K_0402_5% PCH_GPIO49 T32 A6 BJ6 T33
VSS_NCTF_6 VSS_NCTF_24
T34 B3 C2 T35
VSS_NCTF_7 VSS_NCTF_25
+3V_PCH T36 B47 C48 T37
VSS_NCTF_8 VSS_NCTF_26
T38 BD1 D1 T39
R345 1 2 10K_0402_5% EC_SMI# VSS_NCTF_9 VSS_NCTF_27
T40 BD49 D49 T41
R271 1 2 10K_0402_5% PCH_GPIO12 VSS_NCTF_10 VSS_NCTF_28
T42 BE1 E1 T43
R273 1 2 1K_0402_5% PCH_GPIO15 VSS_NCTF_11 VSS_NCTF_29
T44 BE49 E49 T45
R347 1 2 10K_0402_5% PCH_GPIO28 VSS_NCTF_12 VSS_NCTF_30
C C
T46 BF1 F1
VSS_NCTF_13 VSS_NCTF_31 T47
R292 1 @ 2 10K_0402_5% PCH_GPIO57
T48 BF49 F49 T49
R352 1 2 10K_0402_5% PCH_GPIO27 VSS_NCTF_14 VSS_NCTF_32

PANTHER-POINT_FCBGA989
For Edge code setting

PCH_GPIO69 PCH_GPIO38 PCH_GPIO67 Function

0 0 0 Optimus
0 0 1 Reserved

0 1 0 DIS
0 1 1 UMA
+3VS
1

R259 R330 R311


10K_0402_5% 10K_0402_5% 10K_0402_5%
D D
@ UMA@ UMA@
2

PCH_GPIO69
PCH_GPIO38
(MB_ID_2)
PCH_GPIO67
(MB_ID_1)
PCH_GPIO67 14 (MB_ID_0)
1

R261 R329 R286 Title


10K_0402_5% 10K_0402_5% 10K_0402_5% Security Classification LC Future Center Secret Data
DIS@ DIS@ PCH (6/9) GPIO, CPU, MISC
Issued Date 2012/07/01 Deciphered Date 2014/07/01
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Saturday, November 03, 2012 Sheet 18 of 59

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+VCCADAC +3VS

+VCCADAC 1 2 L1

C94

1U_0402_16V7K

C99

0.1U_0402_10V7K

C100

10U_0603_6.3V6M

C160

10U_0603_6.3V6M
1 ohm 0603
1 1 1 1

2 2 2 2
A
+1.05VS +1.05VS_PCH U3G POWER A

JP2 1300mA
1 2 +1.05VS_PCH AA23 U48
AC23 VCCCORE[1] 1mA VCCADAC
VCCCORE[2] +3VS

C95

10U_0603_6.3V6M

C96

1U_0402_6.3V6K

C97

1U_0402_6.3V6K

C98

1U_0402_6.3V6K
PAD-OPEN 4x4m AD21

CRT
AD23 VCCCORE[3] U47
1 1 1 1 VCCCORE[4] VSSADAC
AF21

VCC CORE
AF23 VCCCORE[5]
AG21 VCCCORE[6] +1.8VS
2 2 2 2 AG23 VCCCORE[7]
AG24 VCCCORE[8] AK36
AG26 VCCCORE[9] 1mAVCCALVDS +VCCTX_LVDS 0.1UH_MLF1608DR10KT_10%_1608 1 2 L2
AG27 VCCCORE[10] AK37 0.1uH inductor, 200mA
VCCCORE[11] VSSALVDS

C101

0.01U_0402_16V7K

C102

0.01U_0402_16V7K

C103

22U_0805_6.3V6M
AG29
AJ23 VCCCORE[12]
VCCCORE[13] 1 1 1

LVDS
AJ26 AM37
AJ27 VCCCORE[14] VCCTX_LVDS[1]
AJ29 VCCCORE[15] AM38
AJ31 VCCCORE[16] VCCTX_LVDS[2] 2 2 2
+1.05VS_PCH VCCCORE[17] AP36
40mA VCCTX_LVDS[3]
+1.05VS_VCCDPLLEXP
AP37
+1.05VS_PCH AN19 VCCTX_LVDS[4]
VCCIO[28] +3VS

T50 +VCCAPLLEXP BJ22


VCCAPLLEXP

This pin can be left as no connect in V33


AN16 VCC3_3[6]

HVCMOS
On-Die VR enabled mode (default). VCCIO[15]
1
AN17 C104
VCCIO[16] V34 0.1U_0402_10V7K
+1.05VS_PCH VCC3_3[7]
B +1.05VS_VCC_EXP AN21 2 B
VCCIO[17] +VCCAFDI_VRM
AN26
VCCIO[18]
C105

10U_0603_6.3V6M

C106

1U_0402_6.3V6K

C107

1U_0402_6.3V6K

C108

1U_0402_6.3V6K

C109

1U_0402_6.3V6K
AN27 3709mA AT16 +VCCAFDI_VRM
VCCIO[19] VCCVRM[3]
1 1 1 1 1
AP21 +1.05VS_PCH
VCCIO[20] +VCCP_VCCDMI
AP23 AT20
2 2 2 2 2 VCCIO[21] VCCDMI[1]
+1.05VS

DMI
AP24
VCCIO[22]

VCCIO
1
AP26 75mA VCCCLKDMI AB36 C110
VCCIO[23] 1U_0402_6.3V6K
1
AT24 C111
+3VS VCCIO[24] 1U_0402_6.3V6K 2

AN33 2
VCCIO[25]
AN34 AG16 +1.8VS
VCCIO[26] VCCDFTERM[1] +VCCPNAND
1
C112
0.1U_0402_10V7K BH29 AG17 +VCCPNAND R300 1 2 0_0805_5%
VCC3_3[3] 2mA VCCDFTERM[2]

DFT / SPI
2 1
C113
AJ16 1U_0402_6.3V6K
VCCDFTERM[3]
+VCCAFDI_VRM AP16 2
VCCVRM[2] AJ17
VCCDFTERM[4] +3VM +3VS
Place C167 Near BG6 pin
+1.05VS_VCCAPLL_FDI BG6
VccAFDIPLL
+3V_VCCPSPI R166 1 SBA@ 2 0_0402_5%
1
+1.05VS_PCH AP17
@ C114 VCCIO[27] V1 +3V_VCCPSPI R302 1 @ 2 0_0402_5%
C 10mA VCCSPI C
FDI

1U_0402_6.3V6K
2 AU20
VCCDMI[2] 1
C115 11/16
+1.05VS_VCCDPLL_FDI 1U_0402_6.3V6K
+VCCP_VCCDMI PANTHER-POINT_FCBGA989
2

+1.5VS +VCCAFDI_VRM

R304 1 2 0_0603_5% +VCCAFDI_VRM

D D
VCCVRM==>1.5V FOR MOBILE
VCCVRM==>1.8V FOR DESKTOP
VCCVRM = 160mA detal waiting for newest spec

Security Classification LC Future Center Secret Data Title


Issued Date 2012/07/01 Deciphered Date 2014/07/01 PCH (7/9) PWR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Saturday, November 03, 2012 Sheet 19 of 59

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VCC3_3 = 266mA detal waiting for newest spec


Have internal VRM VCCDMI = 42mA detal waiting for newest spec

+3VALW

+5VALW +5VALW_PCH

R308 1 2 0_0603_5% +VCCPDSW


+1.05VS_PCH R309 1 2 0_0603_5%
U3J POWER
If platform does not support 1
A Deep S4/S5 then tie to VccSus3_3. C118 AD49 N26 +1.05VS_PCH A
0.1U_0402_10V7K VCCACLK VCCIO[29]
1
P26 C120
+3VS 2 T16 VCCIO[30] 1U_0402_6.3V6K
VCCDSW3_33mA P28
VCCIO[31] +3V_PCH 2 +1.05VS_VCCUSBCORE
+3VS C121 @ 1 2 +PCH_VCCDSW V12 T27
DCPSUSBYP VCCIO[32]
C116

10U_0603_6.3V6M

C117

1U_0402_6.3V6K

0.1U_0402_10V7K T29
T38 VCCIO[33]
1 1 VCC3_3[5] 1
C122
+1.05VS_PCH C123 @ 2 1 +VCCAPLL_CPY_PCH T23 0.1U_0402_10V7K
BH23 119mA VCCSUS3_3[7]
2 2 10U_0603_6.3V6M VCCAPLLDMI2 T24 2 11/16
AL29 VCCSUS3_3[8]
VCCIO[14] V23
VCCSUS3_3[9]

USB
+VCCDPLL_CPY 1
C124 @ 1 2 +VCCSUS1 AL24 V24 C125 +3V_PCH +5VALW_PCH
DCPSUS[3] VCCSUS3_3[10] 0.1U_0402_10V7K
1U_0402_6.3V6K P24 +1.05VS_PCH
VCCSUS3_3[6]

1
2
AA19 D4 R315
VCCASW[1] T26 +1.05VS_PCH +1.05VS_VCCAUPLL RB751V-40_SOD323-2 10_0402_5%
AA21 VCCIO[34]
VCCASW[2]
903mA
1

2
AA24 M26 +PCH_V5REF_SUS +PCH_V5REF_SUS
VCCASW[3] 1mA V5REF_SUS C132 @ 1
+1.05VS AA26 1U_0402_6.3V6K +3V_PCH C126

Clock and Miscellaneous


@ VCCASW[4] AN23 +VCCA_USBSUS 2 0.1U_0402_10V7K
R316 1 2 0_0805_5% +1.05VM_VCCASW AA27 DCPSUS[4]
VCCASW[5] AN24 +3V_PCH 2
VCCSUS3_3[1]

C127

1U_0402_6.3V6K

C128

1U_0402_6.3V6K

C129

1U_0402_6.3V6K

C130

22U_0805_6.3V6M

C131

22U_0805_6.3V6M
AA29 1
+1.05VM VCCASW[6]
1 1 1 1 1
SBA@ AA31 C133 11/16
R349 1 2 0_0805_5% VCCASW[7]
0.1U_0402_10V7K
B
AC26 P34 +PCH_V5REF_RUN 2 B
2 2 2 2 2 VCCASW[8] 1mA V5REF
if not supply SBA R316 mount , R349 @ AC27 +3VS +5VS
VCCASW[9]
if supply SBA R316 @,R349 mount AC29 VCCSUS3_3[2]
N20 +3V_PCH

PCI/GPIO/LPC
VCCASW[10] 1

1
N22 C134
AC31 VCCSUS3_3[3] 1U_0402_6.3V6K D5 R318
+1.05VS_PCH VCCASW[11] P20 RB751V-40_SOD323-2 10_0402_5%
L4 AD29 VCCSUS3_3[4] 2 +3VS
1 2 +1.05VS_VCCA_A_DPL VCCASW[12] P22

2
10UH_LB2012T100MR_20% AD31 VCCSUS3_3[5] +PCH_V5REF_RUN
C136 C137 VCCASW[13]
1 1
1 W21 AA16 C135
220U_B2_2.5VM_R35 + 1U_0402_6.3V6K VCCASW[14] VCC3_3[1] 1U_0402_6.3V6K
1 1
W23 W16 C141 C140
VCCASW[15] VCC3_3[8] 0.1U_0402_10V7K 0.1U_0402_10V7K 2
2 2 W24 T34
VCCASW[16] VCC3_3[4] 2 2
W26
VCCASW[17]
L5 W29
1 2 +1.05VS_VCCA_B_DPL VCCASW[18]
1
10UH_LB2012T100MR_20% W31 AJ2 C142
C138 C139 VCCASW[19] VCC3_3[2] 0.1U_0402_10V7K
1
1 W33
220U_B2_2.5VM_R35 + 1U_0402_6.3V6K VCCASW[20] AF13 2 +1.05VS_PCH
C143 1 2 +VCCRTCEXT VCCIO[5]
N16
2 2 0.1U_0402_10V7K DCPRTC AH13
VCCIO[12] +1.05VS_SATA3
1
+VCCAFDI_VRM Y49 AH14 Place C199 Near AK1 pin C145
VCCVRM[4] VCCIO[13] +VCCSATAPLL 1U_0402_6.3V6K
+VCCAFDI_VRM 1
AF14 C147 2
+1.05VS_VCCA_A_DPL BD47 VCCIO[6] 10U_0603_6.3V6M
C 1 VCCADPLLA
75mA C

SATA
C144 AK1 @ +VCCAFDI_VRM
1U_0402_6.3V6K +1.05VS_VCCA_B_DPL BF47 VCCAPLLSATA 2
VCCADPLLB
75mA
2 AF11 +VCCAFDI_VRM
+1.05VS_PCH AF17 VCCVRM[1] +1.05VS_PCH
AF33 VCCIO[7]
AF34 VCCDIFFCLKN[1] AC16
VCCDIFFCLKN[2]
55mA VCCIO[2]
AG34
+1.05VS_PCH VCCDIFFCLKN[3] AC17 +1.05VS_VCC_SATA
VCCIO[3]
1 1
C146 AG33 AD17 C148
1U_0402_6.3V6K VCCSSC 95mA VCCIO[4] 1U_0402_6.3V6K

+1.05VS 2 V16 2
DCPSST

R328 1 2 0_0603_5% +1.05VS_SSCVCC T17 T21


V19 DCPSUS[1] VCCASW[22]
1 DCPSUS[2]
Ensure independent power C149 +VCCSST +1.05VM_VCCASW
MISC

1U_0402_6.3V6K V21
routing for SSC and DIFFCLKN +1.05VM_VCCSUS VCCASW[23]
2
CPU

2 1 BJ8 1mA
V_PROC_IO T19
C150 C151 VCCASW[21]
0.1U_0402_10V7K 1U_0402_6.3V6K
1 2 +3V_PCH
@
A22 P32
10mA
RTC

VCCRTC VCCSUSHDA
HDA

+1.05VS_PCH

+V_CPU_IO +1.05VS_PCH PANTHER-POINT_FCBGA989


1
C152

4.7U_0603_6.3V6K

C153

0.1U_0402_10V7K

C154

0.1U_0402_10V7K

C158
1 1 1 0.1U_0402_16V4Z
D +RTCVCC 2 D
11/16
2 2 2
C155

1U_0402_6.3V6K

C156

0.1U_0402_10V7K

C157

0.1U_0402_10V7K

1 1 1

2 2 2 Security Classification LC Future Center Secret Data Title


Issued Date 2012/07/01 Deciphered Date 2014/07/01 PCH (8/9) PWR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Saturday, November 03, 2012 Sheet 20 of 59

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U3H U3I
H5
VSS[0] AY4 H46
AA17 AK38 AY42 VSS[159] VSS[259] K18
AA2 VSS[1] VSS[80] AK4 AY46 VSS[160] VSS[260] K26
AA3 VSS[2] VSS[81] AK42 AY8 VSS[161] VSS[261] K39
AA33 VSS[3] VSS[82] AK46 B11 VSS[162] VSS[262] K46
A A
AA34 VSS[4] VSS[83] AK8 B15 VSS[163] VSS[263] K7
AB11 VSS[5] VSS[84] AL16 B19 VSS[164] VSS[264] L18
AB14 VSS[6] VSS[85] AL17 B23 VSS[165] VSS[265] L2
AB39 VSS[7] VSS[86] AL19 B27 VSS[166] VSS[266] L20
AB4 VSS[8] VSS[87] AL2 B31 VSS[167] VSS[267] L26
AB43 VSS[9] VSS[88] AL21 B35 VSS[168] VSS[268] L28
AB5 VSS[10] VSS[89] AL23 B39 VSS[169] VSS[269] L36
AB7 VSS[11] VSS[90] AL26 B7 VSS[170] VSS[270] L48
AC19 VSS[12] VSS[91] AL27 F45 VSS[171] VSS[271] M12
AC2 VSS[13] VSS[92] AL31 BB12 VSS[172] VSS[272] P16
AC21 VSS[14] VSS[93] AL33 BB16 VSS[173] VSS[273] M18
AC24 VSS[15] VSS[94] AL34 BB20 VSS[174] VSS[274] M22
AC33 VSS[16] VSS[95] AL48 BB22 VSS[175] VSS[275] M24
AC34 VSS[17] VSS[96] AM11 BB24 VSS[176] VSS[276] M30
AC48 VSS[18] VSS[97] AM14 BB28 VSS[177] VSS[277] M32
AD10 VSS[19] VSS[98] AM36 BB30 VSS[178] VSS[278] M34
AD11 VSS[20] VSS[99] AM39 BB38 VSS[179] VSS[279] M38
AD12 VSS[21] VSS[100] AM43 BB4 VSS[180] VSS[280] M4
AD13 VSS[22] VSS[101] AM45 BB46 VSS[181] VSS[281] M42
AD19 VSS[23] VSS[102] AM46 BC14 VSS[182] VSS[282] M46
AD24 VSS[24] VSS[103] AM7 BC18 VSS[183] VSS[283] M8
AD26 VSS[25] VSS[104] AN2 BC2 VSS[184] VSS[284] N18
AD27 VSS[26] VSS[105] AN29 BC22 VSS[185] VSS[285] P30
AD33 VSS[27] VSS[106] AN3 BC26 VSS[186] VSS[286] N47
AD34 VSS[28] VSS[107] AN31 BC32 VSS[187] VSS[287] P11
AD36 VSS[29] VSS[108] AP12 BC34 VSS[188] VSS[288] P18
AD37 VSS[30] VSS[109] AP19 BC36 VSS[189] VSS[289] T33
AD38 VSS[31] VSS[110] AP28 BC40 VSS[190] VSS[290] P40
AD39 VSS[32] VSS[111] AP30 BC42 VSS[191] VSS[291] P43
AD4 VSS[33] VSS[112] AP32 BC48 VSS[192] VSS[292] P47
AD40 VSS[34] VSS[113] AP38 BD46 VSS[193] VSS[293] P7
AD42 VSS[35] VSS[114] AP4 BD5 VSS[194] VSS[294] R2
AD43 VSS[36] VSS[115] AP42 BE22 VSS[195] VSS[295] R48
AD45 VSS[37] VSS[116] AP46 BE26 VSS[196] VSS[296] T12
B
AD46 VSS[38] VSS[117] AP8 BE40 VSS[197] VSS[297] T31 B
AD8 VSS[39] VSS[118] AR2 BF10 VSS[198] VSS[298] T37
AE2 VSS[40] VSS[119] AR48 BF12 VSS[199] VSS[299] T4
AE3 VSS[41] VSS[120] AT11 BF16 VSS[200] VSS[300] W34
AF10 VSS[42] VSS[121] AT13 BF20 VSS[201] VSS[301] T46
AF12 VSS[43] VSS[122] AT18 BF22 VSS[202] VSS[302] T47
AD14 VSS[44] VSS[123] AT22 BF24 VSS[203] VSS[303] T8
AD16 VSS[45] VSS[124] AT26 BF26 VSS[204] VSS[304] V11
AF16 VSS[46] VSS[125] AT28 BF28 VSS[205] VSS[305] V17
AF19 VSS[47] VSS[126] AT30 BD3 VSS[206] VSS[306] V26
AF24 VSS[48] VSS[127] AT32 BF30 VSS[207] VSS[307] V27
AF26 VSS[49] VSS[128] AT34 BF38 VSS[208] VSS[308] V29
AF27 VSS[50] VSS[129] AT39 BF40 VSS[209] VSS[309] V31
AF29 VSS[51] VSS[130] AT42 BF8 VSS[210] VSS[310] V36
AF31 VSS[52] VSS[131] AT46 BG17 VSS[211] VSS[311] V39
AF38 VSS[53] VSS[132] AT7 BG21 VSS[212] VSS[312] V43
AF4 VSS[54] VSS[133] AU24 BG33 VSS[213] VSS[313] V7
AF42 VSS[55] VSS[134] AU30 BG44 VSS[214] VSS[314] W17
AF46 VSS[56] VSS[135] AV16 BG8 VSS[215] VSS[315] W19
AF5 VSS[57] VSS[136] AV20 BH11 VSS[216] VSS[316] W2
AF7 VSS[58] VSS[137] AV24 BH15 VSS[217] VSS[317] W27
AF8 VSS[59] VSS[138] AV30 BH17 VSS[218] VSS[318] W48
AG19 VSS[60] VSS[139] AV38 BH19 VSS[219] VSS[319] Y12
AG2 VSS[61] VSS[140] AV4 H10 VSS[220] VSS[320] Y38
AG31 VSS[62] VSS[141] AV43 BH27 VSS[221] VSS[321] Y4
AG48 VSS[63] VSS[142] AV8 BH31 VSS[222] VSS[322] Y42
AH11 VSS[64] VSS[143] AW14 BH33 VSS[223] VSS[323] Y46
AH3 VSS[65] VSS[144] AW18 BH35 VSS[224] VSS[324] Y8
AH36 VSS[66] VSS[145] AW2 BH39 VSS[225] VSS[325] BG29
AH39 VSS[67] VSS[146] AW22 BH43 VSS[226] VSS[328] N24
AH40 VSS[68] VSS[147] AW26 BH7 VSS[227] VSS[329] AJ3
AH42 VSS[69] VSS[148] AW28 D3 VSS[228] VSS[330] AD47
AH46 VSS[70] VSS[149] AW32 D12 VSS[229] VSS[331] B43
AH7 VSS[71] VSS[150] AW34 D16 VSS[230] VSS[333] BE10
AJ19 VSS[72] VSS[151] AW36 D18 VSS[231] VSS[334] BG41
C C
AJ21 VSS[73] VSS[152] AW40 D22 VSS[232] VSS[335] G14
AJ24 VSS[74] VSS[153] AW48 D24 VSS[233] VSS[337] H16
AJ33 VSS[75] VSS[154] AV11 D26 VSS[234] VSS[338] T36
AJ34 VSS[76] VSS[155] AY12 D30 VSS[235] VSS[340] BG22
AK12 VSS[77] VSS[156] AY22 D32 VSS[236] VSS[342] BG24
AK3 VSS[78] VSS[157] AY28 D34 VSS[237] VSS[343] C22
VSS[79] VSS[158] D38 VSS[238] VSS[344] AP13
PANTHER-POINT_FCBGA989 D42 VSS[239] VSS[345] M14
D8 VSS[240] VSS[346] AP3
E18 VSS[241] VSS[347] AP1
E26 VSS[242] VSS[348] BE16
G18 VSS[243] VSS[349] BC16
G20 VSS[244] VSS[350] BG28
G26 VSS[245] VSS[351] BJ28
G28 VSS[246] VSS[352]
G36 VSS[247]
G48 VSS[248]
H12 VSS[249]
H18 VSS[250]
H22 VSS[251]
H24 VSS[252]
H26 VSS[253]
H30 VSS[254]
H32 VSS[255]
H34 VSS[256]
F3 VSS[257]
VSS[258]

PANTHER-POINT_FCBGA989

D D

Security Classification LC Future Center Secret Data Title


Issued Date 2012/07/01 Deciphered Date 2014/07/01 PCH (9/9) VSS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Saturday, November 03, 2012 Sheet 21 of 59

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PCIE_CTX_GRX_N[0..7]
4 PCIE_CTX_GRX_N[0..7]
+3VS_VGA
PCIE_CTX_GRX_P[0..7]
4 PCIE_CTX_GRX_P[0..7]
PCIE_CRX_GTX_N[0..7] VGA_BL_PWM R1413 1 @ 2 100K_0402_5%
4 PCIE_CRX_GTX_N[0..7]
U1401A VGA_GPIO13 R1415 1 DIS@ 2 10K_0402_5%
PCIE_CRX_GTX_P[0..7] VGA_ENVDD R1411 1 @ 2 100K_0402_5%
4 PCIE_CRX_GTX_P[0..7]
Part 1 of 6
PCIE_CTX_GRX_P0 AG6 C6 FB_CLAMP_MON OVERT# R1408 1 DIS@ 2 100K_0402_5% VGA_ENBKL R1412 1 @ 2 100K_0402_5%
PCIE_CTX_GRX_N0 AG7 PEX_RX0 GPIO0 B2
PCIE_CTX_GRX_P1 AF7 PEX_RX0_N GPIO1 D6 VGA_BL_PWM THERM#_VGA R1410 1 DIS@ 2 100K_0402_5% VGA_GPIO10 R1414 1 @ 2 100K_0402_5%
PCIE_CTX_GRX_N1 AE7 PEX_RX1 GPIO2 C7 VGA_ENVDD
PCIE_CTX_GRX_P2 AE9 PEX_RX1_N GPIO3 F9 VGA_ENBKL VGA_GPIO12 R1409 1 DIS@ 2 100K_0402_5% VGA_GPIO7 R1416 1 @ 2 100K_0402_5%
PCIE_CTX_GRX_N2 AF9 PEX_RX2 GPIO4 A3
PCIE_CTX_GRX_P3 AG9 PEX_RX2_N GPIO5 A4 FB_CLAMP_TGL_REQ#
PCIE_CTX_GRX_N3 AG10 PEX_RX3 GPIO6 B6 VGA_GPIO7
PEX_RX3_N GPIO7 D2414 +3VS_VGA
A PCIE_CTX_GRX_P4 AF10 A6 OVERT# A
PCIE_CTX_GRX_N4 AE10 PEX_RX4 GPIO8 F8 THERM#_VGA RB751V-40_SOD323-2 DIS@
PCIE_CTX_GRX_P5 AE12 PEX_RX4_N GPIO9 C5 VGA_GPIO10 2 1 VGA_AC_DET
PEX_RX5 GPIO10 VGA_AC_DET 41
PCIE_CTX_GRX_N5 AF12 E7 NVVDD_PWM_VID
PEX_RX5_N GPIO11 NVVDD PWM_VID 52 VGA_THRMTRIP# 18

1
PCIE_CTX_GRX_P6 AG12 D7 VGA_GPIO12
PCIE_CTX_GRX_N6 AG13 PEX_RX6 GPIO12 B4 VGA_GPIO13 1 2

GPIO
PEX_RX6_N GPIO13 DPRSLPVR_VGA 52

3
PCIE_CTX_GRX_P7 AF13 B3 R1423
PCIE_CTX_GRX_N7 AE13 PEX_RX7 GPIO14 C3 R1430 10K_0402_5%
AE15 PEX_RX7_N GPIO15 D5 0_0402_5% DIS@ Q1401B

2
AF15 NC GPIO16 D4 5 2N7002KDWH_SOT363-6
NC GPIO17 DIS@
AG15 C2 DIS@
NC GPIO18

6
AG16 F7 +3VS_VGA

4
AF16 NC GPIO19 E6
AE16 NC GPIO20 C4
AE18 NC GPIO21 OVERT# 2
NC DGPU_PWR_EN 17,22,31

2
AF18 AB6 DIS@ Q1401A
AG18 NC NC 2N7002KDWH_SOT363-6
R1575

1
AG19 NC
AF19 NC 10K_0402_5%
NC N14PGV2@
AE19 For GC6

1
NC

1
D

G
AE21 AG3
AF21 NC DACA_RED AF4 PLT_RST_VGA# 2
AG21 NC DACA_GREEN AF3 FB_CLAMP_TGL_REQ# 3 1 G Q1403
NC DACA_BLUE GC6_EVENT# 41
AG22 2N7002KW_SOT323-3

D
S

3
NC 2N7002KW_SOT323-3 DIS@
DIS@ N14PGV2@
PCIE_CRX_GTX_P0 C1401 DIS@ 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P0 AC9 AE3 Q1413
PEX_TX0 DACA_HSYNC

DACs
PCIE_CRX_GTX_N0 C1402 DIS@ 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N0 AB9 AE4 GPIO 6 of GPU connect to EC GPIO
PCIE_CRX_GTX_P1 C1403 DIS@ 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P1 AB10 PEX_TX0_N DACA_VSYNC
PCIE_CRX_GTX_N1 C1404 DIS@ 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N1 AC10 PEX_TX1
PCIE_CRX_GTX_P2 C1405 DIS@ 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P2 AD11 PEX_TX1_N +3VS_VGA

PCI EXPRESS
PCIE_CRX_GTX_N2 C1406 DIS@ 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N2 AC11 PEX_TX2 W5 R1448 1 @ 2 10K_0402_5%
PCIE_CRX_GTX_P3 C1407 DIS@ 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P3 AC12 PEX_TX2_N DACA_VDD AE2
PCIE_CRX_GTX_N3 C1409 DIS@ 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N3 AB12 PEX_TX3 DACA_VREF AF2
PCIE_CRX_GTX_P4 C1410 DIS@ 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P4 AB13 PEX_TX3_N DACA_RSET
B
PCIE_CRX_GTX_N4 C1411 DIS@ 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N4 AC13 PEX_TX4 B
PCIE_CRX_GTX_P5 C1412 DIS@ 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P5 AD14 PEX_TX4_N
PCIE_CRX_GTX_N5 C1413 DIS@ 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N5 AC14 PEX_TX5 +3VS_VGA
PEX_TX5_N

5
PCIE_CRX_GTX_P6 C1414 DIS@ 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P6 AC15
PCIE_CRX_GTX_N6 C1415 DIS@ 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N6 AB15 PEX_TX6 Q1402B DIS@
PCIE_CRX_GTX_P7 C1416 DIS@ 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P7 AB16 PEX_TX6_N B7 I2CA_SCL R1452 1 DIS@ 2 2.2K_0402_5% I2CS_SCL 4 3
PEX_TX7 I2CA_SCL EC_SMB_CK2 14,39,41
PCIE_CRX_GTX_N7 C1417 DIS@ 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N7 AC16 A7 I2CA_SDA R1460 1 DIS@ 2 2.2K_0402_5%
AD17 PEX_TX7_N I2CA_SDA 2N7002KDWH_SOT363-6
AC17 NC C9 I2CB_SCL R1406 1 DIS@ 2 2.2K_0402_5%
AC18 NC I2CB_SCL C8 I2CB_SDA R1407 1 DIS@ 2 2.2K_0402_5% R1442 1 @ 2 0_0402_5%
NC I2CB_SDA

I2C
AB18
AB19 NC A9 I2CC_SCL R1402 1 DIS@ 2 2.2K_0402_5%
NC I2CC_SCL

2
AC19 B9 I2CC_SDA R1403 1 DIS@ 2 2.2K_0402_5%
AD20 NC I2CC_SDA Q1402A DIS@
AC20 NC D9 I2CS_SCL R1404 1 DIS@ 2 2.2K_0402_5% I2CS_SDA 1 6
NC I2CS_SCL EC_SMB_DA2 14,39,41
AC21 D8 I2CS_SDA R1405 1 DIS@ 2 2.2K_0402_5%
AB21 NC I2CS_SDA 2N7002KDWH_SOT363-6
AD23 NC
AE23 NC R1443 1 @ 2 0_0402_5%
AF24 NC 52mA
AE24 NC L6 +PLLVDD 1 2 0_0402_5%
NC CORE_PLLVDD
R1428 @ PU AT EC SIDE, +3VS AND 4.7K
AG24 M6 71mA
AG25 NC SP_PLLVDD
NC N6 +SP_PLLVDD
VID_PLLVDD 41mA
CLK_PCIE_VGA AE8
14 CLK_PCIE_VGA PEX_REFCLK
CLK_PCIE_VGA# AD8 R1436 1 DIS@ 2 10M_0402_5%
14 CLK_PCIE_VGA# PEX_REFCLK_N
CLK_REQ_GPU# AC6
PEX_CLKREQ_N DIS@
1 @ 2 PEX_TSTCLK_OUT AF22 Y1401
Differential signal
CLK

R1432 200_0402_1% PEX_TSTCLK_OUT# AE22 PEX_TSTCLK_OUT C11 XTALIN


PEX_TSTCLK_OUT_N XTAL_IN B10 XTAL_OUT XTALIN 1 3 XTAL_OUT
XTAL_OUT FB_CLAMP_MON 1 3
C PLT_RST_VGA# AC7 A10 XTALSSIN R1435 1 DIS@ 2 10K_0402_5% GND GND C
PEX_RST_N XTAL_SSIN 2 2
1 2 PEX_TERMP AF25 C10 XTALOUT R1433 1 DIS@ 2 10K_0402_5% C1441 C1442
PEX_TERMP XTAL_OUTBUFF

2
R1434 DIS@ 2.49K_0402_1% 22P_0402_50V8J 2 4 22P_0402_50V8J
R1431 DIS@ DIS@
1 27MHZ 16PF X3G027000FG1H-HX 1
Internal Thermal Sensor 0_0402_5%
N14P-GV2-S-A2_FCBGA595 +3VS N14PGV2@
N14PGV2@

1
U1401
10K_0402_5% SA00005NC00
R1444

1
DIS@
1 2 R1424
17,22,31 DGPU_PWR_EN
10K_0402_5% Under GPU(below 150mils)
+3VS_VGA N14PGV2@
1

1
C2154 N14M-GL-S-A2_FCBGA595 150mA L1402 DIS@

1
0.1U_0402_16V4Z N14MGL@ R1425 +SP_PLLVDD 1 2 +1.05VS_VGA
1

@ SA00005N900 10K_0402_5% BLM18PG330SN1_2P


2

C1443

22U_0805_6.3V6M

C1444

4.7U_0402_6.3V6M

C1445

0.1U_0402_10V7K

C1446

0.1U_0402_10V7K
11/17 R1445 N14PGV2@
10K_0402_5% 2 1 1 1 1 180ohms (ESR=0.2) Bead

2
2

DIS@
Q1415
G

DIS@

DIS@

DIS@

DIS@
AP2301GN-HF_SOT23-3
1 3 CLK_REQ_GPU# N14PGV2@ 2 2 2 2
14 GPU_CLKREQA
For GC6
D

1
D
1
1

C2108 Q2414 DIS@ 2


0.1U_0402_16V4Z 17,22,31 DGPU_PWR_EN
2N7002K_SOT23-3 R1446 G
FB_CLAMP 26,31,41
@ 10K_0402_5% Q1414 S
3
2 1 @ 2 @ +3VS_VGA +3VS_VGA 2N7002KW_SOT323-3 L1403 DIS@
N14PGV2@ +PLLVDD 1 2 +1.05VS_VGA
2

1
R1447 0_0402_5% BLM18PG181SN1D_2P

C1448

0.1U_0402_10V7K

C1449

22U_0805_6.3V6M
R1426
10K_0402_5% 1 1 30 ohms @100MHz (ESR=0.05)
1

R1437 1 2 DIS@
@ 0_0402_5% R1438

DIS@

DIS@
10K_0402_5%
D
@ 2 2 D
5

U1402
Under GPU Near GPU
2

PLT_RST# 1
P

14,17,38,39,40,41,42,5 PLT_RST# B 4 PLT_RST_VGA#


DGPU_HOLD_RST# 2 Y
17 DGPU_HOLD_RST# A
G

TC7SH08FUF_SSOP5
3

DIS@ R1441
10K_0402_5% Title
DIS@ Security Classification LC Future Center Secret Data
Issued Date 2012/07/01 Deciphered Date 2014/07/01 N14P_PCIE/DAC/GPIO
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 22 of 59

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U1401C

Part 3 of 6 F11
AC3 NC AD10
AC4 IFPA_TXC NC AD7
Y4 IFPA_TXC_N NC B19
Y3 IFPA_TXD0 NC V5
AA3 IFPA_TXD0_N NC V6
AA2 IFPA_TXD1 NC G1
AB1 IFPA_TXD1_N NC G2
A A
IFPA_TXD2 NC

NC
AA1 G3
AA4 IFPA_TXD2_N NC G4
AA5 IFPA_TXD3 NC G5
IFPA_TXD3_N NC G6
NC G7
AB5 NC V1
AB4 IFPB_TXC NC V2
AB3 IFPB_TXC_N NC W1
AB2 IFPB_TXD4 NC W2
AD3 IFPB_TXD4_N NC W3
AD2 IFPB_TXD5 NC W4
AE1 IFPB_TXD5_N NC
AD1 IFPB_TXD6
AD4 IFPB_TXD6_N
AD5 IFPB_TXD7 D11 R1530 1 DIS@ 2 10K_0402_5%
IFPB_TXD7_N BUFRST_N
D10
T2 NC
T3 IFPC_L0 E9
T1 IFPC_L0_N NC
R1 IFPC_L1 E10
R2 IFPC_L1_N NC

GENERAL
IFPC_L2

LVDS/TMDS
R3 F10
N2 IFPC_L2_N NC
N3 IFPC_L3
IFPC_L3_N D1 STRAP0
STRAP0 STRAP0 29
D2 STRAP1
STRAP1 STRAP1 29
V3 E4 STRAP2
IFPD_L0 STRAP2 STRAP2 29
V4 E3 STRAP3
IFPD_L0_N STRAP3 STRAP3 29
U3 D3 STRAP4
IFPD_L1 STRAP4 STRAP4 29
U4 C1
T4 IFPD_L1_N NC
T5 IFPD_L2 R1532
R4 IFPD_L2_N F6 1 2 40.2K_0402_1%
B
R5 IFPD_L3 MULTI_STRAP_REF0_GND F4 B
IFPD_L3_N NC F5 N14PGV2@
NC
N1
M1 NC
M2 NC F12
M3 NC THERMDP
K2 NC E12
K3 NC THERMDN
K1 NC
J1 NC
NC

M4 F2 VCCSENSE_VGA
NC VDD_SENSE VCCSENSE_VGA 52
M5
L3 NC
L4 NC
K4 NC VSSSENSE_VGA
NC VSSSENSE_VGA 52
K5 trace width: 16mils
J4 NC F1
NC GND_SENSE differential voltage sensing.
differential signal routing.
J5
N4 NC
N5 IFPC_AUX_I2CW_SCL
IFPC_AUX_I2CW_SDA_N
TEST
P3 AD9 TESTMODE R1449 1 DIS@ 2 10K_0402_5%
P4 IFPD_AUX_I2CX_SCL TESTMODE AE5
IFPD_AUX_I2CX_SDA_N JTAG_TCK T1401
AE6
JTAG_TDI T1402
AF6
JTAG_TDO T1403
J2 AD6
IFPE_AUX_I2CY_SCL JTAG_TMS T1404
J3 AG4 R1450 1 DIS@ 10K_0402_5%
IFPE_AUX_I2CY_SDA_N JTAG_TRST_N
C C

H3
H4 IFPF_AUX_I2CZ_SCL +3VS_VGA
IFPF_AUX_I2CZ_SDA_N SERIAL
D12 ROM_CS# R1451 1 DIS@ 2 10K_0402_5%
ROM_CS_N B12 ROM_SI
ROM_SI ROM_SI 29
A12 ROM_SO
ROM_SO ROM_SO 29
C12 ROM_SCLK
ROM_SCLK ROM_SCLK 29

N14P-GV2-S-A2_FCBGA595
N14PGV2@

D D

Security Classification LC Future Center Secret Data Title


Issued Date 2012/07/01 Deciphered Date 2014/07/01 N14P_LVDS/HDMI/THERM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 23 of 59

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+1.5VS_VGA U1401D +1.05VS_VGA


Under GPU(below 150mils) Near GPU
3.5A 2000mA Under GPU(below 150mils)
Part 4 of 6
Near GPU
B26 AA10
C25 FBVDDQ_01 PEX_IOVDDQ_1 AA12
FBVDDQ_02 PEX_IOVDDQ_2
C1483

0.1U_0402_10V7K

C1484

0.1U_0402_10V7K

C1485

0.1U_0402_10V7K

C1486

0.1U_0402_10V7K

C1487

0.1U_0402_10V7K

C1488

0.1U_0402_10V7K

C1489

0.1U_0402_10V7K

C1490

0.1U_0402_10V7K

C1479

1U_0603_10V6K

C1480

1U_0603_10V6K

C1456

4.7U_0603_6.3V6K

C1457

4.7U_0603_6.3V6K

C1458

10U_0805_6.3V6M

C1459

10U_0805_6.3V6M

C1460

10U_0805_6.3V6M

C1461

22U_0805_6.3V6M

C1465

1U_0402_6.3V6K

C1466

1U_0402_6.3V6K

C1467

1U_0402_6.3V6K

C1468

1U_0402_6.3V6K

C1469

4.7U_0603_6.3V6K

C1470

4.7U_0603_6.3V6K

C1471

10U_0603_6.3V6M

C1472

10U_0603_6.3V6M

C1473

10U_0603_6.3V6M

C1474

10U_0603_6.3V6M

C1475

22U_0805_6.3V6M

C1476

22U_0805_6.3V6M

C1477

22U_0805_6.3V6M

C1478

22U_0805_6.3V6M
E23 AA13
E26 FBVDDQ_03 PEX_IOVDDQ_3 AA16
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FBVDDQ_04 PEX_IOVDDQ_4 1 1 1 1 1 1 1 1 1 1 1 1 1 1
F14 AA18
F21 FBVDDQ_05 PEX_IOVDDQ_5 AA19
A A
FBVDDQ_06 PEX_IOVDDQ_6
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
G13 AA20
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 G14 FBVDDQ_07 PEX_IOVDDQ_7 AA21 2 2 2 2 2 2 2 2 2 2 2 2 2 2
G15 FBVDDQ_08 PEX_IOVDDQ_8 AB22
G16 FBVDDQ_09 PEX_IOVDDQ_9 AC23
G18 FBVDDQ_10 PEX_IOVDDQ_10 AD24
G19 FBVDDQ_11 PEX_IOVDDQ_11 AE25
G20 FBVDDQ_12 PEX_IOVDDQ_12 AF26
G21 FBVDDQ_13 PEX_IOVDDQ_13 AF27
H24 FBVDDQ_14 PEX_IOVDDQ_14
H26 FBVDDQ_15
rise 1.5v system source voltage to 1.55-1.57V J21 FBVDDQ_16
FBVDDQ_17 PEX_IOVDD_1
AA22
K21 AB23
L22 FBVDDQ_18 PEX_IOVDD_2 AC24
L24 FBVDDQ_19 PEX_IOVDD_3 AD25
FBVDDQ_20 PEX_IOVDD_4

POWER
L26 AE26
M21 FBVDDQ_21 PEX_IOVDD_5 AE27
N21 FBVDDQ_22 PEX_IOVDD_6
R21 FBVDDQ_23
T21 FBVDDQ_24
FBVDDQ_25 Under GPU Near GPU +3VS_VGA
V21
W21 FBVDDQ_26
FBVDDQ_27 G10 +VDD33 R1461 1 2 0_0603_5%
VDD33_1 G12
VDD33_2

C1507

0.1U_0402_10V7K

C1506

0.1U_0402_10V7K

C1496

0.1U_0402_10V7K

C1497

0.1U_0402_10V7K

C1498

1U_0402_6.3V6K

C1499

4.7U_0603_6.3V6K
G8 DIS@
VDD33_3 G9
VDD33_4 1 1 1 1 1 1
+1.5VS_VGA

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
10K_0402_5% 2 @ 1 R1462 +IFPAB_PLLVDD V7
W7 IFPAB_PLLVDD_1 2 2 2 2 2 2
AA6 IFPAB_PLLVDD_2
10K_0402_5% 2 @ 1 R1471 +IFPAB_IOVDD W6 IFPAB_RSET D22 R1468 1 DIS@ 2 40.2_0402_1% CALIBRATION PIN DDR3
Y6 IFPA_IOVDD FB_CAL_PD_VDDQ
IFPB_IOVDD
C24 R1470 1 DIS@ 2 42.2_0402_1% FB_CAL_x_PD_VDDQ 40.2Ohm
B FB_CAL_PU_GND B

10K_0402_5% 2 @ 1 R1465 +IFPC_PLLVDD M7 B25 R1473 1 DIS@ 2 51.1_0402_1% FB_CAL_x_PU_GND 42.2Ohm


N7 IFPC_PLLVDD_1 FB_CAL_TERM_GND
T6 IFPC_PLLVDD_2
10K_0402_5% 2 @ 1 R1467 +IFPC_IOVDD P6 IFPC_RSET FB_CAL_xTERM_GND 51.1Ohm
IFPC_IOVDD
Place near balls

10K_0402_5% 2 @ 1 R1469 +IFPD_PLLVDD T7


R7 IFPD_PLLVDD_2
U6 IFPD_PLLVDD_1 +3VS_VGA
IFPD_RSET Near GPU(below 150mils)
10K_0402_5% 2 @ 1 R1472 +IFPD_IOVDD R6 AA8 DIS@
IFPD_IOVDD PEX_PLL_HVDD_1 AA9 +PEX_PLLHVDD R1459 1 2 0_0402_5%
PEX_PLL_HVDD_2

C1493

0.1U_0402_10V7K

C1494

4.7U_0603_6.3V6K

C1495

4.7U_0603_6.3V6K
AB8
PEX_SVDD_3V3
1 1 1
J7 +1.05VS_VGA
NC 120mA

DIS@

DIS@

DIS@
K7
K6 NC AA14 L1404 N14MGL@ 2 2 2
H6 NC PEX_PLLVDD_1 AA15 +PEX_PLLVDD 1 2
J6 NC PEX_PLLVDD_2 BLM18PG121SN1D_0603
NC

C1500

0.1U_0402_10V7K

C1501

1U_0603_10V6K

C1502

4.7U_0805_10V4Z
120ohms @100MHz (ESR=0.18)
1 1 1
N14PGV2@

DIS@

DIS@

DIS@
R2155 1 2
2 2 2
N14P-GV2-S-A2_FCBGA595 0_0603_5%
N14PGV2@

Under GPU Near GPU


C C

D D

Security Classification LC Future Center Secret Data Title


Issued Date 2012/07/01 Deciphered Date 2014/07/01 N14P_Power
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 24 of 59

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U1401E

A2 Part 5 of 6 K11 +VGA_CORE +VGA_CORE


A26 GND_001 GND_057 K13 U1401F
AB11 GND_002 GND_058 K15
AB14 GND_003 GND_059 K17 Part 6 of 6
AB17 GND_004 GND_060 L10
A A
AB20 GND_005 GND_061 L12 K10 V18
AB24 GND_006 GND_062 L14 K12 VDD_001 VDD_041 V16
AC2 GND_007 GND_063 L16 K14 VDD_002 VDD_040 V14
AC22 GND_008 GND_064 L18 K16 VDD_003 VDD_039 V12
AC26 GND_009 GND_065 L2 K18 VDD_004 VDD_038 V10
GND_010 GND_066 VDD_005 VDD_037

C1636

47U_0805_4V6
AC5 L23 L11 U17
GND_011 GND_067 VDD_006 VDD_036

POWER
AC8 L25 L13 U15 1
AD12 GND_012 GND_068 L5 L15 VDD_007 VDD_035 U13
AD13 GND_013 GND_069 M11 L17 VDD_008 VDD_034 U11
GND_014 GND_070 VDD_009 VDD_033

DIS@
AD15 M13 M10 T18
AD16 GND_015 GND_071 M15 M12 VDD_010 VDD_032 T16 2
AD18 GND_016 GND_072 M17 M14 VDD_011 VDD_031 T14
AD19 GND_017 GND_073 N10 M16 VDD_012 VDD_030 T12
AD21 GND_018 GND_074 N12 M18 VDD_013 VDD_029 T10
AD22 GND_019 GND_075 N14 N11 VDD_014 VDD_028 R17
AE11 GND_020 GND_076 N16 N13 VDD_015 VDD_027 R15
AE14 GND_021 GND_077 N18 N15 VDD_016 VDD_026 R13
AE17 GND_022 GND_078 P11 N17 VDD_017 VDD_025 R11
AE20 GND_023 GND_079 P13 P10 VDD_018 VDD_024 P18
GND_024 GND_080 VDD_019 VDD_023 Place near balls
AF1 P15 P12 P16
AF11 GND_025 GND_081 P17 VDD_020 VDD_022 P14
GND
AF14 GND_026 GND_082 P2 VDD_021
AF17 GND_027 GND_083 P23
AF20 GND_028 GND_084 P26
AF23 GND_029 GND_085 P5
AF5 GND_030 GND_086 R10
AF8 GND_031 GND_087 R12
AG2 GND_032 GND_088 R14
AG26 GND_033 GND_089 R16
B1 GND_034 GND_090 R18
B11 GND_035 GND_091 T11
B14 GND_036 GND_092 T13 N14P-GV2-S-A2_FCBGA595
B17 GND_037 GND_093 T15 N14PGV2@
B20 GND_038 GND_094 T17
B
B23 GND_039 GND_095 U10 B
B27 GND_040 GND_096 U12
B5 GND_041 GND_097 U14
B8 GND_042 GND_098 U16
E11 GND_043 GND_099 U18
E14 GND_044 GND_100 U2
E17 GND_045 GND_101 U23
E2 GND_046 GND_102 U26
E20 GND_047 GND_103 U5
E22 GND_048 GND_104 V11
E25 GND_049 GND_105 V13
E5 GND_050 GND_106 V15
E8 GND_051 GND_107 V17
H2 GND_052 GND_108 Y2
H23 GND_053 GND_109 Y23
H25 GND_054 GND_110 Y26
H5 GND_055 GND_111 Y5
GND_056 GND_112

AA7
GND AB7
GND

N14P-GV2-S-A2_FCBGA595 VDD33
N14PGV2@

tIFPx_IOVDD
IFPx_IOVDD
C C

tNVVDD
NVVDD

tFBVDDQ
FBVDDQ

tPEX_VDD
PEX_VDD

tIFPy_IOVDD
IFPy_IOVDD

NV Recommended Power On Sequencing Order


D
X=A and B D
Y=C,D,E and F

Security Classification LC Future Center Secret Data Title


Issued Date 2012/07/01 Deciphered Date 2014/07/01 N14P_VGA CORE, GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 25 of 59

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FBA_D[0..63]
27,28 FBA_D[0..63]

27,28 FBA_DQM[7..0]

27,28 FBA_DQS[7..0] FBA_MA[15..0] 27,28

27,28 FBA_DQS#[7..0] FBA_BA[2..0] 27,28 Mode D - Mirror Mode Mapping


DATA Bus
A Address 0..31 32..63 A

U1401B FBx_CMD0 CS0#_L


FBx_CMD1
Part 2 of 6 FBx_CMD2 ODT_L
FBA_D0 E18 C27 FBA_CS0#_L FBx_CMD3 CKE_L
FBA_D00 FBA_CMD0 FBA_CS0#_L 27
FBA_D1 F18 C26
FBA_D2 E16 FBA_D01 FBA_CMD1 E24 FBA_ODT_L
FBA_D02 FBA_CMD2 FBA_ODT_L 27 FBx_CMD4 A14 A14
FBA_D3 F17 F24 FBA_CKE_L
FBA_D03 FBA_CMD3 FBA_CKE_L 27
FBA_D4 D20 D27 FBA_MA14 FBx_CMD5 RST RST
FBA_D5 D21 FBA_D04 FBA_CMD4 D26 FBA_RST#
FBA_D05 FBA_CMD5 FBA_RST# 27,28
FBA_D6 F20 F25 FBA_MA9 FBx_CMD6 A9 A9
FBA_D7 E21 FBA_D06 FBA_CMD6 F26 FBA_MA7
FBA_D8 E15 FBA_D07 FBA_CMD7 F23 FBA_MA2
FBA_D08 FBA_CMD8 FBx_CMD7 A7 A7
FBA_D9 D15 G22 FBA_MA0
FBA_D10 F15 FBA_D09 FBA_CMD9 G23 FBA_MA4
FBA_D10 FBA_CMD10 FBx_CMD8 A2 A2
FBA_D11 F13 G24 FBA_MA1
FBA_D12 C13 FBA_D11 FBA_CMD11 F27 FBA_BA0
FBA_D12 FBA_CMD12 FBx_CMD9 A0 A0
FBA_D13 B13 G25 FBA_WE#
FBA_D13 FBA_CMD13 FBA_WE# 27,28
FBA_D14 E13 G27 FBA_MA15 FBx_CMD10 A4 A4
FBA_D15 D13 FBA_D14 FBA_CMD14 G26 FBA_CAS#
FBA_D15 FBA_CMD15 FBA_CAS# 27,28
FBA_D16 B15 M24 FBA_CS0#_H FBx_CMD11 A1 A1
FBA_D16 FBA_CMD16 FBA_CS0#_H 28
FBA_D17 C16 M23
FBA_D18 A13 FBA_D17 FBA_CMD17 K24 FBA_ODT_H
FBA_D18 FBA_CMD18 FBA_ODT_H 28 FBx_CMD12 BA0 BA0
FBA_D19 A15 K23 FBA_CKE_H
FBA_D19 FBA_CMD19 FBA_CKE_H 28
FBA_D20 B18 M27 FBA_MA13 FBx_CMD13 WE# WE#
FBA_D21 A18 FBA_D20 FBA_CMD20 M26 FBA_MA8
FBA_D22 A19 FBA_D21 FBA_CMD21 M25 FBA_MA6
FBA_D22 FBA_CMD22 FBx_CMD14 A15 A15
FBA_D23 C19 K26 FBA_MA11
FBA_D24 B24 FBA_D23 FBA_CMD23 K22 FBA_MA5
FBA_D24 FBA_CMD24 FBx_CMD15 CAS# CAS#
FBA_D25 C23 J23 FBA_MA3
FBA_D26 A25 FBA_D25 FBA_CMD25 J25 FBA_BA2
B FBA_D26 FBA_CMD26 FBx_CMD16 CS0#_H B
FBA_D27 A24 J24 FBA_BA1
FBA_D28 A21 FBA_D27 FBA_CMD27 K27 FBA_MA12
FBA_D28 FBA_CMD28 FBx_CMD17
FBA_D29 B21 K25 FBA_MA10
FBA_D30 C20 FBA_D29 FBA_CMD29 J27 FBA_RAS#
FBA_D30 FBA_CMD30 FBA_RAS# 27,28 FBx_CMD18 ODT_H
FBA_D31 C21 J26
FBA_D32 R22 FBA_D31 FBA_CMD31
FBA_D32 FBx_CMD19 CKE_H
FBA_D33 R24 D19 FBA_DQM0
FBA_D33 FBA_DQM0

INTERFACE A
FBA_D34 T22 D14 FBA_DQM1 FBx_CMD20 A13 A13
FBA_D35 R23 FBA_D34 FBA_DQM1 C17 FBA_DQM2
FBA_D36 N25 FBA_D35 FBA_DQM2 C22 FBA_DQM3
FBA_D36 FBA_DQM3 FBx_CMD21 A8 A8
FBA_D37 N26 P24 FBA_DQM4

MEMORY
FBA_D38 N23 FBA_D37 FBA_DQM4 W24 FBA_DQM5
FBA_D38 FBA_DQM5 FBx_CMD22 A6 A6
FBA_D39 N24 AA25 FBA_DQM6
FBA_D40 V23 FBA_D39 FBA_DQM6 U25 FBA_DQM7
FBA_D40 FBA_DQM7 FBx_CMD23 A11 A11
FBA_D41 V22
FBA_D42 T23 FBA_D41 F19 FBA_DQS#0
FBA_D42 FBA_DQS_RN0 FBx_CMD24 A5 A5
FBA_D43 U22 C14 FBA_DQS#1
FBA_D44 Y24 FBA_D43 FBA_DQS_RN1 A16 FBA_DQS#2
FBA_D44 FBA_DQS_RN2 FBx_CMD25 A3 A3
FBA_D45 AA24 A22 FBA_DQS#3
FBA_D46 Y22 FBA_D45 FBA_DQS_RN3 P25 FBA_DQS#4
FBA_D46 FBA_DQS_RN4 FBx_CMD26 BA2 BA2
FBA_D47 AA23 W22 FBA_DQS#5
FBA_D48 AD27 FBA_D47 FBA_DQS_RN5 AB27 FBA_DQS#6
FBA_D48 FBA_DQS_RN6 FBx_CMD27 BA1 BA1
FBA_D49 AB25 T27 FBA_DQS#7
FBA_D50 AD26 FBA_D49 FBA_DQS_RN7
FBA_D50 FBx_CMD28 A12 A12
+FB_PLLAVDD FBA_D51 AC25 E19 FBA_DQS0
FBA_D52 AA27 FBA_D51 FBA_DQS_WP0 C15 FBA_DQS1
FBA_D52 FBA_DQS_WP1 FBx_CMD29 A10 A10
C1624

0.1U_0402_10V7K

C1625

1U_0402_6.3V6K

C1626

22U_0805_6.3V6M

FBA_D53 AA26 B16 FBA_DQS2


FBA_D54 W26 FBA_D53 FBA_DQS_WP2 B22 FBA_DQS3
1 1 1 FBA_D54 FBA_DQS_WP3 FBx_CMD30 RAS# RAS#
FBA_D55 Y25 R25 FBA_DQS4
FBA_D56 R26 FBA_D55 FBA_DQS_WP4 W23 FBA_DQS5
FBA_D56 FBA_DQS_WP5
DIS@

DIS@

DIS@

FBA_D57 T25 AB26 FBA_DQS6


2 2 2 FBA_D58 N27 FBA_D57 FBA_DQS_WP6 T26 FBA_DQS7
FBA_D59 R27 FBA_D58 FBA_DQS_WP7
FBA_D60 V26 FBA_D59
FBA_D61 V27 FBA_D60
C C
FBA_D62 W27 FBA_D61
Under GPU Near GPU FBA_D62
FBA_D63 W25
FBA_D63 D24 FBA_CLK0
FBA_CLK0 FBA_CLK0 27
F16 D25 FBA_CLK0#
FB_PLLAVDD_1 FBA_CLK0_N FBA_CLK0# 27
Under GPU P22
FB_PLLAVDD_2 N22 FBA_CLK1
FBA_CLK1 FBA_CLK1 28
+FB_PLLAVDD D23 M22 FBA_CLK1#
FB_VREF_PROBE FBA_CLK1_N FBA_CLK1# 28
0.1U_0402_10V7K DIS@ 2 1 C1622 D18
H22 FBA_WCK01 C18
For GC6 FB_DLLAVDD FBA_WCK01_N D17
@ 1 R1513 2 10K_0402_5% F3 FBA_WCK23 D16
FB_CLAMP FB_CLAMP FBA_WCK23_N T24
22,31,41 FB_CLAMP FBA_WCK45 U24
R1509 1 @ 2 60.4_0402_1% F22 FBA_WCK45_N V24
+1.5VS_VGA FBA_DEBUG0 FBA_WCK67
R1511 1 @ 2 60.4_0402_1% J22 V25
FBA_DEBUG1 FBA_WCK67_N

N14P-GV2-S-A2_FCBGA595
N14PGV2@

30ohms (ESR=0.01) Bead


P/N;SM010007W00
D +1.05VS_VGA +FB_PLLAVDD D

L1414 DIS@
600mA
1 2 +FB_PLLAVDD
FBMA-L11-160808300LMA25T_2P

Place close to BGA

Security Classification LC Future Center Secret Data Title


Issued Date 2012/07/01 Deciphered Date 2014/07/01 N14P_MEM Interface
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 26 of 59

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Memory Partition A - Lower 32 bits


FBA_MA[15..0] 26,28
U1407
U1406
FBA_BA[2..0] 26,28
+FBA_VREF0 M8 E3 FBA_D19
+1.5VS_VGA +FBA_VREF0 M8 E3 FBA_D4 H1 VREFCA DQL0 F7 FBA_D20
H1 VREFCA DQL0 F7 FBA_D1 VREFDQ DQL1 F2 FBA_D17
VREFDQ DQL1 DQL2 FBA_D[0..63] 26,28
A F2 FBA_D7 FBA_MA0 N3 F8 FBA_D21 Group2 (IN1) A
DQL2 A0 DQL3
1
FBA_MA0 N3 F8 FBA_D0 FBA_MA1 P7 H3 FBA_D16
A0 DQL3 A1 DQL4 FBA_DQM[7..0] 26,28
R1481 FBA_MA1 P7 H3 FBA_D6 Group0 (IN3) FBA_MA2 P3 H8 FBA_D23
1.1K_0402_1% FBA_MA2 P3 A1 DQL4 H8 FBA_D3 FBA_MA3 N2 A2 DQL5 G2 FBA_D18
A2 DQL5 A3 DQL6 FBA_DQS[7..0] 26,28
DIS@ FBA_MA3 N2 G2 FBA_D5 FBA_MA4 P8 H7 FBA_D22
FBA_MA4 P8 A3 DQL6 H7 FBA_D2 FBA_MA5 P2 A4 DQL7
FBA_DQS#[7..0] 26,28
2

+FBA_VREF0 FBA_MA5 P2 A4 DQL7 FBA_MA6 R8 A5


FBA_MA6 R8 A5 FBA_MA7 R2 A6 D7 FBA_D10
A6 A7 DQU0
C1522

0.01U_0402_16V7K

FBA_MA7 R2 D7 FBA_D29 FBA_MA8 T8 C3 FBA_D15


A7 DQU0 A8 DQU1
1

1 FBA_MA8 T8 C3 FBA_D25 FBA_MA9 R3 C8 FBA_D8


R1482 FBA_MA9 R3 A8 DQU1 C8 FBA_D30 FBA_MA10 L7 A9 DQU2 C2 FBA_D13
A9 DQU2 A10/AP DQU3 Group1 (TOP)
1.1K_0402_1% FBA_MA10 L7 C2 FBA_D26 FBA_MA11 R7 A7 FBA_D9
A10/AP DQU3 A11 DQU4
DIS@

DIS@ FBA_MA11 R7 A7 FBA_D28 Group3 (BOT) FBA_MA12 N7 A2 FBA_D12


2 FBA_MA12 N7 A11 DQU4 A2 FBA_D24 FBA_MA13 T3 A12 DQU5 B8 FBA_D11
2

FBA_MA13 T3 A12 DQU5 B8 FBA_D31 FBA_MA14 T7 A13 DQU6 A3 FBA_D14


FBA_MA14 T7 A13 DQU6 A3 FBA_D27 FBA_MA15 M7 A14 DQU7
FBA_MA15 M7 A14 DQU7 A15/BA3 +1.5VS_VGA
A15/BA3 +1.5VS_VGA
FBA_BA0 M2 B2
FBA_BA0 M2 B2 FBA_BA1 N8 BA0 VDD D9
FBA_BA1 N8 BA0 VDD D9 FBA_BA2 M3 BA1 VDD G7
FBA_BA2 M3 BA1 VDD G7 BA2 VDD K2
BA2 VDD
VDD
K2 VDD
VDD
K8 Mode D - Mirror Mode Mapping
K8 N1
VDD N1 FBA_CLK0 J7 VDD N9
FBA_CLK0 FBA_CLK0 J7 VDD N9 FBA_CLK0# K7 CK VDD R1
26 FBA_CLK0 CK VDD CK VDD DATA Bus
FBA_CLK0# K7 R1 FBA_CKE_L K9 R9
26 FBA_CLK0# CK VDD CKE/CKE0 VDD
FBA_CKE_L K9 R9 Address 0..31 32..63
26 FBA_CKE_L CKE/CKE0 VDD
1

R1483 FBA_ODT_L K1 A1 FBx_CMD0 CS0#_L


160_0402_1% FBA_ODT_L K1 A1 FBA_CS0#_L L2 ODT/ODT0 VDDQ A8
26 FBA_ODT_L ODT/ODT0 VDDQ CS/CS0 VDDQ
DIS@ FBA_CS0#_L L2 A8 FBA_RAS# J3 C1 FBx_CMD1
26 FBA_CS0#_L CS/CS0 VDDQ RAS VDDQ
FBA_RAS# J3 C1 FBA_CAS# K3 C9 FBA_ODT_L
26,28 FBA_RAS#
2

FBA_CAS# K3 RAS VDDQ C9 FBA_WE# L3 CAS VDDQ D2


26,28 FBA_CAS# CAS VDDQ WE VDDQ FBx_CMD2 ODT_L
FBA_CLK0# FBA_WE# L3 D2 E9
B 26,28 FBA_WE# WE VDDQ VDDQ B
E9 F1 FBA_CKE_L FBx_CMD3 CKE_L
VDDQ F1 FBA_DQS2 F3 VDDQ H2
FBA_DQS0 F3 VDDQ H2 FBA_DQS1 C7 DQSL VDDQ H9
DQSL VDDQ DQSU VDDQ FBx_CMD4 A14 A14

1
FBA_DQS3 C7 H9
DQSU VDDQ R1484 R1485 FBx_CMD5 RST RST
FBA_DQM2 E7 A9 10K_0402_5% 10K_0402_5%
FBA_DQM0 E7 A9 FBA_DQM1 D3 DML VSS B3 DIS@ DIS@
DML VSS DMU VSS FBx_CMD6 A9 A9
FBA_DQM3 D3 B3 E1

2
DMU VSS E1 VSS G8
VSS VSS FBx_CMD7 A7 A7
G8 FBA_DQS#2 G3 J2
FBA_DQS#0 G3 VSS J2 FBA_DQS#1 B7 DQSL VSS J8
DQSL VSS DQSU VSS FBx_CMD8 A2 A2
FBA_DQS#3 B7 J8 M1
DQSU VSS M1 VSS M9
VSS VSS FBx_CMD9 A0 A0
M9 P1
VSS P1 FBA_RST# T2 VSS P9
VSS RESET VSS FBx_CMD10 A4 A4
FBA_RST# T2 P9 T1
26,28 FBA_RST# RESET VSS VSS
T1 L8 T9 FBx_CMD11 A1 A1
L8 VSS T9 ZQ/ZQ0 VSS
ZQ/ZQ0 VSS
FBx_CMD12 BA0 BA0

1
J1 B1
NC/ODT1 VSSQ
1

J1 B1 R1488 L1 B9 FBx_CMD13 WE# WE#


R1486 R1487 L1 NC/ODT1 VSSQ B9 243_0402_1% J9 NC/CS1 VSSQ D1
10K_0402_5% 243_0402_1% J9 NC/CS1 VSSQ D1 DIS@ L9 NC/CE1 VSSQ D8
NC/CE1 VSSQ NCZQ1 VSSQ FBx_CMD14 A15 A15
DIS@ DIS@ L9 D8 E2

2
NCZQ1 VSSQ E2 VSSQ E8 FBx_CMD15 CAS# CAS#
2

VSSQ E8 VSSQ F9
VSSQ F9 VSSQ G1
VSSQ VSSQ FBx_CMD16 CS0#_H
G1 G9
VSSQ G9 VSSQ
VSSQ FBx_CMD17
96-BALL
96-BALL SDRAM DDR3 FBx_CMD18 ODT_H
SDRAM DDR3 K4W4G1646B-HC11_FBGA96
K4W4G1646B-HC11_FBGA96 X76@ FBx_CMD19 CKE_H
X76@
C FBx_CMD20 A13 A13 C

FBx_CMD21 A8 A8
FBx_CMD22 A6 A6
FBx_CMD23 A11 A11
FBx_CMD24 A5 A5
+1.5VS_VGA +1.5VS_VGA FBx_CMD25 A3 A3
U1406 SIDE U1407 SIDE
FBx_CMD26 BA2 BA2
C1541

0.1U_0402_10V7K

C1526

0.1U_0402_10V7K

C1527

0.1U_0402_10V7K

C1528

0.1U_0402_10V7K

C1529

0.1U_0402_10V7K

C1537

1U_0402_6.3V6K

C1531

1U_0402_6.3V6K

C1532

1U_0402_6.3V6K

C1533

1U_0402_6.3V6K

C1534

1U_0402_6.3V6K

C1530

0.1U_0402_10V7K

C1524

0.1U_0402_10V7K

C1525

0.1U_0402_10V7K

C1535

0.1U_0402_10V7K

C1536

0.1U_0402_10V7K

C1538

1U_0402_6.3V6K

C1539

1U_0402_6.3V6K

C1540

1U_0402_6.3V6K

C1545

1U_0402_6.3V6K

C1546

1U_0402_6.3V6K
FBx_CMD27 BA1 BA1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
FBx_CMD28 A12 A12
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
@ @ FBx_CMD29 A10 A10
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
FBx_CMD30 RAS# RAS#

D D

Security Classification LC Future Center Secret Data Title


Issued Date 2012/07/01 Deciphered Date 2014/07/01 N14P_GDDR3_A Lower
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 27 of 59

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Memory Partition A - Upper 32 bits


FBA_D[0..63] 26,27
U1409
+1.5VS_VGA FBA_MA[15..0] 26,27
U1408
+FBA_VREF1 M8 E3 FBA_D36
VREFCA DQL0 FBA_BA[2..0] 26,27
H1 F7 FBA_D34 +FBA_VREF1 M8 E3 FBA_D63
VREFDQ DQL1 VREFCA DQL0

1
A F2 FBA_D37 H1 F7 FBA_D58 A
DQL2 VREFDQ DQL1 FBA_DQM[7..0] 26,27
R1489 FBA_MA0 N3 F8 FBA_D35 F2 FBA_D60
1.1K_0402_1% FBA_MA1 P7 A0 DQL3 H3 FBA_D39 FBA_MA0 N3 DQL2 F8 FBA_D59
A1 DQL4 Group4 (IN1) A0 DQL3 FBA_DQS[7..0] 26,27
DIS@ FBA_MA2 P3 H8 FBA_D32 FBA_MA1 P7 H3 FBA_D61 Group7 (IN3)
FBA_MA3 N2 A2 DQL5 G2 FBA_D38 FBA_MA2 P3 A1 DQL4 H8 FBA_D56
FBA_DQS#[7..0] 26,27
2

+FBA_VREF1 FBA_MA4 P8 A3 DQL6 H7 FBA_D33 FBA_MA3 N2 A2 DQL5 G2 FBA_D62


FBA_MA5 P2 A4 DQL7 FBA_MA4 P8 A3 DQL6 H7 FBA_D57
A5 A4 DQL7
C1547

0.01U_0402_16V7K
FBA_MA6 R8 FBA_MA5 P2
A6 A5
1

1 FBA_MA7 R2 D7 FBA_D44 FBA_MA6 R8


R1490 FBA_MA8 T8 A7 DQU0 C3 FBA_D42 FBA_MA7 R2 A6 D7 FBA_D55
1.1K_0402_1% FBA_MA9 R3 A8 DQU1 C8 FBA_D46 FBA_MA8 T8 A7 DQU0 C3 FBA_D51
A9 DQU2 A8 DQU1
DIS@

DIS@ FBA_MA10 L7 C2 FBA_D41 FBA_MA9 R3 C8 FBA_D54


2 FBA_MA11 R7 A10/AP DQU3 A7 FBA_D47 FBA_MA10 L7 A9 DQU2 C2 FBA_D49
Group5 (TOP)
2

FBA_MA12 N7 A11 DQU4 A2 FBA_D43 FBA_MA11 R7 A10/AP DQU3 A7 FBA_D52


A12 DQU5 A11 DQU4 Group6 (BOT)
FBA_MA13 T3 B8 FBA_D45 FBA_MA12 N7 A2 FBA_D50
FBA_MA14 T7 A13 DQU6 A3 FBA_D40 FBA_MA13 T3 A12 DQU5 B8 FBA_D53
FBA_MA15 M7 A14 DQU7 FBA_MA14 T7 A13 DQU6 A3 FBA_D48
A15/BA3 +1.5VS_VGA FBA_MA15 M7 A14 DQU7
A15/BA3 +1.5VS_VGA
FBA_BA0 M2 B2
FBA_BA1 N8 BA0 VDD D9 FBA_BA0 M2 B2
FBA_CLK1 FBA_BA2 M3 BA1 VDD G7 FBA_BA1 N8 BA0 VDD D9
BA2 VDD K2 FBA_BA2 M3 BA1 VDD G7
VDD K8 BA2 VDD K2
VDD VDD
1

N1 K8
R1491 FBA_CLK1 J7 VDD N9 VDD N1
160_0402_1%
26
26
FBA_CLK1
FBA_CLK1#
FBA_CLK1# K7 CK
CK
VDD
VDD
R1 FBA_CLK1 J7
CK
VDD
VDD
N9 Mode D - Mirror Mode Mapping
DIS@ FBA_CKE_H K9 R9 FBA_CLK1# K7 R1
26 FBA_CKE_H CKE/CKE0 VDD CK VDD
FBA_CKE_H K9 R9
2

CKE/CKE0 VDD
DATA Bus
FBA_CLK1# FBA_ODT_H K1 A1
26 FBA_ODT_H ODT/ODT0 VDDQ
FBA_CS0#_H L2 A8 FBA_ODT_H K1 A1 Address 0..31 32..63
26 FBA_CS0#_H CS/CS0 VDDQ ODT/ODT0 VDDQ
FBA_RAS# J3 C1 FBA_CS0#_H L2 A8
26,27 FBA_RAS# RAS VDDQ CS/CS0 VDDQ
FBA_CAS# K3 C9 FBA_RAS# J3 C1 FBx_CMD0 CS0#_L
26,27 FBA_CAS# CAS VDDQ RAS VDDQ
FBA_WE# L3 D2 FBA_CAS# K3 C9
B 26,27 FBA_WE# WE VDDQ CAS VDDQ B
E9 FBA_WE# L3 D2 FBx_CMD1
VDDQ F1 WE VDDQ E9
FBA_DQS4 F3 VDDQ H2 VDDQ F1
DQSL VDDQ VDDQ FBx_CMD2 ODT_L
FBA_DQS5 C7 H9 FBA_DQS7 F3 H2
DQSU VDDQ FBA_DQS6 C7 DQSL VDDQ H9
DQSU VDDQ FBx_CMD3 CKE_L
FBA_DQM4 E7 A9 FBx_CMD4 A14 A14
FBA_DQM5 D3 DML VSS B3 FBA_DQM7 E7 A9
DMU VSS E1 FBA_DQM6 D3 DML VSS B3
VSS DMU VSS FBx_CMD5 RST RST
G8 E1
FBA_DQS#4 G3 VSS J2 VSS G8
DQSL VSS VSS FBx_CMD6 A9 A9
FBA_DQS#5 B7 J8 FBA_DQS#7 G3 J2
DQSU VSS M1 FBA_DQS#6 B7 DQSL VSS J8
VSS DQSU VSS FBx_CMD7 A7 A7
FBA_CKE_H M9 M1
VSS P1 VSS M9
VSS VSS FBx_CMD8 A2 A2
FBA_RST# T2 P9 P1
26,27 FBA_RST# RESET VSS VSS
FBA_ODT_H T1 FBA_RST# T2 P9 FBx_CMD9 A0 A0
L8 VSS T9 RESET VSS T1
ZQ/ZQ0 VSS L8 VSS T9
ZQ/ZQ0 VSS FBx_CMD10 A4 A4
1

J1 B1 FBx_CMD11 A1 A1
NC/ODT1 VSSQ

1
R1492 R1493 R1494 L1 B9 J1 B1
10K_0402_5% 10K_0402_5% 243_0402_1% J9 NC/CS1 VSSQ D1 R1495 L1 NC/ODT1 VSSQ B9
NC/CE1 VSSQ NC/CS1 VSSQ FBx_CMD12 BA0 BA0
DIS@ DIS@ DIS@ L9 D8 243_0402_1% J9 D1
NCZQ1 VSSQ E2 DIS@ L9 NC/CE1 VSSQ D8 FBx_CMD13 WE# WE#
2

VSSQ E8 NCZQ1 VSSQ E2

2
VSSQ F9 VSSQ E8
VSSQ VSSQ FBx_CMD14 A15 A15
G1 F9
VSSQ G9 VSSQ G1
VSSQ VSSQ FBx_CMD15 CAS# CAS#
G9
96-BALL VSSQ
FBx_CMD16 CS0#_H
SDRAM DDR3 96-BALL
K4W4G1646B-HC11_FBGA96 SDRAM DDR3 FBx_CMD17
X76@ K4W4G1646B-HC11_FBGA96
C X76@ FBx_CMD18 ODT_H C

FBx_CMD19 CKE_H
FBx_CMD20 A13 A13
FBx_CMD21 A8 A8
FBx_CMD22 A6 A6
FBx_CMD23 A11 A11
FBx_CMD24 A5 A5
FBx_CMD25 A3 A3
+1.5VS_VGA +1.5VS_VGA U1408 SIDE FBx_CMD26 BA2 BA2
U1409 SIDE
FBx_CMD27 BA1 BA1
C1549

0.1U_0402_10V7K

C1555

0.1U_0402_10V7K

C1551

0.1U_0402_10V7K

C1552

0.1U_0402_10V7K

C1554

0.1U_0402_10V7K

C1553

1U_0402_6.3V6K

C1556

1U_0402_6.3V6K

C1557

1U_0402_6.3V6K

C1558

1U_0402_6.3V6K

C1559

1U_0402_6.3V6K

C1560

0.1U_0402_10V7K

C1561

0.1U_0402_10V7K

C1562

0.1U_0402_10V7K

C1567

0.1U_0402_10V7K

C1566

0.1U_0402_10V7K

C1565

1U_0402_6.3V6K

C1568

1U_0402_6.3V6K

C1569

1U_0402_6.3V6K

C1570

1U_0402_6.3V6K

C1571

1U_0402_6.3V6K
FBx_CMD28 A12 A12
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
FBx_CMD29 A10 A10
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

@ @ @ @ @ @ @ FBx_CMD30 RAS# RAS#


2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

D D

Security Classification LC Future Center Secret Data Title


Issued Date 2012/07/01 Deciphered Date 2014/07/01 N14P_GDDR3_A Upper
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 28 of 59

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R1514 +3VS_VGA

Physical Logical Logical Logical Logical


Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0

1
10K_0402_5% R1514 R1515 R1516 R1517 R1518 ROM_SCLK +3VS_VGA PCI_DEVID[4] SUB_VENDOR PCI_DEVID[5] PEX_PLL_EN_TERM
N14MGL@ 45.3K_0402_1% 10K_0402_5% 29.4K_0402_1% 10K_0402_5% 10K_0402_5%
SD02810028J N14PGV2@ X76@ X76@ X76@ @ ROM_SI +3VS_VGA RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]

2
N14M @ ROM_SO +3VS_VGA FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE
STRAP0 N14P @
23 STRAP0
STRAP1 STRAP0 +3VS_VGA USER[3] USER[2] USER[1] USER[0]
23 STRAP1
STRAP2
23 STRAP2
STRAP3 STRAP1 +3VS_VGA 3GIO_PADCFG[3] 3GIO_PADCFG[2] 3GIO_PADCFG[1] 3GIO_PADCFG[0]
23 STRAP3
A STRAP4 A
23 STRAP4
STRAP2 +3VS_VGA PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
R1523
STRAP3 +3VS_VGA SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED

1
R1519 R1520 R1521 R1522 R1523 STRAP4 +3VS_VGA RESERVED PCIE_SPEED_ PCIE_MAX_SPEED DP_PLL_VDD33V
10K_0402_5% 10K_0402_5% 10K_0402_5% 4.99K_0402_1% 10K_0402_5% CHANGE_GEN3
@ X76@ X76@ X76@ N14MGL@
N14M @ 45.3K_0402_1%

2
N14P @ N14PGV2@
SD03445328J Pull-up to
Resistor Values +3VS_VGA Pull-down to Gnd
5K 1000 0000
+3VS_VGA 10K 1001 0001
15K 1010 0010
20K 1011 0011
1

1
25K 1100 0100
R1524 R1525 R1526
10K_0402_5% 4.99K_0402_1% 4.99K_0402_1% 30K 1101 0101
@ N14PGV2@ N14PGV2@
35K 1110 0110
2

2
N14M @
N14P @ 45K 1111 0111
ROM_SI
23 ROM_SI
ROM_SO
23 ROM_SO
ROM_SCLK
23 ROM_SCLK SUB_VENDOR 3GIO_PADCFG[3:0]
ZZZ1 ZZZ2 ZZZ3 ZZZ4 0 No VBIOS ROM 0110 Gen1/Gen2 support only
1

1
B B
R1527 R1528 R1529
10K_0402_5% 10K_0402_5% 10K_0402_5% 1 BIOS ROM is present (Default) 0000 Gen3 support
X76@ N14MGL@ N14MGL@
2

Micron Samsung Samsung Micron


M1G@ S1G@ S2G@ M2G@
X7600108001 X7600108002 X7600108004 X7600108005 FB[1:0] SMBUS_ALT_ADDR VGA_DEVICE
0 Reserved 0 0x9E (Default) 0 3D Device (Class Code 302h)

1 Reserved 1 0x9C (Multi-GPU usage) 1 VGA Device (Default)

GPU FB Memory gDDR3 ROM_SO ROM_SCLK ROM_SI STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 2 256MB (Default)
PCIE_MAX_SPEED PEX_PLL_EN_TERM
Samsung K4W2G1646E-BC1A 3 Reserved
1000MHz PU 5K PU 5K PD 45K PU 45K PD 45K PD 15K PD 5K PD 45K 0 Limit booting to PCIE Gen1 0 Disable (Default)
128Mx16 USER Straps 1 Allow booting to PCIE Gen 2/3 1 Enable
Micron MT41J128M16JT-093G User[3:0]
1000MHz PU 5K PU 5K PD 30K PU 45K PD 45K PD 15K PD 5K PD 45K
128Mx16 1000-1100 Customer defined
PCIE_SPEED_CHANGE_GEN3 DP_PLL_VDD33V
N14P-GV2
0 Disable PCIE Gen3 operation 0 Reserved
Samsung K4W4G1646B-HC11
900MHz PU 5K PU 5K PD 20K PU 45K PD 45K PD 15K PD 5K PD 45K
1 Enable PCIE Gen3 operation 1 Default
256Mx16
C C

Micron MT41K256M16HA-107G ZZZ6 ZZZ7 ZZZ8 ZZZ9

900MHz PU 5K PU 5K PD 10K PU 45K PD 45K PD 15K PD 5K PD 45K


256Mx16

MT41J128M16JT K4W2G1646E K4W4G1646B MT41K256M16HA


M1G@ S1G@ S2G@ M2G@
GPU FB Memory gDDR3 ROM_SO ROM_SCLK ROM_SI STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 SA00005M100 SA00005SH10 SA00005OM00 SA00005ON00

Samsung K4W2G1646E-BC1A
PD 10K PD 10K PD 10K PU 10K PD 10K PU 10K PD 10K PD 10K For N14P-GV2 QS Sample
1000MHz ROM_SO change from PU 10K to PU 5K
128Mx16 ROM_SCLK change from PD 15K to PU 5K
STRAP1 change from PD 5K to PD 45K
Hynix H5TQ2G63DFR-N0C STRAP2 change from PU 30K to PD 15K
1000MHz PD 10K PD 10K PD 10K PD 10K PU 10K PU 10K PD 10K PD 10K STRAP4 change from PD 5K to PD 45K
128Mx16

Micron MT41J128M16JT-093G
1000MHz PD 10K PD 10K PD 10K PU 10K PD 10K PD 10K PD 10K PD 10K
128Mx16
N14M-GL
Samsung K4W4G1646B-HC11
900MHz PD 10K PD 10K PD 10K PU 10K PU 10K PD 10K PU 10K PD 10K
D 256Mx16 D

Hynix H5TQ4G63MFR-11C
900MHz PD 10K PD 10K PD 10K PU 10K PU 10K PD 10K PD 10K PD 10K
256Mx16

Micron MT41K256M16HA-107G Security Classification LC Future Center Secret Data Title


900MHz PD 10K PD 10K PD 10K PU 10K PD 10K PU 10K PU 10K PD 10K
Issued Date 2012/07/01 Deciphered Date 2014/07/01 N14P_MISC
256Mx16
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
X76 X76 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 29 of 59

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A A

B B

C C

D D

Security Classification LC Future Center Secret Data Title


Issued Date 2012/07/01 Deciphered Date 2014/07/01 XXX
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 30 of 59

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1 2 3 4 5

+1.5V to +1.5VS_VGA
+1.5V +1.5VS_VGA
+VSB J1402 @
1 2 +5VALW
1 2

C1513

10U_0603_6.3V6M

C1512

10U_0603_6.3V6M

C1627

0.1U_0402_10V7K
JUMP_43X79
1 1 1

1
Q1404 DIS@

1
AO4430L_SO8 R1549

DIS@

DIS@
R1536 8 1 @ 100K_0402_5%
100K_0402_5% 7 2 2 2 2 DIS@
A DIS@ 6 3 A

2
5 FBVDDQ_PWR_EN#
FBVDDQ_PWR_EN# 31

1
R1539

1
470_0603_5%
R1538 1 DIS@ 2 0_0402_5% @ D
R1547 1 DIS@ 2 10K_0402_5% 2 Q1412
31 FBVDDQ_PWR_EN

1 2
1
R1542 1 @ 2 0_0402_5% G 2N7002K_SOT23-3
43,49,52,9 SUSP

0.01U_0603_50V7K
D S DIS@

1
C1516
FBVDDQ_PWR_EN# R1541 1 2 0_0402_5% 2 Q1410 D R1540 @
31 FBVDDQ_PWR_EN#

3
DIS@ G 2N7002K_SOT23-3 2 1 2 FBVDDQ_PWR_EN# R1548
FBVDDQ_PWR_EN# 31

1
S DIS@ G 0_0402_5% 100K_0402_5%

1
Q1408 S @

DIS@
R1537 2N7002K_SOT23-3 R1543 @

2
100K_0402_5% @ 1 2 SUSP
@ 0_0402_5%

2
+5VALW

+3VS to +3VS_VGA

1
R1545
100K_0402_5%
+5VALW +3VS +3VS_VGA DIS@
J1401 @

2
1 2 DGPU_PWROK#
1 2 DGPU_PWROK# 52
B B
JUMP_43X79

1
D
1

Q1405 DIS@ R1544 1 DIS@ 2 10K_0402_5% 2 Q1411


18,31,52 DGPU_PWROK
R1475 AO3413_SOT23-3 G 2N7002K_SOT23-3
100K_0402_5% C1511 DIS@ S DIS@

1
3

D
DIS@ 1 1 2

3
R1546
2

1
10U_0603_6.3V6M 100K_0402_5%
R1533 @

G
2
R1476 470_0603_5%

2
DGPU_PWR_EN# 1 DIS@ 2 @
10K_0402_5%

1 2
1

R1477 1 @ 2 0_0402_5%
41,43,49,51,9 SUSP# D 0.01U_0402_16V7K
C1515

R1478 1 2 0_0402_5% 2 Q1406 D R1479 @


17,22 DGPU_PWR_EN
DIS@ G 2N7002K_SOT23-3 2 1 2 DGPU_PWR_EN#
2

S DIS@ Q1407 G 10K_0402_5%


1

C1521

0.1U_0402_10V7K
2N7002K_SOT23-3 S
3

R1480 DIS@ @ 1
1

3
DIS@

100K_0402_5%

@
2

+3VS

1
D
2 Q1582
17 DGPU_GC6_EN
G 2N7002_SOT23
R1578 S

3
1 @ 2 D1581
R1579 DIS@ DAN202UT106_SC70-3
FB_CLAMP 1 2 0_0402_5% GC6_EN 2
C C
22,26,41 FB_CLAMP
0_0402_5% 1
FBVDDQ_PWR_EN 31
R1580 3
2 1
10K_0402_5% DIS@

1
@ R1583
R1582 200K_0402_5%
1 2 DIS@
18,31,52 DGPU_PWROK

2
@
0_0402_5%

D D

Security Classification LC Future Center Secret Data Title


Issued Date 2012/07/01 Deciphered Date 2014/07/01 N14P_+3VS/+1.05VS POWER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 31 of 59

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LCD POWER CIRCUIT

Place closed to JLVDS1 LCD/LED PANEL Conn.


+3VS

+LCDVDD +5VALW +3VS Q2102 +LCDVDD +LCDVDD_CONN


PN:SP01000XE00
W=60mils DMIC_CLK
W=60mils

1
A 3 1 1 2 DMIC_1_2 +LEDVDD B+ A

47P_0402_50V8J
R2101 R2102 1 FBMA-L11-201209-221LMA30T_0805 1 1
150_0603_1% 100K_0402_5% C2101 L2102 C2103 R2108

RFC47

47P_0402_50V8J

47P_0402_50V8J
C2109

0.1U_0402_16V4Z

C2124

4.7U_0805_10V4Z
4.7U_0805_10V4Z @ 0.1U_0402_16V4Z 1 1 1 2

47P_0402_50V8J
2200P_0402_50V7K

RFC13

RFC14
1 1 1

1
2 AP2301GN-HF_SOT23-3 2 2 @ @ 0_0805_5%

RFC49

RFC50
@ @

47P_0402_50V8J
2200P_0402_50V7K

0.1U_0402_16V4Z
3
2 2
1 1 1 1

1
2 2 2 C2113 C2112

RFC9

RFC10

RFC48
4.7U_0805_25V6-K 680P_0402_50V7K @ @ @
5 R2103 1 2 220K_0402_5% @

2
Q2415B For RF 2 2 2 2
2N7002KDWH_SOT363-6 1
4

C2107 For RF
6 0.1U_0402_16V4Z (20 MIL) JLCD1
40 45
2 39 40 G5 44
For RF
Q2415A 38 39 G4 43
9/19 Del R1010 R2110
38 G3
PCH_ENVDD 2 2N7002KDWH_SOT363-6 100K_0402_5% 37 42
16 PCH_ENVDD 37 G2
1 2 36 41 For RF
DISPOFF# 35 36 G1
1

35
1

INVPWM 34
R2106 33 34
+3VS_CMOS 33
100K_0402_5% 32
31 32
DMIC_CLK 30 31
35 DMIC_CLK
2

DMIC_1_2 29 30
35 DMIC_1_2 29
+3VS 28
LOGO_LED# 27 28
A LOGO RED LIGHT 39,41 LOGO_LED# 27
+3VALW R1209 1 2 4.99K_0402_1% +3VALW_LOGO 26
0_0402_5% 1 2 R2471 USB20_N13_C 25 26
17 USB20_N13 25
CMOS 0_0402_5% 1 2 R2472 USB20_P13_C 24
17 USB20_P13 24
23
16 LVDS_ACLK 23
22
16 LVDS_ACLK# 22
21
B
L2403 @ 20 21 B
16 LVDS_A2 20
USB20_N13 2 1 USB20_N13_C 19
2 1 16 LVDS_A2# 19
18
16 LVDS_A1 18
17
16 LVDS_A1# 17
USB20_P13 3 4 USB20_P13_C 16
3 4 16 LVDS_A0 16
15
16 LVDS_A0# 15
WCM-2012-900T_4P 14
13 14
16 LVDS_BCLK 13
12
+3VS PN: SM070000K0J x 1 16
16
LVDS_BCLK#
LVDS_B2
11
10
12
11
16 LVDS_B2# 10
9
16 LVDS_B1 9
8
16 LVDS_B1# 8
1

7
16 LVDS_B0 7
R2113 6
16 LVDS_B0# 6
4.7K_0402_5% EDID_DATA 5
16 EDID_DATA 5
@ EDID_CLK 4
16 EDID_CLK 4
@ D2101 +3VS 3
2

2 1 2 3
+LCDVDD_CONN 2
1
RB751V-40_SOD323-2 1
ACES_50398-04071-001
ME@
R2114 1 2 0_0402_5% DISPOFF# +3VS
41 BKOFF# +3VS

R2104 1 2 2.2K_0402_5% EDID_CLK R2118 1 2 10K_0402_5% INVPWM


1

R2115 R2116 R2105 1 2 2.2K_0402_5% EDID_DATA C2116 1 2 220P_0402_50V7K INVPWM


10K_0402_5% 10K_0402_5% 1 1
@ C2110 C2111 C2125 @ 1 2 1000P_0402_50V7K INVPWM
10P_0402_50V8J 10P_0402_50V8J
2

@ @ C2117 1 2 220P_0402_50V7K DISPOFF#


2 2
C C

+3VS

CMOS Camera Conn


1

R2154
4.7K_0402_5%
@ +3VS +3VS_CMOS
@ D2102 Q2105 (20 MIL)
2

2 1 AP2301GN-HF_SOT23-3 CMOS SUSPEND 2.4mA


(20 MIL)
RB751V-40_SOD323-2 3 1 R2150 1 2 0_0603_5%

R2107 1 2 0_0402_5% INVPWM +3VALW


1

47P_0402_50V8J
2200P_0402_50V7K
16 PCH_PWM
C2148 1 1 1

1
0.1U_0402_16V4Z C2114 @ C2115

RFC11

RFC12
1 0.1U_0402_16V4Z 10U_0603_6.3V6M @ @
1

2
1

2
R2153 R2137 C2123 C2427 2 2 2
10K_0402_5% 10K_0402_5% 0.1U_0402_16V4Z 0.01U_0402_16V7K
@ @ @ 2
2
2

R2119 1 2 4.7V
18 CMOS_ON#
150K_0402_5%
1
C2118
0.1U_0402_16V4Z For RF
2
D D

Security Classification LC Future Center Secret Data Title


Issued Date 2012/07/01 Deciphered Date 2014/07/01 LVDS CONN.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Saturday, November 03, 2012 Sheet 32 of 59

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W=40mils
+5VS +R_CRT_VCC +CRT_VCC
D2105 F2101
2 1.1A_6V_SMD1812P110TF W=40mils
1 1 2
A 3 A
RB491D_SOT23-3

C2119
0.1U_0402_16V4Z
1
CRT Connector
2 PN:DC061208040

DAC_RED L2104 1 2 FCM1608CF-121T03_2P RED JCRT1


16 DAC_RED
6
T16 11
DAC_GRN L2105 1 2 FCM1608CF-121T03_2P GREEN 1
16 DAC_GRN
7
12
DAC_BLU L2106 1 2 FCM1608CF-121T03_2P BLUE 2
16 DAC_BLU
8

C2120

10P_0402_50V8J

C2121

10P_0402_50V8J

C2122

10P_0402_50V8J

C2126

10P_0402_50V8J

C2127

10P_0402_50V8J

C2128

10P_0402_50V8J
13
1

1
1 1 1 1 1 1 3
R2120 R2121 R2122 9
150_0402_1% 150_0402_1% 150_0402_1% 14 16
4 17
2 2 2 2 2 2 10
2

15

1
5
R314 R319
0_0603_5% 0_0603_5%
TE_2041480-1
ME@

2
L2109 1 2 FCM1608CF-121T03_2P JVGA_HS
+CRT_VCC CRT_DDC_DAT_CONN
B B
C2129 1 2 0.1U_0402_16V4Z R2123 1 2 1K_0402_5% L2110 1 2 FCM1608CF-121T03_2P JVGA_VS
5

CRT_DDC_CLK_CONN

C2132

100P_0402_50V8J

C2133

68P_0402_50V8J
P

OE#

CRT_HSYNC 2 4 CRT_HSYNC_1 1 1 1 1 1
16 CRT_HSYNC A Y C2130 C2131 C2134
G

U2101 10P_0402_50V8J 10P_0402_50V8J 68P_0402_50V8J


74AHCT1G125GW_SOT353-5 @ @ @ @
3

2 2 2 2 2
+CRT_VCC

C2135 1 2 0.1U_0402_16V4Z 5 R2127 1 2 1K_0402_5%

1
P

OE#
CRT_VSYNC 2 4 CRT_VSYNC_1
16 CRT_VSYNC A Y
G

U2102
74AHCT1G125GW_SOT353-5
3

D2103
D2110 JVGA_VS 3 6 JVGA_HS
BLUE 3 6 RED I/O2 I/O4
I/O2 I/O4

2 5 +R_CRT_VCC
2 5 GND VDD
GND VDD +R_CRT_VCC
C C

CRT_DDC_CLK_CONN 1 4 CRT_DDC_DAT_CONN
1 4 GREEN I/O1 I/O3
I/O1 I/O3 AZC099-04S.R7G_SOT23-6
AZC099-04S.R7G_SOT23-6

+3VS +R_CRT_VCC
+3VS

1
R2124 R2125
4.7K_0402_5% 4.7K_0402_5%

2
2
C2152

100P_0402_50V8J

C2153

100P_0402_50V8J

1 1
CRT_DDC_DATA 1 6 CRT_DDC_DAT_CONN
16 CRT_DDC_DATA
2N7002KDWH_SOT363-6 Q2107A

5
2 2
Chip Conn
CRT_DDC_CLK 4 3 CRT_DDC_CLK_CONN
16 CRT_DDC_CLK
D D
2N7002KDWH_SOT363-6 Q2107B

9/27 ESD

Security Classification LC Future Center Secret Data Title


Issued Date 2012/07/01 Deciphered Date 2014/07/01 CRT CONN.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 33 of 59

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A A

+3VS

1
R2126
1M_0402_5%

2
G
Q2109

2
2N7002K_SOT23-3
16 PCH_DPB_HPD 3 1

1
1
R2129 C2137
20K_0402_5% 220P_0402_50V7K
ESD request @
Common mode choke 90ohm on these singals
2
HDMI Connector

2
Compal PN: SM070000K00
Vendor PN: WCM-2012-900T
PN:DC232001K00
+HDMI_5V +HDMI_5V_OUT
16 PCH_DPB_P3 .1U_0402_16V7K 1 2 C2145 HDMI_CLK+ R2128 1 @ 2 0_0402_5% HDMI_R_CK+ W=40mils JHDMI1
D2106 HDMI_HPD 19
1 2 2 F2102 18 HP_DET
1 2 +5VS
1 1 2
W=40mils 17 +5V
+HDMI_5V
L2111 WCM-2012HS-900T 3 HDMI_SDATA 16 DDC/CEC_GND
4 3 RB491D-YS_SOT23-3 1.1A_6V_SMD1812P110TF HDMI_SCLK 15 SDA
4 3 14 SCL
1 Reserved
16 PCH_DPB_N3 .1U_0402_16V7K 1 2 C2144 HDMI_CLK- R2130 1 @ 2 0_0402_5% HDMI_R_CK- C2136 13
0.1U_0402_16V4Z HDMI_R_CK- 12 CEC 20
B
11 CK- GND 21 B
2 HDMI_R_CK+ 10 CK_shield GND 22
.1U_0402_16V7K 1 2 C2143 HDMI_TX0+ R2131 1 @ 2 0_0402_5% HDMI_R_D0+ HDMI_R_D0- 9 CK+ GND 23
16 PCH_DPB_P2 D0- GND
R2149 1 @ 2 0_0805_5% 8
1 2 HDMI_R_D0+ 7 D0_shield
1 2 HDMI_R_D1- 6 D0+
L2112 WCM-2012HS-900T 5 D1-
4 3 HDMI_R_D1+ 4 D1_shield
4 3 HDMI_R_D2- 3 D1+
.1U_0402_16V7K 1 2 C2142 HDMI_TX0- R2132 1 @ 2 0_0402_5% HDMI_R_D0- 2 D2-
16 PCH_DPB_N2 +3VS +HDMI_5V D2_shield
HDMI_R_D2+ 1
D2+

16 PCH_DPB_P1 .1U_0402_16V7K 1 2 C2141 HDMI_TX1+ R2133 1 @ 2 0_0402_5% HDMI_R_D1+ CONCR_099ATAC19NBLCNF


ME@
1 2
1 2

1
L2113 WCM-2012HS-900T footprint check
4 3 R2148 R2143 R2145 R2146
4 3 2.2K_0402_1% 2.2K_0402_1% 2.2K_0402_5% 2.2K_0402_5%
16 PCH_DPB_N1 .1U_0402_16V7K 1 2 C2140 HDMI_TX1- R2134 1 @ 2 0_0402_5% HDMI_R_D1-

2
2

2
16 PCH_DPB_P0 .1U_0402_16V7K 1 2 C2139 HDMI_TX2+ R2135 1 @ 2 0_0402_5% HDMI_R_D2+ 1 6 HDMI_SCLK
16 HDMICLK_NB
Q2111A
1 2 2N7002KDWH_SOT363-6
1 2

5
L2114 WCM-2012HS-900T
Chip Conn
4 3 4 3 HDMI_SDATA
4 3 16 HDMIDAT_NB
Q2111B

1
16 PCH_DPB_N0 .1U_0402_16V7K 1 2 C2138 HDMI_TX2- R2136 1 @ 2 0_0402_5% HDMI_R_D2- 2N7002KDWH_SOT363-6
C2146 @ C2147 @
Place closed to JHDMI1 47P_0402_50V8J 47P_0402_50V8J

2
C C

HDMI_TX2- R2144 1 2 680_0402_5% HDMI_GND


HDMI_TX2+ R2152 1 2 680_0402_5%

HDMI_TX1- R2139 1 2 680_0402_5%


HDMI_TX1+ R2140 1 2 680_0402_5%

HDMI_TX0- R2141 1 2 680_0402_5%


HDMI_TX0+ R2142 1 2 680_0402_5%

HDMI_CLK- R2151 1 2 680_0402_5% D2113 D2112 D2108


HDMI_CLK+ R2147 1 2 680_0402_5% HDMI_HPD 1 1 10 9 HDMI_HPD HDMI_R_CK- 1 1 10 9 HDMI_R_CK- HDMI_R_D2- 1 1 10 9 HDMI_R_D2-

HDMI_SDATA 2 2 9 8 HDMI_SDATA HDMI_R_CK+ 2 2 9 8 HDMI_R_CK+ HDMI_R_D2+ 2 2 9 8 HDMI_R_D2+


1

UMA 680_0402_5% D HDMI_SCLK 4 4 7 7 HDMI_SCLK HDMI_R_D1- 4 4 7 7 HDMI_R_D1- HDMI_R_D0- 4 4 7 7 HDMI_R_D0-


+3VS 2 Q2110
G 2N7002K_SOT23-3 +HDMI_5V_OUT 5 5 6 6 +HDMI_5V_OUT HDMI_R_D1+ 5 5 6 6 HDMI_R_D1+ HDMI_R_D0+ 5 5 6 6 HDMI_R_D0+
S
3 3 3 3 3 3
3

8 8 8
9/27 ESD
YSCLAMP0524P_SLP2510P8-10-9 YSCLAMP0524P_SLP2510P8-10-9 YSCLAMP0524P_SLP2510P8-10-9

D D

Security Classification LC Future Center Secret Data Title


Issued Date 2012/07/01 Deciphered Date 2014/07/01 HDMI CONN.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 34 of 59

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CX20671 +3VS DVDD_3V


High Definition Audio Codec SoC 1
R2414
2
With Integrated Class-D Stereo

1
0_0603_5% FILT_1.65_R C1135 1 2 1U_0402_6.3V6K
Amplifier. C1127 Near Pin 29
C1136 1 2 0.1U_0402_16V4Z
An integrated 5 V to 3.3 V Low-dropout 4.7U_0603_6.3V6K

2
+3VS
voltage regulator (LDO). Layout Note:Path from +5VS to Pin12, Near Pin 18
Pin15 must be very low
An integrated 3.3 V to 1.8V Low-dropout resistance (<0.01 ohms)

1
voltage regulator (LDO). To support Wake-on-Jack or Wake-on-Ring, the CODEC C1121 C1119
+LDO_OUT_3.3V_R C1133 1 2 4.7U_0603_6.3V6K

VAUX_3.3 & VDD_IO pins must be powerd by a rail that 0.1U_0402_16V4Z 4.7U_0603_6.3V6K C1134 1 2 0.1U_0402_16V4Z Near Pin 27

2
A D2417 RB751V-40_SOD323-2 is not removed unless AC power is removed. @ A
2 1 *DSH page42 has more detail. Near Pin 2
AVDD_3.3 pinis output of internal LDO. NOT connect
to external supply.
EC Beep C1141 1 2 @ PC_BEEP_C_R R1120 1 2 33_0402_5% PC_BEEP_C C1111 1 2 0.1U_0402_16V4Z PC_BEEP +5VS
41 BEEP#

1
0.1U_0402_16V4Z C1116 C1114
PC Beep

1
0.1U_0402_16V4Z 1U_0402_6.3V6K @

2
C1142 1 2 @ C1113 C1112 Near Pin 28
ICH Beep 13 HDA_SPKR @
Near Pin 7 0.1U_0402_16V4Z 4.7U_0603_6.3V6K

2
0.1U_0402_16V4Z

D2416 10 mils FILT_1.8_R


2 1
+3VS

1
RB751V-40_SOD323-2

1
C1132 C1130
R1121 0.1U_0402_16V4Z 4.7U_0603_6.3V6K

1
10K_0402_5% Near Pin 3
C1129 C1124
0.1U_0402_16V4Z 4.7U_0603_6.3V6K
2

2
Near Pin 26
Sense resistors must be
connected same power

18

29

27
28
26
that is used for

3
7
2
10K only needed if supply to VAUX_3.3 U1101
Combo Jack detect (normal open) is removed during system re-start. VAUX_3.3

AVDD_5V
AVDD_HP
FILT_1.8
VDD_IO
VAUX_3.3
DVDD_3.3

FILT_1.65

AVDD_3.3
Near Pin 17
MIC_JD 12 +CLASSD_5V R1122 1 2 0_0805_5% +5VS
R1112 1 @ 2 4.7K_0402_5% LPWR_5.0 15
+3VS RPWR_5.0
HDA_RST#_AUDIO 9 17 C1107 1 2 0.1U_0402_16V4Z
13 HDA_RST#_AUDIO RESET# CLASS-D_REF
Q1103
1

B D LBSS138LT1G_SOT-23-3 R1134 1 2 0_0402_5% HDA_BITCLK_AUDIO_R 5 R1113 1 2 5.11K_0402_1% B


13 HDA_BITCLK_AUDIO BIT_CLK +3VS
2 R1130 1 2 33K_0402_5% EXT_MIC HDA_SYNC_AUDIO 8 36 SENSE_A R1114 1 2 20K_0402_1% MIC_JD Port B
13 HDA_SYNC_AUDIO SYNC SENSE_A
G 1 R1115 1 2 33_0402_5% HDA_SDIN0_R 6 R1116 1 2 39.2K_0402_1% PLUG_IN Port A
13 HDA_SDIN0 SDATA_IN PLUG_IN
S C1146 HDA_SDOUT_AUDIO 4
13 HDA_SDOUT_AUDIO
3

1U_0402_6.3V6K SDATA_OUT 35 PORTB C1108 1 2 2.2U_0402_6.3V6M R1133 1 2 100_0402_1% EXT_MIC


PORTB_R 34
External MIC
2 PORTB_L 1109
PLUG_IN EAPD active low 33 +MICBIASB
PC_BEEP 10 B_BIAS
0=power down ex AMP PC_BEEP +MICBIASB
1=power up ex AMP C_BIAS
32
CX_GPIO0 R1129 1 @ 2 33K_0402_5% 31 EXT_MIC R1132 1 2 2K_0402_5% R1128 1 2 4.7K_0402_5%
PORTC_R 30
1 @ PORTC_L
C1147 R1111 1 2 0_0402_5% CX_GPIO0 38
1U_0402_6.3V6K EAPD GPIO0/EAPD#
R1131 1 2 0_0402_5% 37
41 EC_MUTE# GPIO1/SPK_MUTE#
@ 23 HP_OUTR_R R1117 1 2 39_0402_5% HP_OUTR Headphone
2 PORTA_R 22 HP_OUTL_R R1118 1 2 39_0402_5% HP_OUTL
PORTA_L
R1125 1 2 DMIC_CLK_R 40
32 DMIC_CLK DMIC_CLK
DMIC_CLK Internal DMIC FBMA-10-100505-301T_2P 1 24
Decoupling CAP DMIC_1_2
32 DMIC_1_2 DMIC_1/2 NC
NC
25
39
Changed from 5.1ohm to 15ohm
+CLASSD_5V 11 NC for "zi zi"noise.
SPK_L2+
SPK_L1- 13 LEFT+
47P_0402_50V8J

47P_0402_50V8J

C1115 1 2 0.1U_0402_16V4Z LEFT- 21 AVEE C1122 1 2 0.1U_0402_16V4Z


1 1 AVEE
Near Pin 12 Internal SPEAKER 19 FLY_P Near Pin 21
RFC15

RFC16

C1117 1 2 10U_0603_6.3V6M @ @ SPK_R2+ 16 FLY_P 20 FLY_N C1110 1 2 C1125 1 2 4.7U_0603_6.3V6K


SPK_R1- 14 RIGHT+ FLY_N
C1118 1 2 0.1U_0402_16V4Z 2 2 RIGHT- 1U_0402_6.3V6K

GND
Near Pin 15
C1120 @1
@ 2 10U_0603_6.3V6M
CX20671-21Z_QFN40_6X6

41
C
For RF Internal Speaker C
CA8
0.1U_0402_16V4Z JAUHP HP_OUTL HP_OUTR
2 1 EXT_MIC 3
6
DC030008W00

2
@
CA6 HP_OUTL 1 DA1
0.1U_0402_16V4Z PESD5V0U2BT_SOT23-3
2 1 HP_OUTR 2
4 JSPK2
@ SPK_R1- L1102 1 2 0_0603_5% SPK_R1-_CONN SPK_R1-_CONN 1

1
CA1 PLUG_IN 5 SPK_R2+ L1103 1 2 0_0603_5% SPK_R2+_CONN SPK_R2+_CONN 2 1
0.1U_0402_16V4Z 3 2
2 1 4 G1
G2

C1139

1000P_0402_50V7K

C1140

1000P_0402_50V7K
SINGA_2SJ2326-001111 EMC request
@ ME@ Bead 120ohm on these singals 1 1 ACES_85204-02001
CA2 @ @ @ EXT_MIC PLUG_IN ME@
JV PN: SM01001670J
1

0.1U_0402_16V4Z CA3 CA4 CA5


2 1 1000P_0402_50V7K 1000P_0402_50V7K 1000P_0402_50V7K Vendor PN: FBMA-L11-160808-121LMT @ @
3

2
2 2
2

@ DA2 Rdc < 0.05 ohms


PESD5V0U2BT_SOT23-3 Rated Current > 2A
JSPK1
SPK_L1- L1104 1 2 0_0603_5% SPK_L1-_CONN SPK_L1-_CONN 1
1

SPK_L2+ L1105 1 2 0_0603_5% SPK_L2+_CONN SPK_L2+_CONN 2 1


3 2
4 GND
EMI EMI GND

C1137

1000P_0402_50V7K

C1138

1000P_0402_50V7K
1 1 ACES_85205-02001
Width 20 mil ME@

C1102 1 2 0.1U_0402_16V4Z @ @
2 2
C1103 1 2 0.1U_0402_16V4Z
D D
C1104 1 2 0.1U_0402_16V4Z

HDA_RST#_AUDIO
EMI C1123 @1
@ 2 22P_0402_50V8J

HDA_SYNC_AUDIO C1126 @1
@ 2 22P_0402_50V8J R1102 1 2 0_0402_5%

HDA_SDOUT_AUDIO C1128 @1
@ 2 22P_0402_50V8J R1104 1 2 0_0402_5%
Security Classification LC Future Center Secret Data Title
HDA_BITCLK_AUDIO R1123 1 2 33_0402_5% HDA_BITCLK_AUDIO_C C1131 1 2 22P_0402_50V8J R1105 1 2 0_0402_5%
Issued Date 2012/07/01 Deciphered Date 2014/07/01 HD Audio Codec_CX20671
9/28 RF modify THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
GND NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
GND GNDA DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 35 of 59

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SATA HDD CONN.

PN:SP01001HE00
JHDD1

1
SATA_PTX_DRX_P0 2 GND
13 SATA_PTX_DRX_P0 A+
SATA_PTX_DRX_N0 3
13 SATA_PTX_DRX_N0 A-
4
SATA_DTX_C_PRX_N0 C2401 1 2 0.01U_0402_16V7K SATA_DTX_PRX_N0 5 GND
A A
13 SATA_DTX_C_PRX_N0 B-
SATA_DTX_C_PRX_P0 C2402 1 2 0.01U_0402_16V7K SATA_DTX_PRX_P0 6
13 SATA_DTX_C_PRX_P0 B+
7
+3VS GND

8
9 V33
10 V33
11 V33
12 GND
41 HDD_DETECT# GND
13
+5VS @ J2401 14 GND
1 2 5VS_HDD 15 V5
1 2 16 V5
JUMP_43X79 17 V5
18 GND
19 Reserved 23
20 GND GND 24
+5VS 21 V12 GND
22 V12
V12
C2403

1000P_0402_50V7K

C2405

1U_0402_6.3V6K

C2406

10U_0603_6.3V6M

SANTA_198002-1
1 1 1 ME@

@ @
2 2 2 Pin 18 to GND for Gen 3

B B

SATA ODD CONN. APS G-Sensor


PN:SP01000TU10

for Edge 14''

1
JODD1 R2402
100K_0402_5%
1
SATA_PTX_DRX_P2 SATA_PTX_DRX_P2 2 GND1 U2401
13 SATA_PTX_DRX_P2

2
SATA_PTX_DRX_N2 SATA_PTX_DRX_N2 3 A+_RX+
13 SATA_PTX_DRX_N2 A-_RX-
4 2 12 VOUTX R2403 1 2 56K_0402_5%
GND2 41 GS_SELFTEST ST Xout GS_VOUTX 41
SATA_DTX_C_PRX_N2 C2408 1 2 0.01U_0402_16V7K SATA_DTX_PRX_N2 SATA_DTX_PRX_N2 5 10 VOUTY R2404 1 2 56K_0402_5%
13 SATA_DTX_C_PRX_N2 B-_TX- +3VS +3VS_GS Yout GS_VOUTY 41
SATA_DTX_C_PRX_P2 C2409 1 2 0.01U_0402_16V7K SATA_DTX_PRX_P2 SATA_DTX_PRX_P2 6 8
13 SATA_DTX_C_PRX_P2 B+_TX+ Zout
7
+5VS_ODD GND3 R2405 1 @ 2 0_0603_5% 14
Vs

C2411

.1U_0402_16V7K

C2414

.1U_0402_16V7K

C2412

.1U_0402_16V7K

C2415

.1U_0402_16V7K
15
Vs

C2413

10U_0603_6.3V6M

C2410

.1U_0402_16V7K
ODD_DETECT#_R 8 1 1 1 1
+5VS_ODD +5VS_ODD 9 DP 1
+5V_1 1 1 NC
10 11/17 4
R2406 1 2 0_0402_5% ODD_DA#_R ODD_DA#_R 11 +5V_2 3 NC 9
17 ODD_DA# MD BOM modify COM NC 2 2 2 2
C 12 14 5 11 C
13 GND4 GND6 15 2 2 6 COM NC 13
Q2406 GND5 GND7 7 COM NC 16
2N7002K_SOT23-3 COM NC
SUYIN_127382FB013M283ZR APS_GND
1 3 ODD_DETECT#_R ME@ LIS34ALTR_LGA16_4X4
D

13 ODD_DET#
APS_GND J2402
1 2
G
2

2MM
14 ON_ODD_DET
@
APS_GND

ODD_DA# C2155 1 2 220P_0402_50V7K

+3VS +3VS_GS
+VSB +5VS +5VS_ODD Q2402
AP2301GN-HF_SOT23-3
R2409
R2407 1 @ 2 0_0805_5% 3 1 1 2
1

C2425

0.1U_0402_16V4Z

C2407

10U_0603_6.3V6M

11/17 1 0_0603_5% 1
47P_0402_50V8J
2200P_0402_50V7K
D

1
R2408 6 1 1 1 1 C2420
S

470K_0402_5% 5 4 @ R2138 C2417 10U_0603_6.3V6M


RFC45

RFC46

2
C2416 2 @ @ 150K_0402_5% C2426 0.1U_0402_16V4Z @
1U_0402_6.3V6K 1 Q2401 @ 0.01U_0402_16V7K 2 2
2

2 2 2 2
G

2
2
3

SI3456DDV-T1-GE3_TSOP6 R2410
GS_ON# 1 2
41 GS_ON#
ODD_EN 150K_0402_5%
1

D D
1
1

D 1
2 C2419 C2418
18 ODD_EN# 0.1U_0603_25V7K
G R2411 For RF 0.01U_0402_16V7K
Q2403 S 1.5M_0402_5% 2
2N7002K_SOT23-3 2
3

Security Classification LC Future Center Secret Data Title


Issued Date 2012/07/01 Deciphered Date 2014/07/01 HDD/ODD/Card reader/G-Sen
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 36 of 59

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USB 3.0 Conn.

A A

D2411
USB3_TX2_C_P 1 1 10 9 USB3_TX2_C_P

L2402 L2406 L2407 USB3_TX2_C_N 2 2 9 8 USB3_TX2_C_N


USB20_N2 2 1 USB20_N2_C USB3TXDP2 3 4 USB3_TX2_C_P USB3_RX2_P3 4 USB3_RX2_C_P
2 1 3 4 3 4 4 4
B
USB3_RX2_C_P 7 7 USB3_RX2_C_P
B
+USB_VCCB
W=80mils USB20_P2 3 4 USB20_P2_C USB3TXDN2 2 1 USB3_TX2_C_N USB3_RX2_N2 1 USB3_RX2_C_N USB3_RX2_C_N 5 5 6 6 USB3_RX2_C_N
3 4 2 1 2 1
WCM-2012-900T_4P WCM-2012HS-900T WCM-2012HS-900T 3 3
+5VALW +USB_VCCB

PN: SM070000K00 x 1 PN: SM070001S00 x 2 8


1000P_0402_50V7K

C2216

Low Active 1 JUSB2 YSCLAMP0524P_SLP2510P8-10-9


0.1U_0402_10V6K 1 2 C2511 USB3TXDP2 0_0402_5% 1 @ 2 R2425 USB3_TX2_C_P 9
17 USB3_TX2_P SSTX+
1
U2409 0.1U_0402_10V6K 1 2 C2446 USB3TXDN2 0_0402_5% 1 @ 2 R2426 USB3_TX2_C_N 8 VBUS
2 17 USB3_TX2_N SSTX-
C2421 1 8 0_0402_5% 1 @ 2 R2421 USB20_P2_C 3
GND VOUT 17 USB20_P2 D+
0.1U_0402_16V4Z 2 7 7
1 2 3 VIN VOUT 6 0_0402_5% 1 @ 2 R2422 USB20_N2_C 2 GND 10
VIN VOUT 17 USB20_N2 D- GND
USB_ON# 4 5 0_0402_5% 1 @ 2 R2465 USB3_RX2_C_P 6 11
41 USB_ON# EN FLG USB_OC1# 17 17 USB3_RX2_P SSRX+ GND
4 12
G547I2P81U_MSOP8 0_0402_5% 1 @ 2 R2466 USB3_RX2_C_N 5 GND GND 13
1 17 USB3_RX2_N SSRX- GND
C2424
1000P_0402_50V7K SUYIN_020053GR009M2106L
@ D2403 ME@
2 USB20_P2_C 1 4
I/O1 I/O3
+USB_VCCB

2 5
PN:DC233008A00
GND VDD 9/27 ESD

3 6 USB20_N2_C
I/O2 I/O4
AZC099-04S.R7G_SOT23-6

C
PN: SC300001G00 C

+USB_VCCB
D2415
L2401 USB3_TX0_C_P 1 1 10 9 USB3_TX0_C_P
USB20_P0 2 1 USB20_P0_C
2 1

C2422

150U_B2_6.3VM_R35M

C2423

470P_0402_50V7K
USB3_TX0_C_N 2 2 9 8 USB3_TX0_C_N
1
USB20_N0 3 4 USB20_N0_C L2408 L2409 USB3_RX0_C_P 4 4 7 7 USB3_RX0_C_P
3 4 1
USB3TXDP0 3 4 USB3_TX0_C_P USB3_RX0_P 3 4 USB3_RX0_C_P +
WCM-2012-900T_4P 3 4 3 4 5 5
USB3_RX0_C_N 6 6 USB3_RX0_C_N

USB3TXDN0 2 1 USB3_RX0_N 2 1 USB3_RX0_C_N 2 2 3 3


PN: SM070000K00 x 1 2 1
USB3_TX0_C_N
2 1
8
WCM-2012HS-900T WCM-2012HS-900T

YSCLAMP0524P_SLP2510P8-10-9
PN: SM070001S00 x 2
JUSB3
0.1U_0402_10V6K 1 2 C2445 USB3TXDP0 0_0402_5% 1 @ 2 R2461 USB3_TX0_C_P 9
17 USB3_TX0_P SSTX+
1
0.1U_0402_10V6K 1 2 C2444 USB3TXDN0 0_0402_5% 1 @ 2 R2462 USB3_TX0_C_N 8 VBUS
17 USB3_TX0_N SSTX-
USB20_P0 0_0402_5% 1 @ 2 R2413 USB20_P0_C 3
17 USB20_P0 D+
7
USB20_N0 0_0402_5% 1 @ 2 R2412 USB20_N0_C 2 GND 10
17 USB20_N0 D- GND
0_0402_5% 1 @ 2 R2467 USB3_RX0_C_P 6 11
17 USB3_RX0_P SSRX+ GND
4 12
0_0402_5% 1 @ 2 R2468 USB3_RX0_C_N 5 GND GND 13
17 USB3_RX0_N SSRX- GND
SUYIN_020053GR009M2106L
ME@
D2401
D USB20_P0_C 1 4 D
I/O1 I/O3
+USB_VCCB

2
GND VDD
5 PN:DC233008A00
9/27 ESD

3 6 USB20_N0_C
I/O2 I/O4 Title
Security Classification LC Future Center Secret Data
AZC099-04S.R7G_SOT23-6
Issued Date 2012/07/01 Deciphered Date 2014/07/01 USB 3.0 CONN.
PN: SC300001G00 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 37 of 59

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Mini Card Power Rating


Mini-Express Card for WLAN(Half) BT Connector
Power Primary Power (mA) Auxiliary Power (mA)
Mini-Express Card(WLAN)
+3VS +3VS_AOAC +1.5VS +3VS_AOAC +1.5VS
Peak Normal Normal
PN:SP07000JP00 +3VS 1000 750
+3V 330 250 250 (wake enable)

C2452

10U_0603_6.3V6M

C2455

0.1U_0402_16V4Z
J2403 1 1 +1.5VS 500 375 5 (Not wake enable)

1
JUMP_43X79
@

2
2 2

2
JMINI2
A A
WLAN_WAKE# 1 2
41 WLAN_WAKE# 1 2 +3VALW
3 4
WLBT_OFF_5# R2434 1 2 0_0402_5% BT_OFF#_R 5 3 4 6
13 WLBT_OFF_5# 5 6
WLAN_CLKREQ1# 7 8 LPC_FRAME#_R For RF
14 WLAN_CLKREQ1# 7 8
9 10 LPC_AD3_R
11 9 10 12 LPC_AD2_R
14 CLK_PCIE_WLAN1# 11 12
13 14 LPC_AD1_R

47P_0402_50V8J
2200P_0402_50V7K
14 CLK_PCIE_WLAN1 13 14
15 16 LPC_AD0_R 1
15 16

1
PCI_RST#_R 17 18

RFC30

RFC29
R2427 1 2 1K_0402_5% CLK_PCI_DB_R 19 17 18 20 RF_OFF# @ @
17 BT_DET# 19 20 RF_OFF# 41
21 22 PLT_RST#
PLT_RST# 14,17,22,39,40,41,42,5

2
23 21 22 24 2
14 PCIE_PRX_DTX_N2 23 24
25 26
14 PCIE_PRX_DTX_P2 25 26
27 28
29 27 28 30 SMB_CLK_S3
29 30 SMB_CLK_S3 11,12,14,39
31 32 SMB_DATA_S3
14 PCIE_PTX_C_DRX_N2 31 32 SMB_DATA_S3 11,12,14,39
33 34
14 PCIE_PTX_C_DRX_P2 33 34
35 36
+3VS_AOAC 35 36 USB20_N10 17
37 38
37 38 USB20_P10 17
39 40
41 39 40 42
9/19 41 42
43 44
45 43 44 46
R2432 47 45 46 48 +3VALW +3VS_AOAC
47 48 For AOAC assessment +VSB
EC_TX_P80_DATA 1 2 100_0402_1% 49 50
40,41 EC_TX_P80_DATA 49 50
EC_RX_P80_CLK 1 2 100_0402_1% 51 52 @
40,41 EC_RX_P80_CLK 51 52
R2433 R2485 1 2 0_0805_5%

1
1 2 R2470 53 54
18 WLBT_OFF_51# GND1 GND2
1K_0402_5% R2482

D
BELLW_80003-3041 470K_0402_5% 6

S
AOAC@ 1 5 4
1

For EC to detect ME@ C2509 2

2
R2435 1U_0402_6.3V6K 1 Q2400
debug card 100K_0402_5% AOAC@ SI3456DDV-T1-GE3_TSOP6

G
B insert. if AOAC enable +3VS_AOAC always ON 2 AOAC@ B

3
R2483
if AOAC disable +3VS_AOAC same +3VS Reserve for SW mini-pcie debug card.
2

WLAN_EN 1 2
0_0402_5%
Series resistors closed to KBC side.

1
AOAC@

1
D 1 LPC_FRAME#_R R2449 1 2 0_0402_5% LPC_FRAME#
LPC_FRAME# 13,40,41
2 LPC_AD3_R R2455 1 2 0_0402_5% LPC_AD3
41 AOAC_WLAN LPC_AD3 13,40,41
G R2481 C2501 LPC_AD2_R R2456 1 2 0_0402_5% LPC_AD2
LPC_AD2 13,40,41
from EC Q2404 S 1.5M_0402_5% .1U_0603_25V7K LPC_AD1_R R2457 1 2 0_0402_5% LPC_AD1
2 AOAC@ LPC_AD1 13,40,41
2N7002K_SOT23-3 AOAC@ LPC_AD0_R R2458 1 2 0_0402_5% LPC_AD0
LPC_AD0 13,40,41

2
AOAC@ PCI_RST#_R R2459 1 2 0_0402_5% PLT_RST#
CLK_PCI_DB_R R2428 1 2 0_0402_5% CLK_PCI_DB
CLK_PCI_DB 17,40

Mini-Express Card for WWAN/mSATA(Full)


@
1 2 +3VS_AOAC R2436 3G@
1 2 UIM_DATA 1 2 +UIM_PWR
J2406 JUMP_43X79
20K_0402_5%
R2446 @ @ +3VS R2439 @
1 2 1 2 +3VS UIM_VPP 1 2 +UIM_PWR
1 2 10K_0402_5% +3VS
10K_0402_5% JMINI1 J2404 JUMP_43X79
1 2 +3VS_WWAN
18 mSATA_PCH PRESENCE# 3.3VAUX1
R294 1 2 0_0402_5% 3 4
41 mSATA_DETEC# GND 3.3VAUX2
5 6
7 GND FULL_CARD_POWER_OFF# 8 JSIM1
17 USB20_P12 USB_D+ W_DISABLE# 3G_OFF# 18
9 10 R2441 @ D2407
17 USB20_N12 USBD- LED#

4
11 12 1 2 +3VS_WWAN UIM_DET 1 40mil 3
13 GND NC 14 10K_0402_5% D2406 +UIM_PWR 2 CD +UIM_PWR 1

VDD
I/O4

I/O3
SSD@ 15 NC NC 16 3G@ 3 C1 2
C C
R2442 1 2 10K_0402_5% 17 NC NC 18 UIM_RST 4 C5
19 NC NC 20 @ UIM_VPP 5 C2 DAN217T146_SC59-3
R2440 1 @ 2 10K_0402_5% 21 NC AUDIO0 22 UIM_CLK 6 C6
18 3G_DET# WWAN_DETECT# AUDIO1 C3
23 24 UIM_DATA 7 1 1
R2475 1 3G@ 2 10K_0402_5% 25 RESERVED1 AUDIO2 26 C7 C2457 C2458

GND
RESERVED2 AUDIO3 GPS_OFF# 18

I/O2

I/O1
27 28 AZC099-04S.R7G_SOT23-6 8 4.7U_0603_6.3V6K 0.1U_0402_16V4Z
29 GND UIM-RFU 30 UIM_RST 9 GND 3G@ 3G@
31 USB3.0-RX- UIM-RESET 32 UIM_CLK GND 2 2

1
33 USB3.0-RX+ UIM-CLK 34 UIM_DATA
35 GND UIM-DATA 36 +UIM_PWR PLAST_CE1S-148-H-N_7P-T
37 USB3.0-TX- UIM-PWR 38
USB3.0-TX+ DEVSLP 1
0.01U_0402_16V7K 39 40 C2459 ME@
C2461 1 2 SATA_DTX_PRX_P1 41 GND GNSS0 42 0.1U_0402_16V4Z
13 SATA_DTX_C_PRX_P1 SATA-B+ GNSS1
C2462 1 2 SATA_DTX_PRX_N1 43 44 3G@
13 SATA_DTX_C_PRX_N1 SATA-B- GNSS2 2
45 46 +1.8VS
13 SATA_PTX_DRX_N1
0.01U_0402_16V7K SATA_PTX_DRX_N1
SATA_PTX_DRX_P1
47
49
GND
SATA-A-
GNSS3
GNSS4
48
50
PN:SP
13 SATA_PTX_DRX_P1 SATA-A+ RESERVED5
51 52
GND RESERVED6
2
53 54
55 RESERVED3 RESERVED7 56 R2463
57 RESERVED4 NC3 58 +3VS_WWAN
GND NC4 10K_0402_5%
59 60 3G@
61 ANTCTRL0 COEX3 62 For RF
1

63 ANTCTRL1 COEX2 64 R2438 3G@


65 ANTCTRL2 COEX1 66 1 2 UIM_DET
PLT_RST# R2437 1 @ 2 0_0402_5% 67 ANTCTRL3 SIM_DETECT 68

2200P_0402_50V7K
RESET# SUSCLK

C2451

10U_0603_6.3V6M

C2453

47P_0402_50V8J
R2473 1 3G@ 2 10K_0402_5% 69 70 0_0402_5%
PCIE_DETECT 3.3VAUX3
2

1
71 72

RFC31
GND 3.3VAUX4 1 1
73 74 R2464 @
R2474 1 3G@ 2 10K_0402_5% 75 GND 3.3VAUX5
10K_0402_5%

2
USB3.0_DETECT @
3G@ 2 2
76 77
1

PEG1 PEG2

D D
TYCO_2199230-3 ME@

PN:SP01072413J

Security Classification LC Future Center Secret Data Title


Issued Date 2012/07/01 Deciphered Date 2014/07/01 PCIe-WLAN and WWAN_mSATA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 38 of 59

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INT_KBD Conn. Click pad Track point


PN:SP01001BX00 PN:SP01120802J
PN:SP011208010 +5VS

JCP1
JKB1 12 14 1
R2469 1 2 0_0402_5% 11 12 GND 13
11,12,14,38 SMB_CLK_S3 11 GND
KSI1 32 34 10 C2508
Fn_LED# C2467 1 2 @ 100P_0402_50V8J KSI7 31 32 GND2 33 +5VS TP_DATA2 9 10 0.1U_0402_16V4Z
KSI6 30 31 GND1 TP_CLK2 8 9 2
F1_LED# C2468 1 2 @ 100P_0402_50V8J KSO9 29 30 R2479 1 2 0_0402_5% 7 8
KSI[0..7] 29 11,12,14,38 SMB_DATA_S3 7
A KSI4 28 6 JTP1 A
KSI[0..7] 41 28 6
F4_LED# C2469 1 2 @ 100P_0402_50V8J KSI5 27 CP_RESET# 5 TP_DATA2 1
KSO[0..15] 27 41 CP_RESET# 5 1
KSO0 26 TP_CLK 4 TP_RESET 2
KSO[0..15] 41 26 41 TP_CLK 4 41 TP_RESET 2
KSI2 25 TP_DATA 3 3
25 41 TP_DATA 3 3
KSI3 24 2 4
24 41 TP4RST 2 4
KSO5 23 1 1 1 5
23 41 BYPASS_PAD 1 5
KSO2 C2470 1 2 @ 100P_0402_50V8J KSO1 C2471 1 2 @ 100P_0402_50V8J KSO1 22 TP_CLK2 6
KSI0 21 22 C2474 C2475 ACES_51522-01201-001 7 6
KSO15 C2472 1 2 @ 100P_0402_50V8J KSO7 C2473 1 2 @ 100P_0402_50V8J KSO2 20 21 100P_0402_50V8J 100P_0402_50V8J 8 7
KSO4 19 20 @ 2 2@ ME@ 9 8
KSO6 C2476 1 2 @ 100P_0402_50V8J KSI2 C2477 1 2 @ 100P_0402_50V8J KSO7 18 19 10 9
KSO8 17 18 11 10 13
KSO8 C2478 1 2 @ 100P_0402_50V8J KSO5 C2479 1 2 @ 100P_0402_50V8J KSO6 16 17 12 11 GND1 14
KSO3 15 16 12 GND2
KSO13 C2480 1 2 @ 100P_0402_50V8J KSI3 C2481 1 2 @ 100P_0402_50V8J KSO12 14 15
KSO13 13 14 JAE_FL10S012HA1
KSO12 C2482 1 2 @ 100P_0402_50V8J KSO14 C2483 1 2 @ 100P_0402_50V8J KSO14 12 13
KSO11 11 12 ME@
KSO11 C2484 1 2 @ 100P_0402_50V8J KSI7 C2485 1 2 @ 100P_0402_50V8J KSO10 10 11
300_0402_5% KSO15 9 10
KSO10 C2486 1 2 @ 100P_0402_50V8J KSI6 C2487 1 2 @ 100P_0402_50V8J 2 1 R372 8 9
+3VS 8
Fn_LED# 7
18 FN_LED# 7
KSO3 C2488 1 2 @ 100P_0402_50V8J KSI5 C2489 1 2 @ 100P_0402_50V8J F1_LED# 6
18 F1_LED# 6
F4_LED# 5 TP_CLK TP_DATA2
18 F4_LED# 5
KSO4 C2490 1 2 @ 100P_0402_50V8J KSI4 C2491 1 2 @ 100P_0402_50V8J KB_FN 4
41 KB_FN 4
KSO16 3 TP_DATA TP_CLK2
KSI0 C2492 1 2 @ 100P_0402_50V8J KSO9 C2493 1 2 @ 100P_0402_50V8J KSO17 2 3 +5VS
41 KSO17 2
KSO18 1
41 KSO18 1

2
KSO0 C2494 1 2 @ 100P_0402_50V8J KSI1 C2495 1 2 @ 100P_0402_50V8J

KSO17 C2506 1 2 @ 100P_0402_50V8J KB_FN C2496 1 2 @ 100P_0402_50V8J JAE_FL10S032HA1 R2443 1 2 4.7K_0402_5% TP_CLK2
D2408 D2409
KSO18 C2507 1 2 @ 100P_0402_50V8J KSO16 C2497 1 2 @ 100P_0402_50V8J ME@ R2444 1 2 4.7K_0402_5% TP_DATA2 PJDLC05_SOT23-3 PJDLC05_SOT23-3
@ @
R2445 1 2 4.7K_0402_5% TP_RESET
B R2486 1 2 0_0402_5% B

CONN PIN define need double check <BOM Structure>

1
R2447 1 2 100K_0402_1% CP_RESET#

PN: SCA00000A0J X 2

Fintek thermal sensor


placed near by TOP DDR3
Audio+CR Board
+3VS +3VS FAN CONN.
1

+5VS
R2448 JUCR
10K_0402_5% +5VALW 1
@ 2 1
2
1

U2407 3
2

4 3
0_0603_5% 5 4
1 10 EC_SMB_CK2 R2478 6 5
VDD SMCLK EC_SMB_CK2 14,22,41 +3VALW 6
+3VS 7
2

REMOTE1+ 2 9 EC_SMB_DA2 8 7
DP1 SMDATA EC_SMB_DA2 14,22,41 8
C 1 LOGO_LED# 9 C
32,41 LOGO_LED# 9
C2498 REMOTE1- 3 8 USB_OC0# 10
DN1 ALERT# 17 USB_OC0# 10
0.1U_0402_16V4Z C2499 @ 1 2 1U_0402_6.3V6K AOU_EN 11
41 AOU_EN 11
REMOTE2+ 4 7 R2450 1 @ 2 AOU_CTL2 12
2 DP2/DN3 THERM# MAINPWON 41,45,46,48 41 AOU_CTL2 12
0_0402_5% AOU_CTL3 13
41 AOU_CTL3 13
REMOTE2- 5 6 14
DN2/DP3 GND USB20_N9 15 14
17 USB20_N9 15
40mil USB20_P9 16
17 USB20_P9 16
F75303M_MSOP10 +VCC_FAN1 17
JFAN1 PCIE_PRX_DTX_P1 18 17
Address 1001_101xb 1
14 PCIE_PRX_DTX_P1
PCIE_PRX_DTX_N1 19 18
41 EC_FAN_PWM 1 14 PCIE_PRX_DTX_N1 19
2 20
3 2 21 20
2nd source 41 EC_TACH 3 14 PCIE_PTX_C_DRX_P1
PCIE_PTX_C_DRX_P1
21
4 6 PCIE_PTX_C_DRX_N1 22
SA000029210-->EMC1403-2-AIZL-TR 5 4 GND 7
14 PCIE_PTX_C_DRX_N1
23 22
41 FAN_ID 5 GND 23
CARD_CLKREQ# 24
14 CARD_CLKREQ# 24
1 ACES_85205-05001 CLK_PCIE_CARD 25
14 CLK_PCIE_CARD 25
C2503 ME@ CLK_PCIE_CARD# 26
14 CLK_PCIE_CARD# 26
1000P_0402_50V7K PLT_RST# 27
14,17,22,38,40,41,42,5 PLT_RST# 27
@ 28
BOTTOM DDR3 2 29 28
Close U2407 REMOTE1+ 30 GND1
REMOTE1+ GND2
1

1 C ACES_88194-2841
@ C2500 2 Q2407 ME@
C2502 2200P_0402_25V7K B MMST3904-7-F_SOT323-3
PN:SP02000U900
2

2200P_0402_25V7K E
3

2 REMOTE1- REMOTE1-

need change to 28 Pin


REMOTE2+
1
REMOTE2+
TOP CPU_CORE
D D
C2504
1

2200P_0402_25V7K C
2 REMOTE2- @ C2505 2 Q2408
2200P_0402_25V7K B MMST3904-7-F_SOT323-3
2

E
3

REMOTE2-

Security Classification LC Future Center Secret Data Title


REMOTE1,2+/-:
Issued Date 2012/07/01 Deciphered Date 2014/07/01 KB/TP/Thermal Sensor/Audio
Trace width/space:10/10 mil
Trace length:<8" THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 39 of 59

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Power Button CONN. Finger Print Board

ON/OFF switch
Power Button PN:SP01000R400 PN:SP01000R400
SW2 +3VLP +3VALW
1 3
Power Button

1
TOP Side 2 4 +3VLP
R113
A SMT1-05_4P 0_0402_5% 0_0402_5% A
6
5

1
R114 @
R2453 11/21 +3VS JFPB1

2
J2405 100K_0402_5% 8
1 2 JPWR1 7 GND2
Bottom Side GND1
1

2
SHORT PADS R2460 @ ON/OFFBTN# 2 1 6
@ 1 2 3 2 5 6
3 17 USB20_P11 5
4 4
41 LID_SW# 4 17 USB20_N11 4
100K_0402_5% 3
3

2
5 2
6 GND 1 2
1

2
3 GND D2413 C2512 1
ON/OFF 41 42 ON/OFFBTN#
ON/OFFBTN# 1 ACES_88514-0401 AZC199-02SPR7G_SOT23-3 0.1U_0402_10V6K ACES_88514-0060N-071

1
2 51_ON# ME@ FP@ FP@
51_ON# 45 2 ME@

1
D2412
BAV70W_SOT323-3

1
D
EC_ON 2 Q2409
41,48 EC_ON
G 2N7002K_SOT23-3
3 S
1

R2454
100K_0402_5%
2

B B

Touch Panel

TPM +3VS

JTouch
+3VS 1
2 1
3 2
+3VS +3VALW 4 3
14 SMB_DATA_TPanel 4
14 SMB_CLK_TPanel 5
U10 TPM@ JDB3 6 5
1 24 C589 1 2 10U_0603_6.3V6M 1 7 6
SDA VPS 1 17 USB20_N4 7
2 10 C645 1 2 0.1U_0402_16V4Z 2 8
SCL VPS 2 17 USB20_P4 8
3 TPM@ 3 9
7 VNC 28 4 3 10 9
PP VPS1 13,38,40,41 LPC_FRAME# 4 10
27 SERIRQ 5
VPS1 SERIRQ 13,41 13,38,40,41 LPC_AD3 5
6 26 LPC_AD0 6 11
DataAvailable VPS1 LPC_AD0 13,38,40,41 13,38,40,41 LPC_AD2 6 GND1
9 23 LPC_AD1 7 12
AcceptCmd VPS1 LPC_AD1 13,38,40,41 13,38,40,41 LPC_AD1 7 GND2
C 22 LPC_FRAME# 8 C
VPS1 LPC_FRAME# 13,38,40,41 13,38,40,41 LPC_AD0 8
4 20 LPC_AD2 PLT_RST# 9 ACES_50463-0104A-P01
GND1 VPS1 LPC_AD2 13,38,40,41 9
11 17 LPC_AD3 10 1 ME@
GND2 VPS1 LPC_AD3 13,38,40,41 17,38 CLK_PCI_DB 10
18 38,41 EC_TX_P80_DATA 11 13 C2513
GND3 25 12 11 GND 14
NC 38,41 EC_RX_P80_CLK 12 GND
5 21 CLK_PCI_TPM 0.1U_0402_10V6K
NC NC CLK_PCI_TPM 17 2
8 19
12 NC NC 15 PM_CLKRUN# CLK_PCI_DB ACES_85201-1205N Touch@
NC NC PM_CLKRUN# 15
13
14 NC 16 PLT_RST# ME@
NC LRESET# PLT_RST# 14,17,22,38,39,41,42,5

ST33ZP24AR28PVSC TSSOP 28P C5109


12P_0402_50V8J

TPM@
Debug Conn. @

CLK_PCI_TPM R317 1 2 C159 1 2

10_0402_5% 22P_0402_50V8J
TPM@ TPM@
D RF 11/17 D

Security Classification LC Future Center Secret Data Title


Issued Date 2012/07/01 Deciphered Date 2014/07/01 PWR S/B/LID SW/TPM/RJ45
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, November 07, 2012 Sheet 40 of 59

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1 2 3 4 5

+3VALW
+3VLP +3VALW +3VALW_EC +3VLP +EC_AVCC Vcc 3.3V +/- 5%
R2210 100K +/- 1%

1
R310 1 @ 2 0_0603_5% R2210 Board ID
SD028330280 S RES 1/16W 33K +-5% 0402 100K_0402_1%
R2213 VAD_BID min V AD_BID typ VAD_BID max Phase
R313 1 2 0_0603_5%
SD028180280 S RES 1/16W 18K +-5% 0402
0 0K +/- 5% 0 V 0 V 0 V SDV

2
BRDID
+3VALW_EC SD02882018J S RES 1/16W 8.2K +-5% 0402
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V FVT

2
+3VALW_EC
L2201 1 2 0_0603_5% SD028470180 S RES 1/16W 4.7K +-5% 0402 R2213
2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+EC_AVCC

C2203

0.1U_0402_16V4Z

C2204

0.1U_0402_16V4Z

C2205

0.1U_0402_16V4Z

C2206

0.1U_0402_16V4Z

C2208

1000P_0402_50V7K

C2207

1000P_0402_50V7K
8.2K_0402_5%
SD028240280 S RES 1/16W 24K +-5% 0402
3 33K +/- 5% 0.712 V 0.819 V 0.875 V
1 1 1 1 1 1 1 1
C2201 C2202
4 4.7K +/- 5% 0.141 V 0.148 V 0.155 V

1
0.1U_0402_16V4Z 1000P_0402_50V7K
A
2 2 2 2 2 2 2 2 5 24K +/- 5% 0.612 V 0.638 V 0.664 V A

L2202 1 2 0_0603_5% ECAGND


+3VS

111
125
22
33
96

67
9
U2201 R2233 LOGO_LED#
LOGO_LED# 32,39
GC6_EVENT# 1 2

EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC

EC_VDD/VCC

EC_VDD/AVCC
EC_VDD0

1
10K_0402_5%
D Q2104
1 21 LOGO_LED LOGO_LED 2 2N7002K_SOT23-3
18 GATEA20 GATEA20/GPIO00 GPIO0F
KB_RST# 2 23 BEEP# G
18 KB_RST# KBRST#/GPIO01 BEEP#/GPIO10 BEEP# 35
3 26 ODD_DETECT# S
13,40 SERIRQ SERIRQ GPIO12 WLAN_WAKE# 38
4 27 ACOFF
13,38,40 LPC_FRAME# ACOFF 47

3
LPC_AD3 5 LPC_FRAME# ACOFF/GPIO13
13,38,40 LPC_AD3 LPC_AD3
LPC_AD2 7 PWM Output
13,38,40 LPC_AD2 LPC_AD2 +3VALW_EC
LPC_AD1 8 63 FAN_ID Definition FAN_ID (pin 5)
+3VALW_EC 13,38,40 LPC_AD1 LPC_AD1 BATT_TEMP/GPIO38 FAN_ID 39
LPC_AD0 10 64
13,38,40 LPC_AD0 LPC_AD0LPC & MISC GPIO39 65
GS_VOUTX 36 PCC 00
ADP_I/GPIO3A ADP_I 46,47 AVC 01
CLK_PCI_EC 12 AD Input 66 LID_SW# R2203 1 2 100K_0402_5%
17 CLK_PCI_EC CLK_PCI_EC GPIO3B GS_VOUTY 36 Delta 02
13 75 BRDID
14,17,22,38,39,40,42,5 PLT_RST# PCIRST#/GPIO05 GPIO42
R2205 1 2 330K_0402_5% EC_RST# 37 76 +3VS
EC_RST# IMON/GPIO43 IMVP_IMON 53
EC_SCI# 20
18 EC_SCI# EC_SCII#/GPIO0E
1 ADP_PROTECT 38
46 ADP_PROTECT GPIO1D 68 TP4RST R2216 1 @ 2 10K_0402_5%
DAC_BRIG/GPIO3C AOU_CTL2 39
C2210 70
EN_DFAN1/GPIO3D PCH_PWR_EN# 43 +3VLP
0.1U_0402_10V6K DA Output 71
2 IREF/GPIO3E AOU_CTL3 39
KSI0 55 72 AOU_ILIM Muxless_STAT
KSI0/GPIO30 CHGVADJ/GPIO3F TP4RST 39
KSI1 56
KSI2 57 KSI1/GPIO31 VL_OFF# R2218 1 @ 2 10K_0402_5%
C2209 1 2 R2201 1 2 CLK_PCI_EC KSI3 58 KSI2/GPIO32 83 EC_MUTE#
KSI3/GPIO33 EC_MUTE#/GPIO4A EC_MUTE# 35
22P_0402_50V8J 10_0402_5% KSI4 59 84 USB_ON# EC_GPIO R2219 1 @ 2 10K_0402_5%
KSI4/GPIO34 USB_EN#/GPIO4B USB_ON# 37
KSI5 60 85
KSI5/GPIO35 CAP_INT#/GPIO4C AOAC_WLAN 38
RF KSI6 61 PS2 Interface 86
KSI6/GPIO36 EAPD/GPIO4D KB_FN 39
KSI7 62 87 TP_CLK
B KSI7/GPIO37 TP_CLK/GPIO4E TP_CLK 39 B
KSO0 39 88 TP_DATA +3VALW
KSI[0..7] KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA 39
KSO1 40
39 KSI[0..7] KSO1/GPIO21
KSO2 41
KSO[0..15] KSO3 42 KSO2/GPIO22 97 GC6_EVENT# KB_FN R2226 1 2 10K_0402_5%
39 KSO[0..15] KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 GC6_EVENT# 22
KSO4 43 98
KSO4/GPIO24 WOL_EN/GPXIOA01 VGA_AC_DET 22
KSO5 44 99
KSO6 45 KSO5/GPIO25 Int. K/B HDA_SDO/GPXIOA02 109 EC_GPIO
ME_FLASH 13
VL_OFF# R2217 1 @ 2 100K_0402_5%
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00
KSO7/GPIO27 SPI Device Interface
KSO8 47 EC_GPIO R2206 1 @ 2 10K_0402_5%
KSO9 48 KSO8/GPIO28 119
KSO9/GPIO29 SPIDI/GPIO5B M_PWR_ON 43,56
KSO10 49 120 EC_MUTE# R2202 1 2 10K_0402_5%
KSO10/GPIO2A SPIDO/GPIO5C PCH_SLPA# 15 AOU_CTL1
KSO11 50 SPI Flash ROM 126 BATT_LEN#
KSO11/GPIO2B SPICLK/GPIO58 BATT_LEN# 46
KSO12 51 128 BATT_TEMP HDD_DETECT# R2204 1 2 100K_0402_5%
KSO12/GPIO2C SPICS#/GPIO5A BATT_TEMP 46
KSO13 52
KSO14 53 KSO13/GPIO2D ADP_PROTECT R2207 1 @ 2 100K_0402_1%
KSO15 54 KSO14/GPIO2E 73
KSO15/GPIO2F ENBKL/GPIO40 ENBKL 16
39 KSO17 KSO17 81 74 FAN_ID R2208 1 2 10K_0402_5%
KSO16/GPIO48 PECI_KB930/GPIO41 ADP_ID 45
39 KSO18 KSO18 82 89
KSO17/GPIO49 FSTCHG/GPIO50 FSTCHG +5VALW
90
BATT_CHG_LED#/GPIO52 AOU_EN 39
91
CAPS_LED#/GPIO53 mSATA_DETEC# 38
EC_SMB_CK1 77 GPIO 92 USB_ON# R2209 1 2 10K_0402_5%
46,47 EC_SMB_CK1 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 HDD_DETECT# 36
EC_SMB_DA1 78 93
46,47 EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 CP_RESET# 39
EC_SMB_CK2 79 SM Bus 95 SYSON
14,22,39 EC_SMB_CK2 EC_SMB_CK2/GPIO46 SYSON/GPIO56 SYSON 49 +5VS
EC_SMB_DA2 80 121
14,22,39 EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 VR_ON 53
127
PM_SLP_S4#/GPIO59 PM_SLP_S4# 15
TP_CLK R2211 1 2 4.7K_0402_5%

6 100 TP_DATA R2212 1 2 4.7K_0402_5%


15 PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 EC_RSMRST# 15
14 101 EC_WAKE#
15 PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 EC_WAKE# 18
EC_SMI# 15 102 BATT_TEMP C2211 1 2 100P_0402_50V8J
18 EC_SMI# EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 VL_OFF# 47
16 103 H_PROCHOT#_EC R2243 1 @ 2 0_0402_5%
22,26,31 FB_CLAMP GPIO0A H_PROCHOT#_EC/GPXIOA06 PROCHOT 46
17 104 MAINPWON_R R2215 1 @ 2 0_0402_5% ACIN C2212 1 2 100P_0402_50V8J
39 TP_RESET GPIO0B VCOUT0_PH/GPXIOA07 MAINPWON 39,45,46,48
18 GPO 105 BKOFF#
36 GS_ON# GPIO0C BKOFF#/GPXIOA08 BKOFF# 32
ODD_DA# 19 GPIO 106 PBTN_OUT# SA_PGOOD C2510 1 2 0.1U_0402_10V6K
38 RF_OFF# GPIO0D PBTN_OUT#/GPXIOA09 PBTN_OUT# 15,5
C EC_INVT_PWM 46 +VSB_EN 25 107 C
+VSB_EN EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 PCH_APWROK 15
EC_TACH 28 108 SA_PGOOD
39 EC_TACH FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11 SA_PGOOD 50
EC_PME# 29
EC_TX_P80_DATA 30 EC_PME#/GPIO15
38,40 EC_TX_P80_DATA EC_TX/GPIO16
EC_RX_P80_CLK 31 110 ACIN VR_HOT# R2214 1 2 0_0402_5%
38,40 EC_RX_P80_CLK EC_RX/GPIO17 AC_IN/GPXIOD01 ACIN 15,42,47 46,53 VR_HOT# H_PROCHOT# 5
PCH_PWROK 32 112 EC_ON
15 PCH_PWROK PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON 40,48
EC_FAN_PWM 34 114 ON/OFF
39 EC_FAN_PWM SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 ON/OFF 40

1
36 GPI 115 LID_SW#
36 GS_SELFTEST NUM_LED#/GPIO1A LID_SW#/GPXIOD04 LID_SW# 40
116 SUSP# D Q2202
SUSP#/GPXIOD05 SUSP# 31,43,49,51,9
117 BYPASS_PAD_R R2244 1 2 0_0402_5% H_PROCHOT#_EC 2 2N7002K_SOT23-3
GPXIOD06 BYPASS_PAD 39
118 EC_PECI R2245 1 2 43_0402_1% G
PECI_KB9012/GPXIOD07 H_PECI 18,5
AGND/AGND

EC_RTCX1 122 S
+3VALW R2221 1 2 0_0402_5% SUSCLK_R 123 XCLKI/GPIO5D 124 +V18R
GND/GND
GND/GND
GND/GND
GND/GND

15 SUSCLK

3
XCLKO/GPIO5E V18R
1
GND0

1 C2214
1

R2225 1 2 47K_0402_5% KSO1 C2213 4.7U_0805_10V4Z


20P_0402_50V8
R2227 1 2 47K_0402_5% KSO2 R2223 KB9012QF A3 LQFP 128P_14X14 2
11
24
35
94
113

69

100K_0402_5% 2 +3VALW
R2228 1 2 2.2K_0402_5% EC_SMB_CK1
2

ECAGND

1
R2230 1 2 2.2K_0402_5% EC_SMB_DA1
R2220
+3VLP 10K_0402_5%

2
R2231 1 @ 2 2.2K_0402_5% EC_SMB_CK1 (EC_PME#)
R2222 1 2 0_0402_5%
LAN_WAKE# 42
R2232 1 @ 2 2.2K_0402_5% EC_SMB_DA1
EC_RTCX1
R2224 1 @ 2 0_0402_5%
R2229 1 @ 2 10M_0402_5% SUSCLK_R
+3VS
@ EC_PME# 1 3

S
Y2202 PCI_PME# 17
R2452 1 @ 2 10K_0402_5% EC_FAN_PWM Q2203
D D
1 2 11/14 2N7002K_SOT23-3
R2451 1 2 10K_0402_5% EC_TACH @

G
32.768KHZ_12.5PF_CM31532768DZFT +3VALW

2
R2236 1 2 2.2K_0402_5% EC_SMB_CK2

R2237 1 2 2.2K_0402_5% EC_SMB_DA2 1 1


C2218 C2219
C2220 @ 1 2 100P_0402_50V8J EC_SMB_CK2 18P_0402_50V8J 18P_0402_50V8J
@ @ Title
C2221 @ 1 2 100P_0402_50V8J EC_SMB_DA2 2 2 Security Classification LC Future Center Secret Data
R2239 1 2 10K_0402_5% PCH_PWROK
Issued Date 2012/07/01 Deciphered Date 2014/07/01 EC ENE-KB9012
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 41 of 59

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JDCIN2
1
17 USB3_TX3_P 2 1
17 USB3_TX3_N 3 2
4 3
17 USB3_RX3_P 5 4
17 USB3_RX3_N 6 5
7 6
16 DISP_A0P_L 8 7
A 16 DISP_A0N_L 9 8 A
16 DISP_A1P_L 10 9
16 DISP_A1N_L 11 10
12 11
17 USB20_P3 13 12
17 USB20_N3 14 13
DISP_AUXP_CONN 15 14
DISP_AUXN_CONN 16 15
17 16
18 17
HPD 19 18
20 19
40 ON/OFFBTN# 20
21
22 G1
23 G2
24 G3
G4
ACES_50406-02071-001
ME@

+3VS +3VS

B B
1

R2249
20K_0402_5% HPD
2

1
5

R2248
OE#
P

1 2 HHPD 4 2
16 DISP_HPD Y A
G

0_0402_5% UV12 SN74AHCT1G125GW_SOT353-5


3

RJ45 Board
+5VALW

JRJ45
1
DP/TMDS Switch Circuit (1) +3VALW
2 1
3 2
+3VS 3
4
+RTCBATT 4
5
6 5
C 7 6 C
14 PCIE_PRX_DTX_N4 8 7
14 PCIE_PRX_DTX_P4 9 8
10 9
14 PCIE_PTX_C_DRX_N4 11 10
+3VS 14 PCIE_PTX_C_DRX_P4 12 11
13 12
14 CLK_PCIE_LAN# 14 13
14 CLK_PCIE_LAN 15 14
14 LAN_CLKREQ# 16 15
14,17,22,38,39,40,41,5 PLT_RST# 17 16
41 LAN_WAKE# 17
2

18
15 PCIE_WAKE# 19 18
R2487
14 PCH_LAN_25M 20 19
@ 100K_0402_1% 15,41,47 ACIN 21 20
22 GND1
1

GND2
ACES_88194-2041
ME@

DISP_AUXP_R R2247 1 2 0_0402_5% DISP_AUXP_CONN


16 DISP_AUXP_R DISP_AUXN_R 1 2 DISP_AUXN_CONN
16 DISP_AUXN_R
R2246 0_0402_5%
2

D R2488 D
100K_0402_1% @
1

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 DP U3 CONN.


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A

WWW.AliSaler.Com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 42 of 59
1 2 3 4 5
1 2 3 4 5

VL +5VALW
+5VALW TO +5VS +3VALW TO +3VALW(PCH AUX Power)
11/14

1
+5VALW +5VS @ R2308 R2303
U2301 100K_0402_5% 100K_0402_5%
AP4800BGM-HF_SO-8 Short J2301 for PCH VCCSUS3.3

2
8 1 SUSP
31,49,52,9 SUSP
7 2

C2301

10U_0603_6.3V6M

C2302

10U_0603_6.3V6M

C2303

10U_0805_10V4Z

C2304

10U_0603_6.3V6M
6 3 +3VALW +3V_PCH L

1
1 1 5 1 1
R2304 D
J2301
470_0603_5% 40mil 40mil 2 Q2302
31,41,43,49,51,9 SUSP#

4
@ @ 1 2 G 2N7002K_SOT23-3
2 2 2 2 1 2
A S A

1
C2306

10U_0603_6.3V6M

C2308

1U_0402_6.3V6K
H

3
JUMP_43X79 R2306
1 1

1
@ 10K_0402_5%
20mil 10mil
R2313 Q1409 +3V_PCH@ R2318

+3V_PCH@

+3V_PCH@
+VSB R2301 1 2 150K_0402_5% 1 2 5VS_GATE AO3413_SOT23-3 20K_0402_5%

2
82K_0402_5% D 2 2
2 3

D
SUSP 1 @

2
1

1
C2309 G
D 0.01U_0603_50V7K S Q2303
SUSP 2 2N7002K_SOT23-3

G
2

2
G @
Q2301 S
2N7002K_SOT23-3 +3V_PCH@
3

41 PCH_PWR_EN# R171 1 2 0_0402_5%

1
C2322
0.1U_0603_25V7K
@

2
+3VALW TO +3VS
+3VALW U2302 +3VS
AP4800BGM-HF_SO-8 11/21
8 1
C2310

10U_0603_6.3V6M

C2311

10U_0603_6.3V6M

7 2
C2312

10U_0603_6.3V6M

C2313

10U_0603_6.3V6M
1 1 6 3

1
5 1 1
R2309
470_0603_5%
4

2 2 @ @
2 2

2
B B
10mil R2321
R2310 1 2 470K_0402_5% 1 2 3VS_GATE
FOR SBA Function POWER(always mount)
20mil +VSB 3
0_0402_5%
6

5 SUSP +3VALW Q2108 SBA@ +3VM


1

C2314 Q2304B AP2301GN-HF_SOT23-3


SUSP 2 0.01U_0603_50V7K 2N7002KDWH_SOT363-6
4

Q2304A 3 1
2

2N7002KDWH_SOT363-6
1

C2327

10U_0603_6.3V6M

C2329

10U_0603_6.3V6M
1

1
1

2
SBA@ R351 SBA@
SBA@ 390_0402_5%
+3VALW VL 2
2
+1.5V to +1.5VS

2
SBA@
R2320 1 2 47K_0402_5%

3
+1.5V U2303 +1.5VS
AP2301GN-HF_SOT23-3 @ R2324
R2319 1 2 47K_0402_5% M_PWR_ON# 1 2 +3VM_GATE
3 1 10K_0402_5% SBA@ 5 M_PWR_ON#
Q2416B
L

6
C2315

10U_0603_6.3V6M

C2317
0.1U_0402_16V4Z

C2319

10U_0603_6.3V6M

C2320

1U_0402_6.3V6K

2N7002KDWH_SOT363-6

4
1

1 1 1 SBA@
1

1
R2311 C2325
2

470_0603_5% 41,56 M_PWR_ON M_PWR_ON 2 0.1U_0603_25V7K


@ Q2416A SBA@
2

2
2 2 2 2N7002KDWH_SOT363-6
from EC
2

1
SBA@
H 11/14
C 10mil C
R2322
+3VALW R2312 1 2 100K_0402_5% 1 21.5VS_GATE
20mil 0_0402_5%
1
C2321

0.1U_0603_25V7K

D
1 2 SUSP
G
1

S Q2311
D 2N7002K_SOT23-3
3

SUSP# 2 2 @
31,41,43,49,51,9 SUSP#
G
Q2306 S
2N7002K_SOT23-3
3

PJ801
+0.75VS +1.05VS +1.8VS 2 1
+1.05VS 2 1 +1.05VS_PCH
@ JUMP_43X118
1

R2314 R2315 R2316


22_0603_5% 470_0603_5% 470_0603_5%
@ @
1 2

1 2

1 2

D D

D D D
2 SUSP 2 SUSP 2 SUSP
G G G
S Q2307 S Q2308 S Q2309
2N7002K_SOT23-3 2N7002K_SOT23-3 2N7002K_SOT23-3
3

@ @
Security Classification LC Future Center Secret Data Title
Issued Date 2012/07/01 Deciphered Date 2014/07/01 DC INTERFACE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 43 of 59

WWW.AliSaler.Com 1 2 3 4 5
1 2 3 4 5

G3 S5 S0

RTC

RTCRST

EC_111 pin

EC_ON
Screw Hole & FD
MAINPWON
A A

FD1 FD2 FD3 FD4 +5VALW

@ @ @ @ +3VALW/VCCDSW
1

1
FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80
ON/OFF#

EC_RSMRST#

PBTN_OUT#
H19 H18
H5 H6 H_2P5 H_2P5N
H_4P0N H_4P0N SLP_S5#
@ @

1
@ @ SLP_S4#
1

H17 SYSON
GPU Screw H_2P5

H7 H8 SYSON
H_4P0N H_4P2 @

1
PCH_SLPA#
@ @
1

1
H1 H2
H_4P0N H_4P0N M_PWR_ON
B B
@ @ +3VM
1

H10 +1.05VM
H_2P5 H23
CPU Screw H_2P5
PCH_APWROK
@
1

H4 H3 @ H16
1

H_4P0N H_4P0N H_2P5 SLP_S3#


H11
H_2P5 @ @ @ SUSP#
1

@ +1.5V_CPU_VDDQ
1

+1.8VS
H21
H20 H_2P5X3P0N +5VS
H_2P5

@ +3VS
1

@
1

H15
H_2P5 +1.5VS

H12 H13 @ +0.75VS


1

H22 H_2P5 H_2P5 H14


H_2P5X3P0N H_2P5
+V1.05VS(VCCP)
C @ @ C
1

@ @
1

+VCCSA

SA_PGOOD

VR_ON 99ms

PCH_POK

PCH_CLKOUT

DRAMPWROK

H_CPUPWRGD

CPU_VID

CPU_CORE

VGATE

SYS_PWROK
D D
BUF_PLT_RST# ME and BIOS
activity will continue
SPI

DMI Tralning
Security Classification LC Future Center Secret Data Title
Issued Date 2012/07/01 Deciphered Date 2014/07/01 Screw Hole
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Monday, November 05, 2012 Sheet 44 of 59

WWW.AliSaler.Com 1 2 3 4 5
5 4 3 2 1

ADP_ID
PR101
750_0402_1% AC Adapter 90W 65W

680P_0603_50V7K
1 2
+3VALW ADP_ID 41 R(K ohm) open 10

0.1U_0402_16V7K
A/D ADP_ID(V) 3.3 1.65 VL

1
+5VALW

PC101

PC102
2011_0929 PR103 Detection voltage >2.64 1.32~1.98
VL

2
for 0ohm change to 270ohm <BOM Structure>

10K_0402_5% 10K_0402_5%

10K_0402_5%
1

1
+5VALW
VL

PR1209

PR1214
PR103
JDCIN1
D 1
270_0402_1%
1 2
VIN @ D

540_0402NEW_30%_PRF15BB541NB6RC

540_0402NEW_30%_PRF15BB541NB6RC

540_0402NEW_30%_PRF15BB541NB6RC

540_0402NEW_30%_PRF15BB541NB6RC
1 1
2 APDIN F1

2
2

10K_0402_5%
3 1 2 APDIN1 1 2 PC1226
3

10K_0402_5%
4 1U_0603_10V6K
4

1
2

PR1215
5 7A_32V_0437007.WR PL101
5

PR1208

PR1210
8 6 SMB3025500YA_2P
GND1 6

1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J
9 7 @
GND2 7 PU1203

2
1

1
ACES_50271-00701-001 1

2
IN+

RT1

RT2

RT3

RT4
5
2 VCC+ PR1211

2
GND

PC103

PC104

PC105

PC106
4 1 2
3 OUT MAINPWON 39,41,46,48

2
IN- 0_0402_5%
LMV331IDCKRG4_SC70-5

540_0402NEW_30%_PRF15BB541NB6RC

540_0402NEW_30%_PRF15BB541NB6RC

540_0402NEW_30%_PRF15BB541NB6RC

540_0402NEW_30%_PRF15BB541NB6RC
1

1
RT5

RT6

RT7

RT8
Thermal protect

2
RT1 place to closed PQ312 with PU301
RT2 place to closed PQ401 with PU401
RT3 place to closed PQ402 with PU401
C C
RT4 place to closed PQ501 with PU501
RT5 place to closed PL601 with PU601
RT6 place to closed PQ702 with PU701
RT7 place to closed PQ804 with PU801
RT8 place to closed PL1201 with PU1201

VIN

2
PD104
LL4148_LL34-2

PD105
1

LL4148_LL34-2 51ON-1
BATT+ 2 1
1

PR123 PR124
B PQ101 68_1206_5% 68_1206_5% B
TP0610K-T1-GE3_SOT23-3
PR125
2

200_0603_5%
CHGRTCP 1 2 51ON-2 3 1
VS
0.22U_0603_25V7K
1

1
PC114

PR128 PC115
100K_0402_1% 0.1U_0603_25V7K
1

PR129
2

22K_0402_1%
1 2 51ON-3
40 51_ON#
1

RTCVREF
PR131
+CHGRTC 200_0603_5%
PU102
PR132 PR133 BIT3021A-ST9_SOT89-3
PD106 3.3V
2

560_0603_5% 560_0603_5%
+RTCBATT 1 2 1 2 1 2 3 2 CHGRTCIN
VOUT VIN
1

PC117
RB751V-40_SOD323-2
1

GND 1U_0805_25V6K
PC116 @
2

10U_0603_6.3V6M 1
2

A 2011_0805 A

移移 小小
del PD107,PR134,JRTC1
HW
2011_0808 PU102 change
form SA00001PE00(APL5156-33DI-TRL)
2011_0728 del PR130 and +3VLP to SA00002E280(BIT3021A-ST9)
add PR? 1K_0603_5%
change place for R132,R133, +CHGRTC,PD107 Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 PWR-DCIN / Vin Detector


RTC Battery THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A

WWW.AliSaler.Com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 45 of 59
5 4 3 2 1
5 4 3 2 1

VMB2 VMB
PF201 PL201
JBATT1 12A_65V_451012MRL SMB3025500YA_2P
1 1 2 1 2
1 2 BATT+
2 3 EC_SMCA
3 4 EC_SMDA
4 5
5

1
D 6 D
6 7 PC201 PC202
7 8 1000P_0402_50V7K 0.01U_0402_25V7K

2
GND

3
9
GND
1

1
2011_1128
PESD5V0U2BT_SOT23-3
100_0402_1%

100_0402_1%
Add OTP
PD805
@ PR212 and PR206 unmount
@

1
PR202

PR201
SUYIN_200082GR007M211ZR
2

2
2011_0823
change 9P JBATT1 PH1 under CPU botten side :
EC_SMB_CK1 41,47 CPU thermal protection at 93 +-3 degree C
Recovery at 56 +-3 degree C
EC_SMB_DA1 41,47
PR203
100K_0402_1%
2 1
+3VALW
VL
1 2
+3VLP
41,47 ADP_I

21.5K_0402_1%
PR227

1
4.42K_0402_1%

12.7K_0402_1%
2.1K_0402_1%

1
D

PR207
1 2
BATT_TEMP 41 A/D

PR205

PR206
PR204 2

1
750_0402_5% PQ206 G ADP_PROTECT 41
2

PC203 +3VS S S TR 2N7002KW 1N SOT323-3 @

2
0.1U_0603_16V7K PU201

2
1 8 NTC_V_1
PESD5V0U2BT_SOT23-3 VCC TMSNS1

100K_0402_1%
C PD806 2 7 OTP_N_002 2 1 C
GND RHYST1

PR209
@ PR208
1

3 6 Turbo_V_1 10K_0402_1%
41,53 VR_HOT# OT1 TMSNS2

1
PR210 PR230

100K_0402_1%_TSM0B104F4251RZ
4 5 ADP_OCP_2 1 2
+3VALW

1
OT2 RHYST2

1
10K_0402_1%

PH201
PQ201 PR228 0_0402_5%

2
D G718TM1U_SOT23-8 27.4K_0402_1% 0_0402_5%

PR211
2 ADP_OCP_1

2
OTP_N_003
G
S 2N7002KW_SOT323-3 @
PR229 +3VLP 2 1

2
1 2 1 2 PR232

1
PR212 47K_0402_1%
0_0402_5% PR231
0_0402_5%

Turbo_V
41 PROCHOT

NTC_V
1 2 2 1 47K_0402_1%
MAINPWON 39,41,45,48
@
2011_0731 add circuit for battery learning function PR213 0_0402_5%
2011_1119 change circuit to unmount from mount

P2

+3VLP +3VALW
0.01U_0402_25V7K
1

PC207

VMB2
PR222 PR220
2

100K_0402_1% 100K_0402_1%
PR224 PR218
2

255K_0402_1% 10M_0402_5%
1

1 2
B BATT_OUT 47 B
PR219
10K_0402_1%
8

1 2 PQ204
1

3 D 2N7002KW_SOT323-3 PQ202
P

+ 1 2 TP0610K-T1-GE3_SOT23-3
PR221 2 O G
-
G
2

150K_0402_1%<BOM Structure> PU202A S


3

LM393DG_SO8 3 1
B+ +VSBP
4

VL

100K_0402_1%
+3VLP

0.22U_0603_25V7K
1
PQ205
1

1
D 2N7002KW_SOT323-3

PR214

PC204
2

2 PC205
2

G PR216 0.1U_0603_25V7K

2
PR226 S 100K_0402_1% @
3

2
100K_0402_1% PR215
2 1 @ 22K_0402_1%
RTCVREF
1

PR217 1 2
1

PR225 1K_0402_5%
10K_0402_1% 1 2
48 SPOK

41 BATT_LEN#
PR234
1

1K_0402_5% D PJ201
1 2 2 PQ203 @ JUMP_43X39
41 +VSB_EN
G 2N7002KW_SOT323-3 1 2
+VSBP 1 2 +VSB
1U_0402_10V6K

S
3
1

PC206
2

A A
2011_1005 PQ105 change
form SB000006800(2N7002W T/R7 1N SOT-323)
to SB000009Q80( 2N7002KW 1N SOT323-3)

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 PWR-BATTERY CONN/OTP


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A

WWW.AliSaler.Com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 46 of 59
5 4 3 2 1
5 4 3 2 1

P3
B+ PQ302
AO4407AL_SO8
P2 1 8
2 7
PQ301 PQ304 3 6
AO4407AL_SO8 AO4423L 1P SO8 5
8 1 1 8 PR302
VIN 7 2 2 7 0.01_1206_1% B+
SH00000AA00

4
6 3 3 6
5 5 1 2 1 4

PL301 2 3 VIN

4
1UH_PCMB061H-1R0MS_7A_20% PR305
47K_0402_1%

10U_0805_25V6K

10U_0805_25V6K

2200P_0402_50V7K
PQ305 1 2

47P_0402_50V8J
4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
D D
1 2
47K_0402_5%

68P_0402_50V8J
1 1
1

2
200K_0402_1%

RFC32
0.1U_0603_25V7K

PC308
1
PR301

PC303

PC304

PC305

PC306

PC307
LTA044EUBFS8TL_UMT3F PC302

RFC33
3

2
PC301

PR306

10K_0402_1%
5600P_0402_25V7K

1
2 2
2

2
2

PR307
<BOM Structure>

<BOM Structure>
2
ACN

1DISCHG_G-1
1

2
2ACOFF-1

1SS355_SOD323-2
PR308
1

ACP 200K_0402_1%
1

PD302

1
P2-1

0.1U_0603_25V7K
2
PQ307

1
PC309 PC310

1
LTC015EUBFS8TL_UMT3F +3VALW P 2 1 2
PR331 ACPRN 1 2 2 1
3

20K_0402_1% PD303
0.1U_0603_25V7K 1SS355_SOD323-2

100K_0402_1%

2N7002KDW-2N_SOT363-6
1 2
6

@ 10K_0603_1%
PQ317 PQ308

0.1U_0603_25V7K
3
1

6
D

PR337 @

PQ311A
2N7002KW _SOT323-3 PC312 LTC015EUBFS8TL_UMT3F
150K_0402_1%

1
PR309

PR336

PC311
PQ310A
2 BATT_OUT 46,47
2N7002KDW -2N_SOT363-6 G 0.1U_0603_25V7K
S 2 PACIN
P2
3

2
2 1
1

2
VIN PR338 @ PR339 @

1
2 1 1 2
432K_0603_1% 4.7M_0603_1%
1

5
P2-2

10_1206_5%
39.2K_0402_1%

2
C C
PR314

PQ312

TPCA8065-H_PPAK56-8-5
2N7002KDW-2N_SOT363-6

PR317
3
PQ310B

ACOK

CMPIN

CMPOUT

ACP

ACN
PR318 PR319 41,46 ADP_I
2

47K_0402_1% 64.9K_0603_1% 21 4

1
PACIN 1 2 5 1 2 6 TP
PACIN ACDET PC314
PL302
1 2 PC313 20 BQ24727VCC-1 1 2 10UH_PCMB104T-100MS_6A_20% PR320
4

1 2 7 VCC 0.01_1206_1%

3
2
1
IOUT
PC323 0.1U_0603_25V7K
1U_0603_25V6M BATT+
1

PQ313 100P_0603_50V8 19 LX_CHG 1 2 CHG 1 4


LTC015EUBFS8TL_UMT3F 41,46 EC_SMB_DA1 8 PU301 PHASE
SDA 2 3
BQ24737RGRR_VQFN20_3P5X3P5
PR321 18 DH_CHG
HIDRV

1
1 2ACOFF-12 41,46 EC_SMB_CK1 9
SA000051W00

4.7_1206_5%
41 ACOFF SCL

5
6
7
8

PR322
10K_0402_5% PR324

PQ314
PR323 2.2_0603_5%

TPC8A03-H_SO8
1

1 2 10 17 BST_CHG 1 2 2 1 SRP SRN

10U_0805_25V6K

10U_0805_25V6K
ILIM BTST
1

PR332 +3VALW 316K_0402_1%


PD301
3

2
0_0402_5% PC315

LODRV

1
16 2 1 4

PC316

PC317
PR325 0.047U_0603_25V7M

GND
SRN

SRP

24727_SN
REGN

BM
100K_0402_1%
2N7002KW_SOT323-3
2

RB751V-40_SOD323-2
2

2
PQ318

680P_0603_50V7K
11 BQ24737_VDD

1 12

13

14

15
1

1
D

10_0603_5%
6.8_0603_5%

3
2
1
2

PR327
PC318
46,47 BATT_OUT

1
PR326
G PR333 1U_0603_25V6M

2
S 0_0402_5%
3

PC319
@
2

2
1 2
2

PC320 DL_CHG
2

B 41 VL_OFF# 0.1U_0603_25V7K B
@ 2 1
PR330
CHGVADJ=(Vcell-4)/0.10627 10K_0402_5%
1

Vcell CHGVADJ

1
PC321 <BOM Structure>
4V 0V 0.1U_0603_25V7K PC322
2

2 0.1U_0603_25V7K
4.2V 1.882V +3VS

4.35V 3.2935V

BQ24737_VDD
CC=0.25A~3A
IREF=1.016*Icharge PR334
10K_0402_1%
1

IREF=0.254V~3.048V 1 2
ACIN 15,41,42
PR329
VCHLIM need over 95mV PR328 10K_0402_1%
47K_0402_1%
2

PACIN
2N7002KDW-2N_SOT363-6

1
3
PQ311B

PR335

ACPRN 5 12K_0402_1%
2

A A
4

For disable pre-charge circuit.


Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 PWR-CHARGER-BQ24737


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.A

WWW.AliSaler.Com
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 47 of 59
5 4 3 2 1
5 4 3 2 1

PJ402
PR402 +3VALWP 2 1 +3VALW
13K_0402_1% 2 1
1 2 @ JUMP_43X118

PC411 PC425
0.1U_0402_25V6 0.1U_0402_25V6
D D
1 2 1 2 PJ403
2 1
+3VLP +5VALWP 2 1 +5VALW
PR403 @ JUMP_43X118
30K_0402_1%
1 2

PR404 PR405

1U_0603_10V6K
2
0_0603_5%~D
20K_0402_1% 20K_0402_1%

1
PR419

PC402
1 2 1 2

2
1

100K_0402_1%
2
100K_0402_1%
2
TPS51225_B+

PR407
PR406
Name = TPS51225_B+
FB_3V FB_5V

1
1
PJ401

2 1

2200P_0402_50V7K
PU401

47P_0402_50V8J
B+ 2 1

1
2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
0.1U_0603_25V7K

0.1U_0603_25V7K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

1
PC410

PC409

PC408

PC407
@ JUMP_43X118
47P_0402_50V8J

RFC35
CS2

VFB2

VREG3

VFB1

CS1
PC401

PC403

1 21
PAD
1

1
PC405

PC404

PC406

3V_EN 6
RFC34

2
EN2
8
7
6
5

14 2
VO1

5
6
7
8
46 SPOK
2

C 2 PQ401 7 C
PGOOD 19

TPC8065-H_1N_SOP-8
VCLK

PQ402
AO4466L_SO8
4 UG_3V 10 TPS51225CRUKR_QFN20_3X3
PC412 PR408 DRVH2 16 UG_5V 4
0.1U_0603_25V7K 2.2_0603_5% DRVH1 PR409 PC413
1 2 1 2 BST_3V 9 2.2_0603_5% 0.1U_0603_25V7K
VBST2 17 BST_5V 1 2 1 2
1
2
3

VBST1

3
2
1
SW2_3V 8
SW 2 18 SW1_5V

VREG5
+3VALWP

DRVL2

DRVL1
PL401 SW 1
PL402 +5VALWP

EN1
VIN
4.7UH +-20% PCMB063T-4R7MS 5.5A
1 2 1 2

11

12

13

5V_EN 20

15
1

8
7
6
5

5
6
7
8

1
4.7_1206_5%

4.7_1206_5%
LG_3V LG_5V 2.2UH_PCMB063T-2R2MS_8A_20%
PR401

PR410
1 PQ403

PQ404
AO4712L_SO8
+ PC414 1
150U_B2_6.3VM_R45M
1 SNUB_3V 2

2
4 4 + PC415
2 150U_B2_6.3VM_R45M

TPC8A03-H_SO8

1SNUB_5V
2

1U_0603_10V5K
0.1U_0603_25V7K

2
0_0603_5%
680P_0603_50V7K

680P_0603_50V7K
1
2
3

3
2
1
1

1
PC420

PC419

PR412
PC416

PC417
2

2
2

2
B B

TPS51225_B+ VL

40,41 EC_ON
PR413
1 2
47K_0402_1%

5V_EN
39,41,45,46 MAINPWON
PR411
1 2 3V_EN

0_0402_5%

VS
1 2

PR418
40.2K_0402_1%

1U_0603_10V6K
1

100K_0402_1%
1
PR414

PC421

A @ A
@
2
2

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 PWR-3VALWP/5VALWP


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

WWW.AliSaler.Com
Date: Thursday, November 01, 2012 Sheet 48 of 59
5 4 3 2 1
A B C D

PJ501 PC506 PR502


B+ 2
2 1
1 B+_1.5V 0.22U_0402_10V6K 2.2_0603_5%
1 2 1 2
@ JUMP_43X118

2200P_0402_50V7K
47P_0402_50V8J

68P_0402_50V8J

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
1 PR1213

1
PC519

PC504

PC505

PC502

PC503
0_0402_5%

RFC36
1 2
+1.5VP

2
2

+0.75VSP

VIN_0.75V
BST_1.5V

VIN_1.5V
PJ502

DH_1.5V
LX_1.5V
8
7
6
5
1 1
2 1

10U_0805_6.3V6K

10U_0805_6.3V6K
2 1

1
PC703

PC704
TPC8065-H_1N_SOP-8 @ JUMP_43X118

PJ503 +1.5V

16

17

18

19

20

2
4 PU501 +1.5VP 2 1
2 1

PHASE

UGATE

BOOT

VLDOIN

VTT
PQ501 21 @ JUMP_43X118
PAD
PL501 DL_1.5V 15 1

1
2
3
1UH_+-20%_MMD-10DZ-1R0M-X1A_18A LGATE VTTGND
1 2
+1.5VP 14
PGND VTTSNS
2 VTTSNS_0.75V

8
7
6
5
PR503
PQ502 15.8K +-1% 0402
PR504 1 2 CS_1.5V 13 3 PJ702
4.7_1206_5% CS RT8207MZQW _W QFN20_3X3 GND 2 1
+0.75VSP 2 1 +0.75VS
1
+5VALW
2
4 VDDP_1.5V 12 4 VTTREF_0.75V @ JUMP_43X118
+ PC508 PR701 VDDP VTTREF
220U_D2_4VY_R15M 1SNB_1.5V 5.1_0603_5%
2
+5VALW 1 2 VDD_1.5V 11
VDD VDDQ
5 VDDQ_1.5V +1.5VP

PGOOD
680P_0603_50V7K

1
2
3

1
TON
PC509

TPC8A03-H_SO8 PC701 PC702 PC507

FB
S5

S3
1U_0603_10V6K 1U_0603_10V6K 0.033U_0402_16V7K

2
2

10

6
TON_1.5V

FB_1.5V
S5_1.5V

S3_1.5V
2 2

PR507
10K_0402_1%
1 2 +1.5VP
PR506
887K_0402_1% <BOM
PC705
Structure>
PR501 B+_1.5V 1 2 .1U_0402_16V7K
0_0402_5% 1 2
1 2
41 SYSON

2
+5VALW

@
47K_0402_5%

.1U_0402_16V7K
<BOM Structure>
1

PC501
PR505

2
1

2
PR705
100K_0402_5%

1
1
PQ701
2N7002KW _SOT323-3 PR508
10K_0402_1%
PR702

2
1
49.9K_0402_1% D

31,43,52,9 SUSP 1 2 2
G
0.1U_0402_10V7K

S
3
1
PC706

3 3

2011_0801 JP504 form


43x118 change to 43x79
PU502
PL502
PJ504 1UH_PH041H-1R0MS_3.8A_20%
+5VALW
2 1 4 3 1.8VSP_LX 1 2
2 1 IN LX +1.8VSP
@ JUMP_43X79 5 2 2011_0801 JP505 form
68P_0402_50V8J
22U_0805_6.3VAM

22U_0805_6.3VAM

PG GND
1

1
680P_0603_50V7K 4.7_1206_5%

43x118 change to 43x79


1

1
PC510

PC520

6 1
PC511

2011_0826 add
FB EN
PR509

PR510 for EMI


20K_0402_1%

2200P_0402_50V7K

68P_0402_50V8J

0.1U_0402_25V6
2

@ SY8032ABC_SOT23-6

22U_0805_6.3VAM

22U_0805_6.3VAM
1 2

1
PC516

PC518

PC517
PJ505

PC513

PC514
FB=0.6Volt +1.8VSP 2 1 +1.8VS
2 1
31,41,43,51,9 SUSP#
PC512

PR511
2

2
1 2 EN_1.8VSP @ JUMP_43X79
2

0_0402_5%
0.1U_0402_10V7K
2

2011_0826
1

PC515

PR512 mount for EMI 1.8VSP max current=4A


1M_0402_5%
2

<BOM Structure>
1

4
PR513 4

10K_0402_1%
2011_0829
2

change and mount

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 PWR-+1.5VP/+1.8VSP


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

WWW.AliSaler.Com DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 49 of 59
A B C D
5 4 3 2 1

VID [0] VID[1] VCCSA Vout PJ602


+VCC_SAP +VCCSA
0 0 0.9V TDC 4.2A +VCCSAP 2
2 1
1

@ JUMP_43X118
0 1 0.8V Peak Current 6A
1 0 0.725V OCP current 7.2A
1 1 0.675V
output voltage adjustable network
D D
The 1k PD on the VCCSA VIDs are empty.
These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability.

+VCCSAP
2011_0826 add
for EMI

PU601 PL601
PJ601 0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
+5VALW 2 1 +VCCSA_PWR_SRC +VCCSA_PWR_SRC 12 1 1 2
2 1 PVIN LX
2200P_0402_50V7K

0.1U_0603_25V7K
@ JUMP_43X118 11 2

22U_0805_6.3VAM

22U_0805_6.3VAM

0.1U_0402_10V7K
PR1206 PVIN LX

PC620
68P_0402_50V8J
2200P_0402_50V7K
SA_PGOOD 41

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1 2 VCCSA_SVIN10 3 +VCCSA_PWRGD
PC613
1 1 1 1 1 1

.1U_0402_16V7K
SVIN LX
2

1
PC605

PC608

PC609

PC611

PC612
PC617 @
PC1208 PR607

PC614

PC615

PC607
PC601

1
1 2 9 4 1 PR603 2 4.7_1206_5%

PC610
1
10_0402_5% 68P_0402_50V8J FB PG 100K_0402_5% +3VS

2
2 8 5 1 PR605 2+VCCSA_EN 2 2 2 2 2
1.05VS_VCCP_PWRGOOD 51

2
VOUT EN 0_0402_5%

GND
9 H_VCCSA_VID1 7 6 @

0.1U_0603_25V7K
VID1 VID0

1
PC616

PC619
13
1

1
SY8037BDCC_DFN12_3X3 2011_1012
PR602 PR604 680P_0603_50V7K
PC607 PC610 mount for RF

2
1M_0402_5% 1M_0402_5%
PR609
H_VCCSA_VID0 9

2
100_0402_5%
2 1
C C

PR611
0_0402_5%
2 1
+VCCSA_SENSE 9

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 PWR-VCCSAP


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.A

WWW.AliSaler.Com
5 4 3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2
Date: Thursday, November 01, 2012
1
Sheet 50 of 59
5 4 3 2 1

2011_1127
Change PC711 from Sanyo SF000000S80
to panasonic SF000000I80
+1.05VS_VCCPP OCP(min)=20.75A
D 2011_0926 D
change part
to TPC8065
PJ706
del PR705 1.05VS_B+ 2 1 B+

2200P_0402_50V7K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
2 1 B+

68P_0402_50V8J
0.1U_0402_25V6
+3VS @ JUMP_43X118

47P_0402_50V8J

1
PC709

PC710

PC717
1 1

68U_25V_M_R0.36
TPCA8065-H_PPAK56-8-5
5
2011_0801 mount

PC707

PC708
RFC37
PQ702 +

PC711
PR704, PR706

2
2
PR704 2011_0829 PU702 2011_1129 2 2011_0826 add
2
100K_0402_5% PN error,change Change 2.2 for EMI
4
PR706

1
0_0402_5%
1 2 PR707 PC712
50 1.05VS_VCCP_PWRGOOD +1.05VS_VCCPP
PU702 2.2_0603_5% 0.22U_0603_16V7K PL701 2011_0929

3
2
1
1 10 1
BST_1.05VS_VCCP 2 1 2 1UH_+-20%_MMD-10DZ-1R0M-X1A_18A PC1166 non-mount
PGOOD VBST 2 1
TRIP_1.05VS_VCCP 2 9 DH_1.05VS_VCCP
PR708
31,41,43,49,9 SUSP# TRIP DRVH

1
1 2 3 8 LX_1.05VS_VCCP PQ703

4.7_1206_5%
EN SW

5
@ 10K_0402_1%
2

60.4K_0402_1% 4 7

PR710
.1U_0402_16V7K
+5VALW 1 1

TPCA8057-H_PPAK56-8-5
1 VFB V5IN

330U_D2_2VM_R9M

330U_D2_2VM_R9M
PR709

0_0402_5%

PC1167

PC1168
5 6 DL_1.05VS_VCCP + +
PC713

PR711
2
RF DRVL

75K_0402_1%

470K_0402_1%
2

2
11 4
1

TP 2 3 2 3

PR712

PR713
C C

2
TPS51212DSCR_SON10_3X3

1
VFB=0.7V PC716
PC715

3
2
1
1U_0603_10V6K 680P_0603_50V7K

2
2011_1202
PR708 change from 0 to 60.4K 2011_0815 PC1166, PC1167
PC713 mount 2011_1005 PQ805 change PC1168 change place
2011_1007 PR712 form SB00000Q600(TPCA8059-H_PPAK56-8-5) form"+1.05VS"
form 88.7K change to 75K to SB00000Q400(TPCA8057-H_PPAK56-8-5) to"+1.05VS_VCCPP"

1 2
2011_1005 PC1167,PC1168
PR714 2011_1007 PL701 PR716 @ change to 330U_2V_R9M
1

4.99K_0402_1% form SH000004S00(S COIL 1.0UH +-20% PCMC104T- 10_0402_5%


2 1 VCCIO_SENSE 8
1R0MN 20A) change to SH00000CN00(S COIL 1UH +-
PR715
10K_0402_1% 20% MMD-10DZ-1R0M-X1A 18A)
2

B PJ703 B
2 1
2 1
@ JUMP_43X118
+1.05VS_VCCPP PJ704 +1.05VS
2 1
2 1
@ JUMP_43X118

2011_0801 del PJ705 and "+V1.05S_VCCP"

Ivy Bridge CPU ES2 Using

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2012/07/01 Deciphered Date 2014/07/01 PWR-+1.05VS_VCCP/+0.75VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

WWW.AliSaler.Com 5 4 3 2
Date: Thursday, November 01, 2012
1
Sheet 51 of 59
A B C D

NVVDD PWM_VID 22

DPRSLPVR_VGA 22

+VGA_CORE Under VGA Core GB4-128 package NVDD_PWR_EN 17

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M
1

1
+VGA_B+

PC834

PC835

PC836

PC837

PC838

PC839

PC840

PC1209

PC1210

PC1211

PC1212

PC1213

PC1214

PC1215
PL1202
HCB2012KF-121T50_0805

.1U_0402_16V7K
2

2
1 2
B+
1
PL1203 1
<BOM Structure>
<BOM Structure>
<BOM Structure>
<BOM Structure> HCB2012KF-121T50_0805
1 2

100K_0402_5%

2200P_0402_50V7K
RB751V-40_SOD323-2

0.1U_0402_25V6

10U_0805_25V6K

10U_0805_25V6K

47P_0402_50V8J
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

2
1
1

1
PC819

PC816

PC817

PC818

PD801

PR864

PC805

PC806

PC807

PC808

RFC38
PQ804

PC802

TPCA8065-H_PPAK56-8-5
2

2
2

1
PC2428

470P_0402_50V7K
4
1

+VGA_CORE Near VGA Core @ PR821


0_0603_5%
PC809
0.22U_0603_10V7K

3
2
1
2 2 1BOOT1_2_VGA 1 2 PR867
+3VS 0_0402_5%
2 1 UGATE1_2_VGA +VGA_CORE
4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M
1

10K_0402_5%
22U_0805_6.3V6M

47U_0805_6.3V6M
1

1
1 4
PC824

PC825

PC826

PC827

PC1216

PC1217

PC1218

PC1219

PC1220

PC1221

PC1222

PC1223

0_0402_5%

0_0402_5%

BOOT1_VGA

5
2 3
2

1
2
PQ805 PL802
@ @ @ @ @ @ @ PR1212
4.7_1206_5%

PR835

PR836

PR837
1 1

330U_D2_2V_Y

330U_D2_2V_Y
LGATE1_VGA 4

1SNUB1_VGA 2
STDBY_EN + +

PC811

PC812
PR866
100K_0402_1% PR832 PR833
2 1 SSM3K7002FU_SC70-3 20K_0402_1% 20K_0402_1% GPU_VID UGATE1_VGA 2 2

PSI_VGA

EN_VGA

3
2
1
VREF 2 1 2 1VIDBUF TPCA8057-H_PPAK56-8-5
2
G

PR834 PR833 PR832 PR844 PR846 PQ801 PR868

1
9.1K_0402_1% PC1224
3 1 2 1 PR834 @ 680P_0402_50V7K

PHASE1_VGA
S

2K_0402_1%

2
6

1
PR844 PR846
0_0402_5% 18K_0402_1%

HG1

BST1
VID

PSI

EN
VIDBUF
2
2 3K_0402_1% 39K_0402_1% 30K_0402_1% 3K_0402_1% 24K_0402_1% 2 1 2 1 2

N14MGL@ N14MGL@ N14MGL@ N14MGL@ N14MGL@


2 1 PC854 7 24
PC855 REFIN PH1
PRV11 = 71.5K ==>Fsw = 450KHz 2200P_0402_50V7K PC815
1 2 VREF 8 PU801 23 4.7U_0603_10V6K
PR849 VREF LG1
0.01U_0603_50V7K 2 1 FS 9 NCP81172MNTWG_QFN24_4X4 22 1 2
PR859 0_0402_5% 34K_0402_1% FS PGND
1 2 10 21 PVCC_VGA 1 2
23 VSSSENSE_VGA FBRTN PVCC +5VS
PR843 0_0402_5%
PC863 PR852 FB_VGA 11 20
FB LG2
1

PC853 47P_0402_50V8J 51_0402_1% PC843 10P_0402_50V8J +VGA_B+


1000P_0402_50V7K 1 2FB1_VGA1 2 1 2 COMP_VGA 12 19

TALERT#
COMP PH2

PGOOD
PR854
2

TSNS
10K_0402_1%

BST2
GND

VCC

HG2
23 VCCSENSE_VGA 1 2 1<BOM Structure>
2 1 2FB2_VGA1 2

2200P_0402_50V7K

47P_0402_50V8J
0.1U_0402_25V6

10U_0805_25V6K

10U_0805_25V6K
5
PR865 0_0402_5% PC841 PR845 1

25

13

14

15

16

17

18

1
100P_0402_50V8J 82K_0402_1% PQ806

PC858

PC859

PC860

PC861

RFC39
TPCA8065-H_PPAK56-8-5
<BOM Structure>
BOOT2_VGA PR855

2
VCC_VGA
0_0402_5% 2
UGATE2_VGA 2 1 UGATE2_2_VGA 4
100K_0402_1%_NCP15WF104F03RC

DGPU_PWROK 18,31
1

PR831 10K_0402_5% PR857 PC862


5.9K_0402_1%

3
2
1
PC865 2 1 +3VS 0_0603_5% 0.22U_0603_10V7K
2 1 BOOT2_2_VGA 1 2
PH801

.1U_0402_16V7K
2

PR853 2.2_0402_5% +VGA_CORE


2 1 +5VS
2

PHASE2_VGA 1 4
2

1U_0402_10V6K

5
2 3
PR858
2

1
Thermistor near MOSFET
PC856
1

PQ807 @ PL801
trigger point 97 degree C. PR1207
4.7_1206_5% 1 1
VREF

330U_D2_2V_Y

330U_D2_2V_Y
3 LGATE2_VGA 4 3

1SNUB2_VGA 2
+ +

PC866

PC867
N14P-GT 35W N14P-GS 25W 2 2

3
2
1
PR840 10K_0402_5% TPCA8057-H_PPAK56-8-5
Ipeak=50A Ipeak=36A 2 1 +3VS
PC1225
Imax=35A Imax=25A @ 680P_0402_50V7K

2
Iocp=64.8A Iocp=64.8A MDU1512, Rdson(max)=5mohm

Fsw=450KHz Fsw=450KHz
bulk cap 330uF 9m *4 bulk cap 330uF 9m *3

2011_1007
N13M-GE1 +1.05VS +1.05VS_VGA PJ802
VID: 0110100 2 1
0.85V +5VALW +1.05VS 2 1 +1.05VS_VGA
8 1
7 2 @ JUMP_43X118
1

6 3 @
1

PC801 5 PC803 PC810 PR813 2011_0830


10U_0805_10V6K 470_0603_5% change P/N
2
2

TPC8A03-H_SO8 PQ802
<BOM Structure> 10U_0805_10V6K 1U_0603_10V6K
4

PR814 <BOM Structure> PR815


1

20K_0402_1% 0_0402_5%
PR816 @ 1 2
DGPU_PWROK# 31,52
1

100K_0402_5% D
1

1 2 2 1 2 SUSP
SUSP 31,43,49,52,9
1

PC804 PQ803 G
PR818 2011_0727 PR816 0.01U_0603_50V7K S PR817 @
3

0_0402_5% modfiy 10K to 100K. 2N7002KW_SOT323-3 0_0402_5%


2

31,52 DGPU_PWROK# 1 2
4 4
1

31,43,49,52,9 SUSP SUSP 1 2 2


G PQ808
PR819 @ 2N7002KW_SOT323-3
S
Confirm with HW
3

0_0402_5%

2011_1129
Change 2.2

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 PWR-VGA_COREP-ISL62883


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

WWW.AliSaler.Com
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 52 of 59
A B C D
5 4 3 2 1

PC901
PR901 0.033U_0402_16V7 PC902

1200P_0402_50V7K
1 2 FBA3 1 2 1 2

820P_0402_25V7
D PUT COLSE D

75K_0402_1%
10_0402_1% .1U_0402_16V7K
TO GT

1
PR904 1 PR902 2

PC903

PC904

PR905
TRBSTA# 1 2 FBA1 1 2 PH901 Inductor
24.9K_0402_1% PR906 PC906

1
1
PR903 10.7K_0402_1% 220K_0402_5%_ERTJ0EV224J CSCOMPA 1 2 DROOPA 1 2 CSREFA
8.2K_0402_1% PC905 @ PR907 <BOM Structure>

2
PR908 PC907 PC908 2 1 NTC_PH203 1K_0402_1% 1000P_0402_50V7K

2
0.033U_0402_16V7 1 2 FBA2 1 2 1 2 165K_0402_1%
10_0402_1%
560P_0402_50V7K PR910 10P_0402_50V8J PC909
1 PR909 2 1 2 COMPA1 1 2

CSSUMA
1K_0402_1% 5.11K_0402_1% 1500P_0402_50V7K CSREFA
PR911 PC910 TSENSEA

2
1 2 SWN1A 0.047U_0402_16V7K

66.5K_0603_1% PR912 4.32K_0402_1%

1
CSP1A 1 2
SWN1A 54

2
15.8K_0402_1%
PR913

CSCOMPA
1 2 PC911
9 VCC_AXG_SENSE

2
13.7K_0402_1%
1PR914
0_0402_5% 1000P_0402_50V7K

1
PC912 PH902

PR915
PR916 1000P_0402_50V7K
CSREFA 54

1
1 2 100K_0402_1%_TSM0B104F4251RZ
9 VSS_AXG_SENSE
0_0402_5% PC913

1
+3VS

CSP2A
CSP1A
1 2

TRBSTA#

DROOPA

TSENSEA
COMPA
IMONA
FBA
.1U_0402_16V7K

DIFFA

ILIMA
+1.05VS
1

PR917
10K_0402_1% PR918
1 2 PUT COLSE
26.1K_0402_1%

61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
TO V_GT
2

+5VS 1 PR919 2 PU901


C VR_RDYA C
2_0603_5% HOT SPOT

VSNA
VSPA
DIFFA

FBA
COMPA
IOUTA
ILIMA
DROOPA
CSCOMPA
CSSUMA
CSREFA
CSP2A
CSP1A
TSNSA
PAD

TRBSTA#
6132_PWMA
PC914
1 2 6132_VCC
.1U_0402_16V7K

.1U_0402_16V7K

1 45 PR920 PC917
2.2U_0603_10V7K 2 VCC PWMA 44 BSTA1 1 2 BSTA1_11 2
VDDBP BSTA +5VS
130_0402_1%

54.9_0402_1%

PR923 VR_RDYA 3 43 2.2_0603_5% 0.22U_0603_25V7K


VRDYA HGA HG1A 54
1

PR921 2

1 2VR_ON_CPU 4 42
41 VR_ON EN SWA SW1A 54
PR922

PC915 PC916 0_0402_5% VR_SVID_DAT1 5 41 PR924 PC918


SDIO LGA LG1A 54
VR_SVID_ALRT# 6 40 BST2 1 2 BST2_1 1 2
2

PR927 PR925 VR_SVID_CLK 7 ALERT# BST2 39 2.2_0603_5% 0.22U_0603_25V7K


SCLK HG2 HG2 54

1
PR926 0_0402_5% 69.8K_0402_1% 1 2 VBOOT 8 38 Option for
SW2 54
1

1 2VR_SVID_DAT1 1 2 10K_0402_1% ROSC_CPU 9 VBOOT NCP6132AMNR2G_QFN60_7X7 SW2 37 PC919 PR929


8 VR_SVID_DAT ROSC LG2 LG2 54 1 phase GFX
CPU_B+ 1 2 VRMP 10 36 6132P_VCCP 1 2 0_0402_5%
8 VR_SVID_ALRT# VRMP PVCC
VR_HOT# 11 35 PR928 2.2U_0603_10V7K
8 VR_SVID_CLK VRHOT# PGND
0.01U_0402_25V7K

PR930 1K_0402_1% VGATE 12 34 1 2


LG1 54 +5VS

2
VRDY LG1
1

13 33 0_0402_5% CSP2A
+1.05VS VSN SW1 SW1 54
PC920 14 32 PR931 PC921
+3VS VSP HG1 HG1 54
DIFF_CPU 15 31 BST1 1 2 BST1_1 1 2

CSCOMP
2

DIFF BST1

TRBST#
2.2_0603_5% 0.22U_0603_25V7K

DROOP

CSSUM

DRVEN
CSREF
1

COMP

TSNS
CSP3
CSP2
CSP1

PWM
IOUT
ILIM
1

PR932

FB
PC936 75_0402_1% PR933 +5VS
47P_0402_50V8J 10K_0402_5%
2

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
2

1 PR934 2
41,46 VR_HOT#
2

COMP_CPU

1
FB_CPU 41.2K_0402_1% Option for
TRBST#
15 VGATE
PR936 2 phase CPU PR935

DROOP

TSENSE
ILIM_CPU
1 2 VSN 0_0402_5%
8 VSSSENSE 6132_PWM
1

0_0402_5%
IMON

PC922

2
PR937 1000P_0402_50V7K CSP3
2

1 2 VSP PC923
8 VCCSENSE
2
PR938 12.4K_0402_1%

0_0402_5% 1 2
.1U_0402_16V7K PR940
IMVP_IMON

B CSP2 1 2 B
SWN2 54

1
PR939 PC924 CSP1 4.32K_0402_1% TSENSE
1 2 2 1 CSP2 PC925 PR954
1

CSP3 0.047U_0402_16V7K 20K_0402_1%

2
1K_0402_1% 10P_0402_50V8J @

2
PR941 PC926 PR942 PC927 CSREF
1 2FB_CPU1 1 2 2 1COMP_CPU1 2 1
PC928
PR943 6.04K_0402_1%

13.7K_0402_1%
1 2FB_CPU3 1 2 49.9_0402_1% 560P_0402_50V7K 2200P_0402_50V7K PR944

PR945 1

2
10_0402_1% CSP1 1 2
CSREF 54 SWN1 54
CSCOMP

1
0.033U_0402_25V7K 4.32K_0402_1% PH903
PR946 PR947 PC929 PR955
TRBST# 1 2 FB_CPU2 1 2 1000P_0402_50V7K 20K_0402_1% 100K_0402_1%_TSM0B104F4251RZ
1

2
0.033U_0402_25V7K

PC930 @

1
1

1.21K_0402_1% 9.53K_0402_1% 0.047U_0402_16V7K

2
PC931 CSREF
CSSUM
2

PC932
1 2 PR948
1200P_0402_50V7K 1 2 SWN1
24.9K_0402_1%

127K_0603_1% PUT COLSE


2

.1U_0402_16V7K

TO VCORE
PC933

1 2 PC934 @ 1 PR950 2 SWN2


820P_0402_25V7
PR949

HOT SPOT
1

PR951
1 2NTC_PH201 1 PR952 2
1

127K_0603_1%
PR953 PC935 75K_0402_1% 165K_0402_1%
CSCOMP 1 2 DROOP 1 2 CSREF PH904
PUT COLSE
1K_0402_1% 1000P_0402_50V7K 2 1
TO VCORE
Phase 1 220K_0402_5%_ERTJ0EV224J
A Inductor A

41 IMVP_IMON

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 PWR-CPU_CORE1


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

WWW.AliSaler.Com
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 53 of 59
5 4 3 2 1
5 4 3 2 1

2011_0926
2011_0826 add change part 2011_0826 add
for EMI 2011_0801 PC1009 form SF22004M210_220U 25V M to TPC8065 for EMI
CPU_B+ 8X10.2 CE-AX change to SF000000S80_100U 25V M CPU_B+
del PR1002
6.3X7.7 CE-LX and place

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
B+

0.1U_0402_25V6

0.1U_0402_25V6
2200P_0402_25V7K

2200P_0402_25V7K
5

5
PL1002

PC1017

PC1018
47P_0402_50V8J

68P_0402_50V8J

47P_0402_50V8J

68P_0402_50V8J
PQ1001 1 HCB4532VF-800T90_1812 PQ1002 1 2011_0727

1
TPCA8065-H_PPAK56-8-5

TPCA8065-H_PPAK56-8-5
1 2

PC1001

PC1002

PC1003

PC1005

PC1006

PC1007

PC1004

PC1008
RFC40

RFC41
CPU_B+ chang net name

2
4 2 4 2
1 1

68U_25V_M_R0.36

68U_25V_M_R0.36
53 HG1 53 HG2
+CPU_CORE + + +CPU_CORE

PC1020

PC1009
2011_0815 change PC1009 of place
form"CPU_B+" change to "B+"

3
2
1

3
2
1
D 2 2 D

1 4 1 4
53 SW1 53 SW2
2011_1005 PC1009 change

1
TPCA8057-H_PPAK56-8-5 2 3 form SF000000S80 TPCA8057-H_PPAK56-8-5 2 3

5
PQ1003 PR1003
(100U 25V M 6.3X7.7 CE-LX ) PQ1004 PR1004
PL1001 to SF000000W00 PL1003
4.7_1206_5% 4.7_1206_5%
( 68U 25V M 6.3X5.8 ESR0.36 FK) PR1006

2
PR1005
4 V1N_CPU2 1 4 V2N_CPU 2 1 CSREF
53 LG1 CSREF 53 53 LG2

1SNUB_CPU1

SNUB_CPU2
10_0402_1%
10_0402_1%
SWN1 53 SWN2 53

3
2
1

3
2
1
PC1010 2012_0725
680P_0603_50V7KChange PL1001,PL1003,PL1004

1
PC1011
should change to Panasonic parts

2
680P_0603_50V7K

2
C C

QC 45W CPU DC 35W CPU


VID1=0.9V VID1=1.05V
IccMax=94A IccMax=53A
Icc_Dyn=66A Icc_Dyn=43A
Icc_TDC=52A Icc_TDC=36A
R_LL=1.9m ohm R_LL=1.9m ohm
OCP~110A OCP~65A

2011_0826 add
for EMI CPU_B+
2011_0926
change part
10U_0805_25V6K

10U_0805_25V6K

to TPC8065
0.1U_0402_25V6

2200P_0402_25V7K
68P_0402_50V8J

B del PR1007 B
47P_0402_50V8J

1
PC1019

PC1012

PC1013

PC1014

PC1015

1
RFC42

2
5

2
PQ1005
TPCA8065-H_PPAK56-8-5

4
53 HG1A

+VCC_GFXCORE_AXG
3
2
1

1 4
53 SW1A
1

TPCA8057-H_PPAK56-8-5 2 3
5

PQ1006 PR1008 PL1004


V1N_GFX

4.7_1206_5%
2

4
53 LG1A
SNUB_GFX1

2 PR10091
CSREFA 53
3
2
1

10_0402_1%
1

PC1016
680P_0603_50V7K SWN1A 53
2

A A

QC 45W GT2 DC 35W GT2


VID1=1.23V VID1=1.23V
IccMax=46A IccMax=33A
Security Classification LC Future Center Secret Data Title
Icc_Dyn=37A Icc_Dyn=20.2A
Icc_TDC=38A Icc_TDC=21.5A Issued Date 2012/07/01 Deciphered Date 2014/07/01 PWR-CPU_CORE2
R_LL=3.9m ohm R_LL=3.9m ohm THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
OCP~55A OCP~40A
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.A

WWW.AliSaler.Com 5 4 3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2
Date: Thursday, November 01, 2012
1
Sheet 54 of 59
5 4 3 2 1

+CPU_CORE 2011_0727 2011_0727 Below is 458544_CRV_PDDG_0.5 Table 5-8.


chang net name chang net name +CPU_CORE +VCC_GFXCORE_AXG
1 1 1 1 1
5 x 22 µF (0805)
PC1101
PC1102 PC1103 PC1104 PC1105
Socket Bottom 5 x (0805) no-stuff
2
10U_0805_6.3V7K
2
10U_0805_6.3V7K
2
10U_0805_6.3V7K
2
10U_0805_6.3V7K
2
10U_0805_6.3V7K +VCC_GFXCORE_AXG sites

D
7 x 22 µF (0805) D
Socket Top 2 x (0805) no-stuff
sites

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1

PC1112

PC1113

PC1114

PC1115

PC1116

PC1117

PC1118

PC1119
<BOM Structure>
PC1106 PC1107 PC1108 PC1109 PC1110 PC1111
10U_0805_6.3V7K 10U_0805_6.3V7K 10U_0805_6.3V7K 10U_0805_6.3V7K 10U_0805_6.3V7K 10U_0805_6.3V7K 2011_0808 place power name
2 2 2 2 2 2 2 2 2 2 2 2 2 2
change form +V1.05S_VCCP +1.05VS
to +1.05VS
+CPU_CORE 2011_0727 <BOM Structure>
<BOM Structure>
<BOM Structure>
<BOM Structure> +1.05VS
chang net name

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
2011_0901 unmount PC1114,PC1115 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 PC1118,PC1119 <BOM Structure>

PC1125

PC1126

PC1127

PC1128

PC1129

PC1130

PC1131

PC1132

PC1133

PC1134

PC1135
PC1120 PC1121 PC1122 PC1123 PC1124
2 2 2 2 2 2 2 2 2 2 2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 1 1 1 1 1 1 1 1
2 2 2 2 2

PC1136

PC1137

PC1138

PC1139

PC1140

PC1141

PC1142

PC1143
2 2 2 2 2 2 2 2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1 1 1 1 1 1 1 1
1 1 1 1 1 <BOM Structure>
<BOM Structure>
<BOM Structure> <BOM Structure> <BOM Structure>

PC1149

PC1150

PC1151

PC1152

PC1153

PC1154

PC1155

PC1156
2011_0901 mount PC1140,PC1141
PC1144 PC1145 PC1146 PC1147 PC1148 PC1142,PC1143
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 2 2 2 2 2 2 2 2
2 2 2 2 2
1 1 1

330U_D2_2VM_R9M

330U_D2_2VM_R9M

330U_D2_2VM_R9M
@

PC1158

PC1159

PC1160
+ + +
C C

2 3 2 3 2 3 1

330U_D2_2.5VY_R9M
+

PC714
1 1 1 1 1
PC1161 PC1162 PC1163 PC1164 PC1165
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 2
2 2 2 2 2 2011_0815 PC1160
change form unmount
2011_0815 del PC1157 to mount
2011_0815 PC714 change place
form "+1.05VS_VCCPP" to "+1.05VS"
1 1 1 1 2011_07929
<BOM Structure> <BOM Structure> <BOM Structure> PC1158 non-mount
PC1169 PC1170 PC1171 PC1172
2011_1005 PC714 change to
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 330uF_2V_R9M
2 2 2 2

+CPU_CORE 2011_0727 2011_1007


chang net name PC714
form SGA00001Q802
(S POLY C 330U 2V M X LESR6M SX H1.9)
change to SGA00002680
1 1 1
(330U_D2_2.5VY_R9M)
+ PC1174 + PC1175 + PC1176

330U_D2_2VM_R9M 330U_D2_2VM_R9M 330U_D2_2VM_R9M


B 2 3 2 3 2 3 B

2011_1230
PC1173 unmount
2011_1005
1@ 1 chang to 330uF_2V_R9M
+ PC1177 + PC1178
2011_1230
470U_D2_2VM_R4.5M 330U_D2_2VM_R9M PC1175,PC1176 change to SGA00006100
2 3 2 3

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2012/07/01 Deciphered Date 2014/07/01 PWR-PROCESSOR DECOUPLING
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

WWW.AliSaler.Com 5 4 3 2
Date: Thursday, November 01, 2012 Sheet
1
55 of 59
A B C D

2011_0923 JUMP form 43X79 change to 43X79

1 1

PU1201 PL1201
PJ1201 1UH_PH041H-1R0MS_3.8A_20%
+5VALW
2 1 1.05VMP_VIN 4 3 1.05VMP_LX 1 2
2 1 IN LX +1.05VMP
5 2

68P_0402_50V8J
JUMP_43X39 1 PG GND

1
PC1201

680P_0603_50V7K 4.7_1206_5%

1
@ 6 1

PC1202
PC1207 22U_0805_6.3VAM
FB EN

PR1201
22U_0805_6.3V6M PR1202

2
2 7.5K_0402_1%

2
PJ1202

22U_0805_6.3VAM

22U_0805_6.3VAM
SY8032ABC_SOT23-6

1 2

1
+1.05VMP 2 1 +1.05VM
2 1

PC1204

PC1205
FB=0.6Volt

PC1203
PR1203 @ JUMP_43X79

2
1 2 EN_1.05VMP

2
41,43 M_PWR_ON
0_0402_5%

47P_0402_50V8J

47P_0402_50V8J
0.1U_0402_10V7K
2
1.05VMP max current=1A 1 1

PC1206
PR1204

RFC55

RFC56
1M_0402_5%
1.05VMP_FB

2
1 2 2

1
PR1205
10K_0402_1%

2
2 2

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 PWR-+1.05VMP


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

WWW.AliSaler.Com DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 56 of 59
A B C D
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 PWR-Thermal Protect-NA


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A

WWW.AliSaler.Com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 57 of 59
5 4 3 2 1
5 4 3 2 1

Version change list (P.I.R. List)


Item Reason for change PG# Modify List Date Phase

1
2

D
3 D

4
5
6
7
8
9
10

11

C
12 C

13
14
15
16
17

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 PWR-PIR


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.A

WWW.AliSaler.Com
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 58 of 59
5 4 3 2 1
1 2 3 4 5

Version Change List (P.I.R. List)


Phase Date No. BOM Sch Layout Description function

2012/09/XX No1 V V V Add CXXX,CXXX Add XXX function

A A

B B

C C

D D

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 EE P.I.R.


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
NM-A041
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A

WWW.AliSaler.Com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, November 01, 2012 Sheet 59 of 59
1 2 3 4 5

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