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Compal La-9351p r0.1 Schematics
Compal La-9351p r0.1 Schematics
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VBL30/31 LA-9351P M/B
Date: Monday, July 16, 2012 Sheet 1 of 50
5 4 3 2 1
5 4 3 2 1
Compal Confidential
Model Name : VBL30/31 Fan CONN
page 38
File Name :LA-9351P PCI-E X16 Mobile IVY Bridge
CPU Dual / Quad Core
D Memory BUS(DDRIII) D
C
HDMI Conn. 989pin FCBGA C
USB30 USB 3.0 conn
page 33
SPI ROM SATA port
page 37
Power/B
page 38
Touch Pad/B
page 38
RTC CKT.
page 30
A
DC/DC Interface CKT. A
page 39
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
page 40~50 Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VBL30/31 LA-9351P M/B
Date: Monday, July 16, 2012 Sheet 2 of 50
5 4 3 2 1
5 4 3 2 1
RT8205
Ipeak=5A, Imax=3.5A, Iocp min=7.7 DESIGN CURRENT 5A +3VALW
WOL_EN#
P-CHANNEL DESIGN CURRENT 330mA +3V_LAN
AO-3413
SUSP
N-CHANNEL DESIGN CURRENT 4A +3VS
SI4800
VGA_ENVDD
P-CHANNEL DESIGN CURRENT 1.5A +LCD_VDD
AO-3413
BT_PWR#
DESIGN CURRENT 180mA +BT_VCC
P-CHANNEL
AO-3413
PCIE_OK
DESIGN CURRENT 100mA +3VS_DELAY
C C
P-CHANNEL
AO-3413
VR_ON
DESIGN CURRENT 52A +CPU_CORE
NCP6132AMNR2G
DGPU_PWR_EN / SUSP#
SUSP#
Ipeak=18A, Imax=12.6A, Iocp min=19.8 DESIGN CURRENT 18A +1.05VS_VCCP
TPS51212DSCR
B B
SYSON
Ipeak=15A, Imax=10.5A, Iocp min=16.5 DESIGN CURRENT 15A +1.5V +1.5V_CPU
RT8209BGQW
CPU1.5V_S3_GATE / SUSP
SUSP
DESIGN CURRENT 12A +1.5VS
SI4856ADY
SUSP#
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Map
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VBL30/31 LA-9351P M/B
Date: Monday, July 16, 2012 Sheet 3 of 50
5 4 3 2 1
5 4 3 2 1
Voltage Rails
S0
O O O O SMBUS Control Table
Thermal
WLAN Sensor
S3
O O O SOURCE VGA BATT KB9012 SODIMM PCH
C X WWAN C
SMB_EC_CK1
S5 S4/AC
O O X X SMB_EC_DA1
KB9012 X V X X X X X
+3VALW +3VALW
SMB_EC_CK2
S5 S4/ Battery only
O X X X SMB_EC_DA2
KB9012 X X X X X X V
+3VS
+3VALW
SMBCLK
S5 S4/AC & Battery
X X X X SMBDATA
PCH X X X V
+3VS
V
+3VS
X X
don't exist +3VALW
SML0CLK
SIGNAL SML0DATA
PCH X X X X X X X
+3VALW
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
SML1CLK
Full ON HIGH HIGH HIGH HIGH ON ON ON ON SML1DATA
PCH V
+3VS
X V
+3VS
X X +3VS
V X
+3VALW
1XYWRQ# 1YXWRQ(&
ZZZ DAZ@ ZZZ DA8@ ZZZ DA4@ ZZZ DA2@
:,1# 6XSSRUW:LQ
A PCB LA-6732P REV10 PCB LA-9351P REV01 PCB LS-6732P REV10 PCB LS-6731P REV10 A
;ΛͬKEEΛͬϮΛͬϰΛͬϴΛͬΛͬ<ϵϬϭϮΛͬEKtϴΛͬEƵǀƚŽŶΛͬW,ΛͬWyΛͬZĞǀϬϭΛͬZĞǀϬϮΛͬZĞǀϬϯΛͬZĞǀϬϰΛͬZĞǀϭϬΛͬhDΛͬt/EϴΛͬyϳϲΛͿ
80$# 80$6NX
Security Classification Compal Secret Data Compal Electronics, Inc.
3;# 3;6NX Issued Date 2012/06/01 Deciphered Date 2013/05/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom VBL30/31 LA-9351P M/B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, July 16, 2012 Sheet 4 of 50
5 4 3 2 1
5 4 3 2 1
+1.05VS_VCCP
JCPU1I
RC2 PEG_ICOMPI and RCOMPO signals should be shorted and routed
24.9_0402_1% with - max length = 500 mils - typical impedance = 43 mohms
PEG_ICOMPO signals should be routed with - max length = 500 mils T35 F22
JCPU1A - typical impedance = 14.5 mohms T34 VSS161 VSS234 F19
D J22 PEG_COMP T33 VSS162 VSS235 E30 D
PEG_ICOMPI J21 T32 VSS163 VSS236 E27
B27 PEG_ICOMPO H22 T31 VSS164 VSS237 E24
<21> DMI_PTX_CRX_N0 DMI_RX#[0] PEG_RCOMPO VSS165 VSS238
<21> DMI_PTX_CRX_N1 B25 T30 E21
A25 DMI_RX#[1] T29 VSS166 VSS239 E18
<21> DMI_PTX_CRX_N2 DMI_RX#[2] PCIE_GTX_C_CRX_N[0..15] <13> VSS167 VSS240
<21> DMI_PTX_CRX_N3 B24 K33 PCIE_GTX_C_CRX_N0 T28 E15
DMI_RX#[3] PEG_RX#[0] M35 PCIE_GTX_C_CRX_N1 T27 VSS168 VSS241 E13
B28 PEG_RX#[1] L34 PCIE_GTX_C_CRX_N2 T26 VSS169 VSS242 E10
<21> DMI_PTX_CRX_P0 DMI_RX[0] PEG_RX#[2] VSS170 VSS243
<21> DMI_PTX_CRX_P1 B26 J35 PCIE_GTX_C_CRX_N3 P9 E9
A24 DMI_RX[1] PEG_RX#[3] J32 PCIE_GTX_C_CRX_N4 P8 VSS171 VSS244 E8
<21> DMI_PTX_CRX_P2
DMI
B23 DMI_RX[2] PEG_RX#[4] H34 PCIE_GTX_C_CRX_N5 P6 VSS172 VSS245 E7
<21> DMI_PTX_CRX_P3 DMI_RX[3] PEG_RX#[5] VSS173 VSS246
H31 PCIE_GTX_C_CRX_N6 P5 E6
G21 PEG_RX#[6] G33 PCIE_GTX_C_CRX_N7 P3 VSS174 VSS247 E5
<21> DMI_CTX_PRX_N0 DMI_TX#[0] PEG_RX#[7] VSS175 VSS248
E22 G30 PCIE_GTX_C_CRX_N8 P2 E4
<21> DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8] VSS176 VSS249
F21 F35 PCIE_GTX_C_CRX_N9 N35 E3
<21> DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9] VSS177 VSS250
D21 E34 PCIE_GTX_C_CRX_N10 N34 E2
<21> DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10] VSS178 VSS251
E32 PCIE_GTX_C_CRX_N11 N33 E1
G22 PEG_RX#[11] D33 PCIE_GTX_C_CRX_N12 N32 VSS179 VSS252 D35
<21> DMI_CTX_PRX_P0 DMI_TX[0] PEG_RX#[12] VSS180 VSS253
D22 D31 PCIE_GTX_C_CRX_N13 N31 D32
<21> DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13] VSS181 VSS254
F20 B33 PCIE_GTX_C_CRX_N14 N30 D29
Intel(R) FDI
B21 F33 PCIE_GTX_C_CRX_P7 L8 C10
<21> FDI_CTX_PRX_N4 FDI1_TX#[0] PEG_RX[7] VSS192 VSS265
C20 F30 PCIE_GTX_C_CRX_P8 L6 C1
<21> FDI_CTX_PRX_N5 FDI1_TX#[1] PEG_RX[8] VSS193 VSS266
D18 E35 PCIE_GTX_C_CRX_P9 L5 B22
C <21> FDI_CTX_PRX_N6 FDI1_TX#[2] PEG_RX[9] VSS194 VSS267 C
E17 E33 PCIE_GTX_C_CRX_P10 L4 B19
<21> FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
F32
D34
PCIE_GTX_C_CRX_P11
PCIE_GTX_C_CRX_P12
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
A22 E31 PCIE_GTX_C_CRX_P13 L1 B13
<21> FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13] VSS198 VSS271
G19 C33 PCIE_GTX_C_CRX_P14 K35 B11
<21> FDI_CTX_PRX_P1 FDI0_TX[1] PEG_RX[14] VSS199 VSS272
E20 B32 PCIE_GTX_C_CRX_P15 K32 B9
<21> FDI_CTX_PRX_P2 FDI0_TX[2] PEG_RX[15] VSS200 VSS273
G18 K29 B8
<21> FDI_CTX_PRX_P3 FDI0_TX[3] PCIE_CTX_C_GRX_N[0..15] <13> VSS201 VSS274
B20 M29 PCIE_CTX_GRX_N0 PX@ C136 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N0 K26 B7
<21> FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0] VSS202 VSS275
C19 M32 PCIE_CTX_GRX_N1 PX@ C222 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N1 J34 B5
<21> FDI_CTX_PRX_P5 FDI1_TX[1] PEG_TX#[1] VSS203 VSS276
D19 M31 PCIE_CTX_GRX_N2 PX@ C60 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N2 J31 B3
<21> FDI_CTX_PRX_P6 FDI1_TX[2] PEG_TX#[2] VSS204 VSS277
F17 L32 PCIE_CTX_GRX_N3 PX@ C67 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N3 H33 B2
<21> FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3] VSS205 VSS278
L29 PCIE_CTX_GRX_N4 PX@ C75 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N4 H30 A35
FDI_FSYNC0 J18 PEG_TX#[4] K31 PCIE_CTX_GRX_N5 PX@ C118 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N5 H27 VSS206 VSS279 A32
<21> FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5] VSS207 VSS280
<21> FDI_FSYNC1 FDI_FSYNC1 J17 K28 PCIE_CTX_GRX_N6 PX@ C220 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N6 H24 A29
FDI1_FSYNC PEG_TX#[6] J30 PCIE_CTX_GRX_N7 PX@ C59 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N7 H21 VSS208 VSS281 A26
FDI_INT H20 PEG_TX#[7] J28 PCIE_CTX_GRX_N8 PX@ C62 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N8 H18 VSS209 VSS282 A23
<21> FDI_INT FDI_INT PEG_TX#[8] VSS210 VSS283
H29 PCIE_CTX_GRX_N9 PX@ C70 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N9 H15 A20
FDI_LSYNC0 J19 PEG_TX#[9] G27 PCIE_CTX_GRX_N10 PX@ C115 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N10 H13 VSS211 VSS284 A3
<21> FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10] VSS212 VSS285
<21> FDI_LSYNC1 FDI_LSYNC1 H17 E29 PCIE_CTX_GRX_N11 PX@ C197 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N11 H10
FDI1_LSYNC PEG_TX#[11] F27 PCIE_CTX_GRX_N12 PX@ C223 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N12 H9 VSS213
PEG_TX#[12] D28 PCIE_CTX_GRX_N13 PX@ C61 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N13 H8 VSS214
PEG_TX#[13] F26 PCIE_CTX_GRX_N14 PX@ C68 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N14 H7 VSS215
PEG_TX#[14] E25 PCIE_CTX_GRX_N15 PX@ C88 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N15 H6 VSS216
A18 PEG_TX#[15] H5 VSS217
eDP_COMPIO PCIE_CTX_C_GRX_P[0..15] <13> VSS218
A17 M28 PCIE_CTX_GRX_P0 PX@ C209 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P0 H4
B16 eDP_ICOMPO PEG_TX[0] M33 PCIE_CTX_GRX_P1 PX@ C224 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P1 H3 VSS219
RC4 24.9_0402_1% eDP_HPD# PEG_TX[1] M30 PCIE_CTX_GRX_P2 PX@ C66 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P2 H2 VSS220
EDP_COMP PEG_TX[2] L31 PCIE_CTX_GRX_P3 PX@ C69 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P3 H1 VSS221
+1.05VS_VCCP PEG_TX[3] VSS222
C15 L28 PCIE_CTX_GRX_P4 PX@ C89 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P4 G35
D15 eDP_AUX PEG_TX[4] K30 PCIE_CTX_GRX_P5 PX@ C135 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P5 G32 VSS223
EDP_HPD# eDP_AUX# PEG_TX[5] K27 PCIE_CTX_GRX_P6 PX@ C221 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P6 G29 VSS224
+1.05VS_VCCP
eDP
TYCO_2013620-2_IVY BRIDGE
CONN@
TYCO_2013620-2_IVY BRIDGE
CONN@
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(1/6) DMI,FDI,PEG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom VBL30/31 LA-9351P M/B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, July 16, 2012 Sheet 5 of 50
5 4 3 2 1
5 4 3 2 1
<21> SYS_PWROK
+3V_PCH
+3VS +3V_PCH +3VS
0.1U_0402_16V4Z
+1.5V_CPU_VDDQ
CC33
R104 RC13
RC15 RC11 @ 10K_0402_5% R81
200_0402_1% 200_0402_1% 0_0402_5% 200_0402_1%
@
5
D U5 D
1
G VCC
B 4 PM_SYS_PWRGD_BUF
D_PWG 2 Y
<21> DRAMPWROK A
RC21 0_0402_5%
MC74VHC1G09DFT2G_SC70-5
3
@
R110
39_0402_1%
SSM3K7002FU_SC70-3
@
<10> RUN_ON_CPU1.5VS3# RC17 @ Q5
1
D
0_0402_5% 2
G
<11,39> SUSP @ RC16 S
3
0_0402_5%
+3VS +1.05VS_VCCP
0.1U_0402_16V4Z
R64
C84
75_0402_5%
C C
1
U3 R72
P
NC
<22,31,32,36> PLT_RST# 2 4 BUFO_CPU_RST# BUF_CPU_RST#
A Y 43_0402_1%
G
SN74LVC1G07DCKR_SC70-5
3
@
R73
JCPU1B 0_0402_5%
+1.05VS_VCCP
Processor Pullups
T504 @
MISC
CLOCKS
<23> H_SNB_IVB# PROC_SELECT# BCLK# CLK_CPU_DMI# <20>
T505 @
AN34
SKTOCC# A16 CLK_CPU_DPLL_R R126 1K_0402_5%
DPLL_REF_CLK PU/PD for JTAG signals
A15 CLK_CPU_DPLL#_R R115 1K_0402_5% +1.05VS_VCCP
DPLL_REF_CLK# +1.05VS_VCCP
THERMAL
RC44 1 2H_PECI_R AN33 R8 H_DRAMRST# XDP_TDI_R 51_0402_5% R59
<23,36> H_PECI PECI SM_DRAMRST# H_DRAMRST# <7>
43_0402_1%
DDR3 Compensation Signals XDP_PREQ#_R 51_0402_5% @ R60
DDR3
MISC
R58
<36,40> H_PROCHOT# H_PROCHOT#_R AL32 AK1 SM_RCOMP_0 SM_RCOMP_0 140_0402_1% RC42 XDP_TDO_R 51_0402_5% R75
56_0402_5% PROCHOT# SM_RCOMP[0] A5 SM_RCOMP_1
B SM_RCOMP[1] A4 SM_RCOMP_2 SM_RCOMP_1 25.5_0402_1% RC43 B
SM_RCOMP[2]
H_THERMTRIP# AN32 SM_RCOMP_2 200_0402_1% RC45 XDP_TCK_R 51_0402_5% R116
<23> H_THERMTRIP# THERMTRIP#
XDP_TRST#_R 51_0402_5% R74
AP29 XDP_PRDY#_R
PRDY# AP27 XDP_PREQ#_R
PREQ#
AR26 XDP_TCK_R
TCK AR27 XDP_TMS_R
PWR MANAGEMENT
TMS
JTAG & BPM
A A
TYCO_2013620-2_IVY BRIDGE
CONN@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(2/6) PM,XDP,CLK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom VBL30/31 LA-9351P M/B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, July 16, 2012 Sheet 6 of 50
5 4 3 2 1
5 4 3 2 1
JCPU1C
JCPU1D
AB6
<11> DDR_A_D[0..63] SA_CLK[0] DDRA_CLK0 <11>
AA6
SA_CLK#[0] DDRA_CLK0# <11>
D DDR_A_D0 C5 V9 AE2 D
SA_DQ[0] SA_CKE[0] DDRA_CKE0 <11> <12> DDR_B_D[0..63] SB_CLK[0] DDRB_CLK0 <12>
DDR_A_D1 D5 AD2
SA_DQ[1] SB_CLK#[0] DDRB_CLK0# <12>
DDR_A_D2 D3 DDR_B_D0 C9 R9
SA_DQ[2] SB_DQ[0] SB_CKE[0] DDRB_CKE0 <12>
DDR_A_D3 D2 DDR_B_D1 A7
DDR_A_D4 D6 SA_DQ[3] AA5 DDR_B_D2 D10 SB_DQ[1]
SA_DQ[4] SA_CLK[1] DDRA_CLK1 <11> SB_DQ[2]
DDR_A_D5 C6 AB5 DDR_B_D3 C8
SA_DQ[5] SA_CLK#[1] DDRA_CLK1# <11> SB_DQ[3]
DDR_A_D6 C2 V10 DDR_B_D4 A9 AE1
SA_DQ[6] SA_CKE[1] DDRA_CKE1 <11> SB_DQ[4] SB_CLK[1] DDRB_CLK1 <12>
DDR_A_D7 C3 DDR_B_D5 A8 AD1
SA_DQ[7] SB_DQ[5] SB_CLK#[1] DDRB_CLK1# <12>
DDR_A_D8 F10 DDR_B_D6 D9 R10
SA_DQ[8] SB_DQ[6] SB_CKE[1] DDRB_CKE1 <12>
DDR_A_D9 F8 DDR_B_D7 D8
DDR_A_D10 G10 SA_DQ[9] AB4 DDR_B_D8 G4 SB_DQ[7]
DDR_A_D11 G9 SA_DQ[10] RSVD_TP[1] AA4 DDR_B_D9 F4 SB_DQ[8]
DDR_A_D12 F9 SA_DQ[11] RSVD_TP[2] W9 DDR_B_D10 F1 SB_DQ[9] AB2
DDR_A_D13 F7 SA_DQ[12] RSVD_TP[3] DDR_B_D11 G1 SB_DQ[10] RSVD_TP[11] AA2
DDR_A_D14 G8 SA_DQ[13] DDR_B_D12 G5 SB_DQ[11] RSVD_TP[12] T9
DDR_A_D15 G7 SA_DQ[14] DDR_B_D13 F5 SB_DQ[12] RSVD_TP[13]
DDR_A_D16 K4 SA_DQ[15] AB3 DDR_B_D14 F2 SB_DQ[13]
DDR_A_D17 K5 SA_DQ[16] RSVD_TP[4] AA3 DDR_B_D15 G2 SB_DQ[14]
DDR_A_D18 K1 SA_DQ[17] RSVD_TP[5] W10 DDR_B_D16 J7 SB_DQ[15] AA1
DDR_A_D19 J1 SA_DQ[18] RSVD_TP[6] DDR_B_D17 J8 SB_DQ[16] RSVD_TP[14] AB1
DDR_A_D20 J5 SA_DQ[19] DDR_B_D18 K10 SB_DQ[17] RSVD_TP[15] T10
DDR_A_D21 J4 SA_DQ[20] DDR_B_D19 K9 SB_DQ[18] RSVD_TP[16]
DDR_A_D22 J2 SA_DQ[21] AK3 DDR_B_D20 J9 SB_DQ[19]
SA_DQ[22] SA_CS#[0] DDRA_SCS0# <11> SB_DQ[20]
DDR_A_D23 K2 AL3 DDR_B_D21 J10
SA_DQ[23] SA_CS#[1] DDRA_SCS1# <11> SB_DQ[21]
DDR_A_D24 M8 AG1 DDR_B_D22 K8 AD3
SA_DQ[24] RSVD_TP[7] SB_DQ[22] SB_CS#[0] DDRB_SCS0# <12>
DDR_A_D25 N10 AH1 DDR_B_D23 K7 AE3
SA_DQ[25] RSVD_TP[8] SB_DQ[23] SB_CS#[1] DDRB_SCS1# <12>
DDR_A_D26 N8 DDR_B_D24 M5 AD6
DDR_A_D27 N7 SA_DQ[26] DDR_B_D25 N4 SB_DQ[24] RSVD_TP[17] AE6
DDR_A_D28 M10 SA_DQ[27] DDR_B_D26 N2 SB_DQ[25] RSVD_TP[18]
DDR_A_D29 M9 SA_DQ[28] AH3 DDR_B_D27 N1 SB_DQ[26]
SA_DQ[29] SA_ODT[0] DDRA_ODT0 <11> SB_DQ[27]
DDR_A_D30 N9 AG3 DDR_B_D28 M4
SA_DQ[30] SA_ODT[1] DDRA_ODT1 <11> SB_DQ[28]
DDR SYSTEM MEMORY A
TYCO_2013620-2_IVY BRIDGE
@ R123
R124 0_0402_5% 1K_0402_5%
Q6
S
R119
4.99K_0402_1% DRAMRST_CNTRL DRAMRST_CNTRL_PCH <10,20>
R118 0_0402_5%
A A
2 1
DRAMRST_CNTRL_EC <36>
R83 DS3@ 0_0402_5%
DS3
C86
0.047U_0402_16V4Z
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/06/01 Deciphered Date 2013/05/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(3/6) DDRIII
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom VBL30/31 LA-9351P M/B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, July 16, 2012 Sheet 7 of 50
5 4 3 2 1
5 4 3 2 1
JCPU1E RC51
1K_0402_1%
AH27 @ T0749
T1 @ CFG0 AK28 VCC_DIE_SENSE AH26 @ T0750
T2 @ CFG1 AK29 CFG[0] VSS_DIE_SENSE
T3 @ CFG2 AL26 CFG[1]
T4 @ CFG3 AL27 CFG[2]
T5 @ CFG4 AK26 CFG[3] L7 @ T0704
T6 @ CFG5 AL29 CFG[4] RSVD28 AG7 @ T0705
CFG[5] RSVD29 PEG Static Lane Reversal - CFG2 is for the 16x
T7 @ CFG6 AL30 AE7 @ T0701
T8 @ CFG7 AM31 CFG[6] RSVD30 AK2 @ T0702
T9 @ CFG8 AM32 CFG[7] RSVD31
CFG[8] 1:(Default) Normal Operation; Lane #
T10 @ CFG9 AM30 W8 @ T0706 CFG2
CFG
T11 @ CFG10 AM28 CFG[9] RSVD32 definition matches socket pin map definition
T12 @ CFG11 AM26 CFG[10]
CFG[11] 0:Lane Reversed
T13 @ CFG12 AN28 AT26 @ T0707
T14 @ CFG13 AN31 CFG[12] RSVD33 AM33 @ T0708
T15 @ CFG14 AN26 CFG[13] RSVD34 AJ27 @ T0709
T16 @ CFG15 AM27 CFG[14] RSVD35 CFG4
T17 @ CFG16 AK31 CFG[15]
T18 @ CFG17 AN29 CFG[16]
CFG[17] @ RC52
1K_0402_1%
T8 @ T0710
RSVD37 J16 @ T0711
AJ31 RSVD38 H16 @ T0703
AH31 VAXG_VAL_SENSE RSVD39 G16 @ T0712
AJ33 VSSAXG_VAL_SENSE RSVD40
AH33 VCC_VAL_SENSE
C VSS_VAL_SENSE C
RESERVED
RSVD_NCTF2 AT33 @ T0715
RSVD_NCTF3 AP35 @ T0716
RSVD_NCTF4 1 : Disabled; No Physical Display Port
AR34 @ T0717 CFG4
RSVD_NCTF5 attached to Embedded Display Port
T0724 @ F25 0 : Enabled; An external Display Port device is
T0725 @ F24 RSVD8
T0726 @ F23 RSVD9 connected to the Embedded Display Port
T0727 @ D24 RSVD10 B34 @ T0719
T0729 @ G25 RSVD11 RSVD_NCTF6 A33 @ T0720
T0731 @ G24 RSVD12 RSVD_NCTF7 A34 @ T0721
T0732 @ E23 RSVD13 RSVD_NCTF8 B35 @ T0722 CFG6
T0733 @ D23 RSVD14 RSVD_NCTF9 C35 @ T0723
T0734 @ C30 RSVD15 RSVD_NCTF10 CFG5
T0735 @ A31 RSVD16
T0736 @ B30 RSVD17
T0737 @ B29 RSVD18 @ RC54 @ RC53
T0738 @ D30 RSVD19 AJ32 @ T0728 1K_0402_1% 1K_0402_1%
T0739 @ B31 RSVD20 RSVD51 AK32 @ T0730
T0740 @ A30 RSVD21 RSVD52
T0741 @ C29 RSVD22
RSVD23
AN35 CLK_RES_ITP <20>
T0742 @ J20 BCLK_ITP AM35
RSVD24 BCLK_ITP# CLK_RES_ITP# <20>
T0743 @ B18
RSVD25
CONN@
CFG7
@ RC56
1K_0402_1%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(4/6) RSVD,CFG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom VBL30/31 LA-9351P M/B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, July 16, 2012 Sheet 8 of 50
5 4 3 2 1
5 4 3 2 1
AT35
JCPU1H
AJ22
JCPU1F POWER
AT32 VSS1 VSS81 AJ19
AT29 VSS2 VSS82 AJ16
AT27 VSS3 VSS83 AJ13 +1.05VS_VCCP
AT25 VSS4 VSS84 AJ10 +CPU_CORE
AT22 VSS5 VSS85 AJ7
D AT19 VSS6 VSS86 AJ4 8.5A D
AT16 VSS7 VSS87 AJ3 97AAG35
AT13 VSS8 VSS88 AJ2 AG34 VCC1 AH13
AT10 VSS9 VSS89 AJ1 AG33 VCC2 VCCIO1 AH10
AT7 VSS10 VSS90 AH35 AG32 VCC3 VCCIO2 AG10
AT4 VSS11 VSS91 AH34 AG31 VCC4 VCCIO3 AC10
AT3 VSS12 VSS92 AH32 AG30 VCC5 VCCIO4 Y10
AR25 VSS13 VSS93 AH30 AG29 VCC6 VCCIO5 U10
AR22 VSS14 VSS94 AH29 AG28 VCC7 VCCIO6 P10
AR19 VSS15 VSS95 AH28 AG27 VCC8 VCCIO7 L10
AR16 VSS16 VSS96 AH25 AG26 VCC9 VCCIO8 J14
AR13 VSS17 VSS98 AH22 AF35 VCC10 VCCIO9 J13
AR10 VSS18 VSS99 AH19 AF34 VCC11 VCCIO10 J12
AR7 VSS19 VSS100 AH16 AF33 VCC12 VCCIO11 J11
AR4 VSS20 VSS101 AH7 AF32 VCC13 VCCIO12 H14
AR2 VSS21 VSS102 AH4 AF31 VCC14 VCCIO13 H12
AP34 VSS22 VSS103 AG9 AF30 VCC15 VCCIO14 H11
AP31 VSS23 VSS104 AG8 AF29 VCC16 VCCIO15 G14
AP28 VSS24 VSS105 AG4 AF28 VCC17 VCCIO16 G13
AP25 VSS25 VSS106 AF6 AF27 VCC18 VCCIO17 G12
CORE SUPPLY
AL28 VSS58 VSS139 Y8 Y34 VCC51 +1.05VS_VCCP +1.05VS_VCCP
AL25 VSS59 VSS140 Y6 Y33 VCC52
AL22 VSS60 VSS141 Y5 Y32 VCC53
VSS61 VSS142 VCC54 Place the PU
AL19 Y3 Y31
AL16 VSS62 VSS143 Y2 Y30 VCC55 resistors close to CPU
AL13 VSS63 VSS144 W35 Y29 VCC56 RC137 RC60
AL10 VSS64 VSS145 W34 Y28 VCC57
VSS65 VSS146 VCC58 130_0402_1% 75_0402_5%
AL7 W33 Y27
AL4 VSS66 VSS147 W32 Y26 VCC59
AL2 VSS67 VSS148 W31 V35 VCC60
AK33 VSS68 VSS149 W30 V34 VCC61 AJ29 H_CPU_SVIDALRT# RC61 43_0402_1%
SVID
VSS69 VSS150 VCC62 VIDALERT# VR_SVID_ALRT# <47>
AK30 W29 V33 AJ30 H_CPU_SVIDCLK RC59 0_0402_5%
VSS70 VSS151 VCC63 VIDSCLK VR_SVID_CLK <47>
AK27 W28 V32 AJ28 H_CPU_SVIDDAT RC65 0_0402_5%
VSS71 VSS152 VCC64 VIDSOUT VR_SVID_DAT <47>
AK25 W27 V31
AK22 VSS72 VSS153 W26 V30 VCC65
AK19 VSS73 VSS154 U9 V29 VCC66
AK16 VSS74 VSS155 U8 V28 VCC67
AK13 VSS75 VSS156 U6 V27 VCC68
AK10 VSS76 VSS157 U5 V26 VCC69
AK7 VSS77 VSS158 U3 U35 VCC70
B B
AK4 VSS78 VSS159 U2 U34 VCC71
AJ25 VSS79 VSS160 U33 VCC72
VSS80 U32 VCC73
U31 VCC74
U30 VCC75
U29 VCC76
TYCO_2013620-2_IVY BRIDGE U28 VCC77
U27 VCC78
U26 VCC79
CONN@ VCC80 Place the PU +CPU_CORE
R35
R34 VCC81 resistors close to CPU
R33 VCC82
R32 VCC83
R31 VCC84 R53
R30 VCC85
VCC86 100_0402_1%
R29
R28 VCC87
SENSE LINES
R158
10_0402_1% Close to CPU +1.05VS_VCCP
A A
2
CONN@ 10_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(5/6) PWR,BYPASS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom VBL30/31 LA-9351P M/B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, July 16, 2012 Sheet 9 of 50
5 4 3 2 1
5 4 3 2 1
+1.5V_CPU_VDDQ
+1.5V Q7 +1.5V_CPU_VDDQ
+3VALW +VSB MDU1512RH_PPAK56-8-5
1
2
5 3
2
R135
D R134 100K_0402_5% R131 D
4
100K_0402_5% 220_0402_5%
RUN_ON_CPU1.5VS3
1
3
330K_0402_5%
0.1U_0603_50V7K
1
Q208B D
R136
RUN_ON_CPU1.5VS3# 5 2 RUN_ON_CPU1.5VS3#
RUN_ON_CPU1.5VS3# <6>
C196
G
@ R132 2N7002DW-7-F_SOT363-6 S Q8
3
<36,39,43,44,45,50> SUSP# 2N7002H 1N SOT23-3
6
0_0402_5%
Q208A
R133 2N7002DW-7-F_SOT363-6
<36> CPU1.5V_S3_GATE 2
0_0402_5%
1
@ RC100
100K_0402_5%
JCPU1G
POWER VSS_AXG_SENSE R79 100_0402_1%
+V_SM_VREF should
have 10 mil trace width
RC77
@
0_0402_5%
+V_DDR_REFA +VREF_CA
RC79 @ RC83
33A AT24 AK35 VREFDQ_DIMMA_CPU 2 3
SENSE
LINES
D
AR18 AL1 +V_SM_VREF_CNT 3 1 +V_SM_VREF @
AR17 VAXG11 SM_VREF
AP24 VAXG12
VREF
G
2
AP21 VAXG14 RC119
AP20 VAXG15 B4 VREFDQ_DIMMA_CPU 1K_0402_1% RC78 0_0402_5%
AP18 VAXG16 SA_DIMM_VREFDQ D1 VREFDQ_DIMMB_CPU @ +V_DDR_REFB +VREF_CB
AP17 VAXG17 SB_DIMM_VREFDQ RUN_ON_CPU1.5VS3
AN24 VAXG18
AN23 VAXG19 RC80 @ RC84
AN21 VAXG20 VREFDQ_DIMMB_CPU 2 3
AN20 VAXG21 +1.5V_CPU_VDDQ 0_0402_5% @
AN18 VAXG22 +1.5V 0_0402_5%
DDR3 -1.5V RAILS
10U_0805_10VM
10U_0805_10VM
10U_0805_10VM
10U_0805_10VM
10U_0805_6.3V6M
AM20 AC7 1
VAXG28 VDDQ4
330U_D2_2V_Y
AM18 AC4 DRAMRST_CNT
VAXG29 VDDQ5
CC56
AM17 AC1 +
VAXG30 VDDQ6
CC51
CC52
CC53
CC54
CC55
CC57
AL24 Y7
AL23 VAXG31 VDDQ7 Y4
AL21 VAXG32 VDDQ8 Y1 2
AL20 VAXG33 VDDQ9 U7
AL18 VAXG34 VDDQ10 U4
AL17 VAXG35 VDDQ11 U1
AK24 VAXG36 VDDQ12 P7
AK23 VAXG37 VDDQ13 P4
AK21 VAXG38 VDDQ14 P1
AK20 VAXG39 VDDQ15
AK18 VAXG40
AK17 VAXG41
AJ24 VAXG42
AJ23 VAXG43
B AJ21 VAXG44 B
AJ20 VAXG45
AJ18 VAXG46
AJ17 VAXG47 M27 6A +VCCSA
VAXG48 VCCSA1
SA RAIL
AH24 M26
VAXG49 VCCSA2
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
AH21 J26
AH20 VAXG51 VCCSA4 J25 + RC132 100_0402_5%
VAXG52 VCCSA5
CC168
CC169
CC170
CC172
AH18 J24 @
AH17 VAXG53 VCCSA6 H26
VAXG54 VCCSA7 H25 2
VCCSA8
+1.8VS
1.8V RAIL
H23
VCCSA_SENSE +VCCSA_SENSE <46>
RC120
0_0805_5% 1.5A
+1.8VS_VCCPLL B6
A6 VCCPLL1 C22 @ RC81 +1.5V_CPU_VDDQ +1.5V
MISC
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 A2 C24 0_0402_5%
VCCPLL3 VCCSA_VID[1] H_VCCSA_VID1 <46>
330U_D2_2V_Y
@
CC58
CC59
CC60
+ C199 0.1U_0402_10V7K
CC61
2 2 A19
2 VCCIO_SEL C201 0.1U_0402_10V7K
H_VCCP_SEL VCCP_PWRCTRL
0_0402_5% @ RC114
A A
IVY Bridge drives VCCIO_SEL low
VCCP_PWRCTRL:0
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(6/6) PWR,VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom VBL30/31 LA-9351P M/B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, July 16, 2012 Sheet 10 of 50
5 4 3 2 1
5 4 3 2 1
+1.5V
<7> DDR_A_D[0..63]
+1.5V 4BA2/6W +1.5V
<7> DDR_A_DQS[0..7]
R55
1K_0402_1% DDR3 SO-DIMM A <7> DDR_A_DQS#[0..7]
@ JDDRL
<7> DDR_A_MA[0..15]
+V_DDR_REFA 1 2
3 VREF_DQ VSS1 4 DDR_A_D4
5 VSS2 DQ4
0.1U_0402_10V6K
0.1U_0402_10V6K
2.2U_0603_6.3V6K
DDR_A_D0 6 DDR_A_D5
7 DQ0 DQ5
CD50
CD1
CD2
DDR_A_D1 8
9 DQ1 VSS3 10 DDR_A_DQS#0
R57 11 VSS4 DQS#0 12 DDR_A_DQS0
D 13 DM0 DQS0 14 D
1K_0402_1% DDR_A_D2 15 VSS5 VSS6 16 DDR_A_D6
DDR_A_D3 17 DQ2 DQ6 18 DDR_A_D7
19 DQ3 DQ7 20
DDR_A_D8 21 VSS7 VSS8 22 DDR_A_D12
DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D13
25 DQ9 DQ13 26
DDR_A_DQS#1 27 VSS9 VSS10 28
DDR_A_DQS1 29 DQS#1 DM1 30 SM_DRAMRST# +V_DDR_REFA +V_DDR_REFB
SM_DRAMRST# <7,12>
31 DQS1 RESET# 32
DDR_A_D10 33 VSS11 VSS12 34 DDR_A_D14
DDR_A_D11 35 DQ10 DQ14 36 DDR_A_D15
37 DQ11 DQ15 38 RC82 0_0402_5%
DDR_A_D16 39 VSS13 VSS14 40 DDR_A_D20 @
DDR_A_D17 41 DQ16 DQ20 42 DDR_A_D21
43 DQ17 DQ21 44
DDR_A_DQS#2 45 VSS15 VSS16 46
DDR_A_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_A_D22
DDR_A_D18 51 VSS18 DQ22 52 DDR_A_D23 +VREF_CA +VREF_CB
DDR_A_D19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_A_D28
DDR_A_D24 57 VSS20 DQ28 58 DDR_A_D29
DDR_A_D25 59 DQ24 DQ29 60 RC85 0_0402_5%
61 DQ25 VSS21 62 DDR_A_DQS#3 @
63 VSS22 DQS#3 64 DDR_A_DQS3
65 DM3 DQS3 66
DDR_A_D26 67 VSS23 VSS24 68 DDR_A_D30
DDR_A_D27 69 DQ26 DQ30 70 DDR_A_D31
71 DQ27 DQ31 72
VSS25 VSS26
Layout Note:
C
Place near JDDRL C
DDRA_CKE0 73 74 DDRA_CKE1 +1.5V
<7> DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 <7>
75 76
77 VDD1 VDD2 78 DDR_A_MA15
NC1 A15
330U_B2_2.5VM_R15M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
<7> DDR_A_BS2 DDR_A_BS2 79 80 DDR_A_MA14
BA2 A14
CD7
81 82 1
VDD3 VDD4
CD8
CD9
CD10
CD11
CD12
CD13
CD14
DDR_A_MA12 83 84 DDR_A_MA11 1 1 1 1 1 1 1
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7 + @
87 A9 A7 88
DDR_A_MA8 89 VDD5 VDD6 90 DDR_A_MA6 @
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4 2 2 2 2 2 2 2 2
93 A5 A4 94
DDR_A_MA3 95 VDD7 VDD8 96 DDR_A_MA2
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
99 A1 A0 100
DDRA_CLK0 101 VDD9 VDD10 102 DDRA_CLK1
<7> DDRA_CLK0 CK0 CK1 DDRA_CLK1 <7>
<7> DDRA_CLK0# DDRA_CLK0# 103 104 DDRA_CLK1#
CK0# CK1# DDRA_CLK1# <7> +1.5V
105 106
DDR_A_MA10 107 VDD11 VDD12 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 <7>
<7> DDR_A_BS0 DDR_A_BS0 109 110 DDR_A_RAS#
BA0 RAS# DDR_A_RAS# <7>
111 112
DDR_A_WE# 113 VDD13 VDD14 114 DDRA_SCS0# R56
<7> DDR_A_WE# WE# S0# DDRA_SCS0# <7>
<7> DDR_A_CAS# DDR_A_CAS# 115 116 DDRA_ODT0 1K_0402_1% Layout Note: Place these 4 Caps near
CAS# ODT0 DDRA_ODT0 <7>
117 118
DDR_A_MA13 119 VDD15 VDD16 120 DDRA_ODT1
Command and Control signals of JDDRL
A13 ODT1 DDRA_ODT1 <7>
<7> DDRA_SCS1# DDRA_SCS1# 121 122
123 S1# NC2 124 +1.5V
125 VDD17 VDD18 126
NCTEST VREF_CA +VREF_CA
127 128
VSS27 VSS28
0.1U_0402_10V6K
2.2U_0603_6.3V6K
DDR_A_D32 129 130 DDR_A_D36
DQ32 DQ36
C138
C139
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
DDR_A_D33 131 132 DDR_A_D37
DQ33 DQ37
CD17
CD18
CD19
CD20
133 134
B DDR_A_DQS#4 135 VSS29 VSS30 136 R62 B
DDR_A_DQS4 137 DQS#4 DM4 138 1K_0402_1%
139 DQS4 VSS31 140 DDR_A_D38
DDR_A_D34 141 VSS32 DQ38 142 DDR_A_D39
DDR_A_D35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_A_D44
DDR_A_D40 147 VSS34 DQ44 148 DDR_A_D45
DDR_A_D41 149 DQ40 DQ45 150 +3VALW
151 DQ41 VSS35 152 DDR_A_DQS#5
153 VSS36 DQS#5 154 DDR_A_DQS5
155 DM5 DQS5 156
DDR_A_D42 157 VSS37 VSS38 158 DDR_A_D46
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47 R5536
161 DQ43 DQ47 162
VSS39 VSS40 100K_0402_5%
DDR_A_D48 163 164 DDR_A_D52 Layout Note:
DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D53
167 DQ49 DQ53 168 0.75VR_EN# Place near JDDRL.203,204
DDR_A_DQS#6 169 VSS41 VSS42 170
DDR_A_DQS6 171 DQS#6 DM6 172
173 DQS6 VSS43 174 DDR_A_D54
VSS44 DQ54 <45> 0.75VR_EN
3
DDR_A_D50 175 176 DDR_A_D55 +0.75VS
DDR_A_D51 177 DQ50 DQ55 178 Q5520B
179 DQ51 VSS45 180 DDR_A_D60
DDR_A_D56 181 VSS46 DQ60 182 DDR_A_D61 0.75VR_EN 5 2N7002DW-T/R7_SOT363-6
DQ56 DQ61 <44,46> +V1.05S_VCCP_PWRGOOD
DDR_A_D57 183 184
DQ57 VSS47
1U_0402_6.3V6K
CD21
1U_0402_6.3V6K
CD22
1U_0402_6.3V6K
CD23
1U_0402_6.3V6K
CD24
185 186 DDR_A_DQS#7 R5535
4
187 VSS48 DQS#7 188 DDR_A_DQS7 100K_0402_5%
DM7 DQS7 1 1 1 1
189 190
VSS49 VSS50
6
DDR_A_D58 191 192 DDR_A_D62 Q5520A
DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63 2N7002DW-T/R7_SOT363-6
195 DQ59 DQ63 196 2 2 2 2
197 VSS51 VSS52 198 SUSP 2
A SA0 EVENT# <6,39> SUSP A
199 200 PM_SMBDATA
+3VS VDDSPD SDA PM_SMBDATA <12,20,32>
2.2U_0603_6.3V6K
0.1U_0402_10V6K
C161
10K_0402_5%
R68
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-DDRL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom VBL30/31 LA-9351P M/B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, July 16, 2012 Sheet 11 of 50
5 4 3 2 1
5 4 3 2 1
+1.5V
330U_B2_2.5VM_R15M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
+V_DDR_REFB 1 2
3 VREF_DQ VSS1
CD31
4 DDR_B_D4 1
<7> DDR_B_DQS[0..7]
5 VSS2 DQ4
2.2U_0603_6.3V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
CD34
CD35
CD36
CD37
CD38
CD39
CD40
CD41
DDR_B_D0 6 DDR_B_D5 1 1 1 1 1 1 1 1
DDR_B_D1 7 DQ0 DQ5 8 +
<7> DDR_B_MA[0..15]
9 DQ1 VSS3 10 DDR_B_DQS#0
11 VSS4 DQS#0
C162
C163
C164
R65 12 DDR_B_DQS0 @ @ @
13 DM0 DQS0 14 2 2 2 2 2 2 2 2 2
D 1K_0402_1% DDR_B_D2 15 VSS5 VSS6 16 DDR_B_D6 D
DDR_B_D3 17 DQ2 DQ6 18 DDR_B_D7
19 DQ3 DQ7 20
DDR_B_D8 21 VSS7 VSS8 22 DDR_B_D12
DDR_B_D9 23 DQ8 DQ12 24 DDR_B_D13
25 DQ9 DQ13 26
DDR_B_DQS#1 27 VSS9 VSS10 28
DDR_B_DQS1 29 DQS#1 DM1 30 SM_DRAMRST#
SM_DRAMRST# <7,11>
31 DQS1 RESET# 32
DDR_B_D10 33 VSS11 VSS12 34 DDR_B_D14
DDR_B_D11 35 DQ10 DQ14 36 DDR_B_D15 Layout Note: Place these 4 Caps near
37 DQ11 DQ15 38
DDR_B_D16 39 VSS13 VSS14 40 DDR_B_D20
Command and Control signals of JDDRH
DDR_B_D17 41 DQ16 DQ20 42 DDR_B_D21
43 DQ17 DQ21 44 +1.5V
DDR_B_DQS#2 45 VSS15 VSS16 46
DDR_B_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_B_D22
51 VSS18 DQ22
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
DDR_B_D18 52 DDR_B_D23
53 DQ18 DQ23
CD29
CD32
CD30
CD33
DDR_B_D19 54
55 DQ19 VSS19 56 DDR_B_D28
DDR_B_D24 57 VSS20 DQ28 58 DDR_B_D29
DDR_B_D25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_B_DQS#3
63 VSS22 DQS#3 64 DDR_B_DQS3
65 DM3 DQS3 66
DDR_B_D26 67 VSS23 VSS24 68 DDR_B_D30
DDR_B_D27 69 DQ26 DQ30 70 DDR_B_D31
71 DQ27 DQ31 72
VSS25 VSS26
C DDRB_CKE0 73 74 DDRB_CKE1 C
<7> DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 <7>
75 76 Layout Note:
77 VDD1 VDD2 78 DDR_B_MA15
DDR_B_BS2 79 NC1 A15 80 DDR_B_MA14
Place near JDDRH.203 and 204
<7> DDR_B_BS2 BA2 A14
81 82
DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11 +0.75VS
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
DDR_B_MA8 89 VDD5 VDD6 90 DDR_B_MA6
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
A5 A4
1U_0603_10V6K
1U_0603_10V6K
1U_0603_10V6K
1U_0603_10V6K
93 94
VDD7 VDD8
CD42
CD43
CD44
CD45
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
99 A1 A0 100
DDRB_CLK0 101 VDD9 VDD10 102 DDRB_CLK1
<7> DDRB_CLK0 CK0 CK1 DDRB_CLK1 <7>
<7> DDRB_CLK0# DDRB_CLK0# 103 104 DDRB_CLK1#
CK0# CK1# DDRB_CLK1# <7> +1.5V
105 106
DDR_B_MA10 107 VDD11 VDD12 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 <7>
<7> DDR_B_BS0 DDR_B_BS0 109 110 DDR_B_RAS#
BA0 RAS# DDR_B_RAS# <7>
111 112
DDR_B_WE# 113 VDD13 VDD14 114 DDRB_SCS0# R71
<7> DDR_B_WE# WE# S0# DDRB_SCS0# <7>
<7> DDR_B_CAS# DDR_B_CAS# 115 116 DDRB_ODT0 1K_0402_1%
CAS# ODT0 DDRB_ODT0 <7>
117 118
DDR_B_MA13 119 VDD15 VDD16 120 DDRB_ODT1
A13 ODT1 DDRB_ODT1 <7>
<7> DDRB_SCS1# DDRB_SCS1# 121 122
123 S1# NC2 124
125 VDD17 VDD18 126 +VREF_CA
NCTEST VREF_CA +VREF_CB
0.1U_0402_10V6K
2.2U_0603_6.3V6K
127 128
DDR_B_D32 129 VSS27 VSS28 130 DDR_B_D36
DQ32 DQ36
C167
C168
DDR_B_D33 131 132 DDR_B_D37
133 DQ33 DQ37 134
DDR_B_DQS#4 135 VSS29 VSS30 136 R69
B DDR_B_DQS4 137 DQS#4 DM4 138 1K_0402_1% B
139 DQS4 VSS31 140 DDR_B_D38
DDR_B_D34 141 VSS32 DQ38 142 DDR_B_D39
DDR_B_D35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_B_D44
DDR_B_D40 147 VSS34 DQ44 148 DDR_B_D45
DDR_B_D41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_B_DQS#5
153 VSS36 DQS#5 154 DDR_B_DQS5
155 DM5 DQS5 156
DDR_B_D42 157 VSS37 VSS38 158 DDR_B_D46
DDR_B_D43 159 DQ42 DQ46 160 DDR_B_D47
161 DQ43 DQ47 162
DDR_B_D48 163 VSS39 VSS40 164 DDR_B_D52
DDR_B_D49 165 DQ48 DQ52 166 DDR_B_D53
167 DQ49 DQ53 168
DDR_B_DQS#6 169 VSS41 VSS42 170
DDR_B_DQS6 171 DQS#6 DM6 172
173 DQS6 VSS43 174 DDR_B_D54
DDR_B_D50 175 VSS44 DQ54 176 DDR_B_D55
DDR_B_D51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_B_D60
DDR_B_D56 181 VSS46 DQ60 182 DDR_B_D61
DDR_B_D57 183 DQ56 DQ61 184
185 DQ57 VSS47 186 DDR_B_DQS#7
187 VSS48 DQS#7 188 DDR_B_DQS7
189 DM7 DQS7 190
DDR_B_D58 191 VSS49 VSS50 192 DDR_B_D62
DDR_B_D59 193 DQ58 DQ62 194 DDR_B_D63
R76 195 DQ59 DQ63 196
10K_0402_5% 197 VSS51 VSS52 198
199 SA0 EVENT# 200 PM_SMBDATA
+3VS VDDSPD SDA PM_SMBDATA <11,20,32>
2.2U_0603_6.3V6K
0.1U_0402_10V6K
C186
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-DDRH
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VBL30/31 LA-9351P M/B
Date: Monday, July 16, 2012 Sheet 12 of 50
5 4 3 2 1
5 4 3 2 1
PX@
PCIE_CTX_C_GRX_P4 R29 T26 PCIE_GTX_CRX_P4 C24 1 2 PX@ 0.1U_0402_16V7KPCIE_GTX_C_CRX_P4
PCIE_CTX_C_GRX_N4 P28 PCIE_RX11P
PCIE_RX11N
PCIE_TX11P
PCIE_TX11N
T27 PCIE_GTX_CRX_N4 C25 1 2 PX@ 0.1U_0402_16V7KPCIE_GTX_C_CRX_N4
LVDS
PCIE_CTX_C_GRX_P3 P30 T24 PCIE_GTX_CRX_P3 C22 1 2 PX@ 0.1U_0402_16V7KPCIE_GTX_C_CRX_P3
PCIE_CTX_C_GRX_N3 N31 PCIE_RX12P PCIE_TX12P T23 PCIE_GTX_CRX_N3 C23 1 2 PX@ 0.1U_0402_16V7KPCIE_GTX_C_CRX_N3
PCIE_RX12N PCIE_TX12N
B B
PCIE_CTX_C_GRX_P2 N29 P27 PCIE_GTX_CRX_P2 C20 1 2 PX@ 0.1U_0402_16V7KPCIE_GTX_C_CRX_P2
PCIE_CTX_C_GRX_N2 M28 PCIE_RX13P PCIE_TX13P P26 PCIE_GTX_CRX_N2 C21 1 2 PX@ 0.1U_0402_16V7KPCIE_GTX_C_CRX_N2
PCIE_RX13N PCIE_TX13N
CLOCK
CLK_PCIE_VGA AK30
<20> CLK_PCIE_VGA PCIE_REFCLKP
CLK_PCIE_VGA# AK32
<20> CLK_PCIE_VGA# PCIE_REFCLKN
0_0402_5%
2 @ 1 R767 CALIBRATION
<23,50> VGA_PWROK
Y22 1.27K_0402_1% 1 PX@ 2 R298
PCIE_CALRP
2 R299 1 PX@ N10 AA22 2K_0402_1% 1 PX@ 2 R301 +1.0VS_DGPU
10K_0402_5% PWRGOOD PCIE_CALRN
A A
PLTRST_VGA# AL27
<22> PLTRST_VGA# PERSTB
Security Classification Compal Secret Data Compal Electronics, Inc.
216-0774207-A11ROB_FCBGA631 2012/06/01 2013/05/12 Title
PX@
Issued Date Deciphered Date
SeymourXT-S3 PCIE/LVDS
PCIE LANE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B
Document Number Rev
0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, July 16, 2012 Sheet 13 of 50
5 4 3 2 1
5 4 3 2 1
UV1B
AF2
TXCAP_DPA3P AF4
Y11 TXCAM_DPA3N
AE9 DVCLK AG3
L9 DVCNTL_0 TX0P_DPA2P AG5
N9 DVCNTL_1 DVO DPA TX0M_DPA2N
DVCNTL_2 AH3
AE8 TX1P_DPA1P AH1
AD9 DVDATA_12 TX1M_DPA1N
AC10 DVDATA_11 AK3
+1.8VS_DGPU +DPC_VDD18 AD7 DVDATA_10 TX2P_DPA0P AK1
L8 AC8 DVDATA_9 TX2M_DPA0N
2 1 +DPC_VDD18 AC7 DVDATA_8 AK5
DVDATA_7 TXCBP_DPB3P
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
BLM15BD121SN1D_0402 AB9 AM3
DVDATA_6 TXCBM_DPB3N
C304
C305
C306
PX@ 1 1 1 AB8
D
AB7 DVDATA_5 AK6 D
AB4 DVDATA_4 TX3P_DPB2P AM5
@ @ @ VRAM_ID2 AB2 DVDATA_3 DPB TX3M_DPB2N
2 2 2 <17> VRAM_ID2 DVDATA_2
VRAM_ID1 Y8 AJ7
<17> VRAM_ID1 DVDATA_1 TX4P_DPB1P
VRAM_ID0 Y7 AH6
<17> VRAM_ID0 DVDATA_0 TX4M_DPB1N
AK8
TX5P_DPB0P AL7
TX5M_DPB0N
0.1U_0402_10V6K
1U_0402_6.3V4Z
BLM15BD121SN1D_0402 W3
TX0P_DPC2P
C307
C346
C347
I2C
R1
R3 SCL
SDA
AM26 T55
GENERAL PURPOSE I/O R AK26
GPU_GPIO0 U6 RB
C C
GPU_GPIO1 U10 GPIO_0 AL25 T56
GPU_GPIO2 T10 GPIO_1 G AJ25
VGA_SMB_DA2_R U8 GPIO_2 GB
CH751H-40PT_SOD323-2
D4
@ VGA_SMB_CK2_R U7 GPIO_3_SMBDATA AH24 T57
0117 AMD request to stuff R320
1 2 GPU_GPIO5 T9 GPIO_4_SMBCLK B AG25 +VGA_AVDD +1.8VS_DGPU
<21,36,41> ACIN GPIO_5_AC_BATT BB
T8 DAC1 L14 +3VS_DGPU
T7 GPIO_6 AH26 VGA_HSYNC +VGA_AVDD 1 2
GPIO_7_BLON HSYNC
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
GPU_GPIO8 P10 AJ27 VGA_VSYNC BLM15BD121SN1D_0402 GPU_GPIO0 R339 2 @ 1 10K_0402_5%
GPIO_8_ROMSO VSYNC
C397
C401
C407
GPU_GPIO9 P4 1 1 1 GPU_GPIO1 R338 2 1 10K_0402_5%
P2 GPIO_9_ROMSI PX@ GPU_GPIO2 R325 2 PX@ 1 10K_0402_5%
GPIO_10_ROMSCK PX@
GPU_GPIO11 N6 AD22 1 R318 2 GPU_GPIO5 R320 2 PX@ 1 10K_0402_5%
GPU_GPIO12 N5 GPIO_11 RSET 499_0402_1% PX@ PX@ PX@
GPU_GPIO13 N3 GPIO_12 AG24 +VGA_AVDD 2 2 2 GPU_GPIO8 R313 2 @ 1 10K_0402_5%
GPIO_13 AVDD +VGA_AVDD
Y9 AE22 GPU_GPIO9 R314 2 @ 1 10K_0402_5%
GPU_VID0 N1 GPIO_14_HPD2 AVSSQ
<50> GPU_VID0 GPIO_15_PWRCNTL_0
T63 M4 AE23 +VDD1DI +VDD1DI GPU_GPIO11 R315 2 PX@ 1 10K_0402_5%
R6 GPIO_16_SSIN VDD1DI AD23 GPU_GPIO12 R316 2 @ 1 10K_0402_5%
PX@ W10 GPIO_17_THERMAL_INT VSS1DI GPU_GPIO13 R317 2 @ 1 10K_0402_5%
R319 1 2
10K_0402_5% M2 GPIO_18_HPD3 +VDD1DI +1.8VS_DGPU
+3VS_DGPU GPU_VID1 P8 GPIO_19_CTF AM12 L27 VGA_HSYNC R548 1 @ 2 10K_0402_5%
<50> GPU_VID1 GPIO_20_PWRCNTL_1 R2
T70 P7 AK12 +VDD1DI 1 2 VGA_VSYNC R549 1 @ 2 10K_0402_5%
GPIO_21_BB_EN R2B
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
N8 BLM15BD121SN1D_0402
GPIO_22_ROMCSB
C313
C396
C315
PEG_CLKREQ# N7 AL11 1 1 1 PX@
<20> PEG_CLKREQ# GPIO_23_CLKREQB G2 AJ11
GPIO24_TRSTB L6 G2B
PX@ 1 R321 2
10K_0402_5% GPIO24_TRSTB GPIO25_TDI L5 JTAG_TRSTB AK10 PX@ PX@ PX@
PX@ 1 R322 2
10K_0402_5% GPIO25_TDI GPIO26_TCK L3 JTAG_TDI B2 AL9 2 2 2
PX@ 1 R323 2
10K_0402_5% GPIO27_TMS GPIO27_TMS L1 JTAG_TCK B2B
PX@ 1 R324 2
10K_0402_5% GPIO26_TCK T64 GPIO28_TDO K4 JTAG_TMS
1R326 2 TEST_EN K7 JTAG_TDO AH12
PX@ 5.11K_0402_1% AF24 TESTEN C AM10
T65 TESTEN_LEGACY Y AJ9
COMP
AB13 DAC2
W8 GENERICA AL13 T53
+1.8VS_DGPU +DPLL_PVDD W9 GENERICB H2SYNC AJ13 T54
L30 W7 GENERICC V2SYNC +3VS_DGPU
B
2 1 +DPLL_PVDD AD10 GENERICD B
GENERICE_HPD4
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
BLM15BD121SN1D_0402 AD19
VDD2DI
C323
C324
C325
1
4.7K_0402_5%
PX@ PX@ PX@ @ AE20 R327 R328
2 2 2 A2VDD 10K_0402_5% 10K_0402_5%
AE17
A2VDDQ
2
2
2
+1.8VS_DGPU AE19
PX@ A2VSSQ VGA_SMB_CK2_R 1 6
EC_SMB_CK2 <20,36>
2 R329 1499_0402_1% +VREFG_GPU AC16 PX@ PX@
VREFG
5
+1.0VS_DGPU +DPLL_VDDC AG13 1 R330 2 Q64A
L49 2 R335 1249_0402_1% R2SET 715_0402_1% 2N7002DW-T/R7_SOT363-6
2 1 +DPLL_VDDC PX@ @ VGA_SMB_DA2_R 4 3
EC_SMB_DA2 <20,36>
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
BLM15BD121SN1D_0402 2 1
PX@
C330
C331
C332
1U_0402_6.3V4Z
0.1U_0402_16V4Z
C335
C336
1 1 1 PX@
PX@ AE16
DDCCLK_AUX5P AD16
PX@ PX@ PX@ DDCDATA_AUX5N
2 2 2 AC1 T58
T4 THERMAL DDC6CLK AC3 T59
T2 DPLUS DDC6DATA
DMINUS
A A
@
1 2 +3VS_DGPU 1 R334 22.61K_0402_5% R5
R337 10M_0402_5% +TSVDD AD17 TS_FDO
+TSVDD TSVDD
PX@ AC17
TSVSS
Y6
4 3 XTALOUT
NC OSC 216-0774207-A11ROB_FCBGA631
XTALIN 1 2
OSC NC
PX@
Security Classification Compal Secret Data Compal Electronics, Inc.
2 27MHZ 16PF +-30PPM X3G027000FG1H-HX 2 Issued Date 2012/06/01 Deciphered Date 2013/05/12 Title
PX@ PX@ PX@
C341 SJ100009700 C350
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SeymourXT-S3 Main Generic/MSIC
10P_0402_50V8J 10P_0402_50V8J Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
1 1 C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, July 16, 2012 Sheet 14 of 50
5 4 3 2 1
5 4 3 2 1
10U_0603_6.3V6M
10U_0603_6.3V6M
C375
C386
C355
C357
C358
C359
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1 1 1 1 1 1
MBK1608121YZF_0603 UV1G MBK1608121YZF_0603
Change to 0 ohm @ @ @ @ @ @ Change to 0 ohm
2 2 2 DP E/F POWER DP A/B POWER 2 2 2
P/N 130mA P/N
+1.0VS_DGPU AG15 AE11 +DPAB_VDD18
D AG16 DPE_VDD18#1 DPA_VDD18#1 AF11 D
+DPEF_VDD10 DPE_VDD18#2 DPA_VDD18#2 +DPAB_VDD10 +1.0VS_DGPU
total:240mA@LVDS PX@
L31 L33
PX@ total:220mA@DP 110mA total:220mA
2 1 AG20 AF6 1 2
10U_0603_6.3V6M DPE_VDD10#1 DPA_VDD10#1
10U_0603_6.3V6M
C356
C360
C363
C364
C368
C367
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1 1 1 AG21 AF7 1 1 1
DPE_VDD10#2 DPA_VDD10#2
MBK1608121YZF_0603 MBK1608121YZF_0603
Change to 0 ohm
@ @ @ AG14 AE1 @ @ @ Change to 0 ohm
P/N 2 2 2 AH14 DPE_VSSR#1 DPA_VSSR#1 AE3 2 2 2
AM14 DPE_VSSR#2 DPA_VSSR#2 AG1 P/N
AM16 DPE_VSSR#3 DPA_VSSR#3 AG6
AM18 DPE_VSSR#4 DPA_VSSR#4 AH5
DPE_VSSR#5 DPA_VSSR#5
+DPEF_VDD18 +DPAB_VDD18
130mA
AF16 AE13 +DPAB_VDD18
AG17 DPF_VDD18#1 DPB_VDD18#1 AF13
DPF_VDD18#2 DPB_VDD18#2
+DPEF_VDD10 +DPAB_VDD10
110mA
AF22 AF8 +DPAB_VDD10
AG22 DPF_VDD10#1 DPB_VDD10#1 AF9
DPF_VDD10#2 DPB_VDD10#2
C C
AF23 AF10
AG23 DPF_VSSR#1 DPB_VSSR#1 AG9
AM20 DPF_VSSR#2 DPB_VSSR#2 AH8
AM22 DPF_VSSR#3 DPB_VSSR#3 AM6
AM24 DPF_VSSR#4 DPB_VSSR#4 AM8
DPF_VSSR#5 DPB_VSSR#5
R463 PX@
2 1 AF17 AE10 1 R464 2
150_0402_1% DPEF_CALR DPAB_CALR 150_0402_1%
+DPEF_VDD18 PX@ +DPAB_VDD18
20mA 20mA
+DPEF_VDD18 AG18 DP PLL POWER AG8 +DPAB_VDD18
AF19 DPE_PVDD DPA_PVDD AG7
DPE_PVSS DPA_PVSS
+DPEF_VDD18 +DPAB_VDD18
20mA 20mA
+DPEF_VDD18 AG19 AG10 +DPAB_VDD18
AF20 DPF_PVDD DPB_PVDD AG11
DPF_PVSS DPB_PVSS
B B
216-0774207-A11ROB_FCBGA631
PX@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SeymourXT-S3 DP PWR
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, July 16, 2012 Sheet 15 of 50
5 4 3 2 1
5 4 3 2 1
+1.5VS_DGPU
2.3A(RMS)/2.8A(Peak)
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
C365
C366
C369
C370
C420
C383
C385
C392
C437
C419
C441
C395
C394
1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2
+PCIE_VDDR +1.8VS_DGPU
9/28 Reserved for VGA_CORE
504mA L34
UV1D +PCIE_VDDR 2 1
10/8 change to B2 size UV1E
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
D PX@ PX@ PX@ PX@ PX@ D
C436
C413
C391
C384
PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ MEM I/O 1 1 1 1 MBK1608121YZF_0603
PCIE Change to 0 ohm
H13 AB23 AA27 A3
H16 VDDR1#1 PCIE_VDDR#1 AC23 P/N PX@ AB24 PCIE_VSS#1 GND#1 A30
H19 VDDR1#2 PCIE_VDDR#2 AD24 2 2 2 2 AB32 PCIE_VSS#2 GND#2 AA13
J10 VDDR1#3 PCIE_VDDR#3 AE24 AC24 PCIE_VSS#3 GND#3 AA16
J23 VDDR1#4 PCIE_VDDR#4 AE25 AC26 PCIE_VSS#4 GND#4 AB10
J24 VDDR1#5 PCIE_VDDR#5 AE26 AC27 PCIE_VSS#5 GND#5 AB15
J9 VDDR1#6 PCIE_VDDR#6 AF25 AD25 PCIE_VSS#6 GND#6 AB6
K10 VDDR1#7 PCIE_VDDR#7 AG26 +1.0VS_DGPU AD32 PCIE_VSS#7 GND#7 AC9
VDDR1#8 PCIE_VDDR#8 PX@ PX@ PCIE_VSS#8 GND#8
K23 PX@ PX@ AE27 AD6
K24 VDDR1#9 AF32 PCIE_VSS#9 GND#9 AD8
K9 VDDR1#10 L23
1920mA AG27 PCIE_VSS#10 GND#10 AE7
VDDR1#11 PCIE_VDDC#1 PCIE_VSS#11 GND#11
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
L11 L24 AH32 AG12
VDDR1#12 PCIE_VDDC#2 PCIE_VSS#12 GND#12
C398
C409
C421
C439
C408
L12 L25 1 1 1 1 1 K28 AH10
+1.8VS_DGPU +VDDC_CT L13 VDDR1#13 PCIE_VDDC#3 L26 K32 PCIE_VSS#13 GND#13 AH28
L20 VDDR1#14 PCIE_VDDC#4 M22 L27 PCIE_VSS#14 GND#14 B10
L46 L21 VDDR1#15 PCIE_VDDC#5 N22 M32 PCIE_VSS#15 GND#15 B12
1 2
110mA L22 VDDR1#16 PCIE_VDDC#6 N23 2 2 2 2 2 N25 PCIE_VSS#16 GND#16 B14
VDDR1#17 PCIE_VDDC#7 PCIE_VSS#17 GND#17
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
C405
C422
TRANSLATION
1U_0402_6.3V4Z
C411
C428
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
AB21 CORE N15 V32 C1
2 2 2 VDD_CT#4 VDDC#2 PCIE_VSS#26 GND#26
C450
C448
C443
C442
C452
C445
C444
C451
C423
C427
C435
C426
N17 1 1 1 1 1 1 1 1 1 1 1 1 W25 C32
VDDC#3 R13 W26 PCIE_VSS#27 GND#27 E28
PX@ VDDC#4 PCIE_VSS#28 GND#28
PX@ PX@ I/O R16 W27 F10
AA17 VDDC#5 R18 Y25 PCIE_VSS#29 GND#29 F12
60mA VDDR3#1 VDDC#6 PCIE_VSS#30 GND#30
AA18 Y21 2 2 2 2 2 2 2 2 2 2 2 2 Y32 F14
AB17 VDDR3#2 VDDC#7 T12 PCIE_VSS#31 GND#31 F16
PX@ VDDR3#3 VDDC#8 GND#32
PX@ AB18 T15 F18
L24 VDDR3#4 VDDC#9 T17 GND#33 F2
1 2 V12 VDDC#10 T20 GND#34 F20
170mA VDDR4#1 VDDC#11 GND#35
0.1U_0402_10V6K
1U_0402_6.3V4Z
C BLM15BD121SN1D_0402 Y12 U13 PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ M6 F22 C
U12 VDDR4#2 VDDC#12 U16 PX@ PX@ PX@ PX@ N11 GND#56 GND#36 F24
VDDR4#3 VDDC#13 GND#57 GND#37
POWER
C440
C433
Change to
PX@0 ohm U18 N12 F26
1 1
AA11 VDDC#14 V21
7/22 modify N13 GND#58 GND#38 F6
P/N AA12 NC#1 VDDC#15 V15 N16 GND#59 GND#39 F8
PX@ PX@
2 2 V11
NC#2
NC#3
VDDC#16
VDDC#17
VDDC#18
V17
V20
N18
N21
GND#60
GND#61
GND#62
GND GND#40
GND#41
GND#42
G10
G27
U11 Y13 P6 G31
NC#4 VDDC#19 Y16 P9 GND#63 GND#43 G8
VDDC#20 Y18 R12 GND#64 GND#44 H14
VDDC#21
55mA@1.0V, in BACO mode GND#65 GND#45
M11 R15 H17
L47
0120 change power rail to +PCIE_VDDR VDDC#22 M12 R17 GND#66 GND#46 H2
1 2 MEM CLK VDDC#23 +BIF_VDDC +VGA_CORE R20 GND#67 GND#47 H20
GND#68 GND#48
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
C447
C449
1 1 1 T16 J27
L16 +BIF_VDDC T18 GND#70 GND#50 J31
PX@ +PCIE_VDDR NC_VSSRHA GND#71 GND#51
T21 K11
GND#72 GND#52
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1 2 T6 K2
2 2 2 GND#73 GND#53
C470
C516
For Seymour, PCIE_PVDD is PCIE_VDDR. PLL 1 1 R398 0_0805_5% U15 K22
AM30 U17 GND#74 GND#54 K6
PCIE_PVDD PX@ GND#75 GND#55
R21 U20
BIF_VDDC#1 GND#76
1
U21 U9
BIF_VDDC#2 2 2 GND#77
+MPV18 75mA L8 NC_MPV18
C342 PX@ V13
GND#78
PX@ 22U_0603_6.3V6K V16
2
L48 PX@ PX@ V18 GND#79
1 2 GND#80
+SPV18 75mA H7 SPV18
Y10
GND#81
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
C454
C463
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1 2 M18
VDDCI#5
10U_0603_6.3V6M
C465
C460
C461
C466
0.1U_0402_10V6K
1U_0402_6.3V4Z
BLM15BD121SN1D_0402 M20 1 1 1 1
VDDCI#6
C457
C464
C458
1 1 1 M21
VDDCI#7 N20
PX@ VDDCI#8 PX@
216-0774207-A11ROB_FCBGA631
2 2 2 2
PX@ 2 2 2
PX@ PX@
B PX@ B
216-0774207-A11ROB_FCBGA631
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SeymourXT-S3 PWR/GND
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2 Date: Monday, July 16, 2012 1Sheet 16 of 50
5 4 3 2 1
UV1C +1.8VS_DGPU
M_DA[63..0]
<18> M_DA[63..0] GDDR5/DDR3 GDDR5/DDR3 R461 1 X76@ 2 10K_0402_5% VRAM_ID0
M_MA[13..0] VRAM_ID0 <14>
M_DA0 K27 K17 M_MA0 R462 1 X76@ 2 10K_0402_5%
<18> M_MA[13..0] DQA0_0/DQA_0 MAA0_0/MAA_0
M_DA1 J29 J20 M_MA1 R359 1 X76@ 2 10K_0402_5% VRAM_ID1
M_DQM[7..0] DQA0_1/DQA_1 MAA0_1/MAA_1 VRAM_ID1 <14>
M_DA2 H30 H23 M_MA2 R360 1 X76@ 2 10K_0402_5%
<18> M_DQM[7..0] DQA0_2/DQA_2 MAA0_2/MAA_2
M_DA3 H32 G23 M_MA3 R361 1 X76@ 2 10K_0402_5% VRAM_ID2
M_DQS[7..0] DQA0_3/DQA_3 MAA0_3/MAA_3 VRAM_ID2 <14>
M_DA4 G29 G24 M_MA4 R362 1 X76@ 2 10K_0402_5%
<18> M_DQS[7..0] DQA0_4/DQA_4 MAA0_4/MAA_4
MEMORY INTERFACE
M_DA5 F28 H24 M_MA5
M_DQS#[7..0] M_DA6 F32 DQA0_5/DQA_5 MAA0_5/MAA_5 J19 M_MA6
<18> M_DQS#[7..0] DQA0_6/DQA_6 MAA0_6/MAA0_6
M_DA7 F30 K19 M_MA7
D M_DA8 C30 DQA0_7/DQA_7 MAA0_7/MAA0_7 J14 M_MA8 D
M_DA9 F27 DQA0_8/DQA_8 MAA1_0/MAA_8 K14 M_MA9
M_DA10 A28 DQA0_9/DQA_9 MAA1_1/MAA_9 J11 M_MA10
PARK SCL has M_DA11 C28 DQA0_10/DQA_10 MAA1_2/MAA_10 J13 M_MA11
different recommand 9/28 change P/N to M_DA12 E27 DQA0_11/DQA_11 MAA1_3/MAA_11 H11 M_MA12
M_DA13 G26 DQA0_12/DQA_12 MAA1_4/MAA_12 G11 M_BA2
SD034100A80 R455 DQA0_13/DQA_13 MAA1_5/MAA_13/BA2 M_BA2 <18>
M_DA14 D26 J16 M_BA0
DQA0_14/DQA_14 MAA1_6/MAA_14/BA0 M_BA0 <18>
10_0402_1% M_DA15 F25 L15 M_BA1
DQA0_15/DQA_15 MAA1_7/MAA_15/BA1 M_BA1 <18>
1 R366 2 2 1 DRAM_RST M_DA16 A25 Vendor VRAM_ID0 VRAM_ID1 VRAM_ID2
<18> DRAM_RST# DQA0_16/DQA_16
51.1_0402_1% M_DA17 C25 E32 M_DQM0
PX@ M_DA18 E25 DQA0_17/DQA_17 WCKA0_0/DQMA_0 E30 M_DQM1
DQA0_18/DQA_18 WCKA0B_0/DQMA_1
1
1 M_DA19 D24 A21 M_DQM2 K4W1G1646G-BC11
C469 M_DA20 E23 DQA0_19/DQA_19 WCKA0_1/DQMA_2 C21 M_DQM3
PX@R456 DQA0_20/DQA_20 WCKA0B_1/DQMA_3
64MX16 (512MB) Samsung 128MB R461 R360 R362
120P_0402_50V8J 4.99K_0402_1% M_DA21 F23 E13 M_DQM4
M_DA22 D22 DQA0_21/DQA_21 WCKA1_0/DQMA_4 D12 M_DQM5 PN:SA00004GS00 1 0 0
2 M_DA23 F21 DQA0_22/DQA_22 WCKA1B_0/DQMA_5 E3 M_DQM6 H5TQ1G63DFR-11C
2
M_DA24 E21 DQA0_23/DQA_23 WCKA1_1/DQMA_6 F4 M_DQM7
DQA0_24/DQA_24 WCKA1B_1/DQMA_7
64MX16 (512MB) Hynix 128MB R462 R359 R362
PX@ M_DA25 D20
PX@ M_DA26 F19 DQA0_25/DQA_25 H28 M_DQS0 PN:SA000041S20 0 1 0
M_DA27 A19 DQA0_26/DQA_26 EDCA0_0/RDQSA_0 C27 M_DQS1 K4W2G1646C-HC11
M_DA28 D18 DQA0_27/DQA_27 EDCA0_1/RDQSA_1 A23 M_DQS2
M_DA29 F17 DQA0_28/DQA_28 EDCA0_2/RDQSA_2 E19 M_DQS3
Samsung 256MB R461 R360 R361
128M16 (1GB)
M_DA30 A17 DQA0_29/DQA_29 EDCA0_3/RDQSA_3 E15 M_DQS4 PN:SA000047Q00 1 0 1
M_DA31 C17 DQA0_30/DQA_30 EDCA1_0/RDQSA_4 D10 M_DQS5 H5TQ2G63BFR-11C/H5TQ2G63DFR-11C
C +1.5VS_DGPU DQA0_31/DQA_31 EDCA1_1/RDQSA_5 C
M_DA32 E17 D6 M_DQS6 Hynix 256MB R462 R359 R361
+1.5VS_DGPU M_DA33 D16 DQA1_0/DQA_32 EDCA1_2/RDQSA_6 G5 M_DQS7 128M16 (1GB)
M_DA34 F15 DQA1_1/DQA_33 EDCA1_3/RDQSA_7 PN:SA00003YO10/ 0 1 1
DQA1_2/DQA_34
1
G14
GDDR5 MAA1_8 G20 M_MA13
DRAM_RST L10 MAA0_8
DRAM_RST
1R466@ 51.1_0402_1%
2 1C515@20.1U_0402_16V4Z K8
1 2 1 2 L7 CLKTESTA
R373@ 51.1_0402_1% C517@ 0.1U_0402_16V4Z CLKTESTB
A A
Route 50ohms single-ended/100ohm diff and keep short 216-0774207-A11ROB_FCBGA631 PX@
debug only, for clock observation,if Security Classification Compal Secret Data Compal Electronics, Inc.
not need, DNI. Issued Date 2012/06/01 2013/05/12 Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SeymourXT-S3 MEM Interface
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, July 16, 2012 Sheet 17 of 50
5 4 3 2 1
5 4 3 2 1
M_DA[63..0]
<17> M_DA[63..0]
M_MA[13..0]
<17> M_MA[13..0]
M_DQM[7..0]
<17> M_DQM[7..0]
M_DQS[7..0]
<17> M_DQS[7..0]
M_DQS#[7..0]
<17> M_DQS#[7..0]
K1
VRAM_ODT0 A1 VRAM_ODT0 K1 A1 K1
VRAM_ODT1 A1 VRAM_ODT1 K1 A1
<17> VRAM_ODT0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ <17> VRAM_ODT1 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
M_CS#0 L2 A8 M_CS#0 L2 A8 M_CS#1 L2 A8 M_CS#1 L2 A8
<17> M_CS#0 CS/CS0 VDDQ CS/CS0 VDDQ <17> M_CS#1 CS/CS0 VDDQ CS/CS0 VDDQ
M_RAS#0 J3 C1 M_RAS#0 J3 C1 M_RAS#1 J3 C1 M_RAS#1 J3 C1
<17> M_RAS#0 RAS VDDQ RAS VDDQ <17> M_RAS#1 RAS VDDQ RAS VDDQ
M_CAS#0 K3 C9 M_CAS#0 K3 C9 M_CAS#1 K3 C9 M_CAS#1 K3 C9
<17> M_CAS#0 CAS VDDQ CAS VDDQ <17> M_CAS#1 CAS VDDQ CAS VDDQ
M_WE#0 L3 D2 M_WE#0 L3 D2 M_WE#1 L3 D2 M_WE#1 L3 D2
<17> M_WE#0 WE VDDQ WE VDDQ <17> M_WE#1 WE VDDQ WE VDDQ
E9 E9 E9 E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
M_DQS2 F3 VDDQ H2 M_DQS3 F3 VDDQ H2 M_DQS4 F3 VDDQ H2 M_DQS6 F3 VDDQ H2
M_DQS0 C7 DQSL VDDQ H9 M_DQS1 C7 DQSL VDDQ H9 M_DQS5 C7 DQSL VDDQ H9 M_DQS7 C7 DQSL VDDQ H9
C C
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ
1
J1 B1 J1 B1 J1 B1 J1 B1
R454 L1 NC/ODT1 VSSQ B9 R451 L1 NC/ODT1 VSSQ B9 R410 L1 NC/ODT1 VSSQ B9 R444 L1 NC/ODT1 VSSQ B9
243_0402_1% J9 NC/CS1 VSSQ D1 243_0402_1% J9 NC/CS1 VSSQ D1 243_0402_1% J9 NC/CS1 VSSQ D1 243_0402_1% J9 NC/CS1 VSSQ D1
L9 NC/CE1 VSSQ D8 L9 NC/CE1 VSSQ D8 L9 NC/CE1 VSSQ D8 L9 NC/CE1 VSSQ D8
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
2
2
VSSQ E8 VSSQ E8 VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
PX@ VSSQ G1 PX@ VSSQ G1 PX@ VSSQ G1 PX@ VSSQ G1
VSSQ G9 VSSQ G9 VSSQ G9 VSSQ G9
VSSQ VSSQ VSSQ VSSQ
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
H5TQ1G63DFR-11C H5TQ1G63DFR-11C H5TQ1G63DFR-11C H5TQ1G63DFR-11C
X76@ X76@ X76@ X76@
1
R450 R379 R380 R381 R382 R383 R384 R385
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
2
2
+VREFD_Q1 +VREFC_A1 +VREFC_A2 +VREFD_Q2 +VREFC_A3 +VREFD_Q3 +VREFC_A4 +VREFD_Q4
PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@
1
1
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
C472
C474
C480
C476
C482
C479
C523
C485
1 1 1 1 1 1 1 1
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
R386 R387 R388 R449 R448 R447 R446 R445
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
2 2 2 2 2 2 2 2
2
2
PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@
M_CLK0 1 2
R443 56_0402_1% PX@ PX@ PX@
PX@ PX@ PX@ PX@ PX@
PX@
M_CLK#0 1 2 +1.5VS_DGPU
R397 56_0402_1% +1.5VS_DGPU
PX@ 1 0.01U_0402_25V7K 1U_0402_6.3V4Z 1U_0402_6.3V4Z
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
PX@ C506 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
+1.5VS_DGPU
2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C500
C501
C484
C508
C509
C502
C503
C504
C505
C487
1 1 1 1 1 1 1 1 1 1
C521
C510
C483
C493
C494
C499
C496
C497
C498
C522
C488 C489 C490 C520 C495 C511
2 2 2 2 2 2 @ 2 2 2 2 2 2 2 2@ 2 2@
10U_0603_6.3V6M 10U_0603_6.3V6M
10U_0603_6.3V6M 2 2 2 2 2 2 2 2 2 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
M_CLK1 1 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z
R423 56_0402_1% PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@
PX@ PX@ PX@ PX@ PX@ PX@ PX@
A PX@ A
PX@ PX@ PX@ PX@ PX@
M_CLK#1 1 2 PX@ PX@
R436 56_0402_1% 1 0.01U_0402_25V7K
PX@ C507
PX@
2
ref 139-02 recommand
add off page Security Classification Compal Secret Data Compal Electronics, Inc.
Park SCL recommand pu 60.4 Issued Date 2012/06/01 Deciphered Date 2013/05/12 Title
ohm to 1.5VGS 0619 update
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SeymourXT-S3 VRAM
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, July 16, 2012 Sheet 18 of 50
5 4 3 2 1
5 4 3 2 1
2 1 PCH_RTCX1
C204 18P_0402_50V8J
1
10M_0402_5%
32.768KHZ_12.5PF
Y2
R94
2
2
2 1 PCH_RTCX2
C205 18P_0402_50V8J
+RTCVCC
D SM_INTRUDER# D
R95 1M_0402_5%
UH1A
CMOS
+RTCVCC PCH_RTCX1 A20 C38 LPC_AD0
RTCX1 FWH0 / LAD0 LPC_AD0 <36>
2
@ A38 LPC_AD1
FWH1 / LAD1 LPC_AD1 <36>
LPC
C206 JCOMS PCH_RTCX2 C20 B37 LPC_AD2
RTCX2 FWH2 / LAD2 LPC_AD2 <36>
1U_0603_10V4Z SHORT PADS C37 LPC_AD3
LPC_AD3 <36>
1
1 2 PCH_RTCRST# D20 FWH3 / LAD3
R97 20K_0402_5% RTCRST# D36 LPC_FRAME#
FWH4 / LFRAME# LPC_FRAME# <36>
PCH_SRTCRST# G22
R98 20K_0402_5% SRTCRST# E36
LDRQ0#
RTC
@ SM_INTRUDER# K22 K36 LPC_LDRQ1#
C207 JME1 INTRUDER# LDRQ1# / GPIO23 @ T1509 PAD
1U_0603_10V4Z SHORT PADS PCH_INTVRMEN C17 V5 SERIRQ SERIRQ <36>
1
INTVRMEN SERIRQ
ME CMOS
CLP1 & CLP2 place near DIMM
+RTCVCC AM3 SATA_PRX_C_DTX_N0
SATA0RXN SATA_PRX_C_DTX_N0 <30>
AZ_BITCLK N34 AM1 SATA_PRX_C_DTX_P0 HDD
HDA_BCLK SATA0RXP SATA_PRX_C_DTX_P0 <30> +3VS
PCH_INTVRMEN R96 330K_0402_5% AP7 SATA_PTX_DRX_N0
SATA 6G
SATA0TXN SATA_PTX_DRX_N0 <30>
AZ_SYNC L34 AP5 SATA_PTX_DRX_P0
HDA_SYNC SATA0TXP SATA_PTX_DRX_P0 <30>
HΚIntegrated VRM enable PCH_SPKR T10 AM10 SERIRQ R99 10K_0402_5%
* LΚIntegrated VRM disable <34> PCH_SPKR SPKR SATA1RXN
SATA1RXP
AM8
AZ_RST# K34 AP11 PCH_GPIO21 R205 10K_0402_5%
HDA_RST# SATA1TXN AP10
PCH_INTVRMEN RH37 @ 330K_0402_5% SATA1TXP SATA_LED# R113 10K_0402_5%
AZ_SDIN0_HD E34 AD7 SATA_PRX_C_DTX_N2
<34> AZ_SDIN0_HD HDA_SDIN0 SATA2RXN SATA_PRX_C_DTX_N2 <30>
AD5 SATA_PRX_C_DTX_P2
SATA2RXP SATA_PRX_C_DTX_P2 <30>
G34 AH5 SATA_PTX_DRX_N2 ODD PCH_GPIO21 R2071 2 10K_0402_5%
HDA_SDIN1 SATA2TXN SATA_PTX_DRX_N2 <30>
<36> HDA_SDO AZ_SDOUT AH4 SATA_PTX_DRX_P2 @
SATA2TXP SATA_PTX_DRX_P2 <30>
R180 0_0402_5% C34
HDA_SDIN2 AB8
IHDA
C SATA3RXN C
1 2 AZ_BITCLK A34 AB10
<34> AZ_BITCLK_HD HDA_SDIN3 SATA3RXP +3VS
R101 33_0402_5% AF3
SATA3TXN AF1
AZ_SDOUT A36 SATA3TXP
1 2 AZ_RST# HDA_SDO Y7 PCH_SPKR R1291 @ 1K_0402_5%
SATA
<34> AZ_RST_HD# SATA4RXN
R106 33_0402_5% Y5
1 2 AZ_SDOUT C36 SATA4RXP AD3
<34> AZ_SDOUT_HD HDA_DOCK_EN# / GPIO33 SATA4TXN LOW=Default
R108 33_0402_5% AD1
N32
HDA_DOCK_RST# / GPIO13
SATA4TXP *HIGH=No Reboot
Y3
SATA5RXN Y1
+3VALW +3VALW +3VALW SATA5RXP AB3
T1512 PAD PCH_JTAG_TCK J3 SATA5TXN AB1
JTAG_TCK SATA5TXP HDA_SDO +3V_PCH
1
JTAG
@ @ @
200_0402_5% 200_0402_5% 200_0402_5% T1514 PAD PCH_JTAG_TDI K5 Y10 SATA_COMP AZ_SDOUT R182 @ 1K_0402_5%
JTAG_TDI SATAICOMPI R1202 37.4_0402_1% L=>security measures defined in the Flash
T1515 PAD PCH_JTAG_TDO H1
*Low = Disabled
2
PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI JTAG_TDO AB12 +1.05VS_SATA3 Descriptor will be in effect (default) High = Enabled
SATA3RCOMPO
H=>Flash Descriptor Security will be overridden
1
PCH_SPI_CS0# Y14
<37> PCH_SPI_CS0# SPI_CS0#
PCH_SPI_CS1# T1 AZ_SYNC
<37> PCH_SPI_CS1# SPI_CS1#
SPI
P3 SATA_LED#
SATALED# SATA_LED# <38>
R125 2 @ 1 PCH_JTAG_TCK This signal has a weak internal pull-down
51_0402_5% PCH_SPI_MOSI V4 V14 PCH_GPIO21 On Die PLL VR is supplied by
Intel DPDG Rev1.2 requirement. <37> PCH_SPI_MOSI SPI_MOSI SATA0GP / GPIO21
1.5V when smapled high
PCH_SPI_MISO U3 P1 BBS_BIT0_R 2 1 +3VS
+5VS <37> PCH_SPI_MISO SPI_MISO SATA1GP / GPIO19 1.8V when sampled low
R208 10K_0402_5%
Needs to be pulled High for Chief River platfrom
B PANTHER-POINT_FCBGA989 B
+3V_PCH
2
G
BSS138_SOT23
Q10
1 @ 2
0_0402_5% R188
1
R409
1M_0402_5%
2
RTC Battery
+RTCBATT
MAX. 8000mil
RH62
1K_0402_5%
W=20mils
1
DH1
+RTCVCC +CHGRTC
2
A W=20mils W=20mils A
1 BAS40-04_SOT23-3
CH8
1U_0603_10V4Z
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (1/8) SATA,HDA,SPI, LPC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom VBL30/31 LA-9351P M/B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, July 16, 2012 Sheet 19 of 50
5 4 3 2 1
5 4 3 2 1
PCH_GPIO11
R155 10K_0402_5%
PCH_SMBCLK R1322 2 1 2.2K_0402_5% +3V_PCH
PCH_SMBDATA R1222 2 1 2.2K_0402_5%
UH1B
PCH_SML0CLK
D BG34 R1331 2.2K_0402_5% D
<31> PCIE_PRX_C_LANTX_N1 PERN1
<31> PCIE_PRX_C_LANTX_P1 BJ34 E12 PCH_GPIO11 PCH_SML0DATA
C217 1 2 0.1U_0402_16V7K PCIE_PTX_LANRX_N1 AV32 PERP1 SMBALERT# / GPIO11 R1224 2.2K_0402_5%
10/100/1G LAN ---> <31> PCIE_PTX_C_LANRX_N1 PETN1
C218 1 2 0.1U_0402_16V7K PCIE_PTX_LANRX_P1 AU32 H14 PCH_SMBCLK PCH_SMLCLK1
<31> PCIE_PTX_C_LANRX_P1 PETP1 SMBCLK
MEMORY R130 2.2K_0402_5%
<32> PCIE_PRX_WLANTX_N2 BE34 C9 PCH_SMBDATA PCH_SMLDATA1
BF34 PERN2 SMBDATA R1206 2.2K_0402_5%
<32> PCIE_PRX_WLANTX_P2 PERP2
MiniWLAN (Mini Card 1)---> C215 1 2 0.1U_0402_16V7K PCIE_PTX_WLANRX_N2 BB32
<32> PCIE_PTX_C_WLANRX_N2 PETN2
C216 1 2 0.1U_0402_16V7K PCIE_PTX_WLANRX_P2 AY32 PCH_HOT#
<32> PCIE_PTX_C_WLANRX_P2 PETP2
SMBUS
A12 DRAMRST_CNTRL_PCH R1320 10K_0402_5%
SML0ALERT# / GPIO60 DRAMRST_CNTRL_PCH <7,10>
BG36 DRAMRST_CNTRL_PCH
BJ36 PERN3 C8 PCH_SML0CLK RH80 1K_0402_1%
AV34 PERP3 SML0CLK PEG_CLKREQ#_R R25 1 210K_0402_5%
AU34 PETN3 G12 PCH_SML0DATA UMA@
PETP3 SML0DATA
BF36
BE36 PERN4 CLKIN_DMI2# RH91 10K_0402_5%
AY34 PERP4 C13 PCH_HOT# CLKIN_DMI2 RH89 10K_0402_5%
PETN4 SML1ALERT# / PCHHOT# / GPIO74 PCH_HOT# <36>
BB34 CLKIN_DMI# RH92 10K_0402_5%
PETP4 E14 PCH_SMLCLK1 CLKIN_DMI RH90 10K_0402_5%
SML1CLK / GPIO58
PCI-E*
BG37 CLKIN_DOT96# RH76 10K_0402_5%
BH37 PERN5 M16 PCH_SMLDATA1 CLKIN_DOT96 RH77 10K_0402_5%
AY36 PERP5 SML1DATA / GPIO75 CLKIN_SATA# RH78 10K_0402_5%
BB36 PETN5 CLKIN_SATA RH79 10K_0402_5%
PETP5 CLK_PCH_14M RH183 10K_0402_5%
BJ38 +5V_PCH
BG38 PERN6
PERP6
Controller
AU36 M7 CL_CLK_DMC R219 1 2 2.2K_0402_5% If use extenal CLK gen, please place close to CLK gen
AV36 PETN6 CL_CLK1 @ else, please place close to PCH
PETP6
Link
BG40 T11 CL_DATA_DMC R222 1 2 2.2K_0402_5%
BJ40 PERN7 CL_DATA1 @
C AY40 PERP7 C
BB40 PETN7 P10 CL_RST#_DMC R223 1 2 10K_0402_5%
PETP7 CL_RST1# @
BE38
BC38 PERN8 @
AW38 PERP8 2 R9 1
PETN8 PEG_CLKREQ# <14>
AY38 0_0402_5%
PETP8 PX@
M10 PEG_CLKREQ#_R R63 1 210K_0402_5%
R1213 1 2 0_0402_5% CLK_R_LAN# Y40 PEG_A_CLKRQ# / GPIO47
<31> CLK_LAN#
R1214 1 2 0_0402_5% CLK_R_LAN Y39 CLKOUT_PCIE0N R253 PX@
VGA
10/100/1G LAN ---> <31> CLK_LAN CLKOUT_PCIE0P AB37 CLK_VGA# 0_0402_5% 2 1 CLK_PCIE_VGA# <13>
1 2 CLKREQ_LAN# J2 CLKOUT_PEG_A_N AB38 CLK_VGA 0_0402_5% 2 1
CLOCKS
+3V_PCH PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P CLK_PCIE_VGA <13>
<31> CLKREQ_LAN# R1527 10K_0402_5% R254 PX@
2
Y45
CLKOUT_PCIE4P AK7 CLKIN_SATA#
R1528 10K_0402_5% PCH_GPIO26 L12 CLKIN_SATA_N AK5 CLKIN_SATA PCH_SMBCLK 6 1
+3V_PCH PCIECLKRQ4# / GPIO26 CLKIN_SATA_P PM_SMBCLK <11,12,32>
2N7002DW-T/R7_SOT363-6
V45 K45 CLK_PCH_14M Q3A
@ R265 @ C459 V46 CLKOUT_PCIE5N REFCLK14IN
33_0402_5% 22P_0402_50V8J CLKOUT_PCIE5P
5
CLK_PCH_14M 2 1 1 2 +3V_PCH R1504 10K_0402_5% PCH_GPIO44 L14 H45 CLK_PCILOOP
PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCILOOP <22>
PCH_SMBDATA 3 4
PM_SMBDATA <11,12,32>
AB42 V47 PCH_X1
@ @ AB40 CLKOUT_PEG_B_N XTAL25_IN V49 PCH_X2 2N7002DW-T/R7_SOT363-6
R269 C453 CLKOUT_PEG_B_P XTAL25_OUT
Q3B
CLK_PCILOOP 2 1 1 2 +3V_PCH R1530 10K_0402_5% PCH_GPIO56 E6
33_0402_5% 22P_0402_50V8J PEG_B_CLKRQ# / GPIO56
Reserve for EMI please close to Y47 XCLK_RCOMP +1.05VS_VCCDIFFCLKN
V40 XCLK_RCOMP RH115 90.9_0402_1% +3VS
UH4 CLKOUT_PCIE6N
V42
CLKOUT_PCIE6P
+3V_PCH R1505 10K_0402_5% PCH_GPIO45 T13
PCIECLKRQ6# / GPIO45 +3VS
2
PCH_X1 V38 K43
CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64
FLEX CLOCKS
V37
PCH_X2 CLKOUT_PCIE7P F47 RC50 PCH_SMLCLK1 6 1
CLKOUTFLEX1 / GPIO65 EC_SMB_CK2 <14,36>
1M_0402_5% R1216 +3V_PCH R1521 10K_0402_5% PCH_GPIO46 K12 UMA@ 10K_0402_5%
PCIECLKRQ7# / GPIO46 H47 2N7002DW-T/R7_SOT363-6
Y3 CLK_BCLK_ITP# AK14 CLKOUTFLEX2 / GPIO66
CLKOUT_ITPXDP_N Q4A PU AT EC SIDE, +3VS AND 2.2K
CLK_BCLK_ITP AK13 K49 DGPU_PRSNT#
CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67
5
1 3
1 3
2
A A
GND GND RH108 2 @ 1 0_0402_5% PANTHER-POINT_FCBGA989 PX@ R1534 PCH_SMLDATA1 3 4
<8> CLK_RES_ITP# EC_SMB_DA2 <14,36>
RH110 2 @ 1 0_0402_5% 10K_0402_5%
2 4 <8> CLK_RES_ITP 2N7002DW-T/R7_SOT363-6
10P_0402_50V8J
2 2
Q4B
1
25MHZ_10PF_7V25000014 C225
10P_0402_50V8J
1 C869 1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/06/01 Deciphered Date 2013/05/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (2/8) PCIE, SMBUS, CLK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom VBL30/31 LA-9351P M/B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, July 16, 2012 Sheet 20 of 50
5 4 3 2 1
5 4 3 2 1
PCH_ENBKL 2 1 PCH_ENBKL_R
<36> PCH_ENBKL
R297 0_0402_5%
2
R300
UH1C 100K_0402_5%
UH1D
Pull high at LVDS conn side.
1
<5> DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0 FDI_CTX_PRX_N0 <5> PCH_ENBKL_R J47 AP43
DMI_CTX_PRX_N1 BE20 DMI0RXN FDI_RXN0 AY14 FDI_CTX_PRX_N1 M45 L_BKLTEN SDVO_TVCLKINN AP45
<5> DMI_CTX_PRX_N1 DMI1RXN FDI_RXN1 FDI_CTX_PRX_N1 <5> <28> PCH_ENVDD L_VDD_EN SDVO_TVCLKINP
<5> DMI_CTX_PRX_N2 DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2 FDI_CTX_PRX_N2 <5>
DMI_CTX_PRX_N3 BG20 DMI2RXN FDI_RXN2 BH13 FDI_CTX_PRX_N3 P45 AM42
<5> DMI_CTX_PRX_N3 DMI3RXN FDI_RXN3 FDI_CTX_PRX_N3 <5> <28> PCH_BL_PWM L_BKLTCTL SDVO_STALLN
BC12 FDI_CTX_PRX_N4 FDI_CTX_PRX_N4 <5> AM40
DMI_CTX_PRX_P0 BE24 FDI_RXN4 BJ12 FDI_CTX_PRX_N5 T40 SDVO_STALLP
<5> DMI_CTX_PRX_P0 DMI0RXP FDI_RXN5 FDI_CTX_PRX_N5 <5> <28> PCH_EDID_CLK L_DDC_CLK
<5> DMI_CTX_PRX_P1 DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6 FDI_CTX_PRX_N6 <5> K47 AP39
DMI1RXP FDI_RXN6 <28> PCH_EDID_DATA L_DDC_DATA SDVO_INTN
D <5> DMI_CTX_PRX_P2 DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7 FDI_CTX_PRX_N7 <5> AP40 D
DMI_CTX_PRX_P3 BJ20 DMI2RXP FDI_RXN7 CTRL_CLK T45 SDVO_INTP
<5> DMI_CTX_PRX_P3 DMI3RXP L_CTRL_CLK
BG14 FDI_CTX_PRX_P0 FDI_CTX_PRX_P0 <5> CTRL_DATA P39
DMI_PTX_CRX_N0 AW24 FDI_RXP0 BB14 FDI_CTX_PRX_P1 L_CTRL_DATA
<5> DMI_PTX_CRX_N0 DMI0TXN FDI_RXP1 FDI_CTX_PRX_P1 <5>
DMI_PTX_CRX_N1 AW20 BF14 FDI_CTX_PRX_P2 FDI_CTX_PRX_P2 <5> 2 1 LVDS_IBG AF37 P38
<5> DMI_PTX_CRX_N1 DMI1TXN FDI_RXP2 LVD_IBG SDVO_CTRLCLK PCH_HDMI_CLK <29>
DMI_PTX_CRX_N2 BB18 BG13 FDI_CTX_PRX_P3 FDI_CTX_PRX_P3 <5> RH245 2.37K_0402_1% AF36 M39
<5> DMI_PTX_CRX_N2 DMI2TXN FDI_RXP3 LVD_VBG SDVO_CTRLDATA PCH_HDMI_DATA <29>
DMI_PTX_CRX_N3 AV18 BE12 FDI_CTX_PRX_P4 FDI_CTX_PRX_P4 <5>
<5> DMI_PTX_CRX_N3 DMI3TXN FDI_RXP4
DMI
FDI
BG12 FDI_CTX_PRX_P5 FDI_CTX_PRX_P5 <5> AE48
DMI_PTX_CRX_P0 AY24 FDI_RXP5 BJ10 FDI_CTX_PRX_P6 AE47 LVD_VREFH AT49
<5> DMI_PTX_CRX_P0 DMI0TXP FDI_RXP6 FDI_CTX_PRX_P6 <5> LVD_VREFL DDPB_AUXN
DMI_PTX_CRX_P1 AY20 BH9 FDI_CTX_PRX_P7 FDI_CTX_PRX_P7 <5> AT47
<5> DMI_PTX_CRX_P1 DMI1TXP FDI_RXP7 DDPB_AUXP
DMI_PTX_CRX_P2 AY18 AT40
<5> DMI_PTX_CRX_P2 DMI2TXP DDPB_HPD PCH_HDMI_HPD <29>
DMI_PTX_CRX_P3 AU18 PCH_TXCLK- AK39
<5> DMI_PTX_CRX_P3 DMI3TXP <28> PCH_TXCLK- LVDSA_CLK#
LVDS
AW16 FDI_INT PCH_TXCLK+ AK40 AV42 PCH_HDMI_TX2-
FDI_INT FDI_INT <5> <28> PCH_TXCLK+ LVDSA_CLK DDPB_0N PCH_HDMI_TX2- <29>
AV40 PCH_HDMI_TX2+
+1.05VS_PCH DDPB_0P PCH_HDMI_TX2+ <29>
BJ24 AV12 FDI_FSYNC0 PCH_TXOUT0- AN48 AV45 PCH_HDMI_TX1-
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 <5> <28> PCH_TXOUT0- LVDSA_DATA#0 DDPB_1N PCH_HDMI_TX1- <29>
PCH_TXOUT1- AM47 AV46 PCH_HDMI_TX1+
CRT
<36> PCH_RSMRST# C21 H4 PM_SLP_S4# PCH_CRT_CLK T39 AT43
RSMRST# SLP_S4# PM_SLP_S4# <36> <27> PCH_CRT_CLK CRT_DDC_CLK DDPD_AUXP
PCH_CRT_DATA M40 BH41
<27> PCH_CRT_DATA CRT_DDC_DATA DDPD_HPD
R1489 0_0402_5% T1704 PAD
2 1 SUSWARN#_R K16 F4 PM_SLP_S3# BB43
<36> SUSWARN# SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# PM_SLP_S3# <36> DDPD_0N
DS3@ <27> PCH_CRT_HSYNC M47 BB45
M49 CRT_HSYNC DDPD_0P BF44
For DS3 PBTN_OUT#_R E20 G10 PM_SLP_A# T1724 PAD
<27> PCH_CRT_VSYNC CRT_VSYNC DDPD_1N BE44
<36> PBTN_OUT# PWRBTN# SLP_A# DDPD_1P
RH137 0_0402_5% BF42
DH2
For DS3 CRT_IREF T43 DDPD_2N BE42
1 2 PCH_ACIN H20 G16 SLP_SUS# T42 DAC_IREF DDPD_2P BJ42
<14,36,41> ACIN ACPRESENT / GPIO31 SLP_SUS# SLP_SUS# <36> Can be left NC when IAMT is CRT_IRTN DDPD_3N
not support on the platfrom BG42
RB751V-40_SOD323-2 T1706 PAD DDPD_3P
PCH_LOW_BAT# E10 AP14 H_PM_SYNC PANTHER-POINT_FCBGA989
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC <6>
R1250
1K_0402_0.5%
RI# A10 K14 PCH_GPIO29
RI# SLP_LAN# / GPIO29
+3VS
+3VS
R303 1 2 2.2K_0402_5% CTRL_CLK
RH291 1 2 2.2K_0402_5% PCH_CRT_CLK
+3VS R302 1 2 2.2K_0402_5% CTRL_DATA
RH292 1 2 2.2K_0402_5% PCH_CRT_DATA
5
R283
PCH_RSMRST# R1257 10K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/06/01 Deciphered Date 2013/05/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (3/8) DMI,FDI,PM,GFX,DP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom VBL30/31 LA-9351P M/B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, July 16, 2012 Sheet 21 of 50
5 4 3 2 1
5 4 3 2 1
UH1E
AY7
RSVD1 AV7
BG26 RSVD2 AU3
BJ26 TP1 RSVD3 BG4
BH25 TP2 RSVD4
BJ16 TP3 AT10
GPIO19 => BBS_BIT0
BG16 TP4 RSVD5 BC8
AH38 TP5 RSVD6 GPIO51 => BBS_BIT1
AH37 TP6 AU2
TP7 RSVD7 Boot BIOS Strap
AK43 AT4
AK45 TP8 RSVD8 AT3
TP9 RSVD9 BBS_BIT0 BBS_BIT1 Boot BIOS
C18 AT1
N30 TP10 RSVD10 AY3 Location
H3 TP11 RSVD11 AT5
D TP12 RSVD12 0 0 LPC D
AH12 AV3
AM4 TP13 RSVD13 AV1
TP14 RSVD14 0 1 Reserved(NAND)
AM5 BB1
Y13 TP15 RSVD15 BA3
TP16 RSVD16 1 0 Reserved
K24 BB5
L24 TP17 RSVD17 BB3
TP18 RSVD18 1 1 SPI *
AB46 BB7
AB45 TP19 RSVD19 BE8
TP20 RSVD20
RSVD
BD4
RSVD21 BF6
RSVD22
B21 AV5 NV_ALE
M20 TP21 RSVD23 AV10
AY16 TP22 RSVD24
TP23
Intel Anti-Theft Techonlogy
BG46 AT8
TP24 RSVD25
High=Endabled
AY5 NV_ALE
RSVD26 BA2 Low=Disable(floating)
<33> USB3_RX0_N BE28
USB3Rn1
RSVD27 *
BC30 AT12
BE32 USB3Rn2 RSVD28 BF3 +1.8VS
BJ32 USB3Rn3 RSVD29
BC28 USB3Rn4 NV_ALE @ R341 1K_0402_5%
<33> USB3_RX0_P USB3Rp1
BE30
BF32 USB3Rp2
BG32 USB3Rp3 C24 USB20_N0
AV26 USB3Rp4 USBP0N A24 USB20_P0
USB20_N0 <33> USB3.0
<33> USB3_TX0_N USB3Tn1 USBP0P USB20_P0 <33>
BB26 C25
AU28 USB3Tn2 USBP1N B25
AY30 USB3Tn3 USBP1P C26 USB20_N2
USB3Tn4 USBP2N USB20_N2 <32>
AU26 A26 USB20_P2 Port 2 : BT
<33> USB3_TX0_P USB3Tp1 USBP2P USB20_P2 <32>
AY26 K28
C AV28 USB3Tp2 USBP3N H28 C
AW30 USB3Tp3 USBP3P E28
USB3Tp4 USBP4N D28
USBP4P C28
USBP5N A28
USBP5P C29
USBP6N B29
PCI_PIRQA# K40 USBP6P N28
PCI_PIRQB# K38 PIRQA# USBP7N M28
HM70 not support USB port 4,5,6,7,12,13
PIRQB# USBP7P +3V_PCH
PCI
PCI_PIRQC# H38 L30 USB20_N8
PIRQC# USBP8N USB20_N8 <32>
PCI_PIRQD# G38 K30 USB20_P8 R-CONN
PIRQD# USBP8P USB20_P8 <32>
G30 USB20_N9 USB_OC0# 1 2
USBP9N USB20_N9 <32>
DGPU_HOLD_RST# 2 PX@ 1 DGPU_HOLD_RST#_R C46 E30 USB20_P9 R-CONN R1267 10K_0402_5%
REQ1# / GPIO50 USBP9P USB20_P9 <32>
USB
R262 0_0402_5% PCH_GPIO52 C44 C30 USB20_N10 USB_OC1# 1 2
REQ2# / GPIO52 USBP10N USB20_N10 <28>
<39,50> DGPU_PWR_EN 1 PX@ 2 DGPU_PWR_EN_R E40 A30 USB20_P10 Port 10 : Int. Carema R1269 10K_0402_5%
REQ3# / GPIO54 USBP10P USB20_P10 <28>
RH161 0_0402_5% L32 USB20_N11 USB_OC5# 1 2
USBP11N USB20_N11 <33>
PCH_GPIO51 D47 K32 USB20_P11 Port 11 : Card Reader R1306 10K_0402_5%
GNT1# / GPIO51 USBP11P USB20_P11 <33>
PCH_GPIO53 E42 G32 USB_OC6# 1 2
PCH_GPIO55 F46 GNT2# / GPIO53 USBP12N E32 R1307 10K_0402_5%
GNT3# / GPIO55 USBP12P C32 USB_OC2# 1 2
USBP13N A32 R1308 10K_0402_5%
PCH_GPIO2 G42 USBP13P USB_OC3# 1 2
ODD_DA# G40 PIRQE# / GPIO2 R1309 10K_0402_5%
<30> ODD_DA#
PCH_GPIO4 C42 PIRQF# / GPIO3 C33 USBRBIAS
Within 500 mils USB_OC4# 1 2
PCH_GPIO5 D44 PIRQG# / GPIO4 USBRBIAS# R1266 22.6_0402_1% R1310 10K_0402_5%
PIRQH# / GPIO5 USB_OC7# 1 2
B33 R1311 10K_0402_5%
PAD T1834 @ K10 USBRBIAS
PME#
PLT_RST# 2 1 BUF_PLT_RST# C6 A14 USB_OC0#
<6,31,32,36> PLT_RST# PLTRST# OC0# / GPIO59 USB_OC0# <33>
R259 0_0402_5% K20 USB_OC1#
OC1# / GPIO40 B17 USB_OC2#
B 22_0402_5% 2 R280 1 CLK_PCI_EC_R H49 OC2# / GPIO41 C16 USB_OC3# B
<36> CLK_PCI_EC CLKOUT_PCI0 OC3# / GPIO42
22_0402_5% 2 R285 1 CLK_PCI H43 L16 USB_OC4#
<20> CLK_PCILOOP CLKOUT_PCI1 OC4# / GPIO43
PAD T1836 @ CLK_PCI2 J48 A16 USB_OC5#
CLKOUT_PCI2 OC5# / GPIO9 USB_OC5# <32>
PAD T1835 @ CLK_PCI3 K42 D14 USB_OC6#
PAD T1833 @ CLK_PCI4 H40 CLKOUT_PCI3 OC6# / GPIO10 C14 USB_OC7#
CLKOUT_PCI4 OC7# / GPIO14
PANTHER-POINT_FCBGA989
+3VS
+3VS
RP1
5
8 1 PCH_GPIO55 U8
7 2 PCH_GPIO51 BUF_PLT_RST# 1
P
8.2K_0804_8P4R_5% @ SN74AHC1G08DCKR_SC70-5
3
2
2
RP3 R151
8 1 PCH_GPIO2 R157
7 2 PCH_GPIO4 100K_0402_5% +3VS 100K_0402_5%
6 3 PCH_GPIO53 @
1
5 4 PCI_PIRQC# 2
1
8.2K_0804_8P4R_5% C477
0.1U_0402_16V4Z
1 PX@ 2 DGPU_HOLD_RST#_R 1 PX@
5
R350 8.2K_0402_5%
1 2 PCI_PIRQB# 1
P
R348 8.2K_0402_5%
1 2 DGPU_PWR_EN_R SN74AHC1G08DCKR_SC70-5
3
1 2 PCI_PIRQD#
R311 8.2K_0402_5% R408
1K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/06/01 Deciphered Date 2013/05/12 Title
2 @ 1 DGPU_PWR_EN @
10K_0402_5% R1277 PCH (4/8) PCI, USB, NVRAM
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom VBL30/31 LA-9351P M/B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, July 16, 2012 Sheet 22 of 50
5 4 3 2 1
5 4 3 2 1
+3VS
10K_0402_5% PCH_GPIO0
R1325
200K_0402_5% 2 1 ODD_DETECT# UH1F
R353
10K_0402_5% PCH_GPIO6 PCH_GPIO0 T7 C40 ODD_EN#
BMBUSY# / GPIO0 TACH4 / GPIO68 ODD_EN# <30>
R1286 DMI Termination Voltage
10K_0402_5% PCH_GPIO34 PCH_GPIO1 A42 B41 PROJECT_ID0
R352 TACH1 / GPIO1 TACH5 / GPIO69
Set to Vcc when HIGH
10K_0402_5% KB_RST# PCH_GPIO6 H36 C41 PROJECT_ID1 +3VS NV_CLE
R1274 TACH2 / GPIO6 TACH6 / GPIO70
Set to Vss when LOW
10K_0402_5% PCH_GPIO48 <36> EC_SCI# EC_SCI# E38 A40 PROJECT_ID2
D R356 TACH3 / GPIO7 TACH7 / GPIO71 D
Weak internal
10K_0402_5% PCH_GPIO22 EC_SMI# C10 R1259 +1.8VS
<36> EC_SMI# GPIO8 PU,Do not pull low
R342 10K_0402_5%
10K_0402_5% ODD_EN# PCH_GPIO12 C4
R1287 LAN_PHY_PWR_CTRL / GPIO12
10K_0402_5% VGA_PWROK_R LID_SW_OUT# G2 P4 GATEA20
<36> LID_SW_OUT# GPIO15 A20GATE GATEA20 <36>
R1278 R344
10K_0402_5% EC_SCI# AU16 PCH_PECI_R @ 2.2K_0402_5%
PECI H_PECI <6,36>
R1296 PCH_GPIO16 U2 0_0402_5% RH159
SATA4GP / GPIO16 P5 NV_CLE
RCIN# KB_RST# <36> H_SNB_IVB# <6>
PX@ 1K_0402_5% R336
GPIO
1 2 VGA_PWROK_R D40 AY11
<13,50> VGA_PWROK TACH0 / GPIO17 PROCPWRGD H_PWRGOOD <6>
CPU/MISC
RH172 0_0402_5% CLOSE TO THE BRANCHING POINT
PCH_GPIO1 PCH_GPIO22 T5 AY10 PCH_THRMTRIP# H_THERMTRIP# H_THERMTRIP# <6>
10K_0402_5% R1323 SCLOCK / GPIO22 THRMTRIP# 390_0402_5% R1261
@ PCH_GPIO37 PCH_GPIO24 E8 T14
10K_0402_5% R354 @ GPIO24 INIT3_3V#
CE_EN 1 2 PCH_GPIO27 E16 AY1 NV_CLE INIT3_3V
<36> EC_WAKE# GPIO27 DF_TVS
10K_0402_5% R1324 RH173 0_0402_5%
PCH_GPIO39 PCH_GPIO28 P8 This signal has weak internal
10K_0402_5% R1326 GPIO28 AH8
PCH_GPIO49 PCH_GPIO34 K1 TS_VSS1 PU, can't pull low
10K_0402_5% R355 STP_PCI# / GPIO34 AK11
PCH_GPIO16 PCH_GPIO35 K4 TS_VSS2
10K_0402_5% R1280 GPIO35 AH10
ODD_DETECT# V8 TS_VSS3
<30> ODD_DETECT# SATA2GP / GPIO36 AK10
PCH_GPIO37 M5 TS_VSS4
SATA3GP / GPIO37 PROJECT_ID2 1 2
<28> CE_EN CE_EN N2 P37 R1279 10K_0402_5%
+3V_PCH SLOAD / GPIO38 NC_1
PCH_GPIO39 M3
C 10K_0402_5% PCH_GPIO28 SDATAOUT0 / GPIO39 C
R346 PCH_GPIO48 V13 BG2
10K_0402_5% PCH_GPIO57 SDATAOUT1 / GPIO48 VSS_NCTF_15 +3VS
R1276 PCH_GPIO49 V3 BG48
10K_0402_5% @ PCH_GPIO24 SATA5GP / GPIO49 / TEMP_ALERT# VSS_NCTF_16
R1327 PCH_GPIO57 D6 BH3 PROJECT_ID2 1 2
10K_0402_5% EC_SMI# GPIO57 VSS_NCTF_17 R1281 @10K_0402_5%
R61 BH47
10K_0402_5% PCH_GPIO12 VSS_NCTF_18 PROJECT_ID0 1 PX@ 2
R1284 A4 BJ4 10K_0402_5% R351
1K_0402_5% R141 LID_SW_OUT# VSS_NCTF_1 VSS_NCTF_19 1 UMA@ 2
A44 BJ44 10K_0402_5% R370
VSS_NCTF_2 VSS_NCTF_20
A45 BJ45 PROJECT_ID1 1 @ 2
@ PCH_GPIO27 VSS_NCTF_3 VSS_NCTF_21 10K_0402_5% R414
NCTF
R343 10K_0402_5% A46 BJ46 1 2
PCH_GPIO37 VSS_NCTF_4 VSS_NCTF_22 10K_0402_5% R411
R367 10K_0402_5% A5 BJ5
R1275 1 @ 2 PCH_GPIO35 VSS_NCTF_5 VSS_NCTF_23
PROJECT_ID2 PROJECT_ID1 PROJECT_ID0
10K_0402_5% A6 BJ6
VSS_NCTF_6 VSS_NCTF_24
B3 C2 VBL30(UMA) 0 0 0
VSS_NCTF_7 VSS_NCTF_25
+3VALW B47 C48
For DS3 VSS_NCTF_8 VSS_NCTF_26 VBL31(PX) 0 0 1
@ BD1 D1
R209 2 1 10K_0402_5% PCH_GPIO27 VSS_NCTF_9 VSS_NCTF_27
BD49 D49
VSS_NCTF_10 VSS_NCTF_28
BE1 E1
VSS_NCTF_11 VSS_NCTF_29
GPIO28
On-Die PLL Voltage Regulator BE49 E49
B VSS_NCTF_12 VSS_NCTF_30 B
This signal has a weak internal pull up
BF1 F1
VSS_NCTF_13 VSS_NCTF_31
HΚOn-Die voltage regulator enable
* LΚOn-Die PLL Voltage Regulator disable BF49
VSS_NCTF_14 VSS_NCTF_32
F49
PCH_GPIO28
PANTHER-POINT_FCBGA989
@ R345 1K_0402_5%
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (5/8) GPIO, CPU, MISC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom VBL30/31 LA-9351P M/B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, July 16, 2012 Sheet 23 of 50
5 4 3 2 1
5 4 3 2 1
+3VS
To solve CRT issue
L13 PCH Power Rail Table
+VCCADAC 1 2 2 1
+1.05VS_VCCP +1.05VS_PCH 1 1 1 R105 BLM18PG181SN1D_2P Refer to CPU EDS R1.5
.01U_0402_16V7K
C287
0.1U_0402_10V7K
C294
2.2_0603_1%
UH1G POWER C289
10U_0603_6.3V6M
S0 Iccmax
Voltage Rail Voltage Current (A)
@ JPH2 1300mA 2 2 2
1 2 AA23 U48
1 2 AC23 VCCCORE[1] 1mA VCCADAC
VCCCORE[2]
V_PROC_IO 1.05 0.001
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
JUMP_43X118 1 AD21
CRT
AD23 VCCCORE[3] U47
VCCCORE[4] VSSADAC
CH31
CH33
CH34
CH32 AF21 V5REF 5 0.001
VCC CORE
10U_0805_6.3V6M AF23 VCCCORE[5]
D 2 AG21 VCCCORE[6] R332 +3VS D
AG23 VCCCORE[7] 0_0603_5%
VCCCORE[8]
V5REF_Sus 5 0.001
AG24 AK36 +VCCALVDS 1 2
AG26 VCCCORE[9] 1mAVCCALVDS
AG27 VCCCORE[10] AK37 +1.8VS
VCCCORE[11] VSSALVDS
Vcc3_3 3.3 0.228
AG29 L25
AJ23 VCCCORE[12] 0.1UH_MLF1608DR10KT_10%_1608
VCCCORE[13]
LVDS
AJ26 AM37 +VCCTX_LVDS 2 1 VccADAC 3.3 0.001
AJ27 VCCCORE[14] VCCTX_LVDS[1]
VCCCORE[15] 1 0.1uH inductor, 200mA
+1.05VS_PCH AJ29 AM38
AJ31 VCCCORE[16] VCCTX_LVDS[2] C296 C297 C295
VCCCORE[17]
VccADPLLA 1.05 0.075
40mAVCCTX_LVDS[3] AP36 .01U_0402_16V7K .01U_0402_16V7K 22U_0805_6.3V6M
2
AP37 VccADPLLB 1.05 0.075
AN19 VCCTX_LVDS[4]
VCCIO[28]
VccCore 1.05 1.3
BJ22
VCCAPLLEXP RH211
V33 +3VS_VCC3_3_6 +3VS VccDMI 1.05 0.042
VCC3_3[6]
HVCMOS
AN16 0_0805_5%
VCCIO[15]
AN17 VccIO 1.05 3.709
VCCIO[16] V34 CH42
VCC3_3[7]
0.1U_0402_10V7K
AN21 VccASW 1.05 0.903
VCCIO[17]
AN26
VCCIO[18]
VccSPI 3.3 0.01
AN27 3709mA AT16 +1.5VS
+1.05VS_PCH VCCIO[19] VCCVRM[3]
160mil AP21 +VCCP_VCCDMI +1.05VS_VCCP VccDSW 3.3 0.001
C VCCIO[20] RH213 C
AP23 AT20 +VCCP_VCCDMI
VCCIO[21] VCCDMI[1]
VccDFTERM 1.8 0.002
DMI
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 AP24 0_0805_5%
VCCIO[22] RH214
VCCIO
+1.05VS_PCH CH48
CH44
CH45
CH46
CH47
DFT / SPI
0.1U_0402_10V7K
CH50 VccCLKDMI 1.05 0.075
AJ16
0.1U_0402_10V7K VCCDFTERM[3]
CH51
+1.5VS AP16 VccSSC 1.05 0.095
VCCVRM[2] AJ17
VCCDFTERM[4]
BG6 VccDIFFCLKN 1.05 0.055
VccAFDIPLL
+3VALW
RH219 0_0805_5%
+VCCP_VCCDMI AU20 VccTX_LVDS 1.8 0.04
VCCDMI[2] 2 1 +3VS
CH53 RH220 0_0603_5%
B PANTHER-POINT_FCBGA989 1U_0402_6.3V6K B
KB9012@
Intel recommand
VCCVRM==>1.5V FOR MOBILE
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (6/8) PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom VBL30/31 LA-9351P M/B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, July 16, 2012 Sheet 24 of 50
5 4 3 2 1
5 4 3 2 1
+5VALW +5V_PCH
This pin can be left as no connect in @ JPH1
On-Die VR enabled mode (default). 2 1
D
3 1
0.1U_0402_10V7K~D
CH55 P26
VCCIO[30]
20K_0402_5%~D
0.1U_0402_10V7K +VCCPDSW T16
VCCDSW3_33mA
1
D P28 CH56 D
G
1
2
VCCIO[31] 1U_0402_6.3V6K
RH228
@
CH57
2 1 +PCH_VCCDSW V12 T27 @
CH58 0.1U_0402_10V7K DCPSUSBYP VCCIO[32]
<39> PCH_PWR_EN# 2
T29
2
+3VS_VCC_CLKF33 T38 VCCIO[33]
This pin can be left as no connect in VCC3_3[5]
On-Die VR enabled mode (default). T23 +3V_PCH
119mA VCCSUS3_3[7]
0.1U_0402_10V7K
PAD T76 @ +VCCAPLL_CPY_PCH BH23
VCCAPLLDMI2 T24
VCCSUS3_3[8] +3V_PCH +5V_PCH +3V_PCH
0.1U_0402_10V7K
+1.05VS_PCH AL29
VCCIO[14]
CH60
V23
VCCSUS3_3[9]
USB
2
CH61
PAD T77 @ +VCCSUS1 AL24 V24
DCPSUS[3] VCCSUS3_3[10] RH232 DH3
+3VS RH239 0_0805_5% P24 100_0402_5%
+3VS_VCC_CLKF33
This pin can be left as no connect in VCCSUS3_3[6] RB751S40T1_SOD523-2
On-Die VR enabled mode (default).
1U_0402_6.3V6K
10U_0805_10V4Z
AA19
1
VCCASW[1] T26 +PCH_V5REF_SUS
VCCIO[34] +1.05VS_PCH
CH73
CH74
AA21 903mA
VCCASW[2]
AA24 M26 +PCH_V5REF_SUS CH63
VCCASW[3] 1mA V5REF_SUS .1U_0603_25V7K
1 1
AA26 This pin can be left as no connect in
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
C RH236 C
AC27 0_0603_5% RH237 DH4
VCCASW[9]
CH67
CH68
CH69
N20 +3V_VCCPSUS +3V_PCH 100_0402_5% RB751S40T1_SOD523-2
VCCSUS3_3[2]
PCI/GPIO/LPC
AC29
VCCASW[10] N22
1
AC31 VCCSUS3_3[3] CH70 +PCH_V5REF_RUN
VCCASW[11] P20 1U_0402_6.3V6K +3VS
AD29 VCCSUS3_3[4]
VCCASW[12] P22 +3VS_VCCPCORE CH71
AD31 VCCSUS3_3[5] RH238 0_0805_5% 1U_0603_10V6K
LH7 VCCASW[13]
10UH_LBR2012T100M_20% W21 AA16 CH72
1 2 +1.05VS_VCCA_A_DPL VCCASW[14] VCC3_3[1] 0.1U_0402_10V7K
W23 W16 +3VS
VCCASW[15] VCC3_3[8]
220U_B2_2.5VM_R35
1U_0402_6.3V6K
10UH_LBR2012T100M_20% 1 1 W26
VCCASW[17] CH75
+ + +3VS
CH93
CH95
W29 0.1U_0402_10V7K
VCCASW[18]
CH94
CH96
RH241
W31 AJ2 +VCC3_3_2
2 2 VCCASW[19] VCC3_3[2] +1.05VS_SATA3
W33 0_0603_5% RH242
VCCASW[20] AF13 CH76
VCCIO[5] +1.05VS_PCH
0.1U_0402_10V7K
+VCCRTCEXT N16 0_0805_5%
DCPRTC AH13 CH77
VCCIO[12] 1U_0402_6.3V6K
CH78 +1.5VS Y49 AH14 +1.05VS_SATA3
0.1U_0402_10V7K VCCVRM[4] VCCIO[13]
B +1.05VS_PCH AF14 B
+1.05VS_VCCA_A_DPL BD47 VCCIO[6]
VCCADPLLA75mA
SATA
+VCCDIFFCLK AK1 This pin can be left as no connect in
RH244 0_0603_5% +1.05VS_VCCA_B_DPL BF47 VCCAPLLSATA @ T19
CH79 VCCADPLLB75mA On-Die VR enabled mode (default).
AF11 +1.5VS
1U_0402_6.3V6K AF17 VCCVRM[1] +1.05VS_VCC_SATA
+1.05VS_PCH +1.05VS_VCCDIFFCLKN AF33 VCCIO[7] RH246
AF34 VCCDIFFCLKN[1] AC16 +1.05VS_VCC_SATA
VCCDIFFCLKN[2]
55mA VCCIO[2] +1.05VS_PCH
+1.05VS_VCCDIFFCLKN AG34
VCCDIFFCLKN[3]
1U_0402_6.3V6K
RH247 0_0603_5% AC17 0_0805_5%
VCCIO[3]
CH82
CH81 AG33 AD17
1U_0402_6.3V6K VCCSSC95mA VCCIO[4]
+1.05VS_PCH CH85
+VCCSST V16 +1.05VS_PCH
0.1U_0402_10V7K DCPSST
PAD T74 @ +1.05VM_VCCSUS
This pin can be left as no connect in T17 T21
CH84 V19 DCPSUS[1] VCCASW[22]
1U_0402_6.3V6K On-Die VR enabled mode (default). DCPSUS[2]
MISC
+1.05VS_VCCP V21
40mil
VCCASW[23]
CPU
0.1U_0402_10V7K
0.1U_0402_10V7K
CH88
CH86
4.7U_0603_6.3V6K
A22 P32 +VCCSUSHDA
RTC
0.1U_0402_10V7K
1U_0402_6.3V6K
PANTHER-POINT_FCBGA989
CH89
CH90
CH91
CH92
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (7/8) PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom VBL30/31 LA-9351P M/B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, July 16, 2012 Sheet 25 of 50
5 4 3 2 1
5 4 3 2 1
UH1I
AY4 H46
AY42 VSS[159] VSS[259] K18
AY46 VSS[160] VSS[260] K26
UH1H AY8 VSS[161] VSS[261] K39
D H5 B11 VSS[162] VSS[262] K46 D
VSS[0] B15 VSS[163] VSS[263] K7
AA17 AK38 B19 VSS[164] VSS[264] L18
AA2 VSS[1] VSS[80] AK4 B23 VSS[165] VSS[265] L2
AA3 VSS[2] VSS[81] AK42 B27 VSS[166] VSS[266] L20
AA33 VSS[3] VSS[82] AK46 B31 VSS[167] VSS[267] L26
AA34 VSS[4] VSS[83] AK8 B35 VSS[168] VSS[268] L28
AB11 VSS[5] VSS[84] AL16 B39 VSS[169] VSS[269] L36
AB14 VSS[6] VSS[85] AL17 B7 VSS[170] VSS[270] L48
AB39 VSS[7] VSS[86] AL19 F45 VSS[171] VSS[271] M12
AB4 VSS[8] VSS[87] AL2 BB12 VSS[172] VSS[272] P16
AB43 VSS[9] VSS[88] AL21 BB16 VSS[173] VSS[273] M18
AB5 VSS[10] VSS[89] AL23 BB20 VSS[174] VSS[274] M22
AB7 VSS[11] VSS[90] AL26 BB22 VSS[175] VSS[275] M24
AC19 VSS[12] VSS[91] AL27 BB24 VSS[176] VSS[276] M30
AC2 VSS[13] VSS[92] AL31 BB28 VSS[177] VSS[277] M32
AC21 VSS[14] VSS[93] AL33 BB30 VSS[178] VSS[278] M34
AC24 VSS[15] VSS[94] AL34 BB38 VSS[179] VSS[279] M38
AC33 VSS[16] VSS[95] AL48 BB4 VSS[180] VSS[280] M4
AC34 VSS[17] VSS[96] AM11 BB46 VSS[181] VSS[281] M42
AC48 VSS[18] VSS[97] AM14 BC14 VSS[182] VSS[282] M46
AD10 VSS[19] VSS[98] AM36 BC18 VSS[183] VSS[283] M8
AD11 VSS[20] VSS[99] AM39 BC2 VSS[184] VSS[284] N18
AD12 VSS[21] VSS[100] AM43 BC22 VSS[185] VSS[285] P30
AD13 VSS[22] VSS[101] AM45 BC26 VSS[186] VSS[286] N47
AD19 VSS[23] VSS[102] AM46 BC32 VSS[187] VSS[287] P11
AD24 VSS[24] VSS[103] AM7 BC34 VSS[188] VSS[288] P18
AD26 VSS[25] VSS[104] AN2 BC36 VSS[189] VSS[289] T33
AD27 VSS[26] VSS[105] AN29 BC40 VSS[190] VSS[290] P40
AD33 VSS[27] VSS[106] AN3 BC42 VSS[191] VSS[291] P43
AD34 VSS[28] VSS[107] AN31 BC48 VSS[192] VSS[292] P47
AD36 VSS[29] VSS[108] AP12 BD46 VSS[193] VSS[293] P7
C AD37 VSS[30] VSS[109] AP19 BD5 VSS[194] VSS[294] R2 C
AD38 VSS[31] VSS[110] AP28 BE22 VSS[195] VSS[295] R48
AD39 VSS[32] VSS[111] AP30 BE26 VSS[196] VSS[296] T12
AD4 VSS[33] VSS[112] AP32 BE40 VSS[197] VSS[297] T31
AD40 VSS[34] VSS[113] AP38 BF10 VSS[198] VSS[298] T37
AD42 VSS[35] VSS[114] AP4 BF12 VSS[199] VSS[299] T4
AD43 VSS[36] VSS[115] AP42 BF16 VSS[200] VSS[300] W34
AD45 VSS[37] VSS[116] AP46 BF20 VSS[201] VSS[301] T46
AD46 VSS[38] VSS[117] AP8 BF22 VSS[202] VSS[302] T47
AD8 VSS[39] VSS[118] AR2 BF24 VSS[203] VSS[303] T8
AE2 VSS[40] VSS[119] AR48 BF26 VSS[204] VSS[304] V11
AE3 VSS[41] VSS[120] AT11 BF28 VSS[205] VSS[305] V17
AF10 VSS[42] VSS[121] AT13 BD3 VSS[206] VSS[306] V26
AF12 VSS[43] VSS[122] AT18 BF30 VSS[207] VSS[307] V27
AD14 VSS[44] VSS[123] AT22 BF38 VSS[208] VSS[308] V29
AD16 VSS[45] VSS[124] AT26 BF40 VSS[209] VSS[309] V31
AF16 VSS[46] VSS[125] AT28 BF8 VSS[210] VSS[310] V36
AF19 VSS[47] VSS[126] AT30 BG17 VSS[211] VSS[311] V39
AF24 VSS[48] VSS[127] AT32 BG21 VSS[212] VSS[312] V43
AF26 VSS[49] VSS[128] AT34 BG33 VSS[213] VSS[313] V7
AF27 VSS[50] VSS[129] AT39 BG44 VSS[214] VSS[314] W17
AF29 VSS[51] VSS[130] AT42 BG8 VSS[215] VSS[315] W19
AF31 VSS[52] VSS[131] AT46 BH11 VSS[216] VSS[316] W2
AF38 VSS[53] VSS[132] AT7 BH15 VSS[217] VSS[317] W27
AF4 VSS[54] VSS[133] AU24 BH17 VSS[218] VSS[318] W48
AF42 VSS[55] VSS[134] AU30 BH19 VSS[219] VSS[319] Y12
AF46 VSS[56] VSS[135] AV16 H10 VSS[220] VSS[320] Y38
AF5 VSS[57] VSS[136] AV20 BH27 VSS[221] VSS[321] Y4
AF7 VSS[58] VSS[137] AV24 BH31 VSS[222] VSS[322] Y42
AF8 VSS[59] VSS[138] AV30 BH33 VSS[223] VSS[323] Y46
AG19 VSS[60] VSS[139] AV38 BH35 VSS[224] VSS[324] Y8
AG2 VSS[61] VSS[140] AV4 BH39 VSS[225] VSS[325] BG29
B AG31 VSS[62] VSS[141] AV43 BH43 VSS[226] VSS[328] N24 B
AG48 VSS[63] VSS[142] AV8 BH7 VSS[227] VSS[329] AJ3
AH11 VSS[64] VSS[143] AW14 D3 VSS[228] VSS[330] AD47
AH3 VSS[65] VSS[144] AW18 D12 VSS[229] VSS[331] B43
AH36 VSS[66] VSS[145] AW2 D16 VSS[230] VSS[333] BE10
AH39 VSS[67] VSS[146] AW22 D18 VSS[231] VSS[334] BG41
AH40 VSS[68] VSS[147] AW26 D22 VSS[232] VSS[335] G14
AH42 VSS[69] VSS[148] AW28 D24 VSS[233] VSS[337] H16
AH46 VSS[70] VSS[149] AW32 D26 VSS[234] VSS[338] T36
AH7 VSS[71] VSS[150] AW34 D30 VSS[235] VSS[340] BG22
AJ19 VSS[72] VSS[151] AW36 D32 VSS[236] VSS[342] BG24
AJ21 VSS[73] VSS[152] AW40 D34 VSS[237] VSS[343] C22
AJ24 VSS[74] VSS[153] AW48 D38 VSS[238] VSS[344] AP13
AJ33 VSS[75] VSS[154] AV11 D42 VSS[239] VSS[345] M14
AJ34 VSS[76] VSS[155] AY12 D8 VSS[240] VSS[346] AP3
AK12 VSS[77] VSS[156] AY22 E18 VSS[241] VSS[347] AP1
AK3 VSS[78] VSS[157] AY28 E26 VSS[242] VSS[348] BE16
VSS[79] VSS[158] G18 VSS[243] VSS[349] BC16
PANTHER-POINT_FCBGA989 G20 VSS[244] VSS[350] BG28
G26 VSS[245] VSS[351] BJ28
G28 VSS[246] VSS[352]
G36 VSS[247]
G48 VSS[248]
H12 VSS[249]
H18 VSS[250]
H22 VSS[251]
H24 VSS[252]
H26 VSS[253]
H30 VSS[254]
H32 VSS[255]
H34 VSS[256]
F3 VSS[257]
A VSS[258] A
PANTHER-POINT_FCBGA989
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (8/8) VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom VBL30/31 LA-9351P M/B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, July 16, 2012 Sheet 26 of 50
5 4 3 2 1
5 4 3 2 1
+5VS
1
@ @ D58 +CRT_VCC_R +CRT_VCC
2 F3 40mil
D29 D30 1 1 2
3 RB491D_SOT23-3 1
PESD5V0U2BT_SOT23-3 PESD5V0U2BT_SOT23-3 1.1A_6V_MINISMDC110F-2
C679
0.1U_0402_16V4Z
2
If=1A 2
D D
L18
RH313 2 1 0_0402_5% CRT_R 1 2 CRT_R_L
<21> PCH_CRT_R
NBQ100505T-800Y_0402
<21> PCH_CRT_G
RH314 2 1 0_0402_5% CRT_G
L19
1 2 CRT_G_L CRT CONNECTOR
NBQ100505T-800Y_0402
L20
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
RH315 2 1 0_0402_5% CRT_B 1 2 CRT_B_L JCRT
<21> PCH_CRT_B
2.2P_0402_50V8C
2.2P_0402_50V8C
NBQ100505T-800Y_0402 6
T264 PAD CRT11 11 RGND
1 1 1 1 1 1 ID0
150_0402_1%
150_0402_1%
150_0402_1%
C683 CRT_R_L 1
Red
1
1
C680 C681 C682 C684 C685 7
R672 R671 R670 CRT_DDC_DAT 12 GGND
2 2 2 2 2 2 CRT_G_L 2 SDA
8 Green
HSYNC 13 BGND
2
2
CRT_B_L 3 Hsync
40mil Blue
+CRT_VCC 9
VSYNC 14 +5V
T265 PAD CRT12 4 Vsync
10 res
CRT_DDC_CK 15 SGND
5 SCL
GND
C +3VS +CRT_VCC 16 C
17 GND
GND
SUYIN_070546FR015S293ZR
2
R678 CONN@
R677
4.7K_0402_5%
4.7K_0402_5%
1
1
2
Q157A
<21> PCH_CRT_DATA RH304 2 1 0_0402_5% CRT_DAT_R 1 6 CRT_DDC_DAT
5
2N7002DW-T/R7_SOT363-6
B B
+CRT_VCC
R1436 10K_0402_5%
1 2 2 1
C686
5
1
0.1U_0402_16V4Z
OE#
P
U38
SN74AHCT1G125GW_SOT353-5
3
1 2 +CRT_VCC
C851
5
1
0.1U_0402_16V4Z
OE#
P
U39
10P_0402_50V8J
10P_0402_50V8J
SN74AHCT1G125GW_SOT353-5
3
1 1
@ C687 @ C688
2 2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VBL30/31 LA-9351P M/B
Date: Monday, July 16, 2012 Sheet 27 of 50
5 4 3 2 1
5 4 3 2 1
R1440
0_0402_5%
1 2 LCD_BL_PWM 2 1 +3VS W=60mils
<21> PCH_BL_PWM
R1438 4.7K_0402_5% R621
1 2 150_0402_1% 1
<36> INVT_PWM
1
0_0402_5% @ R1441 1 1
R627 C908 C671
D C958 4.7K_0402_5% 0.1U_0402_16V4Z 4.7U_0603_6.3V6K D
6
2
180P_0402_50V8J
2 2
R623
3
Q9A S Q26
2N7002DW-T/R7_SOT363-6 2 2 1 2 AP2301GN-HF_SOT23-3
G
R103 100K_0402_5% D
1
33_0402_5% +LCD_VDD
BKOFF# 1 2 BKOFF#_R W=60mils
<36> BKOFF#
3
1 1
1
C673
R1421 C672 0.1U_0402_16V4Z
10K_0402_5% 5 Q9B 4.7U_0603_6.3V6K
<21> PCH_ENVDD 2 2
2 2N7002DW-T/R7_SOT363-6
4
2
R91
100K_0402_5%
1
C C
+5VS +LCD_INV
+5VS B+
1.5A L23
2 1
1
2 FBMA-L11-201209-221LMA30T_0805
C909 1 1 1
@ R628 0.1U_0402_16V7K @
100K_0402_5% C692 C319 @ C400
3
1
S
68P_0402_50V8J 0.1U_0402_25V4K 680P_0402_50V7K
2
1 @ 2CAMPWR_EN# 2
G
Q20 2 2 2
R624 47K_0402_5% AO3413_SOT23
D
1
D Q61
CAMPWR_EN 2 @ 1 2
W=30mils C911
<36> CAMPWR_EN
R1403 0_0402_5% G 2N7002_SOT23-3 +LVDS_CAM 47P_0402_50V8J
W=30mils
1
S@ 1 2 +LVDS_CAM
3
R1422 1
C699
0.1U_0402_16V4Z
10K_0402_5%
@ @ @ R1427 0_0603_5%
B +3VS 2 1 B
2
2 JLVDS
+5VS R1426 2 1 0_0603_5% 2 1
USB20_P10_R 4 2 1 3 PCH_TXCLK+
4 3 PCH_TXCLK+ <21>
USB20_N10_R 6 5 PCH_TXCLK-
6 5 PCH_TXCLK- <21>
8 7
PCH_TXOUT0+ 10 8 7 9
<21> PCH_TXOUT0+ 10 9
PCH_TXOUT0- 12 11
<21> PCH_TXOUT0- 12 11
PCH_TXOUT1+ 14 13
<21> PCH_TXOUT1+ 14 13
PCH_TXOUT1- 16 15 PCH_EDID_CLK PCH_EDID_CLK <21>
<21> PCH_TXOUT1- 16 15
PCH_TXOUT2+ 18 17 PCH_EDID_DAT
<21> PCH_TXOUT2+ 18 17 PCH_EDID_DATA <21>
PCH_TXOUT2- 20 19
<21> PCH_TXOUT2- 20 19
22 21 CE_EN_R 1 @ 2 CE_EN
22 21 CE_EN <23>
24 23 R1831 2
1K_0402_5%
R6 0_0402_5% 26 24 23 25 LCD_BL_PWM R1442 0_0402_5%
1 2 28 26 25 27
28 27 +3VS
30 29 1 1
30 29
1
C399
0.1U_0402_16V4Z
C691
0.1U_0402_16V4Z
R1191
100K_0402_5%
L4 32 31 +LCD_VDD
1 2 USB20_P10_R 34 32 31 33 BKOFF#_R
<22> USB20_P10 1 2 34 33
R143 100_0402_1% 36 35 @
@ 2 @ 1 38 36 35 37 2 2
38 37 +LCD_INV
4 3 USB20_N10_R +LCD_INV 40 39 +LCD_INV
<22> USB20_N10
2
4 3 42 40 39 41
WCM-2012-900T_0805 GND GMD
1 2 ACES_87242-4001-09
R7 0_0402_5% CONN@
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VBL30/31 LA-9351P M/B
Date: Monday, July 16, 2012 Sheet 28 of 50
5 4 3 2 1
5 4 3 2 1
+5VS
+3VS
2
1
2
R980 @ C431 BAV99_SOT23-3
1M_0402_5% Q74 1000P_0402_50V7K D34
0.1U_0402_16V7K 2 1 C430 VGA_DVI_TXC+ 1 @ 2 R164 HDMI_R_CK+ 2
<21> PCH_HDMI_TXC+
1
2
G
0_0402_5% 2N7002H_SOT23-3
1
D L9 D
4 3 3 1 HDMI_HPD
4 3 <21> PCH_HDMI_HPD
D
1 2
1 2
2
WCM-2012-121T_0805 R981
0.1U_0402_16V7K 2 1 C378 VGA_DVI_TXC- 1 @ 2 R166 HDMI_R_CK- 20K_0402_5%
<21> PCH_HDMI_TXC-
0_0402_5%
1
0.1U_0402_16V7K 2 1 C455 VGA_DVI_TXD0+ 1 @ 2 R167 HDMI_R_D0+
<21> PCH_HDMI_TX0+
0_0402_5%
L10
4 3
4 3
1 2 +HDMI_5V_OUT
1 2
WCM-2012-121T_0805 +3VS
0.1U_0402_16V7K 2 1 C377 VGA_DVI_TXD0- 1 @ 2 R172 HDMI_R_D0-
<21> PCH_HDMI_TX0-
1
1
0_0402_5%
R1329 R1328
2
2.2K_0402_5% 2.2K_0402_5%
G
0.1U_0402_16V7K 2 1 C376 VGA_DVI_TXD1+ 1 @ 2 R173 HDMI_R_D1+
<21> PCH_HDMI_TX1+
2
2
0_0402_5% <21> PCH_HDMI_CLK 3 1 HDMI_SCLK
L11
2
S G
D
4 3 BSH111_SOT23-3 Q182
C
4 3 BSH111_SOT23-3 C
Q183
1 2 <21> PCH_HDMI_DATA 3 1 HDMI_SDATA
1 2
D
WCM-2012-121T_0805
0.1U_0402_16V7K 2 1 C434 VGA_DVI_TXD1- 1 @ 2 R176 HDMI_R_D1-
<21> PCH_HDMI_TX1-
0_0402_5%
@
0.1U_0402_16V7K 2 1 C456 VGA_DVI_TXD2+ 1 2 R177 HDMI_R_D2+
<21> PCH_HDMI_TX2+
0_0402_5%
L12
4 3
4 3
1 2
1 2
WCM-2012-121T_0805 +5VS_HDMI
0.1U_0402_16V7K 2 1 C432 VGA_DVI_TXD2- 1 @ 2 R178 HDMI_R_D2-
<21> PCH_HDMI_TX2-
0_0402_5% 40mil
1.1A_6V_MINISMDC110F-2
RB161M-20_SOD123-2 D53 F2
+5VS 2 1 2 1 +HDMI_5V_OUT
1
C250
0.1U_0402_16V4Z
2
B B
HDMI_R_CK+ 1 2
HDMI_R_CK-
R690
1 2
680 +-5% 0402
HDMI Connector
R691 680 +-5% 0402
HDMI_R_D1- 1 2 JHDMI
R692 680 +-5% 0402 HDMI_HPD 19
HDMI_R_D1+ 1 2 18 HP_DET
+HDMI_5V_OUT +5V
R693 680 +-5% 0402 17
HDMI_R_D0- 1 2 HDMI_SDATA 16 DDC/CEC_GND
R694 680 +-5% 0402 HDMI_SCLK 15 SDA
HDMI_R_D0+ 1 2 14 SCL
R695 680 +-5% 0402 13 Reserved
HDMI_R_D2+ 1 2 HDMI_R_CK- 12 CEC 20
R696 680 +-5% 0402 11 CK- GND 21
HDMI_R_D2- 1 2 HDMI_R_CK+ 10 CK_shield GND 22
R697 680 +-5% 0402 HDMI_R_D0- 9 CK+ GND 23
D0- GND
1
D 8
2 Q2 HDMI_R_D0+ 7 D0_shield
+5VS D0+
G 2N7002_SOT23-3 HDMI_R_D1- 6
5 D1-
S
3
1 2 HDMI_R_D1+ 4 D1_shield
R698 100K_0402_5% HDMI_R_D2- 3 D1+
2 D2-
HDMI_R_D2+ 1 D2_shield
1 D2+
SUYIN_100042MR019S153ZL
A A
C266 CONN@
2 0.1U_0402_16V4Z
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI Connector
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VBL30/31 LA-9351P M/B
Date: Monday, July 16, 2012 Sheet 29 of 50
5 4 3 2 1
5 4 3 2 1
JODD1
JHDD1 1
GND 2 SATA_PTX_C_DRX_P2 C518 1 2 0.01U_0402_25V7K
A+ SATA_PTX_DRX_P2 <19>
1 3 SATA_PTX_C_DRX_N2 C519 1 2 0.01U_0402_25V7K
GND A- SATA_PTX_DRX_N2 <19>
2 SATA_PTX_C_DRX_P0 C512 1 2 0.01U_0402_25V7K 4
A+ SATA_PTX_DRX_P0 <19> GND
3 SATA_PTX_C_DRX_N0 C513 1 2 0.01U_0402_25V7K 5 SATA_PRX_DTX_N2 C424 1 2 0.01U_0402_25V7K
A- SATA_PTX_DRX_N0 <19> B- SATA_PRX_C_DTX_N2 <19>
4 6 SATA_PRX_DTX_P2 C425 1 2 0.01U_0402_25V7K
GND B+ SATA_PRX_C_DTX_P2 <19>
5 SATA_PRX_DTX_N0 C410 1 2 0.01U_0402_25V7K 7
B- SATA_PRX_C_DTX_N0 <19> GND
6 SATA_PRX_DTX_P0 C412 1 2 0.01U_0402_25V7K
B+ SATA_PRX_C_DTX_P0 <19>
7
GND 8 ODD_DETECT#_R 0_0402_5% 2 1 R762
DP ODD_DETECT# <23>
C 9 +5VS_ODD +5VS_ODD C
8 +5V 10
V33 9 +5V 11 ODD_DA#_R 0_0402_5% 2 1 R763
V33 MD ODD_DA# <22>
10 15 12
V33 11 14 GND GND 13
GND 12 GND GND
GND J6
13
GND 14 1 2 SANTA_204901-1
V5 +5VS
15 CONN@
V5 16 @
V5 17 PAD-OPEN 2x2m
GND 18
Reserved 19
GND 20
24 V12 21
23 GND V12 22
GND V12
C-H_13-22202201CP_22P
CONN@
+5VS +5VS_ODD
B R107 B
0_0805_5%
+VSB 1 2
D
6
S
2
1 5 4
1U_0402_6.3V6K
CS27
R760 2
470K_0402_5% @ 1 Q55
@ SI3456BDV-T1-E3 1N TSOP6
G
2 @
3
ODD_EN
2
D
1.5M_0402_5%
R764
0.1U_0402_16V4Z
C818
1
2 Q59
<23> ODD_EN#
G SSM3K7002FU_SC70-3 @
@ S @
3
2
1
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SATA-HDD/ODD
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VBL30/31 LA-9351P M/B
Date: Monday, July 16, 2012 Sheet 30 of 50
5 4 3 2 1
A B C D E
Q5513 25MHZ_10PF_7V25000014
YL2
S
3 1 RL21 MCT4
0_0402_5%
AO3413_SOT23 2 2 LAN_X1 1 3 LAN_X2 MCT3
1 3
G
2
LSE-200NX3216TRLF_1206-2
LSE-200NX3216TRLF_1206-2
LSE-200NX3216TRLF_1206-2
LSE-200NX3216TRLF_1206-2
0.1U_0402_25V6
2
2
DL5
DL6
DL8
DL7
@ @ @ @
1
DL36 DL35
3 LAN_MDI1+ 1
I/O1 I/O3
4 LAN_MDI0+
+3V_LAN
LAN_MDI2+ 1
I/O1 I/O3
4 LAN_MDI3+
+3V_LAN LAN_GND
LAN Conn. 3
1
SUPERWORLD_SWG150401
CL35 Security Classification Compal Secret Data Compal Electronics, Inc.
Place CL34 colse 0.1U_0402_25V4K RJ45_GND 2012/06/01 2011/05/17 Title
2 Issued Date Deciphered Date
to LAN chip
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RTL8111F
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VBL30/31 LA-9351P M/B
Date: Monday, July 16, 2012 Sheet 31 of 50
A B C D E
5 4 3 2 1
+5VALW
Slot 1 Half PCIe Mini Card-WLAN & BT3.0 C754 W=60mils
RH124
Function Board 0.1U_0402_16V4Z
2 @1
U25
+USB_VCCA
WLAN/ WiFi 1 8
<31,36> EC_PME# +1.5VS +3VS GND VOUT
@ 0_0402_5% 2 7
JWLAN R149 0_0402_5% 3 VIN VOUT 6
EC_SWI# 1 2 WLAN_WAKE 1 2 1 @ 2 4 VIN VOUT 5 1 2
<21,31> EC_SWI# 1 2 <33,36> USB_EN# EN FLG USB_OC5# <22>
RH121 0_0402_5% 3 4 1 R422 0_0402_5%
5 3 4 6 L54 RT9715BGS_SO8
<36> BT_PWRON 5 6
7 8 <22> USB20_N8 1 2 C438
<20> CLKREQ_WLAN# 7 8 1 2
9 10 USB20_N8_R 4.7U_0805_10V4Z
11 9 10 12 USB20_P8_R 2@
D <20> CLK_WLAN# D
13 11 12 14 4 3
<20> CLK_WLAN 13 14 <22> USB20_P8 4 3
15 16
17 15 16 18 WCM-2012-900T_0805
19 17 18 20
19 20 WL_OFF# <36>
21 22 PLT_RST# 1 @ 2
21 22 PLT_RST# <6,22,31,36>
23 24 R148 0_0402_5%
<20> PCIE_PRX_WLANTX_N2 23 24
25 26
<20> PCIE_PRX_WLANTX_P2 25 26
27 28 JFT
29 27 28 30 R137 0_0402_5% +USB_VCCA
29 30 PM_SMBCLK <11,12,20>
31 32 PM_SMBDATA <11,12,20> 1 @ 2
<20> PCIE_PTX_C_WLANRX_N2 31 32 22
33 34 W=60mils
<20> PCIE_PTX_C_WLANRX_P2 33 34 21
35 36 USB20_N2 <22> L53
37 35 36 38 1 2 USB20_N9_R 20
39 37 38 40
USB20_P2 <22> Bluetooth 3.0 <22> USB20_N9 1 2 19
+3VS 39 40 18
41 42
43 41 42 44 4 3 USB20_P9_R 17
43 44 <22> USB20_P9 4 3 16
R1430 45 46 USB20_N8_R
0_0402_5% 47 45 46 48 WCM-2012-900T_0805 USB20_P8_R 15
1 2 49 47 48 50 14
<36> E51_TXD 49 50 13
1 2 51 52 1 @ 2
<36> E51_RXD 51 52 12
R127 0_0402_5% USB20_N9_R
R1431 53 54 USB20_P9_R 11
0_0402_5% GND1 GND2 10
Debug card using 9
ACES_88910-5204 8
<34> HP_L 7
1
<34> HP_R 6
100K_0402_5% CONN@ 5
MIC1_L
C R1315 HeadPhone/LINE Out JACK <34>
<34>
MIC1_L
MIC1_R
MIC1_R 4
3
C
<34> NBA_PLUG
2
2
+3VS +1.5VS <34> MIC_SENSE 1
0.1U_0402_16V4Z 0.1U_0402_16V4Z
Ext.MIC/LINE IN JACK ACES_85201-2005N
1 1 1 1
1
1 CONN@
CM17 CM18 CM19 CM20 CM21 CM22
2
2 2 2 2
47P_0402_50V8J 4.7U_0805_10V4Z 47P_0402_50V8J 4.7U_0805_10V4Z
For SED request For SED request
+3VS
B B
1 1 1 1 1 1 1
EMI DEMAND
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WLAN/USB
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VBL30/31 LA-9351P M/B
Date: Monday, July 16, 2012 Sheet 32 of 50
5 4 3 2 1
5 4 3 2 1
Card Reader
CC11
1U_0402_6.3V6K Layout note:
2 1 U1 Close to U1 < 3 in 1 Card Reader >
25
CC4 Thermal pad JREAD
D 1U_0402_6.3V6K 24 RC24 1 SDWP_MSCLK_R D
2 1 6 V18 0_0402_5% SD-WP 2 SD_DATA1
SDREG 8 SD_WP/MS_CLK 2 1SDWP_MSCLK_R SD-DAT1 3 SD_DATA0
MS_CLK/SD_WP/SP1 1 SD-DAT0
17 9 MSCD# 4
23 GPIO0 MS_INS#/SP2 10 SD_DATA1 CC10 SD-GND 5
7 XD_D7 SD_D1/SP3 11 SD_DATA0 MS-GND 6 MSBS
XD_CD# SD_D0/SP4 5P_0402_50V8C MS-BS
12 MS_DATA3_SD_DATA7 2 7 MS_DATA2_SDCLK_R +VCC_3IN1
MS_D3/SP5 @ SD-CLK
450mA/ 30mil 13 SDCD# R4 8 MS_DATA1_SD_DATA3
5 SD_CD#/SP6 14 0_0402_5% MS-DAT1 9 MS_DATA0_SD_DATA5
+VCC_3IN1 CARD_3V3 SP7 MS-DAT0
+3VS_CR 4 15 MS_DATA2_SDCLK 2 1 MS_DATA2_SDCLK_R
1 10
3V3_IN MS_D2/SD_CLK/SP8 16 MS_DATA0_SD_DATA5 SD-VCC 11
MS_D0/SP9 18 SDCMD CC9 MS-DAT2 12
SD_CMD/SP10 SD-GND 1 1
USB20_P11 3 19 5P_0402_50V8C 13 MSCD# CC6
<22> USB20_P11 USB20_N11 2 DP SP11 20 MS_DATA1_SD_DATA3 2 MS-INS 14 MS_DATA3_SD_DATA7 CC7
<22> USB20_N11 DM MS_D1/SD_D3/SP12 @ MS-DAT3
21 SD_DATA2_MS_DATA5 15 SDCMD 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
SD_D2/SP13 22 MSBS SD-CMD 16 2 2
1 MS_BS/SP14 MS-SCLK 17
RREF MS-VCC
2
+3VS_CR 18
R3 SD-DAT3 19
1 2 6.19K_0402_1% 22 MS-GND 20 SD_DATA2_MS_DATA5
+3VS GND1 SD-DAT2
RC5 0_0603_5% RTS5129-GR_QFN24_4X4 23 21 SDCD#
GND2 SD-CD
1
1 1 TAITW_R009-025-LR_NR
CC1 CC3 CONN@
4.7U_0805_10V4Z 0.1U_0402_16V4Z
2 2
C C
USB3.0 Port
+5VALW +USB_VCCB
2.5A
UU1 W=100mils
1 8 <22> USB3_RX0_P RU7 @ 0_0402_5% U3RXDP0_L
GND VOUT
1000P_0402_50V7K
2 7
4.7U_0805_10V4Z
4.7U_0805_10V4Z
0.1U_0402_16V4Z
3 VIN VOUT 6 LU2 WCM-2012-121T_0805
VIN VOUT
CU1
CU4
CU3
CU2
0.1U_0402_16V4Z
4 5 4 3
EN FLG 4 3
CU6
0.1U_0402_16V4Z
G547E2P11U
@ 1 2
1 2
1
@
0.1U_0402_16V4Z
B +USB_VCCB CU11 B
JUSB31 1 2USB3_TX0_P_C RU5 @ 0_0402_5% U3TXDP0_L
<22> USB3_TX0_P
U3TXDP0_L 9
1 SSTX+ 0.1U_0402_16V7K LU1 WCM-2012-121T_0805
VBUS
150U_B2_6.3VM_R35M
U3TXDN0_L 8 4 3
USB20_P0_L 3 SSTX- 4 3
7 D+
1 GND
CU5
USB20_N0_L 2 10 USB30_GND 1 2
+ U3RXDP0_L 6 D- GND 11 USB30_GND 1 2
4 SSRX+ GND 12 USB30_GND CU12
U3RXDN0_L 5 GND GND 13 USB30_GND 1 2USB3_TX0_N_C U3TXDN0_L
2 SSRX- GND <22> USB3_TX0_N
RU4 @ 0_0402_5%
ACON_TARA4-9K1311 0.1U_0402_16V7K
RU2
CONN@ 0_0603_5%
DU1
U3RXDN0_L 1 1 109 U3RXDN0_L
U3RXDP0_L 2 2 98 U3RXDP0_L
USB20_N0 RU9 @ 0_0402_5% USB20_N0_L
<22> USB20_N0
U3TXDN0_L 4 4 77 U3TXDN0_L
DU2
3 4 USB20_P0_L 2 U3TXDP0_L 5 5 66 U3TXDP0_L
3 4 1
USB20_N0_L 3 3 3
2 1
A 2 1 A
YSDA0502C 3P C/A SOT-23 8
LU3 WCM-2012-900T_0805
USB20_P0 USB20_P0_L L15ESDL5V0NA-4 SLP2510P8
<22> USB20_P0
RU8 @ 0_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB-Card Reader-RTS5129
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VBL30/31 LA-9351P M/B
Date: Monday, July 16, 2012 Sheet 33 of 50
5 4 3 2 1
5 4 3 2 1
2
1 1 2 2 2 2
1 1 JA1
2
1 2MIC1_LINE1_R CA8 CA7 JUMP_43X39 10U_0805_10V4Z 10U_0805_10V4Z
CA9 4.7U_0603_6.3V6K 10U_0805_10V4Z 0.1U_0402_16V4Z CA1 CA2 2 1 +1.5VS
2 2
1
MIC1_LINE1_R_R 0.1U_0402_16V4Z 10U_0805_10V4Z @ place close to chip
2 2 RA33 0_0603_5%
1
MIC1_LINE1_R_L 1 2MIC1_LINE1_L place close to chip DVT NOT POP RA12, USE JA1
CA10 4.7U_0603_6.3V6K @ RA12
place close to chip
D +PVDD2 2 1 0.1U_0402_16V4Z +5VS D
+AVDD
1 1 BLM18PG181SN1D_0603 1 1
@ RA3 0.1U_0402_16V4Z CA60 CA59 CA58
68 mA 10U_0805_10V4Z 0.1U_0402_16V4Z 2 1 +5VS CA61 @ @ @
+MIC2_VREFO RA39 0_0603_1%
0_0402_5% U143 2 2 2 2
RA25 CA26 1 1 1 1 10U_0805_10V4Z 10U_0805_10V4Z
1K_0402_5% 1U_0402_6.3V4Z 22 1 CA3 CA4 CA5 CA6
2 1 1 2 MIC2R_R 1 2 MIC2_R 21 MIC1_R DVDD 9
MIC1_L DVDD_IO
RA51 1 2 MIC2R_L 1 2 MIC2_L 17 25 2 2 2 2
4.7K_0402_5%
RA26 CA28
16 MIC2_R
MIC2_L
AVDD1
AVDD2
38 10U_0805_10V4Z 0.1U_0402_16V4Z Speaker Connector
1K_0402_5% 1U_0402_6.3V4Z +MIC1_VREFO_L 31 39 +PVDD1 place close to chip placement near Audio Codec
CONN@ 30 MIC1_VREFO_L PVDD1 46 +PVDD2
+MIC1_VREFO_R MIC1_VREFO_R PVDD2
MIC1 +MIC2_VREFO 29 RA13
MIC 1 MIC2_VREFO SPKL- 2 1 SPK_L-
DA10 2 1 15 45 SPKR+ 0_0603_1%
2 LINE2_R SPK_OUT_R+ 1
2 14 44 SPKR-
LINE2_L SPK_OUT_R-
1U_0603_10V6K
1 3 CA19 DA8
GND
CA42
3 4 @ 10U_0805_10V4Z 1 2
GND 20 40 SPKL+ 2 @ 1
PESD5V0U2BT_SOT23-3 ACES_88231-02001 MONO_OUT SPK_OUT_L+ 41 SPKL- 3
SPK_OUT_L- 1
1 2 MONO_IN 12
CA12 100P_0402_50V8J PCBEEP_IN CA46 2 PESD5V0U2BT_SOT23-3
AZ_SYNC_HD 10 33 RA4 75_0402_1% RA14 @ 10U_0805_10V4Z JSPK
<19> AZ_SYNC_HD SYNC HPOUT_R HP_R <32> 2
32 RA5 75_0402_1% SPKL+ 2 1 SPK_L+ SPK_L+ 1
HPOUT_L HP_L <32> 1
11 0_0603_1% SPK_L- 2
<19> AZ_RST_HD# RESET# 2
RA15 SPK_R+ 3
C 5 AZ_SDOUT_HD SPKR- 2 1 SPK_R- SPK_R- 4 3 C
SDATA_OUT AZ_SDOUT_HD <19> 4
8 AZ_SDIN0_HD_R 2 1 0_0603_1% 1
SDATA_IN AZ_SDIN0_HD <19> DA9
20K_0402_1% 1 RA10 2AC_JDREF 19 RA6 33_0402_5%
JDREF
1U_0603_10V6K
CA35 2 110U_0805_10V4Z28 6 AZ_BITCLK_HD CA51 2 ACES_85204-0400N
LDO_CAP BITCLK AZ_BITCLK_HD <19>
CA45
AC_VREF 27 @ 10U_0805_10V4Z 1 1
2.2U_0603_6.3V4Z 2 1CA14 CPVEE 34 VREF 2 @ 3
CPVEE CONN@
1 2 35 24 @ @ 1
CBN NC RA7 CA23
2 1 CA16 36 23 PESD5V0U2BT_SOT23-3
CA17 2.2U_0603_6.3V4Z CBP NC 48 CA39 2
2.2U_0603_6.3V4Z CA18 NC RA44 @ 10U_0805_10V4Z
2 10_0402_5% 10P_0402_50V8J SPKR+ 2 1 2 SPK_R+
1 2 3 GPIO0/DMIC_DATA 26 0_0603_1%
0.1U_0402_16V4Z GPIO1/DMIC_CLK AVSS1 37
Close to Audio Chip
AVSS2 42 AGND
SENSE_A 13 PVSS1 43
place close to chip SENSE_A PVSS2
18 7
SENSE_B DVSS DGND
EAPD 47
<36> EAPD EAPD
EC_MUTE# 4 49
<36> EC_MUTE# PD# THERMAL_PAD
ALC259-VB5-GR_QFN48_7X7
Ext.MIC/LINE IN JACK
CA47 1 2 0.1U_0603_50V7K RA47 2 RA48 1 +MIC1_VREFO_R
1K_0402_5% 4.7K_0402_5%
B RA49 CA48 1 2 0.1U_0603_50V7K MIC1_LINE1_R_R 2 1 B
MIC1_R <32>
1K_0402_5%
EC_MUTE# 2 1 +3VS_DVDD CA49 1 2 0.1U_0603_50V7K
@ MIC1_LINE1_R_L 2 1
MIC1_L <32>
CA50 1 2 0.1U_0603_50V7K 1K_0402_5%
RA45 2 RA46 1 +MIC1_VREFO_L
1 2 4.7K_0402_5%
RA43 0_0603_5%
1
RA16 39.2K_0402_1% 1
5.1K PORT-D (PIN 35, 36) SPK out RA11 CA20
A A
10K_0402_5% 0.1U_0402_16V4Z
2
39.2K PORT-E (PIN 14, 15)
2
20K PORT-F (PIN 16, 17) Int. MIC
SENSE B Security Classification Compal Secret Data Compal Electronics, Inc.
10K PORT-H (PIN 37) Issued Date 2012/06/01 Deciphered Date 2013/05/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD CODEC ALC259
5.1K PORT-I (PIN 32, 33) Size Document Number Rev
Headphone out AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VBL30/31 LA-9351P M/B
Date: Monday, July 16, 2012 Sheet 34 of 50
5 4 3 2 1
5 4 3 2 1
For EMC
KEYBOARD CONN.
KSO10 1 2
C803 100P_0402_50V8J
KSO11 1 2
C804 100P_0402_50V8J JKB
KSO12 1 2 1 KSI1
C805 100P_0402_50V8J 1 2 KSI7
KSO15 1 2 2 3 KSI6
C807 100P_0402_50V8J 3 4 KSO9
KSI7 1 2 4 5 KSI4
D D
C808 100P_0402_50V8J 5 6 KSI5
KSI2 1 2 6 7 KSO0
C810 100P_0402_50V8J 7 8 KSI2
KSI3 1 2 8 9 KSI3
C811 100P_0402_50V8J 9 10 KSO5
KSI4 1 2 10 11 KSO1
C812 100P_0402_50V8J 11 12 KSI0
KSI0 1 2 12 13 KSO2
C813 100P_0402_50V8J 13 14 KSO4
KSI5 1 2 14 15 KSO7
C814 100P_0402_50V8J 15 16 KSO8
KSI6 1 2 16 17 KSO6
C815 100P_0402_50V8J 17 18 KSO3
KSI1 1 2 18 19 KSO12
C816 100P_0402_50V8J 19 20 KSO13
KSO2 1 2 20 21 KSO14
C793 100P_0402_50V8J 21 22 KSO11
KSO1 1 2 22 23 KSO10
C790 100P_0402_50V8J 23 24 KSO15
KSO0 1 2 24 25
C791 100P_0402_50V8J 25 26
KSO4 1 2 27 26
C792 100P_0402_50V8J 28 GND2
KSO3 1 2 GND1
C795 100P_0402_50V8J
KSO5 1 2 E&T_6916-Q26N-00R
C796 100P_0402_50V8J CONN@
KSO14 1 2
C
KSO6
C797
1
100P_0402_50V8J
2
13.3" and 14" C
C798 100P_0402_50V8J
KSO7 1 2
C799 100P_0402_50V8J
KSO13 1 2
C800 100P_0402_50V8J
KSO8 1 2
C801 100P_0402_50V8J
KSO9 1 2 KSI[0..7]
KSI[0..7] <36>
C802 100P_0402_50V8J
KSO[0..15]
KSO[0..15] <36>
Screw Hole
Lid SW
H2 H3 H4 H5 H6 H7 H1
1
+3VALW +3VL
@ @ @ @ @ @ @
H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0
B R142 B
0_0402_5% 0_0402_5%
@
R144
U34
APX9132ATI-TRL_SOT23-3
2 3
Break hole CPU JWLAN VGA
GND
C645 C647
1
0.1U_0402_16V4Z 0.1U_0402_16V4Z
1
1
2 2
@ @ @ @ @
@ @ @ H_4P5 H_4P5 H_4P5 H_4P5 H_3P0X3P5N @ @
H_3P0 H_3P0 H_3P0 H_4P2 H_4P2
1
@ @ @ @
A @ A
1
1
H_3P3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB/PAD/ISPD/LID/ECROM
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VBL30/31 LA-9351P M/B
Date: Monday, July 16, 2012 Sheet 35 of 50
5 4 3 2 1
5 4 3 2 1
+3VS
+3VALW_EC +3VL +3VALW_EC +EC_VCCA
+3VL @ LE1 @
R746 C4907 PCH_HOT#_R R730 1 2 10K_0402_5%
0_0805_5% 1 2 ECAGND
ECAGND <40>
+3VALW 0.1U_0402_16V4Z 0.1U_0402_16V4Z FBMA-L11-160808-800LMT_0603 BKOFF# R724 1 2 10K_0402_5%
R748 1 1 C771 1 1 2 2 0.1U_0402_16V4Z @ +5VS
0_0805_5% <BOM Structure>C770 R740 4.7K_0402_5%
C772 C773 C774 C775 TP_CLK 1 2
1000P_0402_50V7K1000P_0402_50V7K
2 2 2 2 1 1 TP_DATA 1 2
111
125
0.1U_0402_16V4Z 0.1U_0402_16V4Z R741 4.7K_0402_5%
22
33
96
67
UE1
9
KB9012@ WL_OFF# R725 1 2 10K_0402_5% +3VL
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
EC_VDD/VCC
EC_VDD/AVCC
LID_SW# R1215 1 @ 2 10K_0402_5%
D D
For DS3 +3VALW
CLK_PCI_EC GATEA20 1 21
<23> GATEA20 GATEA20/GPIO00 GPIO0F DRAMRST_CNTRL_EC <7>
KB_RST# 2 23 EC_BEEP# LID_SW# R1210 1 2 10K_0402_5%
<23> KB_RST# KBRST#/GPIO01 BEEP#/GPIO10 EC_BEEP# <34>
1
SERIRQ 3 26 LAN_PWR_EN#
<19> SERIRQ SERIRQ GPIO12 LAN_PWR_EN# <31>
R738 LPC_FRAME# 4 27 Board_ID 1 2
<19> LPC_FRAME# LPC_FRAME# ACOFF/GPIO13
@ 10_0402_5% LPC_AD3 5 Ra 100K_0402_5%
<19> LPC_AD3 LPC_AD3
LPC_AD2 7 PWM Output 2 1
<19> LPC_AD2 LPC_AD2
LPC_AD1 8 63 BATT_TEMPA R774 rev01@ 0_0402_5%
<19> LPC_AD1 BATT_TEMPA <40>
2
close U43
C782
R757 100K_0402_5% 4.7U_0805_10V4Z
KB9012QF A3 LQFP 128P
11
24
35
94
113
69
1 2 20mil
C783 20P_0402_50V8
LE2 +3VL
ECAGND 2 1
FBMA-L11-160808-800LMT_0603
reserve for ENE_CS board VR_HOT# 2 1
<47> VR_HOT#
R742 330K_0402_5%
+3VS
0.1U_0402_16V4Z
R749
R4936 0_0402_5%
CRY1 1 2CRY2
@
C4917
@ 20M_0603_5% D64
EC_ACIN 2 1
ACIN <14,21,41>
CH751H-40PT_SOD323-2
1 1
5
@ C784 C785
1
A @ U4902 A
P
15P_0402_50V8J
15P_0402_50V8J
OSC
2 2 Y A
NC
SN74LVC1G06DCKR_SC70-5
1 R4929
1
100K_0402_5%
NC
NC
C4916
47P_0402_50V8J Security Classification Compal Secret Data Compal Electronics, Inc.
2
2
Y5 @ 2012/06/01 2013/05/12 Title
32.768KHZ_12.5PF_Q13MC14610002
Issued Date Deciphered Date
ENE-KB9012
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
UE1 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
NPCE885NA0DX LQFP 128P 0.1
Nuvton@
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VBL30/31 LA-9351P M/B
Date: Monday, July 16, 2012 Sheet 36 of 50
5 4 3 2 1
5 4 3 2 1
33_0402_5% 33_0402_5%
U59 Nuvton@ Nuvton@
WIN8@ SBIOS_SI 5 2 PCH_SPI_MISO_R
<19> PCH_SPI_MOSI SI SO PCH_SPI_MISO <19>
R1550 33_0402_5% R1553 33_0402_5%
WIN8@ SBIOS_CLK 6 WIN8@
<19> PCH_SPI_CLK SCLK
R1551 33_0402_5%
PCH_SPI_CS0#1 2PCH_SPI_CS0_R# 1
<19> PCH_SPI_CS0# CS
R775 KB9012@0_0402_5%
R271 1 2 7 For EMI resuest.
HOLD
3.3K_0402_5%
R221 1 2 3 @ C361 @ R419
WP
3.3K_0402_5% SBIOS_CLK
+3VALW 1 R772 2 8 4
0_0402_5% Nuvton@ VCC GND 6P_0402_25V 10_0402_5%
+3VS 1 R773 2 MX25L3205AZMC-20G_SON8
0_0402_5% KB9012@ C393
0.1U_0402_16V4Z C402 12P_0402_50V8J
P/N: SA00003K800
+3VS +3VALW
2 KB9012@1
R770 1
0_0402_5%
0_0402_5%
R771
Nuvton@
C
BIOS SPI Flash (2MByte*1) For Win8 C
2
+SPI_VCC
C406
U60 WIN8@ WIN8@
PCH_SPI_CS1# 1 R412 2KB9012@ PCH_SPI_CS1_R# 1 8 0.1U_0402_16V4Z
<19> PCH_SPI_CS1# CS# VCC
PCH_SPI_MISO 0_0402_5% SBIOS_SO1 2 7 1 R225 23.3K_0402_5% WIN8@
SO HOLD#
+SPI_VCC R415 WIN8@ 33_0402_5% 1 2 3
WP# SCLK
6 SBIOS_CLK1 R413 33_0402_5% PCH_SPI_CLK
3.3K_0402_5% 4 5 SBIOS_SI1 WIN8@ PCH_SPI_MOSI
R224 GND SI R417 33_0402_5%
MX25L1606EM2I-12G_SO8
6P_0402_25V 10_0402_5%
WIN8@
C403 12P_0402_50V8J
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SBIOS & EC ROM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VBL30/31 LA-9351P M/B
Date: Monday, July 16, 2012 Sheet 37 of 50
5 4 3 2 1
5 4 3 2 1
2
D ACES_88058-060N JTP D
1 D18 D16
1
2
7236LGH
2 1 R154 R156
CONN@ 2
2
3
TP_CLK <36> PJDLC05C_SOT23-3 PJDLC05C_SOT23-3
3 TP_DATA <36>
R152 @ 10K_0603_5% @ 4 LEFT_BTN# 1 1
2 1 100K_0402_5% 100K_0402_5% 4 5 RIGHT_BTN# @ @
5
100P_0402_50V8J
C757
100P_0402_50V8J
C759
R153 @ 10K_0603_5% change conn foot print to 8 pin---0617 6
1
6
%RWWRP6LGH D8 GND
7
8 2 2
1
2 GND
ON/OFFBTN# <36>
ON/OFFBTN#_R 1 ACES_88058-060N
3
CONN@
CHN202UPT SC-70
PWR_ON_LED#
ON/OFFBTN#_R
2
D19
PJDLC05C_SOT23-3
SW7 SW4
SMT1-05-A_4P SMT1-05-A_4P
LEFT_BTN# 3 1 RIGHT_BTN# 3 1
4 2 4 2
5
6
5
6
C @ C
DC-IN LED
D75
1 2 2 1 BLUE PWR_ON_LED# 1A
+5VALW
R778 300_0402_5% 3
HT-110NBQA_BULE_1204
+5VS
FAN Control Circuit
WL&BT LED AMB
D74 2 JFAN
+5VS 1 2 2 1 C863 +FAN1 1
WL_BT_LED# <36> 1
R777 300_0402_5% 10U_0805_10V4Z 2
HT-110UD_1204 1 3 2
2 3
U58
1 8 @ C864 4
2 EN GND 7 1000P_0402_50V7K 5 GND
SATA_LED# +FAN1 3 VIN GND 6 1 GND
HDD LED SATA_LED# <19> VOUT GND
2
B 4 5 ACES_85205-03001 B
<36> EN_DFAN1 VSET GND
2N7002DW-T/R7_SOT363-6 1 CONN@
+3VS 2 R199 1 6 1 10mil G996P11U SOP 8P
10K_0402_5% C1
Q210A 10U_0805_10V4Z R5 10K_0402_5%
2 2 1 +3VS
5
3 AMB 1 2
UD BATT_CHG_LOW_LED# <36>
R203 220_0402_5%
+5VALW 1
1
2 BLUE 1 2
NB BATT_FULL_LED# <36>
C41 R204 220_0402_5%
A A
0.1U_0402_16V4Z
2 HT-210UD/NB_AMB/BLUE del R204, add R270 and R271 for LED issue, 1103
CAP LOCK LED Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/06/01 Deciphered Date 2013/05/12 Title
1 2 2 1 CAPS_LED#
+5VALW
R202 220_0402_5%
CAPS_LED# <36>
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR/TP/LED/FAN
D27 Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
LED 19-213A/T1D-CP2Q2HY/3T 0603 WHITE 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VBL30/31 LA-9351P M/B
Date: Monday, July 16, 2012 Sheet 38 of 50
5 4 3 2 1
5 4 3 2 1
+3VALW TO +3VS
Vgs=-0V,Id=9A,Rds=18.5mohm +5VALW TO +5VS +1.5V to +1.5VS
Vgs=10V,Id=14.5A,Rds=6mohm
+3VALW +3VS 0.1U_0402_16V7K +5VALW +5VS
0.1U_0402_16V7K +1.5V +1.5VS
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
1 1 2 2 2 2 1 1 2 2
Q32 C824 C825 4.7U_0805_10V4Z C843 C844 Q33 C826 C827 C842 C845 1 1
470_0805_5%
470_0805_5%
8 1 @ C853 8 1 1U_0402_6.3V4Z 4.7U_0805_10V4Z Q34
D S D S
470_0805_5%
7 2 C852 @ 7 2 8 1 C828 C829
D S D S D S
2
6 3 2 2 1 1 R781 1 1 6 3 2 2 R782 1 1 7 2 1U_0402_6.3V4Z 4.7U_0805_10V4Z
5 D S 4 5 D S 4 6 D S 3 2 2
D G 1U_0402_6.3V4Z 0.1U_0402_16V7K
0.1U_0402_16V7K D G 5 D S 4 R783
D D
SI4800BDY_SO8 1 R784 2 SI4800BDY_SO8 RUN_ON 1 R785 2 D G
+VSB +VSB
3 1
3 1
0.022U_0402_25V7K
0.1U_0402_16V7K
4.7U_0805_10V4Z
3 1
1
6
0.01U_0402_25V7K
C833
4.7U_0805_10V4Z
C847 C831 C848 C846C854 0.1U_0402_16V7K 1 220K_0402_5%
6
0.1U_0603_25V7K
C830 R787 Q35A C832 R788 Q36A FDS6676AS 1
330K_0402_5% Q35B @ 330K_0402_5% Q36B C834 R789 Q37A
1 2 2 2 SUSP 5 1 1 1 2 2 2 SUSP 5 C835 820K_0402_5% Q37B
2 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 2 2 SUSP 5
2
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 2 2N7002DW-T/R7_SOT363-6
2
2N7002DW-T/R7_SOT363-6
4
4.7U_0805_10V4Z
C344
PX@ 1 2MM 1
C491 2MM 2MM
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1 1 Q43 PX@ C379 U16 PX@ 1
1
10U_0603_6.3V6M PX@ PX@ 10U_0603_6.3V6M AO4430L_SO8 PX@ 4.7U_0603_6.3V6K AO4430L_SO8 PX@ @ R291
2 C345 PX@ +VSB 8 1 2 8 1 C1144 C1148 PX@
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
3 1 C44 C49 1U_0402_6.3V6K 1 7 2 1 1 1 PX@ 7 2 10U_0603_6.3V6M 1U_0402_6.3V6K 470_0603_5%
2
1
1
+5VALW 2 2 2 C473 6 3 PX@ PX@ PX@ @ 6 3 2
C PX@ PX@ PX@ 5 C478 C42 R429 5 C
2
Q54 PX@ R431 C475 C43 470_0603_5%
2
AP2301GN-HF_SOT23-3 220K_0402_5% 2 2 2 2 +VSB
R272 R281
2
4
SB00000RV00 SB00000RV00 @ Q40
R278
1
1 PX@ 2 1 2 1 2 1R1452 PX@2 D
51K_0402_5% PX@R426 1 2 1
DGPU_PWR_EN# 2 2
100K_0402_5% 1 10K_0402_5% @ R288 G
PX@ 330K_0402_5%
1
2
D 0_0402_5% S
3
62K_0402_5%
1
DGPU_PWR_EN 2 C697 PX@ R430 @ R290 D 2N7002K_SOT23-3
1
G Q30 PX@ 0.1U_0402_16V4Z D PX@ 0_0402_5% C481 1
DGPU_PWR_EN# 2 2 D C1150 PX@
S 2N7002K_SOT23-3 2 2
DGPU_PWR_EN# @ 0.047U_0402_25V7K G DGPU_PWR_EN# 2 0.1U_0402_25V6
3
2
G Q13 PX@ 0_0402_5% @ Q31 S G Q38 PX@
2
S 2N7002K_SOT23-3 2N7002K_SOT23-3 S 2N7002K_SOT23-3
3
3
+3VALW to +3V_PCH
+3VALW +3V_PCH
J1 @
1 2
1 2
JUMP_43X79
Q5512
AO3413_SOT23
B B
S
3 1
0.1U_0402_10V7K~D
+3VALW
20K_0402_5%~D
G
2
PCH_PWR_EN#R807 2 1 47K_0402_5%
2
2
2
2 R797
1
2
R796
0.1U_0402_25V6
1
2 PCH_PWR_EN# DGPU_PWR_EN#
<25> PCH_PWR_EN#
1
SYSON# SUSP
SUSP <6,11>
6
Q49 Q201B Q201A
1
2N7002E-T1-GE3_SOT23-3 DTC124EKAT146_SC59-3 Q191 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6
+3VS_DGPU +VGA_CORE 1 D
OUT
+1.05VS_VCCP +1.5V +0.75VS 2 5 2
<36> PCH_PWR_EN <36,45> SYSON SUSP# <10,36,43,44,45,50>
G
2
S 2
<22,50> DGPU_PWR_EN
3
1
IN
2
R458 R459 1 2
GND
R1445 R1446 R826 470_0603_5% 470_0603_5% R816 2 R70 1 R440
470_0805_5% 470_0805_5% 22_0603_5% PX@ PX@ 100K_0402_5% 10K_0402_5% 4.7K_0402_5%
PX@
1
3
+VCCP_R 1
+1.5V_R 2
3+0.75VS_R2
A A
6
D
SUSP 2
G SYSON# 2 5
SUSP 2DGPU_PWR_EN#
5 Security Classification Compal Secret Data Compal Electronics, Inc.
S 2N7002K_SOT23-3 2N7002DW-T/R7_SOT363-6 Q225B
Issued Date 2012/06/01 2013/05/12 Title
Deciphered Date
3
2N7002DW-T/R7_SOT363-6 PX@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PX@ Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VBL30/31 LA-9351P M/B
Date: Monday, July 16, 2012 Sheet 39 of 50
5 4 3 2 1
A B C D
PL1
HCB2012KF-121T50_0805
1 2
VIN
PL2
HCB2012KF-121T50_0805
ADPIN 1 2
PJPDC1 @
1000P_0402_50V7K
1000P_0402_50V7K
100P_0402_50V8J
100P_0402_50V8J
1 1
4
4
1
3
3
PC1
PC2
PC3
PC4
2
2 1
2
1
SINGA_4TRJWT-R2513
100K_0402_1%
0.22U_0603_25V7K
0.1U_0603_25V7K
1
1
PR10
PC8
PC9
VL +3VALW_EC
2
2
2
VL PR12
PQ1
TP0610K-T1-E3_SOT23-3 <36,41> ADP_I
12.7K_0402_1%
21.5K_0402_1%
2 2
22K_0402_1%
1
1.65K_0402_1%
1 2 VSB_N_001
PR18
2
1VSB_N_003
PR25
PR23
@ PR4
1
@
100K_0402_1%
@ PC12 +3VS
2
0.1U_0603_16V7K PU1
@ PR13 PR16
2
1 8 NTC_V_2
1
0_0402_5% 0_0402_5% D
VCC TMSNS1
1 2 1 2VSB_N_002 2 PQ2
100K_0402_1%
<42> SPOK 2 7 OTP_N_002 2 1
G 2N7002KW_SOT323-3 GND RHYST1
PR31
PR30@
.1U_0402_16V7K
S 3 6 Turbo_V_2
+3VLP 10K_0402_1%
3
1
PC10
2
4 5 ADP_OCP_2 1 2
100K_0402_1%_NCP15WF104F03RC
1 2
1
OT2 RHYST2
PH1
<36> VSB_EN PQ4 PR29
2
2
D
10K_0402_1%
@ G718TM1U_SOT23-8 5.11K_0402_1% 0_0402_5%
PR19
2ADP_OCP_1 PR22
OTP_N_003
G 0_0402_5% PR248
1
S 2N7002KW @ PR32 0_0402_5%
2
@ PR17 2 1 2 1
1
PR24 2 1
0_0402_5% 47K_0402_1%
2
+VSBP +VSB <36> VCOUT1_PH 1 2 2 1
VCOUT0_PH <36,42>
0_0402_5%
PJP6 PR247 @
2 1 @ PR20 0_0402_5% 0_0402_5%
<36>
VCIN1_PH
PAD-OPEN 2x2m
1
BATT_1 PL3 ECAGND <36>
HCB2012KF-121T50_0805 @ PR21
1 2 2 1
3
+3VALW 3
VMB 47K_0402_1%
PL4
SUYIN_200275MR009G10PZR HCB2012KF-121T50_0805
1 1 2
1 2 BATT+
2 3
<36>
@ PR6
VCIN0_PH
3 4 BATT_P4 1 2
4 5 +3VALW
2
1
TS_A
5 6 100K_0402_1% PC6 PC7
6 7 PR7 1000P_0402_50V7K 0.01U_0402_25V7K
2
2
7 8 1K_0402_1%
8 9
EC_SMB_CK1_1
EC_SMB_DA1_1
PJSOT24CW_SOT323-3
GND
1
9 10
GND 11 RTC Battery
1
PD1
GND
PD2
@ 2 1
PJP1 +3VALW
1
PR9 @
PR11 6.49K_0402_1% - PBJ1 + PR28 PR27
2
1
100_0402_1%
2 1 +RTCBATT1 1 2+RTCBATT2 1 2
PR15
2
1
PJSOT24CW_SOT323-3
PR14
100_0402_1% +RTCBATT
MAXEL_ML1220T10
2
EC_SMB_CK1 <36,41>
1
PQ100 D
BQ24725_PROT2
G 2N7002KW_SOT323-3
S
3
1 1
PR100 PR101
1 2 1 2 PQ101
MDU1516URH_POWERDFN56-8-5
1M_0402_5% 3M_0402_5% P2 P3
1
PQ103 PL100 2
PQ102 MDS2659URH_SO8 PCMC 063T1R5MN 5 3
VIN TPCA8057 P1 PR102
1 1 8 0.02_1206_1%
0.01U_0402_50V7K
B+
@0_0402_5%
2 2 7
1
5 3 3 6 1 2 1 4
PR103
5
PC101
2200P_0402_25V7K
1
VIN
2200P_0402_50V7K
@10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
2 3
0.1U_0402_25V6
@820P_0402_25V7
@10U_0805_25V6K
10U_0805_25V6K
@0_0402_5%
0.1U_0402_25V6
PC110
PC111
4
4
1
1
10U_0805_25V6K
PC106
PC100
PC107
PR104
PC109
2
1
PC104
PC105
PC108
PC102
PC103
1
2
BQ24725_BATDRV 1 2BQ24725_BATDRV_1
2
PD100
2
2
PR105
BQ24725_VCC1 1
BAS40CW_SOT323-3 4.12K_0603_1%
BQ24725_ACDRV_1
0.1U_0402_25V6
PQ104
0.1U_0603_25V7K
TP0610K-T1-E3_SOT23-3
PC113
1
BQ24725_VCC1 3 1BQ24725_VCC2 PC114
PC112
2
1 2
2
2
1BQ24725_VCC2
PR106
2
100K_0402_1% 0.1U_0402_25V6
0.047U_0402_25V7K
4.12K_0603_1%
4.12K_0603_1%
PC116
1
PC115
1
1
PR107 0.22U_0603_25V7K 1 2BQ24725_BST1
PR108
PR109
1 2 BQ24725_VCC_EN
5
10_1206_1%
0_0603_5%
1BQ24725_VCC_EN1
2 2
PR110
PR111
PD101 PQ105
@22K_0402_1% MDV1528URH_PDFN33-8-5
RB751V-40_SOD323-2
2
2
1
0_0402_5%
PR112
BQ24725_VCC 2
BQ24725_BST 2
BQ24725_REGN2
DH_CHG 1 2DH_CHG1 4
PR113
BQ24725_LX
BQ24725_ACP
PL101 BATT+
2
0_0402_5%
DH_CHG
PC117
D 1 2 PC118 4.7UH_ETQP3W4R7WFN_5.5A_20% PR114
BQ24725_ACN
3
2
1
GREEN_LATCH# 2 PQ106 1 2 0.02_1206_1%
G @2N7002KW_SOT323-3 BQ24725_LX 1 2CHG_OUT 1 4
S 1U_0603_25V6K 1U_0603_25V6K
3
@4.7_1206_5%
2 3
20
19
18
17
16
CSOP1
PU100 PQ107
2200P_0402_50V7K
0.01U_0402_50V7K
CSON1
1
VCC
PHASE
HIDRV
BTST
REGN
PR115
10U_0805_25V6K
10U_0805_25V6K
@820P_0402_25V7
21
0.1U_0402_25V6
0.1U_0402_25V6
PAD
PC125
PC122
PC120
PC121
1
1
PC119
1 15 DL_CHG 4
ACN LODRV
PC123
PC124
1BQ24725_SNUB 2
2
2 14
Vin Dectector ACP GND PR116 AON7406L_DFN8-5
3
2
1
2
BQ24735RGRR_VQFN20_3P5X3P5 10_0603_1%
BQ24725_CMSRC 3 13 SRP1
2 CSOP1
Min. Typ Max. CMSRC SRP
1
PR117
H-->L 17.23V 6.8_0603_1%
@680P_0402_50V7K
BQ24725_ACDRV 4 12 SRN 1 2 CSON1
2
ACDRV SRN
L--> H 17.63V
0.1U_0603_16V7K
PC127
PR118
PC126
+3VALW 1 2BQ24725_ACOK5 11 BQ24725_BATDRV
2
ACOK BATDRV
ILIM and external DPM
ACDET
@10K_0402_1%
IOUT
SDA
SCL
ILIM
PR119
3.97A 1 2
+3VL +3VL
10
1M_0402_1%
PR120 PR121
1 2 BQ24725_ILIM 1 2
3
0.01U_0402_25V7K
<14,21,36> ACIN
100K_0402_1%
10K_0402_1% 169K_0402_1%
For KB9012 (Red square) --> Remove PR117
1
VIN
PC128
PR123
1
Keep PR126 PR122 10/3
BQ24725_IOUT
BQ24725_ACDET
1 2BQ24725_PRECHG
2
154K_0402_1%
<36> GREEN_PWR4
2
255K_0402_1%
1
PR124
+3VL
VIN
@0.1U_0402_10V6K
2
1
PC129
PU101
0.1U_0402_25V6
PR125
66.5K_0402_1%
309K_0402_1% @MC74VHC1G08DFT2G_SC70-5
EC_SMB_CK1 <36,40>
2
1
PC130
5
PR128
PR126
5
PR127 10K_0402_5% PU103
VCC
2
5
100_0402_5% GREEN_PWR3 1 2GREEN_PWR4 1 PU102 1
P
EC_SMB_DA1 <36,40> IN1 INB
4GREEN_PWR1 1 4
P
OUT INB O
2
PR129 GREEN_PWR# 2 4 GREEN_PWR2 2
GND
2
IN2 O INA
G
0.1U_0402_10V7K
2 1 2
ADP_I <36,40> INA
G
47K_0402_1%
@74LVC1G02_04_SOT353
3
PC131 .1U_0402_16V7K @74LVC1G02_04_SOT353
3
1
PC132
1
+3VL
2
Please locate the RC GREEN_LATCH1
Near EC chip
2
PR131 @0_0402_5%
2
1 2 PR132
PR130 <36> GREEN_PWR @0_0402_5%
2
@10K_0402_1%
PR133
1
PR134 @100K_0402_5%
GREEN_PWR5
1
GREEN_LATCH# 1 2
4 4
GREEN_LATCH#
1
@0_0402_5%
1
D
PQ108 2
@SSM3K7002FU_SC70-3 G PR135
S 1 2
3 @0_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-CHARGER
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS VBL30/31 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, July 16, 2012 Sheet 41 of 50
A B C D
A B C D E
2VREF_51125
1
PC300
1U_0603_16V6K
2
1 1
PR300 PR301
13.7K_0402_1% 30.9K_0402_1%
1 2 1 2
PR302 PR303
B+ B++
20K_0402_1% 20K_0402_1%
B++
PL301 1 2 FB_3V FB_5V 1 2
HCB2012KF-121T50_0805
1 2 +3VLP
ENTRIP2
ENTRIP1
PR304 PR305
2200P_0402_50V7K
2200P_0402_50V7K
10U_0805_25V6K
0.1U_0402_25V6
0.1U_0402_25V6
140K_0402_1% 113K_0402_1%
1
1
4.7U_0805_25V6-K
1 2 1 2
1
1
PC309
PC310
PC311
PC312
PC304
PC306
PQ303
2
2
6
1
PU300
2
5
MDV1528URH_PDFN33-8-5
ENTRIP2
FB2
TONSEL
ENTRIP1
REF
FB1
1
PC313
4 10U_0805_6.3V6M 25 PQ305
P PAD
2
7 24 4 MDV1528URH_PDFN33-8-5
VO2 VO1
1
2
3
UG_3V_1
PC314 8 23 PR307 PC301
VREG3 PGOOD
UG_5V_1
0.1U_0402_10V7K PR308 2.2_0402_5% 0.1U_0402_10V7K
1 2 BST1_3V 1 2 BST_3V 9 22 BST_5V 1 2 BST1_5V 1 2
3
2
1
2 PR306 2.2_0402_5% BOOT2 BOOT1 PR309 2
PL303 1 2 UG_3V 10 21 UG_5V 1 2 PL305
4.7UH_ETQP3W4R7WFN_5.5A_20% 0_0402_5% UGATE2 UGATE1 0_0402_5% 4.7UH_ETQP3W4R7WFN_5.5A_20%
2 1 LX_3V 11 20 LX_5V 1 2 +5VALWP
+3VALWP PHASE2 PHASE1
1
1
@4.7_1206_5%
@4.7_1206_5%
LG_3V 12 19 LG_5V
LGATE2 LGATE1
PR312
PQ304
SKIPSEL
PR313
VREG5
1
150U_B_6.3VM_R35M
PR314 1
GND
VIN
PC303
150U_B_6.3VM_R35M
+ 499K_0402_1%
NC
EN
2
PC305
4 1 2 4 +
51125_PWR SPOK <40>
13
14
15
16
17
18
1 SNUB_3V
SNUB_5V
PJP303 2 RT8205LZQW(2)_WQFN24_4X4
1 2 EN0 PQ306 2
+3VALWP +3VALW
AON7406L_DFN8-5 EN0
1
2
3
3
2
1
@680P_0402_50V7K
@680P_0402_50V7K
VL S TR AON7430L 1N DFN
PAD-OPEN 4x4m
1
PC316
PC317
PR315
+3VALW 95.3K_0402_1% PC320
2
1U_0603_10V6K
2
Imax=3.35A
1
Ipeak=4.78A PC318
4.7U_0805_10V6K
2
Iocp=5.74A
1
51125_PWR
PC319 PJP305
2
0.1U_0603_25V7K 1 2 +5VALW
+5VALWP
ENTRIP1
ENTRIP2
2VREF_51125
PAD-OPEN 4x4m
3 3
+5VALW
6
D D
PQ307A 2N_3_5V_001 5 PQ307B Imax=5.2A
2N7002KDW_SOT-363 G G 2N7002KDW_SOT-363 Ipeak=7.4A
S S Iocp=8.88A
1
B+ PR320 51125_PWR
0_0603_5%
2 1 51125_PWR1 1 2
PR318 Vin PD301
1
2.2K_0402_1% PD300
1 2 PR317 2 1 1SS355_SOD323-2 PD302
<36> EC_ON PR316
1 2
100K_0402_5% VL GLZ27D_LL34-2
+3VLP +3VL
N_3_5V_002
1 2 @1SS355_SOD323-2 PJP302
51125_PWR2
<36,40> VCOUT0_PH
2
0_0402_5% 2 1
BATT+
1
S
3
+3VLP +CHGRTC
@1SS355_SOD323-2
1
PC321
PJP300
2 1
1
2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-3.3VALWP/5VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom VBL30/31 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, July 16, 2012 Sheet 42 of 50
A B C D E
A B C D
1 1
PL402
PU401 PL401
4
+3VALW HCB1608KF-121T30_0603 1UH_PH041H-1R0MS_3.8A_20%
1 2 VIN_1.8VSP 10 2 LX_1.8VSP 1 2
PG
PVIN LX +1.8VSP
68P_0402_50V8J
9 3
PVIN LX
1
4.7_0805_5%
1
1
PC404
PC403 8
SVIN
PR403
22U_0805_6.3VAM PR401
6 20K_0402_1%
2
FB
22U_0805_6.3VAM
22U_0805_6.3VAM
5
2
EN
1
NC
NC
TP
PC401
PC402
FB_1.8VSP
<10,36,39,44,45,50> SUSP#
11
2
SNUB_1.8VSP
1 2 EN_1.8VSP
1
1
@0.1U_0402_10V7K
PR404 0_0402_5%
PC405
SY8033BDBC_DFN10_3X3 PR402
1
PR405 10K_0402_1%
@47K_0402_5%
2
2
680P_0402_50V7K
PC406
2
2 2
PJP401
1 2 +1.8VS
+1.8VSP
PAD-OPEN 3x3m
(3.5A,140mils ,Via NO.= 7)
+1.8V
Imax=2.25A
Ipeak=3.22A
3 3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-1.8VSP
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS VBL30/31 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, July 16, 2012 Sheet 43 of 50
A B C D
5 4 3 2 1
PL700
HCB1608KF-121T30
+1.05VSP_B+ 2 1
B+
2200P_0402_50V7K
10U_0805_25V6K
4.7U_0805_25V6-K
0.1U_0402_25V6
D D
1
PC706
+3VS
PC700
PC702
PC703
2
2
5
2
PR700 PQ701
10K_0402_5%
PC704
0.22U_0402_10V6K 4
PR702
1
1 2 BST1_+1.05VSP 1 2
2.2_0402_5% MDV1528URH_PDFN33-8-5
<11,46> +V1.05S_VCCP_PWRGOOD
PU701
1 10 BST_+1.05VSP
3
2
1
PGOOD VBST
PR701 PR703
1 2 TRIP_+1.05VSP 2 9 UG_+1.05VSP 1 2 UG_+1.05VSP1 PL701
TRIP DRVH 0.47UH_PCMB063T-R47MS_18A_20%
180K_0402_1% 0_0402_5%
EN_+1.05VSP 3
EN SW
8 SW_+1.05VSP 1 2 +1.05VSP
5
PR704 FB_+1.05VSP 4 7
0_0402_5% VFB V5IN +5VALW
1
1 2 RF_+1.05VSP 5 6 LG_+1.05VSP PQ702
<10,36,39,43,45,50> SUSP# TST DRVL
1
220U_D2_2VY_R15M
11 PR705
TP
1
PC701
PC705 4 4.7_1206_5% +
1
TPS51212DSCR_SON10_3X3 1U_0603_10V6K
SNUB_+1.05VSP
2
2
PC707 PR706
@0.1U_0402_16V7K 470K_0402_1% 2
2
DMS3014SFG
2
3
2
1
C C
1
PC708
0.1U_0402_10V7K
2
1
PC710 PC709
@1000P_0402_50V7K
PR707 680P_0402_50V7K
1 2 +1.05VSP1 1 2 +1.05VSP
2
@1.2K_0402_1%
PR709
PR708 4.87K_0402_1% 100_0402_1%
2 1 VCCIO_SENSE1 2 1
VCCIO_SENSE <9>
2
PR710
10K_0402_1%
1
PJP700
1 2
PAD-OPEN 4x4m
PJP701
1 2 +1.05VS_VCCP
B +1.05VSP B
PAD-OPEN 4x4m
+1.05VSP
Imax=11.2A
Ipeak=16A
Iocp=20A
A A
0.75Volt +/- 5%
TDC 0.525A
Peak Current 0.75A
PL500
HCB1608KF-121T30 OCP Current 0.9A
D B+ 1 2 1.5V_B+ D
PR500
BST_1.5V 1 2 BOOT_1.5V +1.5VP
2.2_0402_5%
2200P_0402_50V7K
10U_0805_25V6K
@4.7U_0805_25V6-K
PR501
+0.75VSP
0.22U_0402_10V6K
0.1U_0402_25V6
DH_1.5V_1 1 2 DH_1.5V
1
PC508
0_0402_5%
10U_0805_6.3V6M
10U_0805_6.3V6M
PC500
PC502
PC503
PC504
SW_1.5V
1
5
1
PC505
PC506
DL_1.5V
16
17
18
19
20
PQ501 PU501
PHASE
UGATE
VLDOIN
BOOT
VTT
2
PR502 21
PL501 PAD
12.7K_0402_1%
2.2UH_ETQP3W2R2WFN_8.5A_20% 4 UMA@ 15 1
UMA@ LGATE VTTGND
MDV1528URH_PDFN33-8-5
PX@ PL501 PR502 14 2
1UH_VMPI0703AR-1R0M-Z01_11A_20% PX@18.7K_0402_1% PGND VTTSNS
1
2
3
1 2 CS_1.5V
2 1 13 3
+1.5VP PC507 CS RT8207MZQW_WQFN20_3X3 GND
5
1U_0603_10V6K
220U_D2_2VY_R15M
PR504 1 2 12 4 VTTREF_1.5V
VDDP VTTREF
1
1 PQ502 5.1_0603_5%
PX@
+1.5VP
PC501
C + PR503 1 2 VDD_1.5V 11 5 C
VDD VDDQ
PGOOD
@4.7_1206_5% 4
+5VALW
1
TON
SNUB_+1.5VP 2
FB
S5
S3
1U_0603_10V6K 10.2K_0402_1% 0.033U_0402_16V7K
2
DMS3014SFG UMA@
1
2
3
10
6
+5VALW
PQ502
S TR AON7430L 1N DFN PX@ PR505 1/18
UMA@ 10.7K_0402_1%
+1.5VP
1
PC511 FB_1.5V 2 1
TON_1.5V
@680P_0402_50V7K
2
1
Mode Level +0.75VSP VTTREF_1.5V PR506
PR507 10K_0402_1% PC512
S5 L off off 887K_0402_1% .1U_0402_16V7K
2
S3 L off on PR508 1.5V_B+ 1 2
1
0_0402_5%
S0 H on on 1 2 EN_1.5V
<36,39> SYSON
EN_0.75VSP
Note: S3 - sleep ; S5 - power off
1
PR509
2 1
PC513 <11> 0.75VR_EN
2
B @0.1U_0402_10V7K B
@0_0402_5%
PR510
2 1
<10,36,39,43,44,50> SUSP#
0_0402_5%
1
@ PJP502
PC514
2
1 2 @0.1U_0402_10V7K
PAD-OPEN 4x4m
@ PJP501
1 2 +1.5V (13A,520mils ,Via NO.= 26)
+1.5VP
PAD-OPEN 4x4m
@
PJP601
+0.75VSP
1 2 +0.75VS (2A,80mils ,Via NO.= 4)
PAD-OPEN 3x3m
A A
100K_0402_5%
PR801
1K_0402_5%
output voltage adjustable network
1
2 1
PR800
H_VCCSA_VID1 <10>
2
+VCC_SAP
H_VCCSA_VID0 <10>
TDC 4.2A
<36> SA_PGOOD
PR802 Peak Current 6A
1K_0402_5%
2 1 OCP current 7.2A
1U_0603_10V6K
+5VALW
2
PC800
1
+VCCSA_V5FILT
PR803 PR804
10_0402_1% 0_0402_5%
@0.1U_0402_10V7K
2 1 +VCCSA_EN 1 2
+V1.05S_VCCP_PWRGOOD <11,44>
PC801
2.2U_0603_10V7K
1
1 2
PC802
C C
9/28
2
18
17
16
15
14
13
PU801
PR805 PC803
V5DRV
VID1
VID0
V5FILT
PGOOD
EN
2.2_0603_5% 0.22U_0402_10V6K
12 +VCCSA_BT 1 2+VCCSA_BT_1 1 2
19 BST PL800
PGND 0.47UH_PCMB042T-R47MN_6A_20%
SW
11 +VCCSA_PHASE 1 2 +VCCSAP
20
PGND
22U_0805_6.3V6M
1
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
10
2200P_0402_50V7K
21 SW PR806
0.1U_0402_25V6
PGND
2
10U_0805_10V6M
10U_0805_10V6M
PC804
PC805
PC806
PC807
4.7_0805_5%
TPS51461RGER_QFN24_4X4 9 9/28
22 SW
PC809
SNUB_VCCSA 2
1
VIN
2
2
PC810
PC811
PC808
8
23 SW
1
2 VIN
PL801
7
+5VALW 1 2 +VCCSA_PWR_SRC 24
VIN
SW
25
HCB1608KF-121T30_0603 TP
COMP
MODE
1
SLEW
VOUT
VREF
PC812
GND
1000P_0402_25V8J
2
1
6
PR807
+VCCSA_MODE 2 1
+VCCSA_COMP
+VCCSA_SLEW
@33K_0402_5%
PR808
100_0402_5%
PC813 +VCCSA_VOUT 2 1
2 1 +VCCSA_VREF
B B
0.22U_0402_10V6K
PR809
2 1+VCCSA_COMP1 2 1 0_0402_5%
0.01U_0402_25V7K
2 1
+VCCSA_SENSE <10>
PC814 PR810
2
3300P_0402_50V7K 10K_0402_5%
PC815
PJP800
1 2 +VCCSA
+VCCSAP
PAD-OPEN 4x4m
+VCCSA
Imax=4.2A
Ipeak=6A
A Iocp=7.2 A
D D
PC201
1200P_0402_50V7K
1 PR2012 FBA3 1 2 PC200 1 2
220P_0402_50V7K
PUT COLSE
75K_0402_1%
10_0402_1% 680P_0402_50V7K .1U_0402_16V7K
TO GT
1
PR204 1 PR202 2
PC202
PC203
PR205
TRBSTA# 1 PR2032 FBA1 1 2 PH200 Inductor
2P: 24K 24.9K_0402_1% PR206 PC205
1
1
1.21K_0402_1% 10.7K_0402_1% 220K_0402_5%_ERTJ0EV224J CSCOMPA 1 2 DROOPA 1 2 CSREFA
PC204 1P: 24.9K
2
PR207 PC206 PC207 2 PR2081 NTC_PH203 1K_0402_1% 1000P_0402_50V7K
2
4700P_0402_25V7K 1 2 FBA2 1 2 1 2 165K_0402_1%
10_0402_1%
680P_0402_50V7K PR210 10P_0402_50V8J PC208
1 PR2092 1 2 COMPA1 1 2
2
1 PR2112 SWN1A 0.047U_0402_16V7K
SWN1A <48>
82.5K_0603_1% PR212 5.49K_0402_1%
1
CSP1A 1 2 SWN1A
2
DROOPA 15.8K_0402_1%
PC210
<10> VCC_AXG_SENSE
2
1PR213
15.4K_0402_1%
1000P_0402_50V7K
1
PC211 PH201
CSREFA <48>
PR214
1000P_0402_50V7K
1
+5VS 100K_0402_1%_TSM0B104F4251RZ
<10> VSS_AXG_SENSE
PC212
1
CSP1A
1 2
CSCOMPA
TRBSTA#
CSSUMA
CSREFA
TSENSEA
COMPA
IMONA
FBA
.1U_0402_16V7K
DIFFA
C C
ILIMA
PR215
1 2 PUT COLSE
26.1K_0402_1%
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
+5VS 1 PR2162 PU201 TO V_GT
2_0603_5% HOT SPOT
TRBSTA#
PAD
VSNA
VSPA
DIFFA
FBA
COMPA
IOUTA
ILIMA
DROOPA
CSCOMPA
CSSUMA
CSREFA
CSP2A
CSP1A
TSNSA
+1.05VS_VCCP PC213
1
6132_VCC 2
.1U_0402_16V7K
.1U_0402_16V7K
1 45 PR217 PC214
2.2U_0603_10V7K 2 VCC PWMA 44 BSTA1 1 2 BSTA1_11 2
VDDBP BSTA
130_0402_1%
54.9_0402_1%
PR218 2
1 2VR_ON_CPU 4 42
<36> VR_ON EN SWA SW1A <48>
PR219
13 33 0_0402_5%
+1.05VS_VCCP VSN SW1 SW1 <48>
PC219 14 32 PC220
+3VS VSP HG1 HG1 <48>
DIFF_CPU 15 31 BST1 1 PR2272 BST1_1 1 2
CSCOMP
2
DIFF BST1
TRBST#
2.2_0603_5% 0.22U_0402_10V6K
DROOP
CSSUM
DRVEN
CSREF
COMP
1
TSNS
CSP3
CSP2
CSP1
PWM
IOUT
ILIM
1
PR228
FB
75_0402_1% PR229
10K_0402_5%
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
2
1 PR2302
<36> VR_HOT#
COMP_CPU
2
FB_CPU 41.2K_0402_1%
TRBST#
<21> VGATE
DROOP
TSENSE
ILIM_CPU
<9> VSSSENSE
1
IMON
PC221
1000P_0402_50V7K
2
B B
PC222
<9> VCCSENSE
2
PR231 12.4K_0402_1%
1 2
.1U_0402_16V7K
1
10P_0402_50V8J 5.49K_0402_1%
PC224
PR234 PC225 PR235 PC226 0.047U_0402_16V7K
2
1 2FB_CPU1 1 2 2 1COMP_CPU12 1 CSREF
PR236 PC227 49.9_0402_1% 6.04K_0402_1%
15.4K_0402_1%
1 2FB_CPU3 1 2 680P_0402_50V7K 2200P_0402_25V7K
PR238 1
2
10_0402_1% CSP1 1 PR2372 SWN1
CSCOMP
CSREF <48>
2
1
680P_0402_50V7K 5.49K_0402_1% PH202
PR239 PR240 PC228 PC229
TRBST# 1 2 FB_CPU2 1 2 1000P_0402_50V7K 0.047U_0402_16V7K 100K_0402_1%_TSM0B104F4251RZ
1
2
4700P_0402_25V7K
CSREF
1
1
1.21K_0402_1% 9.53K_0402_1%
PC230
CSSUM
2
PC231
1 2
1200P_0402_50V7K 1 PR2412 SWN1
SWN1 <48>
24.9K_0402_1%
.1U_0402_16V7K
TO VCORE
PC232
75K_0402_1%
PR246 PC234 165K_0402_1%
CSCOMP 1 2 DROOP 1 2 CSREF PH203
PUT COLSE
1K_0402_1% 1000P_0402_50V7K 2 1
TO VCORE
Phase 1 220K_0402_5%_ERTJ0EV224J
A A
Inductor
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C VBL30/31 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, July 16, 2012 Sheet 47 of 50
5 4 3 2 1
5 4 3 2 1
D D
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
2 1
B+
@820P_0402_25V7
@820P_0402_25V7
2200P_0402_25V7K
2200P_0402_25V7K
0.1U_0402_25V6
0.1U_0402_25V6
5
5
PL601
HCB2012KF-121T50_0805
1
PC600
PC601
PC604
PC602
PC603
PC605
PC606
PC607
PC608
PC610
PQ201 2 1 PQ204
CPU_B+
1 1
PR601 PR600
2
1 2 HG1_1 4 + + 1 2 HG2_1 4
<47> HG1
0_0603_5% +CPU_CORE PC611 PC609
<47> HG2
0_0603_5%
100U_25V_M @100U_25V_M +CPU_CORE
2 2
S TR MDU1516URH 1N POWERDFN56-8 S TR MDU1516URH 1N POWERDFN56-8
3
2
1
3
2
1
PL201 PL202
0.36UH 20% FDUM0640J-H-R36M 0.36UH 20% FDUM0640J-H-R36M
1 4 1 4
<47> SW1 <47> SW2
1
2 3 2 3
5
5
PQ202 PR602 PQ205 PR603
@4.7_1206_5% @4.7_1206_5%
2
PR604 PR605
4 2 1 4 2 1CSREF
1SNUB_CPU1
SNUB_CPU2
<47> LG1 CSREF <47> <47> LG2
10_0402_1%
10_0402_1%
3
2
1
SWN1 <47>
PC612 SWN2
SWN2 <47>
@680P_0402_50V7K
1
PC613
2
C C
@680P_0402_50V7K
2
DC 35W CPU
VID1=1.05V
PL604 IccMax=53A
HCB2012KF-121T50_0805
Icc_Dyn=43A
10U_0805_25V6K
10U_0805_25V6K
GFX_B+ 2 1
B+
@820P_0402_25V7
2200P_0402_25V7K
0.1U_0402_25V6
Icc_TDC=36A
R_LL=1.9m ohm
1
1
PC614
PC615
PC616
PC617
PC618
OCP~65A
2
2
5
PR606
1 2HG1A_1 4 PQ210
<47> HG1A
0_0603_5%
S TR MDU1516URH 1N POWERDFN56-8
+GFX_CORE
3
2
1
PL204
0.36UH 20% FDUM0640J-H-R36M
1 4
<47> SW1A
1
2 3
5
PR607
@4.7_1206_5%
B B
PQ211 DC 35W GT2
2
4 VID1=1.23V
<47> LG1A
S TR MDU1512RH 1N POWERDFN56-8 IccMax=33A
SNUB_GFX1
Icc_Dyn=20.2A
2 PR6081 Icc_TDC=21.5A
CSREFA <47>
3
2
1
PC619
@680P_0402_50V7K
2
A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-VCC_CORE A
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C VBL30/31 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, July 16, 2012 Sheet 48 of 50
5 4 3 2 1
5 4 3 2 1
1
PC1000 PC1001 PC1002 PC1003 PC1004
Socket Bottom 5 x (0805) no-stuff
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M sites
2
2
D +GFX_CORE D
7 x 22 ȝF (0805)
Socket Top 2 x (0805) no-stuff
sites
1
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 1 1 1 1 1 1
PC1010
PC1011
PC1012
PC1013
PC1014
PC1015
PC1016
PC1017
PC1005 PC1006 PC1007 PC1008 PC1009
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2
2
2 2 2 2 2 2 2 2 +1.05VS_VCCP
+CPU_CORE +1.05VS_VCCP
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1
PC1023
PC1024
PC1025
PC1026
PC1027
PC1028
PC1029
PC1030
PC1031
PC1032
PC1033
PC1018 PC1019 PC1020 PC1021 PC1022
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 1 1
PC1034
PC1035
PC1036
PC1037
2 2 2 2
22U_0805_6.3V6M
1 1
330U_D2_2V_Y
330U_D2_2V_Y
1 1 1 1 1
PC1043
PC1044
PC1045
+ +
1
PC1038 PC1039 PC1040 PC1041 PC1042
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
C 2 2 2 2 2 2 2 C
2
1 1
330U_D2_2V_Y
330U_D2_2V_Y
PC1046
PC1047
+ +
2 2
1 1 1 1 1 1
PC1048 PC1049 PC1050 PC1051 PC1052 PC1053
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2 2 2
+CPU_CORE
1 1 1
1
+ PC1054 + PC1055 + PC1056
330U_D2_2V_Y 330U_D2_2V_Y + PC1057
470U_D2_2VM_R4.5M 330U_D2_2V_Y
2 2 2
2
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR - PROCESSOR DECOUPLING
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS VBL30/31 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, July 16, 2012 Sheet 49 of 50
5 4 3 2 1
A B C D
UGATE2_VGA
1 PX@ PX@ 1
1
PX@ PX@
2200P_0402_50V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
PR924 @
0.1U_0402_25V6
1
1
0_0402_5%
PC902
PR900 PX@
S TR MDU1516URH 1N POWERDFN56-8
PC900
PC903
PC904
0_0402_5%
PX@
2
PX@ @
2
5
5
PC901
2
10P_0402_25V8J
2 1
PX@
PQ900
PQ902
2
2
PX@
4700P_0402_25V7K
PC905
10P_0402_25V8J PR901 4 4
connect PR925 GND to VGA chip 73.2K_0402_1%
2
PX@ PR902
18 PC906
0_0402_5% PX@
1
@ PR925 1 2
19 1
3
2
1
3
2
1
0_0402_5%
1 2 PX@ PL900 PX@
21
20
17
16
PU901 0.36UH_PCMC104T-R36MN1R17_30A_20%
PX@ 1 2
PAD
VSNS
SLEW
TRIP
GND
MODE
+VGA_CORE
PR903
2 1
1 15 PX@ PX@ PX@ PX@ PX@
GSNS V5IN +5VALW
2
10.7K_0402_1%
5
1
1
PX@
PR904
330U_D2_2.5VM_R9M
330U_D2_2.5VM_R9M
330U_D2_2.5VM_R9M
1 1 1
S TR MDU1512RH 1N POWERDFN56-8
S TR MDU1512RH 1N POWERDFN56-8
PX@
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
2 14 PC907 1 1 1
V3 DRVL
10.7K_0402_1%
PC908
PC909
PC910
PC911
PC912
PC913
1U_0603_10V6K PR905 + + +
PQ903
PQ901
PX@ 4.7_1206_5%
21
2
2 2 2 2 2 2
PR906
3 13 UGATE2_VGA 4 4
V2 TPS51518RUKR_QFN20_3X3 DRVH PX@
PX@
1
PX@ PC914
4 12 PX@ 680P_0603_50V7K
21
V1 SW
6.04K_0402_1%
PR908 PC915
3
2
1
3
2
1
2
PR907
2.2_0603_5% 0.1U_0603_25V7K
PX@ 5 11
BOOT2_VGA 2 1 1
BOOT2_2_VGA 2
V0 BST
PGOOD
2 2
1 1
VREF
VID0
VID1
93.1K_0402_1%
EN
PR909
LGATE2_VGA
PX@
6
10
2
0.1U_0402_10V7K
1
+3VS
PC916
PX@
2
+VGA_COREP
1
10K_0402_1%
Seymour XT
PR911 @ Imax=13.4A
0_0402_5%
<13,23> VGA_PWROK 1 2 GPU_VID1 GPU_VID0 Core Voltage Level Ipeak=19.16A
2
Iocp=24A
PR912 PX@
0_0402_5% 1 1 0.9V
<14> GPU_VID0 GPU_VID0 1 2
PR913 1 0 1.0V
0_0402_5%
<14> GPU_VID1 GPU_VID1 1 2
PX@ 0 1 1.1V
0 0 1.15V
PR914
@ 0_0402_5%
1 2 VRON_VGA
<10,36,39,43,44,45> SUSP# +1.5V
2
3 PR915 3
+5VALW PJ904
@
1
DGPU_PWR_EN1 2 2 1
<22,39,50> DGPU_PWR_EN +VGA_PCIEP +1.0VS_DGPU
1
PX@ PJ903 2 1
1
0_0402_5% PC917 JUMP_43X79 JUMP_43X79
PX@ 0.1U_0402_16V7K
1
PC918 PX@ @
2
1U_0402_6.3V6K
2
2
PX@
@ PR916 PR917 PX@
+VGA_PCIEP
1
10k_0402_5% 10K_0402_5% PC919
VGA_PCIEP=1.0V
6
2
RB751V-40_SOD323-2 7 VIN
@ PX@ 1 2 POK 4 Ipeak=2.94A
PR918 PR919 VOUT
+VGA_PCIEP Iocp=3.528A
10k_0402_5% 10K_0402_5% 3
VOUT
22U_0603_6.3V6K
+3VS 1 2 GPU_VID1 1 2
1
DGPU_PWR_EN 1 2 8 2 PX@
<22,39,50> DGPU_PWR_EN EN FB PX@
PC921
PR920
GND
40.2K_0402_1% 9 PR921
2
VIN 1.15K_0402_1%
PX@
1
0.1U_0603_25V7K
APL5912-KAC-TRL_SO8
1
2
PX@
1
PC922
PX@
VGA_PCIE 1.0V 1.1 V
@ PR922
20K_0402_1% PC920
2
PX@ 0.01U_0402_25V7K
2
PR923 4.53K 3K
PR923
4.53K_0402_1%
2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-VGA_CORE/VGA_PCIE
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, July 16, 2012 Sheet 50 of 50
A B C D
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