272 Electronic

Figure 12.55
evices and Croa
(a) shows shunt particularly in digital
circuits, because of relatival
thousands of devices can be fabricated in a singleely small siz
IS employed circuit where he
a

1dentical to the
as
voltage
a
variable resistor. This
Jr
JFET shunt switch
discussed
circu cuit (IC). Since it is
constructed with the gate te graei
difference is that the
gate bias voltage (control earlier.
ninal
aoes not
swing from 0 to a large negative value. voltage) Gs
from the channel. it may be referred to generalt
insula
lated-gate field-efect transistor (1GFET). Howe
an
Can
vary Instead,
Gs
continuously i.e.. it
can have
any value between
of such devices are made using silicon for the semicnce
and VGs ioff Thus, Vos controls the resistance of the Sio, for the insulator. and metal or heavily doped
which then
changes the JFE for the gate electrode. the tem metal-oxide-semico
peak output voltage.
Figure 12.55 (b) depicts a series circuit
with the JFET
effect ransistor (MOSFE) or simply MOS is comtorfel
used as a
voltage variable resistor. The basic idea is the MISFET is the more general term, where the insulator
ator is
same. By
varying Vos. the ac resistance of the JFET can be essarily silicon dioxide (SiO,) and the semiconductor is not t
vared. which causes variation sarily silicon (Si). Here discussion will be about MOsE
in the peak output voltage.
VP
Application of VVR in Automatic Gain Control. Since though the same physics applies to the MISFETs. SFETs
the FET
operated. as described above. behaves like a variable Like. JFET.
a a MOSFET is also a three terminal (s
resistor, it finds applications in gate and drain) device and drain
many areas where this property current in it is also co
is useful. The VVR for
example. can be foremployed varying
by gate bias. The operation of MOSFET is similar to th ontrolle
the voltage gain of
vanes.
a
multistage amplifier as the signal level JFET. It can be employed in any of the circuits covered
fr
JFET and, therefore, all the equations apply equally well
to
When a receiver is tuned from a weak to a MOSFET and JFET in amplifier connections. Howete
the loudspeaker will blare strong station,
(become loud) unless the volume MOSFET has lower capacitance and input impedance much e
is immediately reduced. The than that of a JFET owing to small leakage current In
volume may also change because case of
of fading. a decrease in MOSFET the positive voltage may be applied to the
signal caused by a change in the gate ani
path between the transmitter and receiver. To avoid undesirable sill the gate current remains zero.
variations in the volume. automatic MOSFETs are of two types namely (i) enhancement
gain control (AGC) is ne
used in most modern receivers. MOSFET or E-MOSFET and (ii) depletion type
The basic idea of AGC is
MOSFET
DE-MOSFET. In the depletion-mode construction a chamel is
depicted in Fig. 12.56. An input
signal vin is passed through a JFET employed as a VVR. The physically constructed and a current between drain and soue
signal is amplified to get the output voltage vou Theoutput
is due to voltage applied across the drain-source terminas.
The
signal is fed back to a negative peak detector. The output of enhancement MOSFET structure has no channel formed
durmg
this peak detector supplies the its construction. Voltage is applied to the
gate bias voltage for the VGs gate, in this case. to
JFET develop a channel of charge carriers so that a cureni results
when a voltage is applied across the drain-source terminals

AMPLIFIER The enhancement type MOSFET

(E-MOSFET is widely
used in both discrete and
integrated circuits. In discretæ circuits,
the main use is in power
switching, which means urning larges
currents on and off. In ICs, the main use is in
digital switching
the basic process behind modern
NEGATIVE computers. Although their us
is declined, depletion-mode MOSFETs (DE-MOSFETS) are sal
PEAK DETECTOR
found in
Fig. 12.56. Automatic Gain Control (AGC)
high-frequency
front-end communication circuis
RF amplifiers.
In case the input signal gets strengthened by a considerable
12.21. DEPLETION TYPE MOSFETs
amount, he output voltage will increase. t means that a (DE-MOSFETS)
large negative volage comes out of peak detector. Since VGs In Art. 12.2.5 we have seen
that when the gate is biased negau
becomes more negative, the JFET has a higher ohmic resistance, w.r.t. the source in an
which reduces the strengh of the signal supplied to the amplifier
N-channel JFET, the depletion-eg
wIdths are increased. The increase in the depletion regions
and thus output signal is reduced. reduces the channel thickness, which increases its resista
On the other hand, if the input signal becomes weaker, The net result is that drain
the output voltage falls and the negative peak detector gives
current In is reduced.
If the
polarity of VeG were reversed so as to
aPP
a smaller output. Since VGs becomes lesser negative, the positive bias to the gate een

JFET transmits stronger signal to the amplifier, which raises

w.r.t. source, the
the gate and the channel would then be forward biased. S1nc
P-Njunctuons an
the output. Thus the effect of any sudden change in the input a forward bias reduces the width of a
signal is offset or at least reduced by the AGC action.
depletion e i
thickness of channel would increase with a coTesp
ECrease in channel resistance. AS a result, drain curen
12.20. METAL-INsULATOR-SEMICONDUCTOR WOuld increase
FIELD-EFFECT TRANSISTORS (MISFETSs) beyond the JFET's Inss value. depletion mode

The normal
operation of a JFET is in its
The metal-insulator-semiconductor field-effect iransistor of operation. However, as discussed:above, it is also pos.
to enhance the conductivity of the JFET channel ro
icwt
eevd
e
MISFET) is one of the most wIdely used electronic devices,
the forward bias of the silicon P-N restncte

junction is usuauy
 Feld-Eftect Transistors
273
0.s V (more conservative limit is 0.2 V) so
navimum of mpedance of most JFETs is sufficiently high for applications,
current G IS
Because of very high input impedance, the gate
cument.
limit the gate
to
s As have seen in Art. 12.9,the greater the ly is compared essentially zero for dc-biased configurations.
nsthe greatertht e transconductance s,, will be. In Arts. 12.14
1216 we have seen thatthe voltage gain is directly proportional 12.21.2. Operation
S o . in general. the higher the S the better it is. This It is obvious from Fig.12.57 that there is no P-N junction
diffused channel N, the
able to enhance the channel. between gate and channel. Here the
of the advantages being
of
s one the metal layer of the gate
its name suggests,
the depletion-enhancement MOSFET insulating dielectric Si0, layer and
As DE-MOSFET can be operated
was developed to be used in either or both forms a parallel plate capacitor.
When gate is positive
E-MOSFET)

and enhancement modes. With either a positive or a negative gate.

the depletion in thc enhancement-or
With respect to the source it operates
12.21.1. Construction w.r.t. the source, as
E-mode and when the zate is negative
shows the construction of an
N-channel DE. in depletion-mode.
1257 illustrated in Fig. 12.58, it operates
Eicure
lightly doped P-type substrate into
It consists of a VDD
MOSFET.
ot doped N-type material are diffused
uhich two blocks heavily
and drain. An N-channel is formed by
foming the source
between the source and drain. The type of impurity
diffusion SiO2
is the same as for the source and drain. Now
for the channel GG DIELECTRIC

of SiO, dielectric is grown over the entire surface

a thin layer D
cut through the Si0, (silicon dioxide) layer to
and holes are
with the N-type blocks (Source and Drain).
make contact
the holes to provide drain and
Metal is deposited through
and on the surtace area between drain and
source terminals, N
metal deposited. This layer constitutes the
plate is
sOurce
in an extremely high input impedance
gate. SiO, layer results The chip area
of the order of 10
to
10 2 for this device.which is about
N-CHANNEL

0.003 um* or les P-TYPE SUBSTRATE

of a MOSFET is typically
a BJT.
only 5% of the area required by DIFFUSED Fig. 12.58. Depletion Mode Operation
S1O2 CHANNEL
with respect to source, a drain
DIELECTRIC When the drain is made + ve
the MOSFET
SOURCE GATE
ALUMINIUM current will flow, even
with zero gate potential and
G DRAIN in E-mode. In this mode of operation
S
D is said to be operating the P-substrate to the
the- ve charge carriers from
gate attracts increases
channel resistance and
N-channel and thus reduces the
more positive the gate
is made, the more
the drain current. The
drain current flows.
N On the other hand when the gate
is made - v e with respect
carriers
some of the -ve charge
to the substrate, the gate repells
in the
This creates a depletion region
P-TYPE SUBSTRATE out of the N-channel. increases
12.58, and, therefore,
channel, as illustrated in Fig. The more
drain current.
and reduces the
the channel resistance
DE-MOSFET Structure
less the drain current. In this
mode of operation
Fig. 12.57. N-Channel -ve the gate, the
MOSFET. Here
like an N-channel to as a depletion-mode
A P-channel DE-MOSFET is constructed
the device is referred channel. Thus
P- can pinch-off the
an N-type
substrate and diffusing too much negative gate voltage
DE-MOSFET, starting with
them internally by that of JFET.
blocks and connecting operation is similar to
ype drain and source
12.21.3. Characteristics
a P-dopped channel region. connected to the
the substrate is internally various levels of gate-
In some cases
additional terminal
labelled
Typical drain characteristics, for
others an are shown in
urce terminal S and in device. source voltage,
of an N-channel MOSFET
terminal and the
a four curves are for positive Vos
S provided resulting in
1S
is a type of insulator referred
to as a
Fig. 12.59. The upper The bottom drain curve is
ilicon dioxide (SiO,) the prefix lower curves are for negat've VGS
indicated by
opposing (as FOor aspecified drain-source voltage VDS
electric, which develops dielectric when
exposed to
an
for VasVGs (OFF)
electric fields within the
Is the gate-source voltage atwhich drain current
) is an insulating
The fact that
the SiO, layer VGs (OFF) small value, as shown
AIemally applied field. connection
between
reduces to a certain specified negligibly
direct electrical to the pinch-off voltage
in Fig. 12.59. This voltage corresponds
means that there is no MOSFET. It is
the
r the channel of a between Vcs (OFF) and zero, the device
G and
V of JFET. For Vas
accounts
terminal that
gate the MOSFET
construction
while for Ves exceeding zero the
in
ating layer of SiO,
impedance of the
device.
operates in depletion-mode
These drain curves
tne very desirable high
input much
MOSFET is usually device operates in enhancement mode.
resistance of
a
n lact, the input though the input
JFET, even
ICr than that of a typically
 Electronic Devices and
274 CirKcuicuites
basic formulas are used to determ
gain display an ohmic region, a constant current source here the same rmine the drai
Ip gate-source voltage VGsetc.
region and a cutoff region. MOSFET has two current
major applicalions. discussion is applicable in
viceinciple also
a constant The foregoing
current source and a variable resIstor. DE-MOSFET. For such a device
voltage to the P-channel the
in the characteristics
cs \Figs. 12.59of sign
Vos15VN all currents and voltages
reversed.
and 12.60] must be
VGs1.0 V 12.21.4. Schematic Symbols
the schematic symbol for a DE.MC
2 Vos05V Figure 12.61 (a) shows SFET.
Just to the right of the gate
is the thin vertical
line
Vas 0V the channel. The drain lead comes out from the representing
connect to the
top of the
Vos-1V channel and the source lead bottom.
arrow is on the
P-substrate and points to the N-mat The
Ves-2V In some applications, a voltage can be applied to t naterial.
Vos-3V he
substrate for added control of
drain current. For this ren
leads. But ineason,
Gs(OFF)
12 16 20
some DE-MOSFETs have four terminal
DRAIN-SOURCE VOLTAGE, VDS IN VOLTS
most
applications, the substrate is connected to the soure
Usually the substrate is connected to the source internall
Fig. 12.59. Drain Characteristics by the manufacturer. This results in a three terminal device
whose schematic symbol is shown in Fig. 12.61 6).
Schematic symbol for a three terminal P-channel DE.
MOSFET device is shown in Fig. 12.61 (c). The schematic
DEPLETION ENHANCEMENT
symbol of a P-channel DE-MOSFET is similar to that of an
MODE
MODE
N-channel DE-MOSFET, except that the arrow points outward,
12.21.5. DE-MOSFET Amplifiers
lpss
DE-MOSFET can be operated either with positive or negative
gate, so its operating or quiescent point can be set at Vos =0 V.
as illustrated in Fig. 12.62 (6). In Fig. 12.62 (a) the gate G is
at ground potential for dc since ac signal source appears to be
short circuited for de and sets Q-point at Vcs =0 V. The ac
input signal causes the gate-source voltage V, to vary above
GSIOFF and below zero developing drain current
Ip and drain voltage
Vou The biasing circuit given in Fig. 12.62 (a) has Ve = 0V
Vos -VGS Dpss and de drain voltage
IN VOLTS IN VOLTS

Fig. 12.60. Transfer Characteristic

DSsVDDpss Rp ..(12.51)

The transfer (or transconductance) characteristic for an 0* VDD

N-channel DE-MOSFET is shown in Fig. 12.60. Inss is the TRANSFER
CHARACTERISTIC

drain current with a shorted gate. Since the curve extends to D

the right of the origin, Ipss is no longer the maximum 2 OUTPUT
possible SIGNAL
drain current. Mathematically, the curve is still part of a
parabola and the same square-law relation exists as with a
JFET. In fact, the depletion-mode MOSFET has a drain current
given by the same transconductance equation as before,
E -V

Eq. (12.1). Furthermore, it has the same equivalent circuits INPUT

RG SIGNAL
as a JFET. Because of this, the analysis of a depletion-mode
MOSFET circuit is almost lentical to that of a JFET
circuit.
The only difference is the analysis lor a positive gate, but even
(a)
Fig. 12.62 (b)
D DRAIN
The zero bias ol
D DRAIN
Do DRAIN
D DRAIN Fig. 12.62 (a) is unique
SUBSTRATE SUBSTRATE with depletion-mode
MOSFETs. Although
JFET bjas-
b SOURCE
SOURCE
GATE any of the
s 60URCE sOURCE will work
Ing method
(a) (b) N-Chunnel DE-MOSFET with a depletion-mode
bias
Fig. 12.61. Schematic Symbols For c)P-Channel DE-MOSFET MOSFET, the zero-
DE-MOSFETs
 Field-Effect Transistors
275
in Fig. 12.62 («) is preterred as it does the the JFET and is as given12.64. The transconductance
in Fig.
shown
ethoa
od
and the interelectrode capacitances have
comparable values
and adequately. in
sinmply the figures given
job MOSFET to a Q-point, it Tor the two devices, as obvious from
biasing the depletion-mode
After in Table 12.3, the
drain
The JFET mulas for voltage gain Table 12.3. However, as indicated
small signals. much smaller than that
anplity resistance r, of the MOSFET is very
to a MOSFET amplifier. But like the JFET,
an the
applied directly from Table 12.3 that
can be of the JFET. II is also to be noted
MOSFET has a relatively low voltage gain. are very
the pletion-mode feedback resistance rd
low-noise properties, a detinite advan- Input resistance r and the JFET.
OSEETS have excellent much larger for the MOSFET
than for the
tront end of a where the connected to the source,
for any stage near the eceiver. As system If the substrate terminal is
G, not
TV with a JFET, the followsS:
ienal is weak, such ascase MOSFET.can be controlled
a be generalized as
the model of Fig. 12.64 must
nsconductance s,
n of by MOSFET
trans to the fact that a DE. Values For JFET and
voltage V Due TABLE 12.3. Range of Parameter
arving the gate-source
an on device, it is also possible to use MOSFET
MOSFET is normally Parameter JFET
a source resistor. The operation beconmes the
self-bias by adding 0.1- 10 mS
0 . 1 - 2 0 mS or more
JFET circuit.
same as
a selt-biased
Sn M2
I.0- 50 k2
0.1-
Sketch the transfer characteristic for an 0.I-1pF
Example 12.32. 0.1 1 pF
type MOSFET with IDSs = 10 mA and
N-channel depletion 1.0 10 pF
I.0 10 pF
10 Q
- 4 V. 10
Solution: From Eq. (12.1) gd
D D S S = 1 0 mA
At VGs = 0.
D

D 10 mA| I5.625 mA
AtVas ds

AtVGs IV
10 mA1 =5.625 mA T 9m'gs

Model
Fig. 12.64. Small-Signal MOSFET
mA is added to represent
At Vas-2 V. D 10mA1-25 Between node and S, a diode
G,
substrate and
D,
the source. Similarly
the P-N junction between the
and D to account G,
0 mA a second diode is included between
D,
10 mA |1-
=

p drain.
AtVcs-4V for the P-N junction formed the substrate by and
shown in Fig. 12.63.
curve is drawn as
in Fig. 12.65
The transfer characteristic 12.33. The DE-MOSFET amplifier given
Example 4S. Determine
18 2 V, = 4 mA,
DSs and smo 2,000 =
has VGsofn circuit.
the output voltage of the
16
+WDo 20 V
Ro 2.5 ks2
oul

AL 20 k2

DsS
2 0 mV Rg 1 M2

Fig. 12.65

0 and Ip 4 mA
Vas
=

Solution : With the source grounded,

=

Drain-to-source voltuge,
20-4x 10 x 2.5 x 10' = 10V
VsVDD- lp Rp
=

Since Vas 0 V. s
= =
8mo
= 2,000x 10° S
2.5 k2 || 20 k2
2 The output resistance, rut Rp ll R =

-1
-3 -2
VGs IN VOLTS _2.5X 20 k2 =2.22 k2
2.5+20
For An N-Channel
Depletion Voltage gain, Ay = Sn u t
ig. 12.63, Transfer Characteristic =4V 2,000 x 10 x 2.72 x 10 = 4.44
= 10 mA and V,
Type MOSFET With 1Ns Ans
Output voltage. vut Ay X =444 x 20 mV =
888 mV
MODEL
12.22. MoSFET SMALL SIGNAL 12.23. ENHANCEMENT-ONLY MOSFET (E-M0SFETs
and drain are

t h e small bulk resistances of the source

MOSFET Although DE-MOSFET is useful in special applications, it does
circuit of the
eglected, the small-signal equivalent identical with that for not enjoy widespread use. However, it played an important role
Delween terminals G (G,), S,
and D is
 Electronic Device
276 and Cirouts
When drain is applied with +ve voltage with r
istory because it was part of the evolution towards the E-moue and no potential is applied to the gate, the twe respect to soirCA
rE a device that has revolutionized the electronic
ndustry. E-MOSFET has become enormously important in digta
and
back
one P-substrate
form two

with a resistance of the

P-Njunctions conn
P-substrate, Both
the
Nrbceackgiosto
elecironics and computers. In the absence of E-MOSFETs, the cannot be forward biased at the same time, so only a
junctiong
an extremely
Personal computers (PCs) that are now so widespread would
not exist.
small drain current i.e., a reverse
leakage curre
substrate iS now connected to s, i
the sour
the P-type source
there is zero voltage across the source-substrate
terminal,
12.23.1. Construction
the drain-substrate junction remains reverse biased junction,
Figure 12.66 shows the construction of an N-channel E-MOSFE
the en the
with respect to the source and
Ihe main difference between the construction of DE-MOSFET gate is made positive
negative (i.e., minority) charge carriers within the s substrale
and that ofE-MOSFET, as we see from Figs. 12.57 and 12.66
attracted to the +ve gate and accumulate close to the su. substrate
respectively, is that in E-MOSFET substrate extends all the
substrate. As the gate voltage is increased, more and moreahe
way to the silicon dioxide (Si0,) and no channels are doped
accumulate under the gate. Since these electrons eanon
between the source and the drain. Channels are electrically induced
across the insulated layer
of silicon dioxide to the o
in these MOSFETs, when a gate,
positive gate-source voltage Vcs accumulate at the surface of the substrate just below they
minority charge carriers make an Ng
the
is applied to it.
These accumulated
METALLIZATION
channel stretching from drain to source. When this
LAYER
channel is induced by forming what iS termed an inversion n
Dccurs, a
DRAIN
GATE
SOURCE G
D (N-type). Now a drain current starts flowing. The strength ofh
drain current depends upon the channel resistance, which in tin
SiO2 depends on the number of charge carriers attracted to the positie
DIELECTRIC
LAYER gate. Thus drain current is controlled by the gate potential,
Since the conductivity of the channel is enhanced by the
+ve bias on the gate, this device is called the enhancemem
N-DOPED MOSFET or E-MOSFET.
N-DOPED REGION
The minimum value of gate-to-source voltage Vcs that is
REGION
required to form the inversion layer (N-type) is termed the gae
to-source threshold voltage VosST. For VGs below VGST, the drain
current I =0. But for Vas exceeding VGST an N-type inversion
layer connects the source to drain and the drain current I is
NO CHANNEL
large. Depending upon the device being used, VST may vary
from less than 1 V to more than 5 V.
SUBSTATE
JFETS and DE-MOSFETs are classified as the depletion
Fig. 12.66. A Metallic Crystal Structure
mode devices because their conductivity depends on the action
of depletion layers. E-MOSFET is classified as an enhancement
mode device because its conductivity depends on the action of te
Inversion layer. Depletion-mode devices are normally ON when
ALUMINIUM
METALLIZATION
the gate-source voltage Vos = 0, whereas the enhancement-moue
LAYER devices are normally OFF when Vgs = 0.
D
12.23.3. Characteristics
,SIO2 Drain characteristics of an N-channel E-MOSFET are shown n
Y DIELECTRIC
LAY ER Fig. 12.68. The lowest curve is the Vcsr curve. When YGs

INDUCED
N-CHANNEL
Vas4.0 V
P-TYPE SUBsTAATE
Vos3.0
Fig. 12.67. Operation of N-ChannelE-MOSFET Ves2V
12.23.2. Operation Gs1V
VoST
As its name indicates, this MOSFET operates only in the 20
4 12 16
enhancement mode and has no depletuon mode. It operates with DRAIN-SOURCE VOLTAGE, VDs IN VOLTS
large positive gale volage only. It does not conduct when gate
Fig. 12.68. Drain Characteristics
source voltage Vas =0. This is the reason that it is called lesser than grealer

than VaST,osT
In these MOSFETs drain current is approximately When Vcs
zero.
normally-of MOSFET. the device turns on and the drain current
only when Vos exceeds GST LBaie-l0-Source threshold voltagel have
controlled by the gate voltage. es
The characteristic cu
 Field-Effect Transistors

277
and almost hornzontal parts. The almost vertical
al and
almost vertical
12.23.4. Schematic Symbols
mponents of the curves correspond to the ohmic region, and
components correspond to the constant current
honzontal
Schematic symbols for an N-channel E-MOSFET are shown in
tne Thus E-MOSFET can be operated in either of these Fig. 12.70 (a). For zero value of Vgs. the E-MOSFET is OFF
region.

regions
1.e.. 1l can be used zas because there is no conducting channel between source and
resistor drain. Each of schematic symbols shown in Figs. 12.70 (a) (i)
variable voltage
a
as a constant 12DON) and 12.70 (a) (ii), has broken channel line to indicate this nor
or
VVR) mally OFP condition. As we know that for VGs exceeding the
current source
12.69 shows a threshold voltage VcsT, an N-type inversion layer, connecting
Figure
ypical transconductance
the source to drain, is created. In each of the schematic sym-
bols, the arrow points to this inversion layer, which acts like an
curve.
The current
IDSs at
N-channel when the device is conducting. In each case, the fact
small, being
Vos0 is very few
that the device has an insulated gate is indicated by the gate not
order of a
of the making direct contact with the channel. The schematic symbol
nanoamperes. When the V GS
the drain shown in Fig. 12.70 (a) (ii) shows the source and substrate in-
is made positive, DSS GSO ternally connected, while the other symbol shown in Fig. 12.70
increases slowly at
current GST 6 (a) (i) shows the substrate connection brought out separately
much more
first. and then -GATE-SOURCE VOLTAGE,
from the source.
with an increase in Vas IN VOLTS
rapidly The schematic symbols for a P-channel E-MOSFET are
manufacturer ig 12.69. Transfer Characteristic
Vc The shown in Fig. 12.70 (6). In these cases the arrow points outwards.
sometimes indicates the gate-source threshold voltage VcsT at
which the drain current ip attains some defined small value, say 12.23.5. E-MOSFET Data Sheets
10 uA. The current Ip ON) COrTesponding approximately to the As already mentioned above, there are three key quantities
maximum permissible value of drain current given on the drain Data sheets may
characteristics and the values of Vgs required to give this current
p (ON GST and Vas (ON)] with E-MOSFETs.
one and one contain
vary from one manufacturer to another may
also usually given on the manufacturers data sheet. some informations somewhat different from those given in
VcsON are
The equation for the transfer characteristic does not obey another manufacturer's data sheet. But almost all data sheets
Eq. (12.1). However, it does follow a similar "square-law type" regarding VosT Io (oN) and
of relationship. The equation for the transfer characteristic of E
include information
information regarding VGs (oN Some also include information
most include
MOSFETs is given as on the drain resistance Rps. This resistance may be symbolised
Ip = K(VGs-VosT 12.52) Rps or it may appear as rDS(ON) "ds (ON) etc.
where K. typically 0.3 mA/VÍ, is a property of the device 12.23.6. MOSFET Biasing
construction. Note that Ipss cannot be assocíated with an
MOSFET bias circuits are quite similar to the circuits used for
EMOSFET, because no drain current flows with VGs 0 volt. =
JFET biasing. In the case of DE-MOSFETs, the gate-source
With JFETs and DE-MOSFETs, the value of Ipss and
voltage Vcs may be either positive or negative in both N-channel
GS OF, are the key quantities required for analysis. With and P-channel devices. Any of the JFET bias circuits already
E-MOSFETS, the key quantities are Ip ON VoST and Vas(ON discussed can be used to give a negative Vcs for an N-channel
indicated in Fig. 12.69. These three quantities are the first items device, or a positive Vas for a P-channel device. To operate
o look for on a data sheet. By substituting these quantities in an N-channel MOSFET in enhancement mode (cither a DE-
Eg. (12.52), the equation can be arranged in a more useful form: MOSFET or E-MOSFET), the gate is required to be biased
Ip = Klp ON .(12.53) positively with respect to the source. The self-bias circuit is
unsuitable in such a case, and if fixed voltage bias is to be used.
where K =-Ves-VosST_ .12.54) VCs must be a positive quantity. The same remarks apply for a
VGs (ON YGST P-channel MOSFET operating in E-mode, except that the gate
must be rade negative w.r.t. the source.
The input impedance of the E-MOSFET is very high (of the
A popular cireuit arrangement for biasing the N-channel
from
Order of 102) as the gate ofthe E-MOSFET is insulated E-MOSFET is shown in Fig. 12.71. Resistor R,brings a suitably
the channel. Transconductance for this device ranges typically large voltage (Vas>Vs)to the gatetodrive theE-MOSFET on.
from 1,000 uS to 2,000 uS (or I to 2 mA per volt).
D DRAIN
D DRAN D DRAIN D DRAIN
D DRAIN

BUBSTRATE 8UBSTRATE
6UBSTRATE
U
GATE OATE OATE
GATE SSOURCcE
6 60URCE 88OURCE 0OURCE
s soURCE (ii)
(i) (ii) (b) P-Channet B-MOSPET
(aj N-Channel E-MOSFET
Fig. 12.70. Sehematie Symbols For -MOSFETs
278 Electronic Devices
and Circuits
he drain current l increases
until an equilibrium condition o
Ds (or VGs) and drain current In is established. The MOSFET
drain curTent is fixed by Vcs as given by Eq. (12.52). The
drain current
I causes a voltage drop across Rp. S0 tnat
Ro1
..(12.55) D

2
s

Fig. 12.73. Potential Divider Biasing Circuit For SFET

Vas- VpD
Here VGs V2 Rp, +Rp RD2 .(12.58)
and Vps VDD - p Rp

Fig. 12.71. Drain Feedback 12.59)

Biasing Circuit For E-MOSFET where Ip K
(VGs -V
Since the gate current The value of resistors used in this divider circuit is
IgG 0, the voltage Vos VDS
=
SO
quite
Eq. (12.52) may be written as high as E-MOSFET gate draws very littlee current due to the
insulation layer.
Ip K(VpS VasST .(12.56)
With Vs =
0 volt, the value of is 12.23.7. E-MOSFET Amplifier
Vps
VDs = Vp -Vs = VpD - Ip Rp An N-channel E-MOSFET having a
(12.57) potential divider bias is
If tries to increase due to some reason (say due to shown in Fig. 12.73. AC signal source is applied to the
gate
increase in temperature) through coupling capacitor C and the gate is biased with a
Vps will decrease due to larger voltage positive voltage such that Vas>
drop in Rp and cause VGs to decrease. So Ip will decrease to
As illustrated in Fig. 12.74, the
GST
overcome the original increase in
Ip. Thus operating or quiescent input signal voltage
point remains fixed. produces a swing below and above its Q-point. This, in um,
causes a swing in drain current
If for of linearity in device
reasons
operation or maximum Ip: Thus Vp or Vu Vares being
output voltage, equality of Vas and Vps is not desirable, equal to VpD- IpRp
then the circuit shown in Fig. 12.72, known as
bias circuit may be used. Here, the
drain-to-gate OUTPUT
gate bias voltage is SIGNAL
TRANSFER
CHARACTERISTIC
R VpS
VGs R+Ry This circuit also, like that shown in
Fig. 12.71, offers the dc stabilization through the feedback DO
resistor R However, the input resistance is reduced
because
of the Miller effect,
R,corresponds
to an equivalent resistance,
R R0 -Ay) shunting the
amplifier input.
Also, the voltage divider biasing technique (circuit shown
in Fig. 12.73) can be used for E-MOSFET. Here the de
stability
is accomplished by the feedback through source resistance R.
VpD

S
GST -VGs IN vOLTS
R
ww-
VOut INPUT SIGNAL

Gsa
Un

Fig. 12.74
12.23.8. E-MOSFET
Ideal drain Equivalent Circuit
curves
All drain curves
for an E-MOSFET
are shown in
12.75.
Fig. 12.72. lmproved Version of Circuit Showa in Fig. 12.7/
superimpose in the ohmic region to give
single, almost vertical line and are horizontal cumen

in tne
 Field-Effect Transistors

sourceregion.
There is 279
no breakdown region. 12.24. MosFET RESISTOR
These ideal drain
The MOSFET can be employed as a resistor. DE-MOSFET can be
are
similar to
curves
depleti0n-mode employcd resistor by connecting the gate to the is
as a source, as

except for the shown in Fig. 12.77 (a), that gate-to-source voltage VGs
so zero.
curves,
proportional knee E-MOSFET may also be enmploycd as a resistor by connecting the
gate to the drain, as shown in Fig. 12.77 (h) so that gate-to-source
voltage VK
which is Vas VasT vollage VGs becomes equal to drain-to-source voltage Vps
given as

V Rps (12.60) NGS D

This voltage V'k is
DRAIN-SOURCE VOLTAGE,
between the Vps IN VOLTS-
the border
the
ohmic region and Fig. 12.75
source region in G
curment
an ideal enhancement-mode device. This border concept is
identical to Vp. Since E-MOSFET does not have a pinch-off
voltage where depletion layers meet together, S
p i8 not used.
loctead, they have an inversion layer. Becausea different physical (a) DE-MOSFET (b) E-MOSFET
mechanism is involved, symbol V g is used for the border between
Fig. 12.77. MOSFET Resistor
the two regions.
Two ideal equivalent circuits for an E-MOSFET are shown
12.25. MOS CAPACITOR
in Fig. 12.76. These equivalent circuits are the sane as for
The metal-oxide-semiconductor (MOS) capacitor shown in
aJFET. except for Ip (ON)and the positive gate-source voltage.
In other words, the E-MOSFET can operate like a voltage Fig. 12.78 (a) is the heart of the MOSFET. The metal may be
variable resistor (VVR) or like a constant current source aluminiunm or some other type of metal. In most cases, the metal
depending upon the location of the operating point. The is replaced by a high-conductivity polycrystalline silicon layer
proportional knee voltage is the guide. When VDs exceeds
VK the device is a constant current device and Vn below 9 GATE TERMINAL
METAL
Vg the device is a resistor. INSULATOR
(OXIDE)
P-TYPEh FIELD
|SEMICONDUCTOR
SUBSTRATE
Vos Ras DS Yos Ros ~ os DS sUBSTRATE
KlDON)
(a) Basic MOS Capacitor (b)
Structure
(a) (b) E-FIELD

Fig. 12.76. ldeal Equivalent Circuits For E-MOSFETs

Example 12.34. An N-channel E-MOSFET with the common-

source amplifier, shown in Fig. 12.73, has the following parameters:

P-TYPE
DON4 mA at VGsoN)=8V, VGsr=4 V, 8m = 2,000 juS.
ACCUMULATION LAYER
Determine gate-source voltage Vcs, drain current Ip, drain-
OF ELECTRONS
sOurce voltage Vps and output voltage if in the circuit shown,
(c)
40 k2, 6 k2, Vpp 15 V and ae
Ro= 60 k2, Rp =
R = =

input signal is of 80 mV.

Solution: Gate-source voltage,
15x 40 6 V Ans.
Gs RpVDDxRD2
+Rp2 60+40 INDUCED NEGATIVE
TYPE
SPACE CHARGE REGION

K
Ip ON) 4
0.25 mA/V (d)
(8-4)2
(Vos(ON) VaST)
So drain current,
(6 4) I mA Ans.
K(VGs VosT)
=
0.25
D
-
- =

Drain-source voltage,
15 (1 mA x 6 ks2) = 9 V Ans. P-TYPE
VDD pRy = -

DS
-

ELECTRON
Voltage gain, INDUCED NEGATIVE INVERSION
SPACE CHARGE REG ION LAYER
6 10' 12
= 2,000 x
10 x x =
(e)
So output voltage. ig. 12.78. MOS Cupacitor
I2 80 x 10 = 0,96 V Aus.
Ou A, x Vi= x
 Electronic Devices
280 and Craulg
source for unit no. 2. TH
I and us the curre
drain for unit
no.
deposited the oxide. However, the term metal is still useu
on controlled by the
flow through the MOSFETis voltag of bouth
referring MOSFETs. In the figure, the parameter S
to current Ip can be cutoff by making
thickness of the oxide and e is the permittivity of the Oxide. the gates. Drain either gle
sufficiently negative.
A MOS capacitor with a P-type semiconductor substrate is MOSFET may be considered toL e
The dual-gate the coun
shown in Fig. 12.78 (b). The top metal terminal, also known as tetrode (or pentode), due to the
terpart of a controllin
(a) may capabili.
the gate, is at a positive voltage with respect to the semiconduCtor
ties exerted by two gates. Although, Fig. 12.79
Substrate. We can see that a positive charge will exist on the top
a symmetrical
device, it is Gate number
I provideo Sugges
that
plate and an electric field will be induced in the direction of the two units (each gher
metal forward transconductance (&)
the figure. If the electric ficld penetrates the
shown in the same value of cutoff voltage, however). So, the
signal
s

semiconductor, holes in the P-type material will experience a

amplification is connected to Gate 1, while Gate 2 haundr
force away from the oxide-semiconductor interface. As the holes
age that is to control the gain in an Automatic ol
Gain Cont ol (AGC)
are
pushed away from the interface, a negative space-charge
region is produced, because of the fixed capacitor impurity
application.
Symbol indicating the substrate and case tied to t
atoms. The
to the source
negative charge
in the induced depletion region is shown in Fig. 12.79 (b).
corresponds to the negative charge on the bottom plate of the
MOS capacitor. Figure 12.78 (d) shows the equilibrium distribution 12.27. PoWER MOSFETS (OR V-FETs)
of charge in the MOS with this
capacitor applied voltage. Power MOSFETs are usually constructed in V-configurati
When a larger positive voltage is
applied to the gate, the mag-
nitude of the induced electric field increases. Minority carrier elec-
as shown in Fig. 12.80. That is why, the device is
etimes someti
called the V-MOSFET or V-FET. V-shaped cut penetrale
trons are attracted to the oxide-semiconductor interface as shown from the device surface almost to the N substrate throuok
in Fig. 12.78 (e). This
region of minority carrier electrons is known N, P and N layers, as seen from fig. 12.80. The N
as an electron inversion
layer The magnitude of the charge in the layers are heavily doped, low resistive material, while the
inversion layer is a function of the applied gate voltage.
The same basic charge distribution can be obtained in a MOS
N layer lightly doped, high-resistance region. The
is a

silicon dioxide dielectric layer covers both the horizontal

capacitor with an N-type substrate. surface and V-cut surface. The insulated gate is metal
The term enhancement mode means that a
voltage must be film deposited on the Si0, in the V-cut. Source
terminals
applied to the gate to produce the electron inversion layer. For make contact to the upper N* and P-layers
the MOS capacitor with a through the Sio,
P-type substrate, a positive voltage layer. The N* substrate is the drain terminal of the device.
must be applied to
produce the electron in version layer, for the SOURCE GATE
SOURCE
MOS capacitor with an N-type substrate, a
negative gate volt- METAL
S

age must be applied to produce the hole inversion layer. FILM

12.26. DUAL-GATE MOSFET

s N*
*
Z
LAYER
ACIRC

Cross view of a dual-gate N-channel

depletion type MOSFET is P
shown in Fig. 12.79. It acts as if
two FETs are connected in
series, as is obvious from Fig. 12.79. The middle block acts as
N EPITAXIAL LAYER
SOURCE GATE No. 1 GATE No. 2 DRAIN SIO2
S
o D DIELECTRIC
METALLIZATION2
LAYER
N'SUBSTRATE
LAYER

D DRAIN
SOURCE DRAIN No. 1
No. 1 AND DRAIN
sOURCE No. 2 No. 2 Fig. 12.80. N-Channel V-MOSFET
N
N N V-MOSFET is an E-mode FET and no channel exists betwetn
DIFFUSED arain and source
DIFFUSED
CHANNEL
No. 1 CHANNELL the
regions until the gate is made positive w.rk
No. 2 source. On
P-TYPE SUBSTRATE
making
positive gate source,ofw.r.t. the
N-type channel is formed close to the gate, as in the
(a) Dual-Gate N-Chamnel Depletion Type MOSFET an
E-MOSFET. In this case, cast
DAAIN, D path for the N-type channel provides d
charge carriers to flow between the N SuOs
(Le., drain) and the N*
negative, no channel exists andtermination. When VGs Ze
source 1S
GATE 2
the drain current is
2erO.
ne drain and transfer characteristics for the enhancemc
GATE 1
mode N-channel power MOSFET are similar to those ro
tne
E-MOSFET, as illustrated in Figs. 12.68 and 12.69
soURCE, Ss
With the
reduced and,
increase in gate
voltage, the channel ress tance
respeets
(b) Synbol of a Dual-Gae N-Chanel Depletion Type
of MOSFEr the drain therefore, the drain current Ip Thus

Fig. 12.79 current ln can be

controlled
increu control
so that for a by gate voltag nt
over a wide given level of Vce, In remains Constant

fairiy
range of Vps levels.
Fiel-Effect Transistors
281
Drin terminal being at the bottom of the V-MoSFET
sd of at the top surface) can have a considerable large
Figure 12.81 illustrates +Vpo
how a digital IC can control HIGH POWER
for any gven
size of the device. This allows nmuch greater a high-power load. The output
LOAD
a
w e r dissipations than are possible in a MOSFET having of the digital IC drives the
at the surface.
th drain and source
gate of the power MOSFET. DIGITAL
ln the power or V-MOSFETs the channel length is When the digital output is1C POW ER
dremined by diffusion process, while in other MOSFETs MOSFET
high, the power MOSFET acts
channel length depends upon the dimensions of the
like a closed switch. When the
ASTaphic masks used in the ditfusion process. By controlling
digital output is low, the power Fig. 12.81. Power MOSFET as
the doping
density and the diffusion time, much shorter channels
are possible With mask control of channel
MOSFET acts like an open an Interface
an be produced than switch. Interfacing digital 1Cs
iength. These shorter channels allow much more current of
to a high-power loads is one of the important application
nsities. which again contribute to larger power dissipations.
power MOSFET.
Theshorter channellength also allows larger
a transconductance
t o be attained in the V-FET and very considerably improves 12.35. Two MOSFETs having drain resistances of a1
Example
and amplification factors of and u2 respectively are
response and the device switching time.
the frequency and a
connected in parallel. Show that
Another very important factor in the geometry of the
nower MOSFET
is the presence of the lightly doped N and (i) =
enitatial layer close to the N substrate. When Vos is zero Td tTdz
[U.P.S.C. 1.E.S. Electrical Engine ring I1, 1998]
r negative and the drain is positive w.r.t. the source, the since
junction between the P-layer and the N layer is reverse Solution: When two MOSFETs are connected in parallel,

biased. The depletion region at this junction penetrates deep across both equal and total drain current is equal to sum
voltage are

into the N layer and thus punch-ihrough from drain to source of two drain currents
are avoided. So relatively high VDS can be applied without
aDS DS = YpS where r is equivalent resistance
device breakdown.
any danger of d2 d
P-channel V-MOSFETs are also available. Their
) a s desired.
characteristics are similar to those of N-channel MOSFETs, or

except that the current directions and voltage polarities are

(i) Vos &m = VGs &m + Vas 8m
reversed
One main advantage of power MOSFETs over BJTs is or 8m 8m * 8m2
the lack of thermal runaway. The Rpsíon) of a MOSFET has or ..)
a positive temperature coefficient. With the increase in
internal d2
and reduces the drain current
emperature, Rps(on) încreases, Hd2 2'd
lowers the As a result, power MOSFETs i i ) as desired.
Which temperature. or

are inherently temperature-stable and cannot go

into thermal dd
runaway. Example 12.36. Two MOSFETs which are connected in parallel
Another advantage of power MOSFETs is that they
can
similar to that shown in Fig. 12.82, carry a total current I =25 A.
be operated in parallel while power BJTs cannot, because in The drain-to source voltage of M, is Vps, = 2.0 V and that of M, is

BJIs, VBE drops do not match closely enough. If

the BJTs
Vns, = 3.5 V. Determine the drain current of each transistor and
This means difference in current sharing if the current sharing series resistances
are connected in parallel, current hogging
occurs.

more collector current are: )Rs, =0.35 , Rs, =0.2 Q and (iü) Rs, = Rs, = 0.5 2.
that the BJT with the lower VRE takes
do not suffer [U.P.S.C. 1.E.S. Electrical Engineering ll, 2005]
tnan the others. Power MOSFETs in parallel If one of the power
Irom the problem of current hogging. will increase.
MOSFET tries to hog the current, its temperature reduces its drain
T
nis causes increase in its Rns/an which
MOSFETs to
curTent. The overall effect is for all the power
have equal drain currents.
In addition to above, power MOSFETs have
the advantage
BJT can, because
SWitching a large current off faster than
Or a

power MOSFET does not have minority

carriers. Typically,
of current in tens
power MOSFET can switch off amperes faster than with a gRs2
Of nanoseconds. This is 10 to 100 times

Comparable BJT.
ICs are low- Fig. 12.82
Power MOSFET as an Interface. Digital
used to drive a high- Solution For MOSFET
POwer devices and if they are to be M,. Vp =Vps, + lp, +Re
can be used
as an interface (a SoVp = 2.0 +0.351p,
uent load, power MOSFET communicate with or control
B that allows device A to For MOSFET Mz. VD =VDS+ Ip, + Rs,
device
device C). or Vp = 3.5 +0.21p ..i)
 ElectroniC Devices and Circuits
282 when the
case
In other V pD
From Eqs. (i) and (i), we have level
at high
..ii) input is kept the
0.351p,- 0.21p, = 1.5
.(iv) i.e, +Vpp
volts then
and Ip,+ lb, = l= 25 is at
Solving Eqs. (ii) and (iv), we have gate ofMOSFET T, to the
relative
zero potential
D=1.818 A Ans. will be OFF
source, so T,
D, 13.182 A Ans. with its resistance ROFF
Difference in current sharing while gate of
2
10
Ip,-p, = 13.182 -
11.818 =
1.364 AAns. MOSFET will be at
T, - INPUT VOLTAGE,V.
In second case, when Rs, = Rs = 0.5 2, we have relative to
positive potential Fig. 12.84. Input-Output
D 2.0+0.51p, ...) For MOSFET M
MOSFET
its s o u r c e so the Relationship For CMOs
...(vi) For MOSFET M, will be ON with its
and re-
VD 3.5 +0.5p, T,
From above two Eqs. (V) and (vi), we have I k2. In this
sistanceRoN=
approximately 0 volt.
D-, (3.5-2.0)x2=3 ...(vii) case output will be
Except for a short time as the voltage drop from +n
Solving Eqs. (iv) and (vii), we have
to zero or rises from zero to +VDD the series combinati
D 14A Ans.
D,=11A Ans. of P-channel MOSFET (or PMOS)
and N-channel MOsE
Difference in current sharing (or NMOS) has one transistor off with no current then drawn
=3A Ans.
DD,=14- 11 from the power supply. Thus the CMOS circuit operates Wi
12.28. COMPLEMENTARY MOSFET OR CMOS the input either high or low while drawing no power from
the supply except during the brief time while switching between
With active-load switching, the current drain with a low output high and low output levels, when both transistors are ON as
is approximately equal to Ipsat This may cause a problem
one is turning ON and the other is turning OFE. In fact, the
with battery operated equipment. One way to reduce the
power consumption of a CMOS circuit is 0 at de conditions
current drain of a digital circuit is with complementary MOS
increasing as the applied signal frequency increases since
(CMOS).
the circuit is switching more often.
Complementary metal oxide semiconductor devices are
The CMOS device is used primarily in digital circuits,
chips in which both P-channel and N-channel enhancement
operating to provide output of either 0 V or + Von (+5 V)
MOSFETs are connected in push-pull arrangement. The basic
connections for CMOS are shown in Fig. 12.83(a) and while drawing very little power from the supply. Most low
power ICs (integrated circuits) are built using CMOS
Fig. 12.83(b).
transistors. Curve shown in Fig. 12.84 gives relation between
In this circuit, two MOSFETs (P-channel MOSFET and
input and output voltages.
N-channel MOSFET) are connected in series so that source
The main advantage of CMOS is that the power
of P-channel device is connected to a
positive voltage supply dissipation
is very small typically 50
VDD and the source of N-channel device is connected to nW
the ground. Gates of both the devices are connected as a 12.29. MOSFET HANDLING
common input and drain terminals of both the devices are
connected together as a common output. MOSFET requires very careful handling particularly when
When the input is kept low i.e., at 0 out of circuit. In circuit, a MOSFET is as rugged as any
volt, then gate of
MOSFET T, is at negative potential w.r.t. the source other solid-state device of similar
S,. So construction and size.
MOSFET T, will be ON with its resistance MOSFET has an ultra thin silicon dioxide
RoN = | kS2,
the channel and the layer between
while gate of MOSFET T, will be at 0 volt relative to gate. Because the insulating layer is s0
its
source. So T, will be OFF with its resistance thin, it is easily
ROFF 10 2. destroyed by excessive gate source voage
Both of these resistances act like a
potential divider and output GsOn application of large gate voltage, an open-circuit gae
of this will be
approximately +VpD
Volts. may accumulate enough charge so as to develop an electric
field large enough to puncture the thin SiO, layer.
Vin Aside due to direct application
Vout of an excessive gate-to-source
PNEL voltage Vge, the thin SiO, layer may
G2 D2 D G get destroyed in more subtle ways.
Si02 If a MOSFET is inserted or removed
DIELECTRIC
LAYER
N
Irom a circuit while the power 15
2
NCHANNEL
MOSFET
ON, transient voltages causeu
SUBSTRATE
inductive kickback and other effects
(a) may exceed VGs
(b) (max)
will wipe out the MOSFET. Even
Fig. 12.83. Basic CMOS
Connections picking up a MOSFET may depos
enough static charge to exceed
 Field-Effect Transistors
283
rating. Generally. grounding rings are used to I. In MOSFETs (DE-MOSFETs as well as E-MOSFETs).
VGS (max)
ll leads of a MOSFET for avoiding any voltage build
short.
the transverse electric field induced across an insulating
and sour These grounding layer deposited on the semiconductor material controls
up
between gate or
shorting
are
moved only after the MOSFET is connected in the conductivity f the channel whereas in the JFETs the
rings
dhecireuit. Sometimes, conducting foam is applied between transverse electric field across the reverse-biased PN

the leads instead of using shorting or grounding rings. junction controls the conductivity of the channel.
Some MOSFETs are protected 2. JFETs can only be operated in the depletion mode whereas
D

zener diodes in parallel MOSFETs can be operated in either depletion or in

by built-in
enhancement mode. In a JFET, if the gate is
forward
and source, as shown
with the gate G
biased, excess-carrier injunction occurs and the gate
12.85. With normal operating
in Fig. is
the zener diode remains current is substantial. Thus channel conductance
voltages, but the
and does not influence the enhanced to some degree due to excess carriers
open biased because
of the circuit. In case of device is never operated with gate forwárd
working Fig. 12.85
the gate current is undesirable.
an extremely high VGS. zener

diode breaks down thereby limiting the gate potential to 3. MOSFETs have input impedance much higher than that
a value equal to the zener diode breakdown voltage, much of JFETs because of small leakage currents. The input
1052
smaller than VGs (mas) rating. The disadvantage of these impedance of the MOSFET is ofthe order of 100 to
is of the order of
internal zener diodes is that MOSFET's high input whereas the input impedance of JFET
impedance is reduced. The trade-off is worth it in some 10 2.
applications because expensive MOSFETs get easily destroyed 4. JFETs have characteristic curves more flatter than those
without zener protection. of MOSFETs indicating a higher drain resistance.
Caution : MOSFETs are delicate devices and can get The drain resistance of a JFET is of the order of 10' to
easily destroyed. So they are to be handled carefully. 10° 2 whereas the drain resistance of a MOSFET is of
Furthermore, they should never be connected or disconnected the order of I to 50 k2.
while the power is ON. Finally, before picking up a MOSFET 5. MOSFET is very susceptible to overload voltage and
device, get your body grounded by touching the chasis of
needs special handling during installation. It may get
the equipnment you are working on.
damaged easily if not properly handled.
12.30. TESTING OF FETs 6. Capacitive effects may be considerably lower in dual gate
FETs are checked by measuring different resistances by a MOSFETs, as explained in Art. 12.26.
multimeter. When resistance is checked between source and 7. Special digital CMOS circuits are available which involve
drain, it should be of the order of 10 k2. near zero power dissipation and very low voltage and
When a JFET is checked as a diode (gate-to-channel current requirements. This makes them most suitable for
junction)multimeter should indicate low resistance between portable systems.
resistance
gate and source with one polarity and very high 8. When JFET is operated with a reverse bias on the junction,
between gate and source with meter polarity reversed. the gate current I is larger than it would be in a
If the meter indicates high resistance with both the comparable MOSFET. The current caused by minority
polarities, it means that the junction is open. On the
gate carrier extraetion across a reverse biased junction is
other hand, if meter indicates low resistance with both polarities, greater, per unit area, than the leakage current that is

It means that the gate junction is shorted. supported by the oxide layer in a MOSFET. Thus
between MOSFET devices are more useful in electrometer
While checking MOSFET, the resistance measured applications than are the JFETs.
gate and drain should be infinitely high in either polarity.
Low resistance means faulty device. For the above reasons, and also because MOSFETs are
somewhat easier to manufacture, they are more widely used
12.31. coMPARISON OF N-CHANNEL FETs WITH
than are the JFETs.
P-CHANNEL FETS
12.33. COMPARISON BETWEEN NMOS AND PMOS
| S. No. N-Channel P-Channel
Particulars
FETS FETs 1. P-channel is much easier and cheaper to produce than the
Electrons Holes N-channel device.
Current carriers 2. The drain resistance of P-channel MOSFET is three times
Large Poor
Mobility higher than that of an identical N-channel device.
More
Noise Less
Lesser
3. The N-channel MOSFET is smaller for the same
4. Larger
Transconductance complexity than the P-channel MOSFET.
12.32. COMPARISON OF JFETs AND MOSFETS 4. The N-channel MOSFET has the higher packing density
similar in their operating which makes it faster in switching applications due to the
rES and MOSFETs are quite
characteristics. However, smaller junction areas and low inherent capacitances.
nciples and in their electrical
here
ney differ in some aspects, as detailed
 Electronic Devices
vices and
and Circuits
284 operating conditions
are determin
mined by
9. Maximum the
S. A P-channel MOSFET occupies a larger area than nc
product of
the Vps and IpJFET in the
mic
N-channel MOSFET for the given drain current rating. 10. Gate bias
is used to
bias a
a JFET is region. When
This is because the electron mobility is 2.5 times of that it operates
in the
ohmic region,
1o
of Kps.
equivalent to a
ensSure operation the ohmic
n
small resistance into hard saturation
of an hole. JFET 15 driven
region, the by
6. The N-channel MOSFET has higher false turn-on
0 and p'sat) pss using
VGs
=

than the P-channel device because of

the 1S determinDe
possibility transconductance parameter 8m
11. The
Al, associate
in drain
current the
positively charged contaminants ratio of the change
in gate-to-source voltage Av
particular change In the
interest. The steeper the slope of ths
of
region
Highlights VGs curve, the greater
is
tne
value of
8m In adddition, the
of interest to the saturation current
closer the point or region
1. The FET is a majority carrier device, and is, therefore, 1s the transconductance parame
Inss, the greater The
approaches zero.
often called a unipolar transistor. Like its bipolar counterpart, 8m increases as VGs Data sheets
quantity siemens.
the FET is a three-terminal (namely drain, source and gate) in
may list
12. JFETs
8m or 8
are mainly small-signal devices because most JFET
semiconductor device in which current conduction is by
one type of majority carriers (either electrons or holes). of less than 1 W. When
have power rating
a
2. Field-effect devices are controlled by an electric field (or the maximum ratings. Sometimes dataa sheets
sheets, start with
parameters. The
voltage) and give an extremely high input impedance omit the minimum VGs (om or oner large
most important advantage over BJT devices. FETs are of spread in JFET parameters justifies using ideal approximaations
several types such as JFETs, MESFETs and MISFETs. and troubleshooting.
for preliminary analysis
3. The JFET is a voltage controlled device and has two diodes; has, as the label implies,
a fired
the gate-source diode and the gate-drain diode. For normal
13. A fixed bias configuration
dc voltage applied from gate to source to establish the
operation,the diode is reverse biased. Then
gate-source operating point.
the gate voltage controls the drain current. When the gate voltage is much larger than Vos (ie., V.>>
4. The JFET has a high input impedance (of the order of Vre), voltage-divider bias can set up a stable Q-point in the
100 MQ), a high degree of isolation between input and active region. When positive and negative supply voltages
Output, and a low noise figure. The main disadvantage of a are available, two-supply source bias can be employed to
JFET is its relatively low gain-bandwidth product, due to
swamp out the variations in Vas and set up a stable Q-point
the junction capacitive effects. When supply voltages are not large, current-source bias
5. The JFET can actually be used as a voltage-controlled can be used to have a stable Q-point. Self-bias is used
resistor because of unique sensitivity of the drain-to-source
only with small-signal amplifiers because the Q-point is
resistance Rps to the gate-to-source voltage VGs less stable than with the other biasing methods.
6. The curve drawn between drain current I and drain-to- 14. A common-source amplifier has a voltage gain of s , and
source voltage Vps with gate-to-source voltage Vos as the
parameter is called the drain characteristic.
produces an inverted output signal.
The gate-to drain capacitance, Cd is mainly responsible
Maximum drain current for any JFET Ilabelled as Ipss OcCurs
when the gate-source voltage Vcs is zero. The minimum for limiting the high frequency operation of the CS amplifier
drain current for a JFET occurs at pinch-off voltage defined since the total input capacitance given by the Miller effect is
by VGs Vp The pinch-off voltage separates the ohmic Cin=C+ (1 - Ay)Cgd Ay is negative
and active regions for VGs 0 . The gate-source cutoff 15. The common-drain amplifier (or source follower) has a
voltage has the same magnitude as the pinch-off voltage. voltage gain less than unity, but a higher input resistance
turns the JFET off. with a bootstrapped bias circuit. One of the most
GS(ofM
7. The relationship between the drain current Ip and the gate applications of a JFET amplifier is the source follower,
to-source voltage Vos of a JFET is a nonlinear defined by which is often used at the front end of the systems because
Shockley's equation of high input resistance.
16. common-gate amplifier has a characteristicaly low
Vas 72 The
input resistance and a high output resistance, although ius
Ipss 1 Vosio: voltage gain may be quite high. It has few applications.
17.
As the current level approaches Ipss the sensitivity of I to
JFETs are employed in multiplexers, chopper amplifiers, buffer
variations in Vas increases significantly. amplifiers, voltage-controlled resistors, cascade amplitiers,
8. The curve drawn between drain current Ip and gate-to Current limiters, current sources and AGC cireuits.
18. The
source voltage Vos for a given value of drain-to-source operation of a metal-semiconductor field-effect
voltage Vps is called the transfer characteristic. The transfer transistor (MOSFET) is identical to that of a JFET. In the
characteristics are the characteristies of the device itself MOSFET, however, a metal-semiconductor rectifying contde
and are not sensitive to the circuit in which the JFET is used. instead of
a P-N junction, is used for the
gate electroue
The drain current increases more rapidly as Vgs approaches 19. The MOSFET is a
field-effect transistor in which the me
zero. Because the drain current equation contains a squared gate is insulated by a very thin oxide layer from tn
quantity, JFETs are referred to as square-law devices. The Semiconductor channel. It is actually a four-terminal devi
normalized transconductance curve indicates that Ip equals with the substrate or
body being the fourth terminal
one-quarter of the maximum when Vs equals half of the There are two
types of MOSFETs-the N-channel in whicu
cutoff ie.p whenV s | and at a point Current 1s due to the
flow of electrons in the invei
layer, and the P-channel in which current is due lo flow
I C S in the inversion layer. Each of these devicesnecan
where Ip =D, VGs = 0.3 v. either
enhancement mode (E-mode) in which dev
normally "off" and is turmed onby applying a gate voug