BUBT

Bangladesh University of Business and Technology

Rupnagar R/A, Mirpur
Mirpur-2, Dhaka-1216, Bangladesh

Lab Assignment-01
Course Name: Digital Logic Design Lab
Course No: CSE 206

Submit to:
Nahid Anwar
Submit by:
Assistant Professor
Ferdous Mostafa Meem
Department of CSE Intake: 42
Sec: 01
Bangladesh University ID: 18193103036
of Business and
Technology
 Lab No-01
AND Gate:
An AND gate is an electrical circuit that combines two signals so that the output is
on if both signals are present.

F=X.Y

Truth Table:
X Y F
0 0 0
0 1 0
1 0 0
1 1 1

Logic Diagram:

OR Gate:
A logical operation which gives the value one if at least one operand has the value
one, and otherwise gives a value of zero.

F=X+Y
Truth Table:
X Y F
0 0 0
0 1 1
1 0 1
1 1 1

Logic Diagram:

Inverter Gate:
In digital logic, an inverter or NOT gate is a logic gate which implements logical
negation.

F=X’

Truth Table:
X F
0 1
1 0
Logic Diagram:

Buffer Gate:
A buffer, is a basic logic gate that passes its input, unchanged, to its output.

F=X

Truth Table:
X F
0 0
1 1

Logic Diagram:

NAND Gate:
In digital electronics, a NAND gate (NOT-AND) is a logic gate which produces an
output which is false only if all its inputs are true; thus its output is complement to
that of an AND gate.

F= (X.Y)’
Truth Table:
X Y F
0 0 1
0 1 1
1 0 1
1 1 0

Logic Diagram:

NOR Gate:
A Boolean operator which gives the value one if and only if all operands have a
value of zero and otherwise has a value of zero.

F= (X+Y)’

Truth Table:
X Y F
0 0 1
0 1 0
1 0 0
1 1 0
Logic Diagram:

Exclusive- OR Gate:
XOR gate (sometimes EOR, or EXOR and pronounced as Exclusive OR) is a
digital logic gate that gives a true (1 or HIGH) output when the number of true
inputs is odd.

F=X’Y+XY’

=X ⊕Y

Truth Table:
X Y F
0 0 0
0 1 1
1 0 1
1 1 0
Logic Diagram:

Exclusive- NOR Gate:

The XNOR gate is a digital logic gate whose function is the logical complement of
the Exclusive OR gate.

F=XY+X’Y’

=(X⊕Y)’

Truth Table:
X Y F
0 0 1
0 1 0
1 0 0
1 1 1

Logic Diagram:
 Lab No-02
Given function,

F = A’B’ + AB + AB’

Truth Table:
A B F
0 0 1
0 1 0
1 0 1
1 1 1

Logic Diagram:
Given function,

F = AB’C + ABC’ + A’BC + A’B’C

Truth Table:
A B C F
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0

Logic Diagram:
 Lab No-03

Implementation of logic gates using universal gates:

Basic gates using NAND gate:

Basic gates using NOR gate:
Represent X-OR Gate by different gates:
Represent X-NOR Gate by different gates:
 Lab No-04

Given function,

F = A’B’C’D+A’B’CD+A’BC’D’+A’BCD’+A’BCD+AB’CD’+ABC’D’+ABCD

Truth Table:
Minterms
A B C D Term Designation F

0 0 0 0 A’B’C’D’ m0 0
0 0 0 1 A’B’C’D m1 1
0 0 1 0 A’B’CD’ m2 0
0 0 1 1 A’B’CD m3 1
0 1 0 0 A’BC’D’ m4 1
0 1 0 1 A’BC’D m5 0
0 1 1 0 A’BCD’ m6 1
0 1 1 1 A’BCD m7 1
1 0 0 0 AB’C’D’ m8 0
1 0 0 1 AB’C’D m9 0
1 0 1 0 AB’CD’ m10 1
1 0 1 1 AB’CD m11 0
1 1 0 0 ABC’D’ m12 1
1 1 0 1 ABC’D m13 0
1 1 1 0 ABCD’ m14 0
1 1 1 1 ABCD m15 1
Logic Diagram:
Before minimization:-
Minimization :
Given function,

F = A’B’C’D+A’B’CD+A’BC’D’+A’BCD’+A’BCD+ABCD+AB’CD’+ABC’D’

= A’B’D (C’+C) + A’BD’ (C’+C) + BCD (A’+A)+ AD’(B’C+BC’)

= A’B’D+A’BD’+BCD+AD’ (B’C+BC’)

= A’ (B’D+BD’) +BCD+ AD’ (B’C+BC’)

= A’ (B⊕D) + BCD + AD’ (B⊕D)

Logic Diagram:
After minimization:-
 Lab No-05

Given function,

F = A’B’C’D’ + A’B’CD’ + A’BCD’ + AB’CD + ABC’D + ABCD’

Truth Table:
Minterms
A B C D F
Term Designation
0 0 0 0 A’B’C’D’ m0 1
0 0 0 1 A’B’C’D m1 0
0 0 1 0 A’B’CD’ m2 1
0 0 1 1 A’B’CD m3 0
0 1 0 0 A’BC’D’ m4 0
0 1 0 1 A’BC’D m5 0
0 1 1 0 A’BCD’ m6 1
0 1 1 1 A’BCD m7 0
1 0 0 0 AB’C’D’ m8 0
1 0 0 1 AB’C’D m9 0
1 0 1 0 AB’CD’ m10 0
1 0 1 1 AB’CD m11 1
1 1 0 0 ABC’D’ m12 0
1 1 0 1 ABC’D m13 1
1 1 1 0 ABCD’ m14 1
1 1 1 1 ABCD m15 0
Logic Diagram:
Before minimization:-
Minimization :
Given function,

F = A’B’C’D’ + A’B’CD’ + A’BCD’+ ABCD’ + AB’CD + ABC’D

= A’B’D’ (C’+C) + BCD’ (A' + A) + AD (B’C+BC’)

= A’B’D’+ BCD’+ AD (B ⊕ C)

Logic Diagram:
After minimization:-