Lenovo - S530-13 (ELZ02) Compal LA-G651P R02 180517A

A B C D E
v o 1
Compal Confidential
no
2
S530 (ELZ02)
DIS M/B Schematics Document
L e 2
o
Intel Whiskey Lake U Processor with LPDDR3
r
F
N17S-LG (Geforce MX150) (23x23mm)
l
3
p a 2018-5-21
LA-G651P
3
o m R E V ：0 . 2
A
C B
Security Classification
Issued Date 2018/2/5
Compal Secret Data
Deciphered Date 2019/2/5
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C D
Title
Custom
Date:
Compal Electronics, Inc.
Size Document Number
LA-G651P
Cover Page
Friday, May 18, 2018 Sheet

E
1 of 52
Rev
0.2
4
5 4 3 2 1
D
N17S-LG (MX150)
VRAM(GDDR5)*2
2GB
PCIe x4
2 Lanes
Channel A/B
(1866 MT/s)
USB3.0
On board X 4
LPDDR3
v o D
o
USB3.0 Connector
USB2.0
eDP Panel eDP x1 (USB charger port)
FHD LCD 2 Lanes
n
USB3.0 redriver
USB3.0 TI USB3.0 Connector
SN65LVPE502A
e
HDMI CONN USB2.0
DDI x1 IO/B
USB2.0 Camera
L
Intel WHL-U_15W
C C
PCIE x1
Wireless LAN USB2.0 Finger print
4+2
r
GEN1 : 2.5G
WIFI /BT combo
NGFF USB2.0 x1
1528 pin BGA
o
PCIE x4 SSD CONN
NGFF
DDI x1 Int. Speaker
Type-C DP/USB3 Switch
F
Type-C USB 3.0
Conn Realtek RTS5455 Audio Codec
USB 2.0 HDA Int. Array Mic x2
Realtek ALC3240
MIC B
l
Combo Jack
Touch Pad IO/B
a
I2C
B B
mp
Sub-Board
EC
ENE
KB9022
LPC SPI
SPI ROM
16 MB
Co
IO/B
USB3.0 *1
Combo Jack *1
MIC B
Int. Array Mic x2
Int. KBD Hall Sensor x1
Compal Secret Data
Title
Size
Custom
BLOCK DIAGRAM
Document Number Rev
0.2
A
Date:
LA-G651P
Friday, May 18, 2018 Sheet 2 of 52
5 4 3 2 1
1 2 3 4 5
BOM Structure Table USB 2.0 Port Table

Item BOM Structure
Voltage Rails Port PCIE Port Table
For DIS DIS@
For UMA UMA@ 1 USB2/3 (re-driver) ( I/O BD)
o
For GPU GC6 GC6@ 2 USB2/3 (Charger) Port Lane
+5VS No GPU GC6 NOGC6@ 3 Type-C
1
+3VS For Keyboard backlight KBL@ 4
power 2
A plane +VCCPLL_OC No Keyboard backlight NOKBL@ 5 Camera A
v
3
+VCCCORE For RF RF@ 6 FP
+5VALW 4
+1.2V +VCCGT No RF @RF@ 7
+2.5V 5
B+ +3VALW +1.05V_VCCST For EMI EMI@ 8
6
+1.05VS_VCCIO No EMI @EMI@ 9
o
+1.8VALW 7
+1.8VS For ESD ESD@ 10 NGFF WLAN+BT(CNVi)
8 0 NGFF WLAN+BT
State +1.05VALW +1.8V_MEM No ESD @ESD@
9 3
Connector ME@
10 2
n
For Samsung VRAM S2G@ USB 3.0 Port Table SSD
11 1
For Micron VRAM M2G@
12 0
For Hynix VRAM H2G@ Port
13 0
For samsung 4G DRAM S4G@
e
1 USB2/3 (re-driver) (I/O SB) 14 1
For samsung 8G DRAM S8G@ GPU
2 USB2/3 (for charger) 15 2
S0
O O O O For samsung 16G DRAM S16G@
3 Type-C 16 3
For Hynix 4G DRAM H4G@
4
For Hynix 8G DRAM H8G@
5
L
S3
O O O X For Hynix 16G DRAM H16G@
6
For Micron 4G DRAM M4G@
S5 S4/AC O O X X For Micron 8G DRAM M8G@
B
For Micron 16G DRAM M16G@ B
S5 S4/ Battery only

O X X X X4E for UMA X4E_UMA
r
X4E for DIS X4E_DIS
S5 S4/AC & Battery
X X X X For CNVi interface CNVi@
don't exist
Non CNVi interface NONCNVi@ EMC/ESD UMA Discrete
For XDP CMC@
o
ZZZ X4E_UMA@ ZZZ X4E_DIS@
For Thermal Sensor EX_THM@
For 8G_16G DRAM CHA@
X4E_UMA
X4E_DIS
F
X4EADO38L02 X4EADO38L01
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
l
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF UC1 ZZZ
SA0000C1510
S IC FJ8068403999819 QQAT W0 1.8G C38
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF I7@
a
UC1
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF SA0000C1610 DA8001FP000
S IC FJ8068404000016 QQAU W0 1.6G C38 PCB 2D5 LA-G651P REV0 M/B 2
C
I5@ LPDDR3 Onboard RAM C
p
ZZZ X76@ ZZZ X76@ ZZZ X76@
CPU MB 4G
SMBUS Control Table
LPDDR3_S4G LPDDR3_H4G LPDDR3_M4G
ZZZ 45@ X7679138L01 X7679138L02 X7679138L03
m
ZZZ X76@ ZZZ X76@ ZZZ X76@
SOURCE VGA BATT CHARGER Thermal Touch Pad PCH TypeC-Mux

Sensor HDMI Logo
RO0000003HM
8G
EC_SMB_CK1
EC_SMB_DA1
KB9022QD
+3VL X V V X X X X LPDDR3_S8G LPDDR3_H8G LPDDR3_M8G
o
X7679138L04 X7679138L05 X7679138L06
EC_SMB_CK2
EC_SMB_DA2
KB9022QD
+3VS V X X Reserve X V Reserve ZZZ X76@ ZZZ X76@ ZZZ X76@
X HDMI Logo
PCH_SMB_CLK
PCH_SMB_DATA
PCH
+3VS X X X X X X 16G
I2C1_SCL_TS
X X X X X X V
LPDDR3_S16G LPDDR3_H16G LPDDR3_M16G
C
PCH
I2C1_SDA_TS +3VS X7679138L07 X7679138L08 X7679138L09
D I2C0_SCL_TP
I2C0_SDA_TP
PCH
+3VS X X X X V X X D
Address Write
Read 0X9E 0X4C 0X2C 0X5C
Security Classification Compal Secret Data

Title
Issued Date 2018/2/5 Deciphered Date 2019/2/5
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Notes List
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
Date: Friday, May 18, 2018
LA-G651P
Sheet 3 of 52
1 2 3 4 5
5 4 3 2 1
v o D
no
C
L e C
o r
l F
a
B B
mp
A
Co Security Classification
Compal Secret Data
Title
Size Document
Number
Power MAP
Re v
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.2
Date : Friday, May 18, 2018 Sheet 4 of 52
5 4 3 2 1
5 4 3 2 1
[ELZ02-PWR Sequence]
G3->S0 S0->S3/DS3 S0/ DS3 ->S0 S0->S5

+3VL_RTC +3VL_RTC
o
tPCH01_Min : 9 ms
SOC_RTCRST# SOC_RTCRST#
B+ B+
D D
+3VLP/+5VLP +3VLP/+5VLP
v
EC_ON EC_ON
tPCH04_Min : 9 ms
+5VALW/+3VALW/+3VALW_DSW +5VALW/+3VALW/+3VALW_DSW
Pull-up to DSW well if not implemented.
PM_BATLOW# PM_BATLOW#
o
PCH_PWR_EN (SLP_SUS#) PCH_PWR_EN (SLP_SUS#)
+3V_PRIM +3V_PRIM
+1.8V_PRIM +1.8V_PRIM
n
EXT_PWR_GATE# If EXT_PWR_GATE# Toffmin is too small, Pwr EXT_PWR_GATE#
gate may choose to completely ignore it
+1.05V_MPHYPLL +1.05V_MPHYPLL
+1.05V_PRIM_CORE +1.05V_PRIM_CORE
e
tPCH34_Max : 20 ms
+1.05V_PRIM tPCH06_Min : 200 us +1.05V_PRIM
SUSACK# SUSACK#
tPCH02_Min : 10 ms
PCH_DPWROK PCH_DPWROK
L
tPCH03_Min : 10 ms
EC_RSMRST# EC_RSMRST#
tPLT02_Min : 0 ms Max : 90 ms
C C
AC_PRESENT AC_PRESENT
ON/OFF ON/OFF
r
tPCH43_Min : 95 ms
PBTN_OUT# PBTN_OUT#
Minimum duration of PWRBTN# assertion = 16mS. PWRBTN# can assert before or after RSMRST#
PM_SLP_S5# PM_SLP_S5#
o
tPCH18_Min : 90 us
ESPI_RST# ESPI_RST#
SYSON SYSON
F
VCCST VCCST
+1.2V_VDDQ/+1.2V_VCCSFR_OC +1.2V_VDDQ/+1.2V_VCCSFR_OC
l
SUSP# SUSP#
tCPU04 Min : 100 ns
VCCSTG VCCSTG
a
tCPU10 Min : 1 ms
B
VCCIO VCCIO B
T <=10msec
+5VS/+3VS/+1.5VS/+1.05VS
+5VS/+3VS/+1.5VS/+1.05VS
p
T = 10msec
EC_VCCST_PG EC_VCCST_PG
VR_ON VR_ON
tCPU19 Max : 100 ns
DDR_VTT_PG_CTRL DDR_VTT_PG_CTRL
tCPU18 Max : 35 us
+0.6VS +0.6VS
m
tCPU09 Min : 1 ms
+VCC_SA +VCC_SA
+VCC_CORE +VCC_CORE
o
+VCC_GT +VCC_GT
VR_PWRGD VR_PWRGD
tCPU16 Min : 0 ns
PCH_PWROK PCH_PWROK
H_CPUPWRGD H_CPUPWRGD
C
SYS_PWROK SYS_PWROK
A A
SUS_STAT# SUS_STAT#
SOC_PLTRST#
SOC_PLTRST#
Security Classification Compal Secret Data Compal Electronics, Inc.

2018/2/5 2019/2/5 Title
Issued Date Deciphered Date
Power Sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Date: Friday, May 18, 2018 Sheet 5 of 52
5 4 3 2 1
A B C D E
UC1A
AL5 AG4
<29> CPU_DP1_N0 DDI1_TXN_0 EDP_TXN_0 EDP_TXN0 <28>
AL6 AG3
<29> CPU_DP1_P0 DDI1_TXP_0 EDP_TXP_0 EDP_TXP0 <28>
AJ5 AG2
<29> CPU_DP1_N1 AJ6 DDI1_TXN_1 EDP_TXN_1 AG1 EDP_TXN1 <28> eDP
<29> CPU_DP1_P1 DDI1_TXP_1 EDP_TXP_1 EDP_TXP1 <28>
AF6 AJ4
<29> CPU_DP1_N2 DDI1_TXN_2 EDP_TXN_2
AF5 AJ3
HDMI <29> CPU_DP1_P2 DDI1_TXP_2 EDP_TXP_2
o
AE5 AJ2
<29> CPU_DP1_N3 DDI1_TXN_3 EDP_TXN_3
AE6 AJ1
<29> CPU_DP1_P3 DDI1_TXP_3 EDP_TXP_3
AC4
<30> CPU_DP2_N0 DDI2_TXN_0
AC3 AH4
<30> CPU_DP2_P0 DDI2_TXP_0 EDP_AUX_N EDP_AUXN <28>
AC1 AH3
<30> CPU_DP2_N1 DDI2_TXN_1 EDP_AUX_P EDP_AUXP <28>
AC2
1 <30> CPU_DP2_P1 DDI2_TXP_1 1
v
AE4 AM7
MUX <30> CPU_DP2_N2 AE3 DDI2_TXN_2 DISP_UTILS
<30> CPU_DP2_P2 DDI2_TXP_2
AE1 AC7
<30> CPU_DP2_N3 AE2 DDI2_TXN_3 DDI1_AUX_N AC6
<30> CPU_DP2_P3 DDI2_TXP_3 DDI1_AUX_P AD4 CPU_DP2_AUXN <30>
DDI2_AUX_N AD3
DDI2_AUX_P AG7
CPU_DP2_AUXP <30> MUX
DDI3_AUX_N
o
AG6
DDI3_AUX_P
CN6
GPP_E13/DDPB_HPD0/DISP_MISC0 CM6
CPU_DP1_HPD <29> From HDMI
GPP_E14/DDPC_HPD1/DISP_MISC1 CP7
CPU_DP2_HPD <30> From MUX
GPP_E15/DPPD_HPD2/DISP_MISC2 CP6 EC_SCI#
GPP_E16/DPPE_HPD3/DISP_MISC3 EC_SCI# <34>
CM7
n
GPP_E17/EDP_HPD/DISP_MISC4 EDP_HPD <28> From eDP
CK11
EDP_BKLTEN ENBKL <28,34>
CG11
EDP_VDDEN PCH_ENVDD <28>
CH11
EDP_BKLTCTL INVPWM <28>
e
EDP_COMP AM6
DISP_RCOMP
CC8 +3VS
<29> CPU_DP1_CTRL_CLK GPP_E18/DPPB_CTRLCLK/CNV_BT_HOST_WAKE#
CC9
For HDMI 1.4 <29> CPU_DP1_CTRL_DATA GPP_E19/DPPB_CTRLDATA
CH4
CPU_DDPC_CTRL_DATA CH3 GPP_E20/DPPC_CTRLCLK
L
GPP_E21/DPPC_CTRLDATA
CP4
CN4 GPP_E22/DPPD_CTRLCLK EC_SCI# RC480 1 2 10K_0402_5%
GPP_E23/DPPD_CTRLDATA
CR26
2 CP26 GPP_H16/DDPF_CTRLCLK 2
GPP_H17/DDPF_CTRLDATA
r
WHL-U42_BGA1528
1 of 20
+3VS
o
+1.05VS_VCCSTG
RC436 2 1 2.2K_0201_5% CPU_DDPC_CTRL_DATA
< PU/PD for CMC Debug >
1
+1.05VS_VCCSTG
If routed MS, PECI requires 18 mils spacing to other signals
RC4
F
1K_0402_5% UC1D
CATERR# AA4 T6 CPU_XDP_TCK0 SOC_XDP_TMS RC11 1 CMC@ 2 51_0402_5%
H_PECI AR1 CATERR# PROC_TCK U6 SOC_XDP_TDI
<34> H_PECI
2
1 2 H_PROCHOT#_R Y4 PECI PROC_TDI Y5 SOC_XDP_TDO SOC_XDP_TDI RC12 1 CMC@ 2 51_0402_5%

<34> H_PROCHOT# H_THERMTRIP# PROCHOT# PROC_TDO SOC_XDP_TMS
RC6 499_0402_1% BJ1 T5
THRMTRIP# PROC_TMS AB6 SOC_XDP_TRST# DCI SOC_XDP_TDO RC13 1 2 51_0402_5%
U1 PROC_TRST#
U2 BPM#_0
l
U3 BPM#_1 W6
< Compensation PU For eDP > BPM#_2 PCH_TCK SOC_XDP_TDI TP@ T2402 CPU_XDP_TCK0
U4 U5 RC14 1 2 51_0402_5%
BPM#_3 PCH_TDI W5 SOC_XDP_TDO
+1.05VS_VCCIO PCH_TDO P5 SOC_XDP_TMS
CE9 PCH_TMS Y6 SOC_XDP_TRST# DCI
CN3 GPP_E3/CPU_GP0 PCH_TRST# P6 CPU_XDP_TCK0
a
RC3 1 2 EDP_COMP CB34 GPP_E7/CPU_GP1 PCH_JTAGX
24.9_0201_1% CC35 GPP_B3/CPU_GP2
GPP_B4/CPU_GP3 W2
PROC_PREQ# TP@ T2403
3 Trace width=20 mils, Spacing=25mil, Max length=600mils W1 TP@ T2404
3
RC7 2 1 49.9_0402_1% CPU_POPIRCOMP BP27 PROC_PRDY#
RC8 2 1 49.9_0402_1% PCH_OPIRCOMP BW25 PROC_POPIRCOMP
RC9 2 @ 1 49.9_0402_1% EDRAM_OPIO_RCOMP L5 PCH_OPIRCOMP
OPCE_RCOMP
p
+1.05V_VCCST
RC10 2 @ 1 49.9_0402_1% EOPIO_RCOMP N5
OPC_RCOMP
1 2 H_THERMTRIP# WHL-U42_BGA1528
RC5 1K_0402_5%
4 of 20
@
2 1 CATERR#
m
RC19 49.9_0402_1%
Compal Secret Data
Title
Custom
WHL-U(1/12)DDI,EDP,MISC,CMC
Size Document Number R ev
0.2
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G651P
A B C D E
o
5 4 3 2 1
v
Non- Interleaved Memory
o
D D
n
UC1C
<19> DDR_A_D[16..31] DDR_A_D16 DDR_B_CLK#0
UC1B J22 AF28 DDR_B_CLK#0 <20>
<19> DDR_A_D[0..15] DDR_A_D0 DDR_A_D17 DDR1_DQ_0/DDR0_DQ_16
DDR1_CKN_0/DDR1_CKN_0 DDR_B_CLK0
A26 H25 AF29 DDR_B_CLK0 <20>
DDR_A_D1 D26 DDR0_DQ_0/DDR0_DQ_0 V32 DDR_A_CLK#0 DDR_A_D18 G22 DDR1_DQ_1/DDR0_DQ_17DDR1_CKP_0/DDR1_CKP_0 AE28 DDR_B_CLK#1
DDR_A_D2 DDR0_DQ_1/DDR0_DQ_1 DDR0_CKN_0/DDR0_CKN_0 DDR_A_CLK0 DDR_A_CLK#0 <19> DDR_A_D19 DDR1_DQ_2/DDR0_DQ_18
DDR1_CKN_1/DDR1_CKN_1 DDR_B_CLK1 DDR_B_CLK#1 <20>
D28 V31 DDR_A_CLK0 <19>
H22 AE29 DDR_B_CLK1 <20>
DDR_A_D3 C28 DDR0_DQ_2/DDR0_DQ_2 DDR0_CKP_0/DDR0_CKP_0 T32 DDR_A_CLK#1 DDR_A_D20 F25 DDR1_DQ_3/DDR0_DQ_19DDR1_CKP_1/DDR1_CKP_1
DDR_A_D4 DDR0_DQ_3/DDR0_DQ_3 DDR0_CKN_1/DDR0_CKN_1 DDR_A_CLK1 DDR_A_CLK#1 <19> DDR_A_D21 DDR1_DQ_4/DDR0_DQ_20 DDR_B_CKE0
B26 T31 DDR_A_CLK1 <19> J25 T28 DDR_B_CKE0 <20>
DDR_A_D5 DDR0_DQ_4/DDR0_DQ_4 DDR0_CKP_1/DDR0_CKP_1 DDR_A_D22 DDR1_DQ_5/DDR0_DQ_21DDR1_CKE_0/DDR1_CKE_0 DDR_B_CKE1
e
C26 G25 T29 DDR_B_CKE1 <20>
DDR_A_D6 B28 DDR0_DQ_5/DDR0_DQ_5 U36 DDR_A_CKE0 DDR_A_D23 F22 DDR1_DQ_6/DDR0_DQ_22DDR1_CKE_1/DDR1_CKE_1 V28 DDR_B_CKE2
DDR_A_D7 DDR0_DQ_6/DDR0_DQ_6 DDR0_CKE_0/DDR0_CKE_0 DDR_A_CKE1 DDR_A_CKE0 <19> DDR_A_D24 DDR1_DQ_7/DDR0_DQ_23 DDR1_CKE_2/NC DDR_B_CKE3 DDR_B_CKE2 <20>
A28 U37 DDR_A_CKE1 <19> D22 V29 DDR_B_CKE3 <20>
DDR_A_D8 B30 DDR0_DQ_7/DDR0_DQ_7 DDR0_CKE_1/DDR0_CKE_1 U34 DDR_A_CKE2 DDR_A_D25 C22 DDR1_DQ_8/DDR0_DQ_24 DDR1_CKE_3/NC
DDR_A_D9 DDR0_DQ_8/DDR0_DQ_8 DDR0_CKE_2/NC DDR_A_CKE3 DDR_A_CKE2 <19> DDR_A_D26 DDR1_DQ_9/DDR0_DQ_25 DDR_B_CS#0
D30 U35 DDR_A_CKE3 <19> C24 AL37 DDR_B_CS#0 <20>
DDR_A_D10 B33 DDR0_DQ_9/DDR0_DQ_9 DDR0_CKE_3/NC DDR_A_D27 D24 DDR1_DQ_10/DDR0_DQ_26
DDR1_CS#_0/DDR1_CS#_0 AL35 DDR_B_CS#1
DDR_A_D11 DDR0_DQ_10/DDR0_DQ_10 DDR_A_CS#0 DDR_A_D28 DDR1_DQ_11/DDR0_DQ_27
DDR1_CS#_1/DDR1_CS#_1 DDR_B_ODT0 DDR_B_CS#1 <20>
D32 AE32 DDR_A_CS#0 <19> A22 AL36 DDR_B_ODT0 <20>
DDR_A_D12 A30 DDR0_DQ_11/DDR0_DQ_11 DDR0_CS#_0/DDR0_CS#_0 AF32 DDR_A_CS#1 DDR_A_D29 B22 DDR1_DQ_12/DDR0_DQ_28
DDR1_ODT_0/DDR1_ODT_0 AL34
DDR_A_D13 DDR0_DQ_12/DDR0_DQ_12 DDR0_CS#_1/DDR0_CS#_1 DDR_A_ODT0 DDR_A_CS#1 <19> DDR_A_D30 DDR1_DQ_13/DDR0_DQ_29 NC/DDR1_ODT_1 DDR_B_CAB9
C30 AE31 DDR_A_ODT0 <19> A24 AG36 DDR_B_CAB9 <20>
DDR_A_D14 B32 DDR0_DQ_13/DDR0_DQ_13 DDR0_ODT_0/DDR0_ODT_0 AF31 DDR_A_D31 B24 DDR1_DQ_14/DDR0_DQ_30DDR1_CAB_9/DDR1_MA_0 AG35 DDR_B_CAB8
DDR_A_D15 DDR0_DQ_14/DDR0_DQ_14 NC/DDR0_ODT_1 <19> DDR_A_D[48..63] DDR_A_D48 DDR1_DQ_15/DDR0_DQ_31DDR1_CAB_8/DDR1_MA_1 DDR_B_CAB5 DDR_B_CAB8 <20>
C32 G31 AF34 DDR_B_CAB5 <20>
<19> DDR_A_D[32..47]
L
DDR_A_D32 H37 DDR0_DQ_15/DDR0_DQ_15 AC37 DDR_A_CAB9 DDR_A_D49 G32 DDR1_DQ_16/DDR0_DQ_48DDR1_CAB_5/DDR1_MA_2 AG37
DDR_A_D33 DDR0_DQ_16/DDR0_DQ_32 DDR0_CAB_9/DDR0_MA_0 DDR_A_CAB8 DDR_A_CAB9 <19> DDR_A_D50 DDR1_DQ_17/DDR0_DQ_49 NC/DDR1_MA_3
H34 AC36 DDR_A_CAB8 <19>
H29 AE35
DDR_A_D34 K34 DDR0_DQ_17/DDR0_DQ_33 DDR0_CAB_8/DDR0_MA_1 AC34 DDR_A_CAB5 DDR_A_D51 H28 DDR1_DQ_18/DDR0_DQ_50 NC/DDR1_MA_4 AF35 DDR_B_CAA0
DDR_A_D35 DDR0_DQ_18/DDR0_DQ_34 DDR0_CAB_5/DDR0_MA_2 DDR_A_CAB5 <19> DDR_A_D52 DDR1_DQ_19/DDR0_DQ_51DDR1_CAA_0/DDR1_MA_5 DDR_B_CAA2 DDR_B_CAA0 <20>
K35 AC35 G28 AE37 DDR_B_CAA2 <20>
DDR_A_D36 H36 DDR0_DQ_19/DDR0_DQ_35 NC/DDR0_MA_3 AA35 DDR_A_D53 G29 DDR1_DQ_20/DDR0_DQ_52DDR1_CAA_2/DDR1_MA_6 AC29 DDR_B_CAA4
DDR_A_D37 DDR0_DQ_20/DDR0_DQ_36 NC/DDR0_MA_4 DDR_A_CAA0 DDR_A_D54 DDR1_DQ_21/DDR0_DQ_53DDR1_CAA_4/DDR1_MA_7 DDR_B_CAA3 DDR_B_CAA4 <20>
H35 AB35 DDR_A_CAA0 <19> H31 AE36 DDR_B_CAA3 <20>
DDR_A_D38 K36 DDR0_DQ_21/DDR0_DQ_37 DDR0_CAA_0/DDR0_MA_5 AA37 DDR_A_CAA2 DDR_A_D55 H32 DDR1_DQ_22/DDR0_DQ_54DDR1_CAA_3/DDR1_MA_8 AB29 DDR_B_CAA1
DDR_A_D39 DDR0_DQ_22/DDR0_DQ_38 DDR0_CAA_2/DDR0_MA_6 DDR_A_CAA4 DDR_A_CAA2 <19> DDR_A_D56 DDR1_DQ_23/DDR0_DQ_55DDR1_CAA_1/DDR1_MA_9 DDR_B_CAB7 DDR_B_CAA1 <20>
K37 AA36 DDR_A_CAA4 <19> L31 AG34 DDR_B_CAB7 <20>
DDR_A_D40 N36 DDR0_DQ_23/DDR0_DQ_39 DDR0_CAA_4/DDR0_MA_7 AB34 DDR_A_CAA3 DDR_A_D57 L32 DDR1_DQ_24/DDR0_DQ_56
DDR1_CAB_7/DDR1_MA_10 AC28 DDR_B_CAA7
DDR_A_D41 DDR0_DQ_24/DDR0_DQ_40 DDR0_CAA_3/DDR0_MA_8 DDR_A_CAA1 DDR_A_CAA3 <19> DDR_A_D58 DDR1_DQ_25/DDR0_DQ_57
DDR1_CAA_7/DDR1_MA_11 DDR_B_CAA6 DDR_B_CAA7 <20>
N34 W36 DDR_A_CAA1 <19>
N29 AB28 DDR_B_CAA6 <20>
DDR_A_D42 DDR0_DQ_25/DDR0_DQ_41 DDR0_CAA_1/DDR0_MA_9 DDR_A_CAB7 DDR_A_D59 DDR1_DQ_26/DDR0_DQ_58
DDR1_CAA_6/DDR1_MA_12 DDR_B_CAB0
r
R37 Y31 DDR_A_CAB7 <19> N28 AK35 DDR_B_CAB0 <20>
C DDR_A_D43 R34 DDR0_DQ_26/DDR0_DQ_42 DDR0_CAB_7/DDR0_MA_10 W34 DDR_A_CAA7 DDR_A_D60 L28 DDR1_DQ_27/DDR0_DQ_59
DDR1_CAB_0/DDR1_MA_13 C
DDR_A_D44 DDR0_DQ_27/DDR0_DQ_43 DDR0_CAA_7/DDR0_MA_11 DDR_A_CAA6 DDR_A_CAA7 <19> DDR_A_D61 DDR1_DQ_28/DDR0_DQ_60 DDR_B_CAB2
N37 AA34 DDR_A_CAA6 <19> L29 AJ35 DDR_B_CAB2 <20>
DDR_A_D45 N35 DDR0_DQ_28/DDR0_DQ_44 DDR0_CAA_6/DDR0_MA_12 AC32 DDR_A_CAB0 DDR_A_D62 N31 DDR1_DQ_29/DDR0_DQ_61
DDR1_CAB_2/DDR1_MA_14 AK34 DDR_B_CAB1
DDR_A_D46 DDR0_DQ_29/DDR0_DQ_45 DDR0_CAB_0/DDR0_MA_13 DDR_A_CAB0 <19> DDR_A_D63 DDR1_DQ_30/DDR0_DQ_62
DDR1_CAB_1/DDR1_MA_15 DDR_B_CAB3 DDR_B_CAB1 <20>
R36 N32 AJ34 DDR_B_CAB3 <20>
DDR_A_D47 DDR0_DQ_30/DDR0_DQ_46 DDR_A_CAB2 <20> DDR_B_D[16..31] DDR_B_D16 DDR1_DQ_31/DDR0_DQ_63
DDR1_CAB_3/DDR1_MA_16
R35 AC31 DDR_A_CAB2 <19> AJ29
<20> DDR_B_D[0..15] DDR_B_D0 DDR0_DQ_31/DDR0_DQ_47 DDR0_CAB_2/DDR0_MA_14 DDR_A_CAB1 DDR_B_D17 DDR1_DQ_32/DDR1_DQ_16 DDR_B_CAB4
AN35 AB32 DDR_A_CAB1 <19>
AJ30 AJ37 DDR_B_CAB4 <20>
DDR_B_D1 AN34 DDR0_DQ_32/DDR1_DQ_0 DDR0_CAB_1/DDR0_MA_15 Y32 DDR_A_CAB3 DDR_B_D18 AM32 DDR1_DQ_33/DDR1_DQ_17DDR1_CAB_4/DDR1_BA_0 AJ36 DDR_B_CAB6
DDR_B_D2 DDR0_DQ_33/DDR1_DQ_1 DDR0_CAB_3/DDR0_MA_16 DDR_A_CAB3 <19> DDR_B_D19 DDR1_DQ_34/DDR1_DQ_18DDR1_CAB_6/DDR1_BA_1 DDR_B_CAA5 DDR_B_CAB6 <20>
AR35 AM31 W29 DDR_B_CAA5 <20>
DDR_B_D3 DDR0_DQ_34/DDR1_DQ_2 DDR_A_CAB4 DDR_B_D20 DDR1_DQ_35/DDR1_DQ_19DDR1_CAA_5/DDR1_BG_0
o
AR34 W32 DDR_A_CAB4 <19>
AM30
DDR_B_D4 AN37 DDR0_DQ_35/DDR1_DQ_3 DDR0_CAB_4/DDR0_BA_0 AB31 DDR_A_CAB6 DDR_B_D21 AM29 DDR1_DQ_36/DDR1_DQ_20 Y28 DDR_B_CAA9
DDR_B_D5 DDR0_DQ_36/DDR1_DQ_4 DDR0_CAB_6/DDR0_BA_1 DDR_A_CAA5 DDR_A_CAB6 <19> DDR_B_D22 DDR1_DQ_37/DDR1_DQ_21DDR1_CAA_9/DDR1_BG_1 DDR_B_CAA8 DDR_B_CAA9 <20>
AN36 V34 DDR_A_CAA5 <19>
AJ31 W28 DDR_B_CAA8 <20>
DDR_B_D6 AR36 DDR0_DQ_37/DDR1_DQ_5 DDR0_CAA_5/DDR0_BG_0 DDR_B_D23 AJ32 DDR1_DQ_38/DDR1_DQ_22DDR1_CAA_8/DDR1_ACT#
DDR_B_D7 AR37 DDR0_DQ_38/DDR1_DQ_6 V35 DDR_A_CAA8 DDR_B_D24 AR31 DDR1_DQ_39/DDR1_DQ_23 H24 DDR_A_DQS#2
DDR_B_D8 DDR0_DQ_39/DDR1_DQ_7 DDR0_CAA_8/DDR0_ACT# DDR_A_CAA9 DDR_A_CAA8 <19> DDR_B_D25 DDR1_DQ_40/DDR1_DQ_24
DDR1_DQSN_0/DDR0_DQSN_2 DDR_A_DQS2 DDR_A_DQS#2 <19>
AU35 W35 DDR_A_CAA9 <19> AR32 G24 DDR_A_DQS2 <19>
DDR_B_D9 AU34 DDR0_DQ_40/DDR1_DQ_8 DDR0_CAA_9/DDR0_BG_1 DDR_B_D26 AV30 DDR1_DQ_41/DDR1_DQ_25
DDR1_DQSP_0/DDR0_DQSP_2 C23 DDR_A_DQS#3
DDR_B_D10 DDR0_DQ_41/DDR1_DQ_9 DDR_A_DQS#0 DDR_B_D27 DDR1_DQ_42/DDR1_DQ_26
AW35 C27 DDR_A_DQS#0 <19> AV29 D23 DDR_A_DQS3 <19>
DDR_B_D11 AW34 DDR0_DQ_42/DDR1_DQ_10
DDR0_DQSN_0/DDR0_DQSN_0 D27 DDR_A_DQS0 DDR_B_D28 AR30 DDR1_DQ_43/DDR1_DQ_27
DDR1_DQSP_1/DDR0_DQSP_3 G30 DDR_A_DQS#6
DDR_B_D12 DDR0_DQ_43/DDR1_DQ_11
DDR0_DQSP_0/DDR0_DQSP_0 DDR_A_DQS#1 DDR_A_DQS0 <19> DDR_B_D29 DDR1_DQ_44/DDR1_DQ_28
AU37 D31 DDR_A_DQS#1 <19> AR29 H30 DDR_A_DQS6 <19>
F
DDR_B_D13 AU36 DDR0_DQ_44/DDR1_DQ_12
DDR0_DQSN_1/DDR0_DQSN_1 C31 DDR_A_DQS1 DDR_B_D30 AV32 DDR1_DQ_45/DDR1_DQ_29
DDR1_DQSP_2/DDR0_DQSP_6 L30 DDR_A_DQS#7
DDR0_DQSP_1/DDR0_DQSP_1 DDR_A_DQS#4 DDR_A_DQS1 <19> DDR_B_D31 DDR1_DQ_46/DDR1_DQ_30
AW36 J35 DDR_A_DQS#4 <19> AV31 N30 DDR_A_DQS7 <19>
DDR0_DQSN_2/DDR0_DQSN_4 DDR_A_DQS4 <20> DDR_B_D[48..63] DDR_B_D48 DDR1_DQ_47/DDR1_DQ_31
DDR1_DQSP_3/DDR0_DQSP_7 DDR_B_DQS#2
AW37 J34 DDR_A_DQS4 <19>
BA32 AL31 DDR_B_DQS#2 <20>
<20> DDR_B_D[32..47] DDR_B_D32 DDR0_DQ_47/DDR1_DQ_15
DDR0_DQSP_2/DDR0_DQSP_4 DDR_A_DQS#5 DDR_B_D49 DDR1_DQ_48/DDR1_DQ_48
DDR1_DQSN_4/DDR1_DQSN_2 DDR_B_DQS2
BA35 P34 DDR_A_DQS#5 <19> BA31 AL30 DDR_B_DQS2 <20>
DDR_B_D33 BA34 DDR0_DQ_48/DDR1_DQ_32
DDR0_DQSN_3/DDR0_DQSN_5 P35 DDR_A_DQS5 DDR_B_D50 BD31 DDR1_DQ_49/DDR1_DQ_49
DDR1_DQSP_4/DDR1_DQSP_2 AU31 DDR_B_DQS#3
DDR0_DQSP_3/DDR0_DQSP_5 DDR_B_DQS#0 DDR_A_DQS5 <19> DDR_B_D51 DDR1_DQ_50/DDR1_DQ_50
DDR1_DQSN_5/DDR1_DQSN_3 DDR_B_DQS3 DDR_B_DQS#3 <20>
BC35 AP35 DDR_B_DQS#0 <20>
BD32 AU30 DDR_B_DQS3 <20>
DDR_B_D35 BC34 DDR0_DQ_50/DDR1_DQ_34
DDR0_DQSN_4/DDR1_DQSN_0 AP34 DDR_B_DQS0 DDR_B_D52 BA30 DDR1_DQ_51/DDR1_DQ_51
DDR1_DQSP_5/DDR1_DQSP_3 BC31 DDR_B_DQS#6
DDR0_DQSP_4/DDR1_DQSP_0 DDR_B_DQS#1 DDR_B_DQS0 <20> DDR_B_D53 DDR1_DQ_52/DDR1_DQ_52
BA37 AV34 DDR_B_DQS#1 <20>
BA29 BC30 DDR_B_DQS6 <20>
DDR_B_D37 BA36 DDR0_DQ_52/DDR1_DQ_36
DDR0_DQSN_5/DDR1_DQSN_1 AV35 DDR_B_DQS1 DDR_B_D54 BD29 DDR1_DQ_53/DDR1_DQ_53
DDR1_DQSP_6/DDR1_DQSP_6 BH31 DDR_B_DQS#7
DDR0_DQSP_5/DDR1_DQSP_1 DDR_B_DQS#4 DDR_B_DQS1 <20> DDR_B_D55 DDR1_DQ_54/DDR1_DQ_54
BC36 BB35 BD30 BH30
l
DDR0_DQSN_6/DDR1_DQSN_4 DDR_B_DQS4 DDR_B_DQS#4 <20> DDR_B_D56 DDR1_DQ_55/DDR1_DQ_55
DDR1_DQSP_7/DDR1_DQSP_7 DDR_B_DQS7 <20>
BC37 BB34 DDR_B_DQS4 <20>
BG31
DDR_B_D40 BE35 DDR0_DQ_55/DDR1_DQ_39
DDR0_DQSP_6/DDR1_DQSP_4 BF34 DDR_B_DQS#5 DDR_B_D57 BG32 DDR1_DQ_56/DDR1_DQ_56 Y29 Trace width=12~15 mil, Spacing=20 mils
DDR0_DQSN_7/DDR1_DQSN_5 DDR_B_DQS5 DDR_B_DQS#5 <20> DDR_B_D58 DDR1_DQ_57/DDR1_DQ_57 NC/DDR1_ALERT# Max trace length= 500 mil
BE34 BF35 DDR_B_DQS5 <20>
BK32 AE34
DDR_B_D42 BG35 DDR0_DQ_57/DDR1_DQ_41
DDR0_DQSP_7/DDR1_DQSP_5 DDR_B_D59 BK31 DDR1_DQ_58/DDR1_DQ_58 NC/DDR1_PAR BU31
DDR_B_D43 BG34 DDR0_DQ_58/DDR1_DQ_42 W37 DDR_B_D60 BG29 DDR1_DQ_59/DDR1_DQ_59 DRAM_RESET#
DDR_B_D44 BE37 DDR0_DQ_59/DDR1_DQ_43 NC/DDR0_ALERT# W31 DDR_B_D61 BG30 DDR1_DQ_60/DDR1_DQ_60 BN28 SM_RCOMP0 RC246 1 2 200_0402_1%
DDR_B_D45 BE36 DDR0_DQ_60/DDR1_DQ_44 NC/DDR0_PAR F36 +VREF_CA_C DDR_B_D62 BK30 DDR1_DQ_61/DDR1_DQ_61 DDR_COMP_0 BN27 SM_RCOMP1 RC247 1 2 80.6_0201_1%
DDR_B_D46 DDR0_DQ_61/DDR1_DQ_45 DDR_VREF_CA +V_DDR_REFA_C +VREF_CA_C DDR_B_D63 DDR1_DQ_62/DDR1_DQ_62 DDR_COMP_1 SM_RCOMP2
a
B BG36 D35 +V_DDR_REFA_C
BK29 BN29 RC40 1 2 162_0402_1% B
DDR_B_D47 BG37 DDR0_DQ_62/DDR1_DQ_46 DDR0_VREF_DQ_0 D37 Trace width/Spacing >= 20mils DDR1_DQ_63/DDR1_DQ_63 DDR_COMP_2
DDR0_DQ_63/DDR1_DQ_47 DDR0_VREF_DQ_1 E36 +V_DDR_REFB_C
DDR1_VREF_DQ DDR_PG_CTRL +V_DDR_REFB_C
C35 WHL-U42_BGA1528
DDR_VTT_CNTL
3 of 20
WHL-U42_BGA1528
p
2 of 20
+1.2V +3VS
< For ODT & VTT Power Control >
DDR_VTT_CNTL to DDR follow CRB
VTT supplied ramped
1
<35uS 1
100K_0402_5%
RC132
(tCPU18) CC1
0.1U_0201_10V6K
@
UC2 2
m
2
1 5
NC VCC
DDR_PG_CTRL 2
A 4
Y DDR_VTT_PG_CTRL <43>
3
GND
74AUP1G07GW_TSSOP5
SA00005U600
o
A A
C
Issued Date 2018/02/06 Deciphered Date 2020/5/17 Title
WHL-U(2/12)LPDDR3
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
5 4 3 2 1
5 4 3 2 1
+3VALW
SML0ALERT# (Internal Pull Down):
RC437 1 2 100K_0201_5% SOC_SPI_0_SI
RC438 1 2 100K_0201_5% SOC_SPI_0_IO2 eSPI or LPC
RC439 1 2 100K_0201_5% SOC_SPI_0_IO3
o
0 = LPC is selected for EC ==> Default
1 = eSPI is selected for EC
v
D D
UC1E
SOC_SPI_0_CLK CH37 CK14 PCH_SMB_CLK
SOC_SPI_0_SO CF37 SPI0_CLK GPP_C0/SMBCLK CH15 PCH_SMB_DATA SMB
SOC_SPI_0_SI CF36 SPI0_MISO GPP_C1/SMBDATA CJ15 (Link to DDR)
SOC_SPI_0_IO2 CF34 SPI0_MOSI GPP_C2/SMBALERT#
o
SPI ROM SOC_SPI_0_IO3 CG34 SPI0_IO2 CH14 SOC_SML0CLK
SOC_SPI_0_CS#0 CG36 SPI0_IO3 GPP_C3/SML0CLK CF15 SOC_SML0DATA
CG35 SPI0_CS0# GPP_C4/SML0DATA CG15
CH34 SPI0_CS1# GPP_C5/SML0ALERT#
SPI0_CS2# CN15 EC_SMB_CK2
GPP_C6/SML1CLK EC_SMB_DA2 EC_SMB_CK2 <24,30,34,36> SML1
n
CM15 EC_SMB_DA2 <24,30,34,36>
CF20 GPP_C7/SML1DATA CC34 SOC_SML1ALERT# (Link to EC,DGPU,Thermal IC)
CG22 GPP_D1/SPI1_CLK/BK1/SBK1 GPP_B23/SML1ALERT#/PCHHOT#
CF22 GPP_D2/SPI1_MISO_IO1/BK2/SBK2
CG23 GPP_D3/SPI1_MOSI_IO0/BK3/SBK3 CA29 LPC_AD0
GPP_D21/SPI1_IO2 GPP_A1/LAD0/ESPI_IO0 LPC_AD1 LPC_AD0 <34>
CH23 BY29
e
GPP_D22/SPI1_IO3 GPP_A2/LAD1/ESPI_IO1 LPC_AD2 LPC_AD1 <34>
CG20 BY27
GPP_D0/SPI1_CS0#/BK0/SBK0 GPP_A3/LAD2/ESPI_IO2 LPC_AD3 LPC_AD2 <34>
BV27
GPP_A4/LAD3/ESPI_IO3 LPC_FRAME# LPC_AD3 <34>
CA28
GPP_A5/LFRAME#/ESPI_CS# LPC_FRAME# <34>
CA27
+3VS CH7 GPP_A14/SUS_STAT#/ESPI_RESET#
CH8 CL_CLK
CH9 CL_DATA BV32 LPC_CLK0 RC26 1 EMI@ 2 22_0402_5%
L
CL_RST# GPP_A9/CLKOUT_LPC0/ESPI_CLK CLK_LPC_EC <34>
RC25 1 2 8.2K_0402_5% SERIRQ BV30
KB_RST# BV29 GPP_A10/CLKOUT_LPC1 BY30 PM_CLKRUN#
GPP_A0/RCIN#/TIME_SYNC1 GPP_A8/CLKRUN# PM_CLKRUN# <34>
SERIRQ BV28
<34> SERIRQ GPP_A6/SERIRQ
C 1 C
+3VS W HL-U42_BGA1528
33P_0402_50V8J
r
@RF@ CC3865
5 of 20 2
RC112 1 2 10K_0402_5% KB_RST# Close to RC26
+3VS
From SOC
RPC1, RPC3 and RC30 are close to UC3
SOC_SPI_0_SO
SOC_SPI_0_CLK
SOC_SPI_0_SI
SOC_SPI_0_IO3
RC469
RC470
RC471
RC472
SOC_SPI_0_IO2 1
1
1 EMI@
1
1
2
2
2
2
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
2 SOC_SPI_0_IO2_R
SOC_SPI_0_SO_R
SOC_SPI_0_CLK_R
SOC_SPI_0_SI_R
SOC_SPI_0_IO3_R
F o EC_SMB_CK2
EC_SMB_DA2
SOC_SML1ALERT#
RC28
RC29
RC113
1
1 @
2 1K_0402_5%
2 1K_0402_5%
2
150K_0402_5%
l
RC30 33_0402_5%
PCH_SMB_CLK RC465 2 1 1K_0402_5%
PCH_SMB_DATA RC466 2 1 1K_0402_5%
SOC_SML0CLK RC467 2 1 1K_0402_5%
a
SOC_SML0DATA RC468 2 1 1K_0402_5%
EC_SPI_CLK RC473 1 EMI@ 2 33_0402_5% SOC_SPI_0_CLK_R

B <34> EC_SPI_CLK EC_SPI_MOSI SOC_SPI_0_SI_R B
RC474 1 2 33_0402_5%
<34> EC_SPI_MOSI EC_SPI_CS0# SOC_SPI_0_CS#0
From EC RC475 1 2 33_0402_5%
<34> EC_SPI_CS0# EC_SPI_MISO SOC_SPI_0_SO_R
RC476 1 2 33_0402_5% +3VS
p
<34> EC_SPI_MISO
PM_CLKRUN# 1 2
RC31 8.2K_0402_5%
m
< SPI ROM - 16M >
+3VALW
@
UC3 CC2 1 2 0.1U_0201_10V6K
o
SOC_SPI_0_CS#0 1 8
SOC_SPI_0_SO_R 2 CS# VCC 7 SOC_SPI_0_IO3_R
SOC_SPI_0_IO2_R 3 DO(IO1) IO 6 SOC_SPI_0_CLK_R
4 IO2 CLK 5 SOC_SPI_0_SI_R
GND DI(IO0)
1
XM25QH128AHIG SOP 8P
CC3
C
10P_0402_50V8J
2 @EMI@
A A

WHL-U(3/12)SPI,SMB,LPC,ESPI
5 4 3 2 1
5 4 3 2 1
Vender ID
CPU_GPP_G7 CPU_GPP_G6 CPU Memory down vender control table BOM Conf i g
SDRAM_ID4 SDRAM_ID3 CPU_GPP_G7 CPU_GPP_G6 CPU_GPP_G5 CPU_GPP_G4
Vender MD size SDRAM_ID4 SDRAM_ID3 SDRAM_ID2 SDRAM_ID1 LPDDR3
Samsung 0 0 SDRAM_ID4 SDRAM_ID3 Vender SDRAM_ID2 SDRAM_ID1 MD size Vender desciption
RC435 RC433 RC248 RC249 UD3 S4G@ UD4 S4G@
Hynix 0 1 0 0 4GB K4E8E324EB-EGCG 4GB S4G@ S4G@ S4G@ S4G@ SA0000AZT20 SA0000AZT20
Micron 1 0 0 0 Samsung 0 1 8GB K4E6E304EC-EGCG
o
RC435 RC433 RC89 RC249 UD1 S8G@ UD2 S8G@ UD3 S8G@ UD4 S8G@
1 0 16GB K4EBE304EC-EGCG Samsung 8GB S8G@ S8G@ S8G@ S8G@ SA0000AZT20 SA0000AZT20 SA0000AZT20 SA0000AZT20
1 1 4GB K4E6E304EC-EGCG(CHB-ONLY)
RC435 RC433 RC248 RC88 UD1 S16G@ UD2 S16G@ UD3 S16G@ UD4 S16G@
D
0 0 4GB H9CCNNN8GTALAR-NVD 16GB S16G@ S16G@ S16G@ S16G@ SA00008VV20 SA00008VV20 SA00008VV20 SA00008VV20 D
v
CPU_GPP_G5 CPU_GPP_G4 0 1 Hynix 0 1 8GB H9CCNNNBJTALAR-NVD
DRAM Capacity SDRAM_ID2 SDRAM_ID1 RC435 RC432 RC248 RC249 UD3 H4G@ UD4 H4G@
1 0 16GB H9CCNNNCLGALAR-NVD 4GB H4G@ H4G@ H4G@ H4G@ SA0000ALP00 SA0000ALP00
4GB 0 0 1 1 4GB H9CCNNNBJTALAR-NVD(CHB-ONLY)
RC435 RC432 RC89 RC249 UD1 H8G@ UD2 H8G@ UD3 H8G@ UD4 H8G@
8GB 0 1 0 0 4GB MT52L256M32D1PF-093WT:B Hynix 8GB
o
H8G@ H8G@ H8G@ H8G@ SA0000ALP00 SA0000ALP00 SA0000ALP00 SA0000ALP00
16GB 1 0 1 0 Micron 0 1 8GB MT52L512M32D2PF-093WT:B
RC435 RC432 RC248 RC88 UD1 H16G@ UD2 H16G@ UD3 H16G@ UD4 H16G@
1 0 16GB MT52L1G32D4PG-093WT:B 16GB H16G@ H16G@ H16G@ H16G@ SA00009ZL00 SA00009ZL00 SA00009ZL00 SA00009ZL00
1 1 4GB MT52L512M32D2PF-093WT:B(CHB-ONLY)
RC434 RC433 RC248 RC249 UD3 M4G@ UD4 M4G@
n
4GB M4G@ M4G@ M4G@ M4G@ SA0000AM400 SA0000AM400
RC434 RC433 RC89 RC249 UD1 M8G@ UD2 M8G@ UD3 M8G@ UD4 M8G@
< HD AUDIO > HDA_SDOUT reserve 500 ohm PD for Audio 8GB M8G@ M8G@ M8G@ M8G@ SA0000AM400 SA0000AM400 SA0000AM400 SA0000AM400
lost issue
Micron
e
RC434 RC433 RC248 RC88 UD1 M16G@ UD2 M16G@ UD3 M16G@ UD4 M16G@
16GB M16G@ M16G@ M16G@ M16G@ SA00009ZN00 SA00009ZN00 SA00009ZN00 SA00009ZN00
RC477 1 EMI@ 2 33_0402_5% HDA_BIT_CLK
<33> HDA_BIT_CLK_R HDA_SYNC
<33> HDA_SYNC_R RC478 1 2 33_0402_5%
RC479 1 2 33_0402_5% HDA_SDOUT
<33> HDA_SDOUT_R
1
Memory Strap Resistors
33P_0402_50V8J
UC1G
@RF@ CC3866
RC3945 HDA_SYNC BN34
L
Close to RC477 @ HDA_BIT_CLK BN37 HDA_SYNC/I2S0_SFRM CH36
499_0402_1% HDA_BCLK/I2S0_SCLK GPP_G0/SD_CMD
2 HDA_SDOUT BN36 CL35 +3VS +3VS +3VS +3VS
BN35 HDA_SDO/I2S0_TXD GPP_G1/SD3_DATA0 CL36
<33> HDA_SDIN0
2
BL36 HDA_SDI0/I2S0_RXD GPP_G2/SD3_DATA1 CM35

HDA_SDI1/I2S1_RXD/SNDW1_DATA GPP_G3/SD3_DATA2
1
BL35 CN35 SDRAM_ID1
C CK23 HDA_RST#/I2S1_SCLK/SNDW1_CLK GPP_G4/SD_DATA3 CH35 SDRAM_ID2 RC249 RC248 RC432 RC434 C
GPP_D23/I2S_MCLK GPP_G5/SD_CD# CK36 SDRAM_ID3
GPP_G6/SD_CLK 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5%
BL37 CK34 SDRAM_ID4 @ @ @ @
r
BL34 I2S1_SFRM/SNDW2_CLK GPP_G7/SD_WP
2
I2S1_TXD/SNDW2_DATA SDRAM_ID1
< To Enable ME Override > SDRAM_ID2
CNV_RF_RESET# CJ32 SDRAM_ID3
<32> CNV_RF_RESET# GPP_H1/I2S2_SFRM/CNV_BT_I2S_BCLK/CNV_RF_RESET# SDRAM_ID4
CH32
CLKREQ_CNV# CH29 GPP_H0/I2S2_SCLK/CNV_BT_I2S_SCLK
<32> CLKREQ_CNV# GPP_H2/I2S2_TXD/CNV_BT_I2S_SDI/MODEM_CLKREQ
1
CH30 BW36
GPP_H3/I2S2_RXD/CNV_BT_I2S_SDO GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7
o
BY31 RC88 RC89 RC433 RC435
CP24 GPP_A16/SD_1P8_SEL
GPP_D19/DMIC_CLK0/SNDW4_CLK 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5%
RC116 2 1 0_0402_5% HDA_SDOUT CN24 @ @ @ @
<34> ME_EN GPP_D20/DMIC_DATA0/SNDW4_DATA CK33
2
CK25 SD_1P8_RCOMP CM34 SOC_SD_RCOMP RC440 1 2 200_0402_1%
CJ25 GPP_D17/DMIC_CLK1/SNDW3_CLK SD_3P3_RCOMP
GPP_D18/DMIC_DATA1/SNDW3_DATA
HDA_SPKR CF35
<33> HDA_SPKR
F
GPP_B14/SPKR
WHL-U42_BGA1528
7 of 20
l
GC6_FB_EN RC463 2 1 0_0402_5% GC6_FB_EN1V8
<24,25> GC6_FB_EN
DGPU GPU_EVENT# RC464 1 2 0_0402_5% SOC_GPP_C10

<24> GPU_EVENT# GPP_H21 XTAL frequency selected.
0: 38.4/19.2Mhz
a
UC1I 1: 24MHz XTAL selected
CNV_CRX_DTX_N0 CR30 CN27 SOC_C10_GATE# +3VALW
<32> CNV_CRX_DTX_N0 CNV_CRX_DTX_P0 CNV_WR_D0N GPP_H18/CPU_C10_GATE# SOC_C10_GATE# <13>
B
<32> CNV_CRX_DTX_P0
CP30 B
CNV_WR_D0P CM27
CNV_CRX_DTX_N1 CM30 GPP_H19/TIMESYNC_0
<32> CNV_CRX_DTX_N1 CNV_CRX_DTX_P1 CNV_WR_D1N SOC_GPP_H21
CN30 CF25 RC4411 2 4.7K_0402_5%
<32> CNV_CRX_DTX_P1 CNV_WR_D1P GPP_H21
p
CNV_CTX_DRX_N0 CN32 CN26
<32> CNV_CTX_DRX_N0 CNV_CTX_DRX_P0 CM32 CNV_WT_D0N GPP_H22 CM26
<32> CNV_CTX_DRX_P0 CNV_WT_D0P GPP_H23 CK17
CNV_CTX_DRX_N1 CP33 GPP_F10
<32> CNV_CTX_DRX_N1 CNV_CTX_DRX_P1 CNV_WT_D1N SOC_GPD7
CN33 BV35 RC442 1 2 100K_0201_5%
<32> CNV_CTX_DRX_P1 CNV_WT_D1P GPD7 CN20
CLK_CNV_CRX_DTX_N CN31 GPP_F3
1 CNV_RF_RESET# <32> CLK_CNV_CRX_DTX_N CLK_CNV_CRX_DTX_P CNV_WR_CLKN XTAL INPUT MODE (HVM ONLY)
75K_0402_5% CNVi@2 RC3907 CP31 CG25
<32> CLK_CNV_CRX_DTX_P CLK_CNV_CTX_DRX_N CP34 CNV_WR_CLKP GPP_D4/IMGCLKOUT0/BK4/SBK4 CH25 LOW: XTAL INPUT IS SINGLE ENDED
<32> CLK_CNV_CTX_DRX_N CLK_CNV_CTX_DRX_P CNV_WT_CLKN GPP_H20/IMGCLKOUT_1
<32> CLK_CNV_CTX_DRX_P
CN34
CNV_WT_CLKP
HIGH: XTAL IS ATTACHED
CR20
CNV_WT_RCOMP GPP_F12/EMMC_DATA0
m
150_0402_1% 1 CNVi@ 2 RC443 CP32 CM20
CR32 CNV_WT_RCOMP_0 GPP_F13/EMMC_DATA1 CN19
COEX3 CP20 CNV_WT_RCOMP_1 GPP_F14/EMMC_DATA2 CM19
Follow Jefferson Peak schematic check list. <32> COEX3 GPP_F0/CNV_PA_BLANKING GPP_F15/EMMC_DATA3 CN18
GC6_FB_EN1V8 CK19 GPP_F16/EMMC_DATA4 CR18
CG17 GPP_F1 GPP_F17/EMMC_DATA5 CP18
GPP_F2 GPP_F18/EMMC_DATA6 CM18
GPP_F19/EMMC_DATA7
o
CR14
<35> TP_INT# GPP_C8/UART0_RXD
CP14
SOC_GPP_C10 CN14 GPP_C9/UART0_TXD CM16
WLBT_OFF# CM14 GPP_C10/UART0_RTS# GPP_F20/EMMC_RCLK CP16
<32> WLBT_OFF# GPP_C11/UART0_CTS# GPP_F21/EMMC_CLK CR16
+3VS COEX1 CJ17 GPP_F11/EMMC_CMD CN16
<32> COEX1 GPP_F8/CNV_MFUART2_RXD GPP_F22/EMMC_RESET#
COEX2 CH17
<32> COEX2 GPP_F9/CNV_MFUART2_TXD SOC_SD_RCOMP
CK15
RC444 1 2 SOC_A4WP_PRESENT CF17 EMMC_RCOMP
RC487 1 @ 2 10K_0402_5% WLBT_OFF# GPP_F23/A4WP_PRESENT
C
10K_0402_5%
WHL-U42_BGA1528
RC33 1 @ 2 2.2K_0402_5% HDA_SPKR 9 of 20

A A
SPKR (Internal Pull Down):
TOP Swap Override
0 = Disable TOP Swap mode. ==> Default

1 = Enable TOP Swap Mode. Issued Date 2017/5/3 Deciphered Date 2017/6/2 Title
WHL-U(4/12)HDA,EMMC,SDIO,CSI2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
5 4 3 2 1
5 4 3 2 1
+3VS
XCLK_BIASREF RC110 1 2 60.4_0402_1%

RC481 1 2 10K_0402_5% CLKREQ_PCIE#0
RC482 1 2 10K_0402_5% CLKREQ_PCIE#2 UC1J CLKIN_XTAL RC245 1 2 10K_0402_5%
o
RC483 1 2 10K_0402_5% CLKREQ_PCIE#4
AW2 AU1
<21> CLK_PCIE_N0 CLKOUT_PCIE_N_0 CLKOUT_ITPXDP_N
DGPU AY3 AU2
CLKREQ_PCIE#0 <21> CLK_PCIE_P0 CLKREQ_PCIE#0 CF32 CLKOUT_PCIE_P_0 CLKOUT_ITPXDP_P
<21> CLKREQ_PCIE#0 GPP_B5/SRCCLKREQ0#
1
BT32 SUSCLK
BC1 GPD8/SUSCLK SUSCLK <32>
RC140 @
BC2 CLKOUT_PCIE_N_1 CK3 33E_SOC_XTAL24_IN_R
D 10K_0402_5% CLKOUT_PCIE_P_1 XTAL_IN D
33E_SOC_XTAL24_OUT_R
v
CE32 CK2
GPP_B6/SRCCLKREQ1# XTAL_OUT
2
BD3 CJ1 XCLK_BIASREF

<32> CLK_PCIE_N2 BC3 CLKOUT_PCIE_N_2 CLK_BIASREF CM3 CLKIN_XTAL
NGFF WL+BT(KEY E) <32> CLK_PCIE_P2 CLKREQ_PCIE#2 CLKOUT_PCIE_P_2 CLKIN_XTAL CLKIN_XTAL <32>
<32> CLKREQ_PCIE#2 CF30
GPP_B7/SRCCLKREQ2# BN31 SOC_RTCX1
BH3 RTCX1 BN32 SOC_RTCX2
CLKOUT_PCIE_N_3 RTCX2
o
BH4
CE31 CLKOUT_PCIE_P_3 BR37 SOC_SRTCRST#
GPP_B8/SRCCLKREQ3# SRTCRST# BR34 EC_CLEAR_CMOS# 33E_SOC_XTAL24_IN_R 1 EMI@ 2 33E_SOC_XTAL24_IN
BA1 RTCRST# RC58 47_0201_5%
<32> CLK_PCIE_N4 BA2 CLKOUT_PCIE_N_4
SSD <32> CLK_PCIE_P4 CLKREQ_PCIE#4 CLKOUT_PCIE_P_4
CE30
<32> CLKREQ_PCIE#4 GPP_B9/SRCCLKREQ4# LC99 @EMI@
BE1 1 2
n
BE2 CLKOUT_PCIE_N_5 1 2
+3VL_RTC CF31 CLKOUT_PCIE_P_5 RC38 1 2 200K_0402_1%
GPP_B10/SRCCLKREQ5# 4 3
WHL-U42_BGA1528 4 3
RC36 1 2 20K_0402_5% SOC_SRTCRST# DLM0NSN900HY2D_4P
10 of 20 YC3 SJ10000UJ00
e
CC6 2 1 1U_0201_6.3V6M 33E_SOC_XTAL24_OUT_R 1 2 33E_SOC_XTAL24_OUT
24MHZ_18PF_XRCGB24M000F2P51R0
RC63 EMI@ 47_0201_5%
3 1
3 1
NC NC
27P_0402_50V8J
CC19
27P_0402_50V8J
CC20
1 1
RC37 1 2 20K_0402_5% EC_CLEAR_CMOS# <34> 4 2
CC7 2 1 1U_0201_6.3V6M
2 2
L
CLRP2 1 2 SHORT PADS CLR CMOS < PCH PLTRST Buf f er >
RC55 1 2 0_0402_5%
RC39 1 2 1M_0402_5% SM_INTRUDER#
C +3VS C
r
5
+3VALW UC4
SOC_PLTRST# 1
P
B 4
Y PCI_RST# <21,32,34>
2
A
1
TC7SH08FUF_SSOP5 SOC_RTCX2
3
o
1
RC44
100K_0402_5%
@
CC8
100P_0402_50V8J
2
ESD@ SOC_RTCX1
2
RC484 1 2 10K_0402_5% PCH_PWROK 1 2
RC485 1 2 10K_0402_5% EC_RSMRST# RC41 10M_0402_5%
RC486 1 2 10K_0402_5% SYS_RESET#
F
YC2
1 2
32.768KHZ_9PF_X1A000141000200
l
ESD@ 1 2 SYS_RESET#
CC97 100P_0402_50V8J UC1K 1 1
ESD@ 1 2 EC_RSMRST#
CC94 100P_0402_50V8J BJ37 CC9 CC10
ESD@ 1 2 SYS_PWROK SOC_PLTRST# BJ35 GPP_B12/SLP_S0# BU36 PM_SLP_S3# 6.8P_0402_50V8C 6.8P_0402_50V8C
SYS_RESET# GPP_B13/PLTRST# GPD4/SLP_S3# PM_SLP_S4# PM_SLP_S3# <34> 2 2
CC95 100P_0402_50V8J CN10 BU27
a
EC_RSMRST# SYS_RESET# GPD5/SLP_S4# PM_SLP_S5# PM_SLP_S4# <34,41>
BR36 BT29
<34> EC_RSMRST# RSMRST# GPD10/SLP_S5# TP@T131
T31 TP@ AR2 BU29
B EC_VCCST_PG BJ2 PROCPWRGD SLP_SUS# BT31 B
VCCST_PWRGOOD SLP_LAN# BT30
SYS_PWROK CR10 GPD9/SLP_WLAN# BU37
+3VALW <34> SYS_PWROK PCH_PWROK SYS_PWROK GPD6/SLP_A#
BP31
<34> PCH_PWROK PCH_PWROK
p
EC_RSMRST# BP30 BU28 PBTN_OUT#
DSW_PWROK GPD3/PWRBTN# AC_PRESENT_R PBTN_OUT# <34>
BU35 RC103 1 2 0_0402_5% AC_PRESENT <24,34>
RC54 GPD1/ACPRESENT PM_BATLOW#
BV34 BV36
1 2 WAKE# BY32 GPP_A13/SUSWARN#/SUSPWRDACK GPD0/BATLOW# +3VALW
GPP_A15/SUSACK#
WAKE# BU30 BR35 SM_INTRUDER#
1K_0402_5% BU32 WAKE# INTRUDER# PM_BATLOW# 1 2
BU34 GPD2/LAN_WAKE# CC37 RC46 8.2K_0402_5%
GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# CC36 SOC_VRALERT# AC_PRESENT_R 1 @ 2
GPP_B2/VRALERT# RC48 10K_0402_5%
BT27 SOC_INPUT3VSEL SOC_VRALERT# 1 @ 2
INPUT3VSEL
m
+1.05V_VCCST RC50 10K_0402_5%
From EC (Open-Drain) SOC_INPUT3VSEL 1 @ 2
RC445 4.7K_0402_5%
1
WHL-U42_BGA1528 1 2
RC52 RC446 4.7K_0402_5%
11 of 20
1K_0402_5%
o
2
RC53 1 2 60.4_0402_1% EC_VCCST_PG

<34> VCCST_PWRGD
100P_0402_50V8J
CC126 ESD@
C
A A

WHL-U(5/12)CLK,PM,GPIO
5 4 3 2 1
5 4 3 2 1
GSPI0_MOSI (Internal Pull Down):
No Reboot
0 = Disable No Reboot mode. ==> Default
o
1 = Enable No Reboot Mode. (PCH will disable the TCO
Timer system reboot feature). This funct i oni s us ef ul
when running ITP/XDP.
D D
v
GSPI1_MOSI (Internal Pull Down):
UC1F
Boot BIOS Strap Bit CC27
T2406 SOC_GPP_A7 GPP_B15/GSPI0_CS0#
o
CC32 CN22
GPP_B16 CE28 GPP_A7/PIRQA#/GSPI0_CS1# GPP_D9/ISH_SPI_CS#/GSPI2_CS0# CR22
0 = SPI Mode ==> Default CE27 GPP_B16/GSPI0_CLK GPP_D10/ISH_SPI_CLK/GSPI2_CLK CM22
GSPI0_MOSI CE29 GPP_B17/GSPI0_MISO GPP_D11/ISH_SPI_MISO/GSPI2_MISO CP22
TP@
GPP_B18/GSPI0_MOSI GPP_D12/ISH_SPI_MOSI/GSPI2_MOSI
1 = LPC Mode
CA31 CK22
CA32 GPP_B19/GSPI1_CS0# GPP_D5/ISH_I2C0_SDA CH20
CC29 GPP_A11/PME#/GSPI1_CS1#/SD_VDD2_PWR_EN# GPP_D6/ISH_I2C0_SCL
n
+3VS CC30 GPP_B20/GSPI1_CLK CH22
GSPI1_MOSI CA30 GPP_B21/GSPI1_MISO GPP_D7/ISH_I2C1_SDA CJ22
RC59 1 @ 2 4.7K_0402_5% GSPI0_MOSI GPP_B22/GSPI1_MOSI GPP_D8/ISH_I2C1_SCL
CNV_BRI_CRX_DTX CK20
<32> CNV_BRI_CRX_DTX CNV_RGI_CTX_DRX GPP_F5/CNV_BRI_RSP
CG19 CJ27
1 2 150K_0402_5% GSPI1_MOSI <32> CNV_RGI_CTX_DRX CNV_BRI_CTX_DRX CJ20 GPP_F6/CNV_RGI_DT GPP_H10/I2C5_SDA/ISH_I2C2_SDA CJ29 GPP_H11
RC60 @
e
<32> CNV_BRI_CTX_DRX CNV_RGI_CRX_DTX GPP_F4/CNV_BRI_DT GPP_H11/I2C5_SCL/ISH_I2C2_SCL TP@ T2405
CH19
<32> CNV_RGI_CRX_DTX GPP_F7/CNV_RGI_RSP CM24
GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA CN23
CR12 GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL CM23
<32,35> UART0_RX GPP_C20/UART2_RXD GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#
CP12 CR24
<32,35> UART0_TX GPP_C21/UART2_TXD GPP_D16/ISH_UART0_CTS#/SML0BALERT#
CN12
CM12 GPP_C22/UART2_RTS# CG12 DGPU_PWR_EN
GPP_C23/UART2_CTS# GPP_C12/UART1_RXD/ISH_UART1_RXD DGPU_HOLD_RST# DGPU_PWR_EN <24,26,34>
CH12 DGPU
GPP_C13/UART1_TXD/ISH_UART1_TXD GPU_ALL_PGOOD DGPU_HOLD_RST# <21>
CM11 CF12
L
Touch Pad <35> I2C_0_SDA
CN11 GPP_C16/I2C0_SDA GPP_C14/UART1_RTS#/ISH_UART1_RTS# CG14 DGPU_PRSNT# GPU_ALL_PGOOD <21>
+3VS <35> I2C_0_SCL GPP_C17/I2C0_SCL GPP_C15/UART1_CTS#/ISH_UART1_CTS#
CK12 BW35
<30> I2C_1_SDA GPP_C18/I2C1_SDA GPP_A18/ISH_GP0
UCM CJ12 BW34
UART0_RX <30> I2C_1_SCL GPP_C19/I2C1_SCL GPP_A19/ISH_GP1
RC83 1 2 49.9K_0402_1% CA37
C
RC84 1 2 49.9K_0402_1% UART0_TX CF27 GPP_A20/ISH_GP2 CA36 C
RC3941 1 2 2.2K_0402_5% I2C_1_SDA CF29 GPP_H4/I2C2_SDA GPP_A21/ISH_GP3 CA35
RC3942 1 2 2.2K_0402_5% I2C_1_SCL GPP_H5/I2C2_SCL GPP_A22/ISH_GP4 CA34
r
RC488 1 DIS@ 2 10K_0402_5% DGPU_PWR_EN CH27 GPP_A23/ISH_GP5 BW37
RC489 1 2 10K_0402_5% SOC_GPP_A7 CH28 GPP_H6/I2C3_SDA GPP_A12/ISH_GP6/BM_BUSY#/SX_EXIT_HOLDOFF#
1 2 I2C_0_SDA GPP_H7/I2C3_SCL DGPU_PRSNT#
RC42 2.2K_0402_5%
I2C_0_SCL
Funct i on (GPP_C15)
RC43 1 2 2.2K_0402_5% CJ30
RC447 1 @ 2 10K_0402_5% DGPU_HOLD_RST# CJ31 GPP_H8/I2C4_SDA
RC448 1 DIS@ 2 10K_0402_5% DGPU_HOLD_RST# GPP_H9/I2C4_SCL DIS 0
WHL-U42_BGA1528 UMA Only 1
o
6 of 20 +3VS
DGPU_PRSNT# 10K_0402_5% 2 UMA@ 1 R73
10K_0402_5% 2 DIS@ 1 R74
l F
a
B B
Place close to PCH
p
+1.8VALW
CNV_RGI_CRX_DTX RC3939 1 @ 2 20K_0201_5%

CNV_BRI_CRX_DTX RC3938 1 @ 2 20K_0201_5%
o m
C
A A

WHL-U(6/12)GPIO,I2C,GSPI
5 4 3 2 1
5 4 3 2 1
BW9
BW8
BW4
BW3
UC1H
PCIE5_RXN/USB31_5_RXN
PCIE5_RXP/USB31_5_RXP
PCIE5_TXN/USB31_5_TXN
PCIE5_TXP/USB31_5_TXP
PCIE1_RXN/USB31_1_RXN
PCIE1_RXP/USB31_1_RXP
PCIE1_TXN/USB31_1_TXN
PCIE1_TXP/USB31_1_TXP
CB5
CB6
CA4
CA3
BY8
USB3_CRX_DTX_N1
USB3_CRX_DTX_P1
USB3_CTX_DRX_N1
USB3_CTX_DRX_P1
<37>
<37>
<37>
<37>
v oUSB2/3 (re-driver) (I/O SB)

D
o
PCIE2_RXN/USB31_2_RXN/SSIC_1_RXN USB3_CRX_DTX_N2 <37>
BU6 BY9 USB3_CRX_DTX_P2 <37>
BU5 PCIE6_RXN/USB31_6_RXN PCIE2_RXP/USB31_2_RXP/SSIC_1_RXP CA2
BU4 PCIE6_RXP/USB31_6_RXP PCIE2_TXN/USB31_2_TXN/SSIC_1_TXN CA1
USB3_CTX_DRX_N2 <37> USB2/3 (for charger)
PCIE6_TXN/USB31_6_TXN PCIE2_TXP/USB31_2_TXP/SSIC_1_TXP USB3_CTX_DRX_P2 <37>
BU3
PCIE6_TXP/USB31_6_TXP BY7
PCIE3_RXN/USB31_3_RXN USB3_CRX_MTX_N3 <30>
n
BT7 BY6 USB3_CRX_MTX_P3 <30>
BT6 PCIE7_RXN PCIE3_RXP/USB31_3_RXP BY4
BU2 PCIE7_RXP PCIE3_TXN/USB31_3_TXN BY3
USB3_CTX_MRX_N3 <30> Type-C
PCIE7_TXN PCIE3_TXP/USB31_3_TXP USB3_CTX_MRX_P3 <30>
BU1
PCIE7_TXP BW6
BU9 PCIE4_RXN/USB31_4_RXN BW5
e
<32> PCIE_CRX_DTX_N8 PCIE8_RXN PCIE4_RXP/USB31_4_RXP
<32> PCIE_CRX_DTX_P8 BU8 BW2
BT4 PCIE8_RXP PCIE4_TXN/USB31_4_TXN BW1
NGFF WLAN+BT <32> PCIE_CTX_DRX_N8 PCIE8_TXN PCIE4_TXP/USB31_4_TXP
BT3
<32> PCIE_CTX_DRX_P8 PCIE8_TXP CE3 USB20_N1
USB2_1N USB20_P1 USB20_N1 <37>
<32> PCIE_CRX_DTX_N9 BP5 CE4 USB2/3 (re-driver) ( I/O BD)
PCIE9_RXN USB2_1P USB20_P1 <37>
<32> PCIE_CRX_DTX_P9 BP6
BR2 PCIE9_RXP CE1 USB20_N2
L
<32> PCIE_CTX_DRX_N9 PCIE9_TXN USB2_2N USB20_P2 USB20_N2 <37>
BR1 CE2 USB2/3 (Charger)
<32> PCIE_CTX_DRX_P9 PCIE9_TXP USB2_2P USB20_P2 <37>
BN6 CG3 USB20_N3
<32> PCIE_CRX_DTX_N10 PCIE10_RXN USB2_3N USB20_P3 USB20_N3 <31>
<32> PCIE_CRX_DTX_P10 BN5 CG4 Type-C
PCIE10_RXP USB2_3P USB20_P3 <31>
C BR4 C
<32> PCIE_CTX_DRX_N10 PCIE10_TXN
BR3 CD3
<32> PCIE_CTX_DRX_P10 PCIE10_TXP USB2_4N
r
SSD CD4
BN10 USB2_4P
<32> PCIE_CRX_DTX_N11 BN8 PCIE11_RXN/SATA0_RXN CG5 USB20_N5
<32> PCIE_CRX_DTX_P11 PCIE11_RXP/SATA0_RXP USB2_5N USB20_P5 USB20_N5 <28>
BN4 CG6 Camera
<32> PCIE_CTX_DRX_N11 PCIE11_TXN/SATA0_TXN USB2_5P USB20_P5 <28>
BN3
<32> PCIE_CTX_DRX_P11 PCIE11_TXP/SATA0_TXP
CC1 USB20_N6
o
BL6 USB2_6N USB20_P6 USB20_N6 <35>
<32> PCIE_CRX_DTX_N12 PCIE12_RXN/SATA1A_RXN CC2 FP
BL5 USB2_6P USB20_P6 <35>
<32> PCIE_CRX_DTX_P12 BN2 PCIE12_RXP/SATA1A_RXP CG8
<32> PCIE_CTX_DRX_N12 BN1 PCIE12_TXN/SATA1A_TXN USB2_7N CG9
<32> PCIE_CTX_DRX_P12 PCIE12_TXP/SATA1A_TXP USB2_7P
<21> PCIE_CRX_DTX_N13 BK6 CB8
BK5 PCIE13_RXN USB2_8N CB9
<21> PCIE_CRX_DTX_P13
F
CC114 DIS@ 1 2 0.22U_0201_6.3V6M PCIE_CTX_DRX_N13 BM4 PCIE13_RXP USB2_8P
<21> PCIE_CTX_C_DRX_N13 PCIE13_TXN
<21> PCIE_CTX_C_DRX_P13 CC149 DIS@ 1 2 0.22U_0201_6.3V6M PCIE_CTX_DRX_P13 BM3 CH5
PCIE13_TXP USB2_9N CH6
BJ6 USB2_9P
<21> PCIE_CRX_DTX_N14 PCIE14_RXN USB20_N10
BJ5 CC3
<21> PCIE_CRX_DTX_P14 PCIE14_RXP USB2_10N USB20_N10 <32>
CC188 DIS@ 1 2 0.22U_0201_6.3V6M PCIE_CTX_DRX_N14 BL2 CC4 USB20_P10
CNVi
l
<21> PCIE_CTX_C_DRX_N14 PCIE14_TXN USB2_10P USB20_P10 <32>
CC187 DIS@ 1 2 0.22U_0201_6.3V6M PCIE_CTX_DRX_P14 BL1
<21> PCIE_CTX_C_DRX_P14 PCIE14_TXP CC5 USB2_COMP RC70 1 2 113_0402_1%
BG5 USB2_COMP CE8 USB2_ID 1 2 0_0402_5%
dGPU <21> PCIE_CRX_DTX_N15 PCIE15_RXN/SATA1B_RXN USB2_ID USB2_SENSE
RC104 @
BG6 CC6 RC105 1 @ 2 1K_0402_5% Trace length max: 450mils
<21> PCIE_CRX_DTX_P15 CC185 DIS@ 1 2 0.22U_0201_6.3V6M PCIE_CTX_DRX_N15 BL4 PCIE15_RXP/SATA1B_RXP USB2_VBUSSENSE
<21> PCIE_CTX_C_DRX_N15
a
CC186 DIS@ 1 2 0.22U_0201_6.3V6M PCIE_CTX_DRX_P15 BL3 PCIE15_TXN/SATA1B_TXN CK6 USB_OC0#
<21> PCIE_CTX_C_DRX_P15 PCIE15_TXP/SATA1B_TXP GPP_E9/USB2_OC0#/GP_BSSB_CLK CK5 USB_OC1#
BE5 GPP_E10/USB2_OC1#/GP_BSSB_DI CK8 USB_OC2#
B <21> PCIE_CRX_DTX_N16 BE6 PCIE16_RXN/SATA2_RXN GPP_E11/USB2_OC2# CK9 USB_OC3# B
<21> PCIE_CRX_DTX_P16 CC184 DIS@ 1 2 0.22U_0201_6.3V6M PCIE_CTX_DRX_N16 BJ4 PCIE16_RXP/SATA2_RXP GPP_E12/USB2_OC3#
<21> PCIE_CTX_C_DRX_N16 PCIE16_TXN/SATA2_TXN
CC183 DIS@ 1 2 0.22U_0201_6.3V6M PCIE_CTX_DRX_P16 BJ3 CP8
p
<21> PCIE_CTX_C_DRX_P16 PCIE16_TXP/SATA2_TXP GPP_E4/DEVSLP0 CR8 W L_OFF#
PCIE_RCOMPN GPP_E5/DEVSLP1 W L_OFF# <32>
RC71 1 2 100_0402_1% CE6 CM8
PCIE_RCOMPP CE5 PCIE_RCOMP_N GPP_E6/DEVSLP2
Near UC1 PCIE_RCOMP_P CN8
CR28 GPP_E0/SATAXPCIE0/SATAGP0 CM10
CP28 GPP_H12/M2_SKT2/CFG_0 GPP_E1/SATAXPCIE1/SATAGP1 CP10
CN28 GPP_H13/M2_SKT2/CFG_1 GPP_E2/SATAXPCIE2/SATAGP2 +3VALW
CM28 GPP_H14/M2_SKT2/CFG_2 CN7
GPP_H15/M2_SKT2/CFG_3 GPP_E8/SATALED#/SPI1_CS1#
m
AR3
UFS_RESET#
W HL-U42_BGA1528
USB_OC2# RC490 2 1 10K_0402_5%
8 of 20 USB_OC0# RC491 2 1 10K_0402_5%
USB_OC3# RC492 2 1 10K_0402_5%
o
USB_OC1# RC493 2 1 10K_0402_5%
When PCIE16/SATA2 is used as SATA Port 1 (ODD), then
PCIE15/SATA1B (M.2 SSD) cannot be used as SATA Port 1.
+3VS
C
@
W L_OFF# RC131 1 2 10K_0402_5%
A A

WHL-U(7/12)PCIE,USB,SATA
5 4 3 2 1
5 4 3 2 1
+1.2V
+1.05VALW TO +1.05V_VCCST +VL +1.05VALW
UC1N
+1.05VS_VCCIO
+1.8VALW AK24 3.679A

+1.8VALW TO +1.8VS 3.3A AD36
AH32 VDDQ1
VCCIO1
VCCIO2
AK26
AL24
I(Max) : 0.16 A(+1.05V_VCCST) VDDQ2 VCCIO3
1U_0201_6.3V6M
RON(Max) : 25 mohm AH36 AL25
VDDQ3 VCCIO4
1
AM36 AL26
V drop : 0.004 V
o
+1.05V_VCCST VDDQ4 VCCIO5
CC150
AN32 AL27
AW32 VDDQ5 VCCIO6 AM25
2
UC7 RC451 AY36 VDDQ6 VCCIO7 AM27
1 14 +1.05V_VCCST_R 1 2 0_0402_5% BE32 VDDQ7 VCCIO8 BH24
2 VIN1 VOUT1 13 BH36 VDDQ8 VCCIO9 BH25
VIN1 VOUT1 VDDQ9 VCCIO10
0.1U_0201_10V6K
CC151 @
R32 BH26
v
D 1 VDDQ10 VCCIO11 D
RC450 1 2 0_0402_5% EN_1.0V_VCCSTU 3 12 1 2 Y36 BH27
<34,43,44> SYSON ON1 CT1 CC152 +1.05V_VCCST VDDQ11 VCCIO12 BJ24
4 11 8200P_0402_25V7K VCCIO13 BJ26
VBIAS GND 2 VCCIO14 BP16
RC452 1 2 0_0402_5% EN_1.8VS 5 10 1 2 +VCCPLL_OC +1.05VS_VCCSTG BC28 VCCIO15 BP18 +VCCSA
<34,38,43> SUSP# ON2 CT2 CC153 RSVD1 VCCIO16
o
6 9 1000P_0402_50V7K BP11 BG8 6A
7 VIN2 VOUT2 8 BP2 VCCST1 VCCSA2 BG10
VIN2 VOUT2 VCCST2 VCCSA1 BH9
15 +1.8VS VCCSA3 BJ8
GPAD BG1 VCCSA5 BJ9
0.02A VCCSTG1 VCCSA6
n
AOZ1331 DFN 14P RC453 BG2 BJ10
+1.8VS_R 1 2 0_0402_5% VCCSTG2 VCCSA4 BK8
BL27 VCCSA9 BK25
I(Max) : 0.2 A(+1.8VS) 0.12A VCCPLL_OC1 VCCSA7
0.1U_0201_10V6K
CC154 @
RON(Max) : 25 mohm 1 BM26 BK27
VCCPLL_OC2 VCCSA8 BL8
V drop : 0.005 V BR11 VCCSA13 BL9
Follow 543977_SKL_PDDG_Rev0_91 0.19A
e
BT11 VCCPLL1 VCCSA14 BL10
CC24 10PF ->22us(Spec:<= 65us) 2 VCCPLL2 VCCSA10 BL24
VCCSA11 BL26
VCCSA12 BM24
VCCSA15 BN25
VCCSA16
+VL +1.05VALW +1.05VALW TO +1.05VS_VCCIO BP28
L
VCCIO_SENSE BP29
VSSIO_SENSE
Trace Length Match < 25 mils
I(Max) : 3.675 A(+1.05VS_VCCIO)
VSSSA_SENSE
1U_0201_6.3V6M
RON(Max) : 6.2 mohm BE7

VSSSA_SENSE VCCSA_SENSE VSSSA_SENSE <46>
0.1U_0201_10V6K
1 BG7
V drop : 0.019 V VCCSA_SENSE VCCSA_SENSE <46> C
1
CC30
CC32
C 1uF X1
UC6 0.1uF X1 W HL-U42_BGA1528
+1.05VS_VCCIO
r
@ 1 +1.05V_VCCST
2
2 2 VIN1 14 of 20
VIN2
PSC Side
RC79 +VCCPLL_OC +1.05VS_VCCSTG
7 6 +1.05VS_VCCIO_STG 1 2 PSC Side PSC Side
VIN thermal VOUT
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1
0.1U_0201_10V6K
CC33
1U_0201_6.3V6M
1U_0201_6.3V6M
3 0_0805_5% 1 1 1 1 1
VBIAS
1
@ CC41
@ CC28
CC29
CC35
SUSP# 4 5 @
ON GND 2
CC159
CC34
CC31
2 2 2 2 2
2
EM5201V_DFN8_3X3
F
Close to BP11 & BP2 Close to BR11 & BT11 Close to BM26 Close to BG1 & BG2
+1.05VS_VCCIO change package of 1U from 0201 to 0402

+1.2V change package of 1U from 0201 to 0402
l
BSC Side PSC Side PSC Side BSC Side
a
10P_0402_50V8J
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
4.7U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 1 1 1 1 1 1
1
1
@ CC161
@ CC189
@ CC47
@ CC44
B B
RF@
CC3867
CC39
CC40
CC37
CC38
CC160
CC36
CC163
CC164
CC172
CC173
CC167
CC45
CC46
CC49
CC50
@
2
2
2 2 2 2 2 2 2 2 2 2 2 @
p
@
Close to CPU Underneath CPU Underneath CPU Close to CPU
+1.05VALW TO +1.05VS_VCCSTG CPU C10 Save Power +1.2V TO +VCCPLL_OC
m
+1.2V +VCCPLL_OC
+VL +1.2V
+VL +1.05VALW
I(Max) : 120m A(+VCCPLL_OC)
I(Max) : 20m A(+1.05VS_VCCSTG) RON(Max) : 6.2 mohm RC454 1 2 0_0402_5%
0.1U_0201_10V6K
1U_0201_6.3V6M
RON(Max) : 6.2 mohm
o
1 V drop : 0.019 V
1
+1.05VS_VCCSTG
0.1U_0201_10V6K
1U_0201_6.3V6M
CC178
1 +3VALW
V drop : 0.019 V
1
CC174
CC176
CC177 UC10 @
+VCCPLL_OC
CC175
UC8 @ UC9 @ 0.1U_0201_10V6K @ @ 1
2
1 SOC_C10_GATE# 1 6 1 2 2 2 VIN1
2
2 2 VIN1 <9> SOC_C10_GATE# A VCC @ VIN2 RC456

@ VIN2 RC455 SUSP# 2 5 7 6 +VCCPLL_OC_R 1 2
7 6 +1.05VS_VCCSTG_R 1 2 B NC VIN thermal VOUT
VIN thermal VOUT 1
3 4 S0_C10_GATE# 3 0_0402_5%
C
1 GND Y VBIAS
3 0_0402_5% CC179
VBIAS CC180 @ 74LVC1G08FZ4-7_X2-DFN1410-6 S0_C10_GATE# 4 5 @
ON GND 0.1U_0201_10V6K
S0_C10_GATE# 4 5 2
A ON GND 0.1U_0201_10V6K A
2
TPS22961DNYR_W SON8
TPS22961DNYR_W SON8 RC457 1 @ 2 0_0402_5%

+1.05VS_VCCIO_STG +1.05VS_VCCSTG_R 2017/5/3 2017/6/2 Title
WHL-U(8/12)Power
RC458 1 2 0_0402_5% DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
5 4 3 2 1
5 4 3 2 1
+1.05VALW +1.05VALW
1U_0201_6.3V6M
1
CC66
1U_0201_6.3V6M
1
CC56
2
2
@
o
Close to BV18 Close to BP20
Imax : 4.982A
D
+1.05VALW D
v
+1.05VALW +1.05VALW
+1.05VALW +3VALW
UC1P RTC Bat t er y
BP20
VCCPRIM_1P05_1
1U_0201_6.3V6M
1 1 BW16 CB16
VCCPRIM_1P05_9 VCCPRIM_3P3_3
1
BW18 +3VL_RTC +RTCBATT

VCCPRIM_1P05_10 +3VL_RTC
CC68
CC169 CC171 BW19

VCCPRIM_1P05_11
o
4.7U_0402_6.3V6M 10U_0402_6.3V6M BY16 W=20mils
2
2 2 +1.8VALW CA14 VCCPRIM_1P05_12 BR23

VCCPRIM_1P05_14 VCCRTC RC90 1 2 0_0402_5%
CC15 BY20 @
Imax : 0.702A VCCPRIM_1P8_1 VCCPRIM_1P05_13
1U_0201_6.3V6M
Close to BV12 CD15 BP24 +DCPRTC CC62 1 2 1U_0201_6.3V6M
VCCPRIM_1P8_4 DCPRTC
1
CD16
+3VALW VCCPRIM_1P8_5
CC82
Close to BV2 CP17 Close to BP24
VCCPRIM_1P8_8 BR20
2
CB22 VCCPRIM_1P05_3
Imax : 0.21A VCCPRIM_3P3_4 Close to BR23
CB23 BT12
CC22 VCCPRIM_3P3_5 VCCAPLL_1P05_3
+1.8VALW CC23 VCCPRIM_3P3_6 BP14
CD22 VCCPRIM_3P3_7 VCCA_BCLK_1P05
VCCPRIM_3P3_8 Saf t y s ugges t i on r emove EE s i de , Keep PW
R s i de
CD23 BR14
e
CP29 VCCPRIM_3P3_9 VCCAPLL_1P05_1
VCCPRIM_3P3_10
1U_0201_6.3V6M
1
BU15 BU12
VCCPRIM_CORE1 VCCA_SRC_1P05
CC181
BU22
VCCPRIM_CORE2 +1.05VALW
BV15 CP5
2
BV16 VCCPRIM_CORE3 VCCA_XTAL_1P05

BV18 VCCPRIM_CORE4 BY24
BV19 VCCPRIM_CORE5 VCCDPHY_1P24_2 CA24
BV20 VCCPRIM_CORE6 VCCDPHY_1P24_4 +VCCDPHY_1.24V
L
VCCPRIM_CORE7
1U_0201_6.3V6M
10P_0402_50V8J
CC3868 RF@
BV22 BY23 Close to CP25 1
VCCPRIM_CORE8 VCCDPHY_1P24_1
1
Close to CP17 BW20 CA23 Intenal LDO
VCCPRIM_CORE9 VCCDPHY_1P24_3 VCCDPHY_EC_1P24
CC155
BW22 CP25 CC182 1 2 4.7U_0402_6.3V6M
CA12 VCCPRIM_CORE10 VCCDPHY_EC_1P24
2
CA16 VCCPRIM_CORE11 BT23 +1.05VALW 2
C CA18 VCCPRIM_CORE12 VCCDSW_3P3_2 C
+3VALW CA19 VCCPRIM_CORE13 BR12
CA20 VCCPRIM_CORE14 VCCA_19P2_1P05
r
CB12 VCCPRIM_CORE15
VCCPRIM_CORE16 +1.8VALW
1U_0201_6.3V6M
1 CB14 Close to CP5 Close to BP14

VCCPRIM_CORE17
1
@ Close to BT24 CB15

VCCPRIM_CORE18
CC57
CC79 Internal LDO CC18

0.1U_0201_10V6K CC55 2 1 1U_0201_6.3V6M +DCPDSW BT24 VCCPRIM_1P8_2 CC19
Imax : 0.702A
2
2 VCCDSW_1P05 VCCPRIM_1P8_3 CD18

@ BU14 VCCPRIM_1P8_6 CD19
VCCAPLL_1P05_4 VCCPRIM_1P8_7
o
CP23
BV12 VCCPRIM_1P8_9
BW12 VCCPRIM_MPHY_1P05_1 BW23
Close to CP29 VCCPRIM_MPHY_1P05_3 VCCPRIM_3P3_2
BW14
BY12 VCCPRIM_MPHY_1P05_4
BY14 VCCPRIM_MPHY_1P05_5
VCCPRIM_MPHY_1P05_6 BP23 +VCCDPHY_1.24V
+3VALW BV2 VCCPRIM_3P3_1 +1.8VALW
F
VCCAMPHYPLL_1P05 CB36
GPP_B0/CORE_VID0 PD_INT# <30,34>
BR15 CB35
VCCAPLL_1P05_2 GPP_B1/CORE_VID1 VCCDPHY_EC_1P24 R3248 1 CNVi@ 2 0_0201_5%
+3VALW
1U_0201_6.3V6M
CC12
VCCDUSB_1P05
1
1U_0201_6.3V6M
CC59
1
CC157
BR24 When CNVi is not used in the design:

+3V_1.8V_HDA VCCDSW_3P3_1 VCCDPHY_1P24 pin shall be disconnected from the VCCLDOSRAM_IN_1P24 pin.
2
BT20 The decoupling capacitor shall remain connected to the VCCDPHY_1P24 pin.
l
2
VCCHDA @
@ BV23
BT18 VCCSPI
BT19 VCCPRIM_1P05_4
VCCPRIM_1P05_5 Close to CP23
Close to BR24 BU18
BU19 VCCPRIM_1P05_7
a
VCCPRIM_1P05_8
BT22
+3VALW RF@ +3V_1.8V_HDA BP22 VCCPRIM_1P05_6
B VCCPRIM_1P05_2 B
LC4 BV14
1 2 VCCPRIM_MPHY_1P05_2
BLM15BB221SN1D_2P WHL-U42_BGA1528
p
RF@ 16 of 20
1
CC52
0.1U_0201_10V6K
2
UC1O
close to BP20 K12

VCCOPC1 VCCEOPIO1
AA24
K14 AA26
K15 VCCOPC2 VCCEOPIO2 AB25
VCCOPC3 VCCEOPIO3
m
K17 AC24
K18 VCCOPC4 VCCEOPIO4 AC25
K20 VCCOPC5 VCCEOPIO5 AC26
L25 VCCOPC6 VCCEOPIO6 AD24
M24 VCCOPC7 VCCEOPIO7 AD26
M26 VCCOPC8 VCCEOPIO8
P24 VCCOPC9 V25
VCCOPC10 VCCEOPIO_SENSE
o
P26 T25
R24 VCCOPC11 VSSEOPIO_SENSE
R25 VCCOPC12
R26 VCCOPC13
VCCOPC14
W25
V24 VCC_OPC_1P8_2
VCC_OPC_1P8_1
Y25
C
Y24 VCC_OPC_1P8_4
VCC_OPC_1P8_3
A A
WHL-U42_BGA1528
15 of 20
VCCOPC and VCCEOPIO for CFL U43e only

WHL-U(9/12)Power
5 4 3 2 1
5 4 3 2 1
+VCC_GT +VCC_GT
+VCCCORE +VCCCORE
UC1M
o
UC1L A5 D15
A6 VCCGT8 VCCGT58 D17
AN9 AW24 A8 VCCGT9 VCCGT59 D18
AN10 VCCCORE5 VCCCORE35 AW25 A11 VCCGT10 VCCGT60 D20
AN24 VCCCORE1 VCCCORE36 AW26 A12 VCCGT1 VCCGT61 E4
v
D D
AN26 VCCCORE2 VCCCORE37 AW27 A14 VCCGT2 VCCGT64 F5
AN27 VCCCORE3 VCCCORE38 AY24 A15 VCCGT3 VCCGT69 F6
AP2 VCCCORE4 VCCCORE44 AY26 +VCCCORE A17 VCCGT4 VCCGT70 F7
AP9 VCCCORE6 VCCCORE45 BA5 A18 VCCGT5 VCCGT71 F8
AP24 VCCCORE9 VCCCORE48 BA7 A20 VCCGT6 VCCGT72 F11
AP26 VCCCORE7 VCCCORE49 BA8 AA9 VCCGT7 VCCGT65 F14
o
AR5 VCCCORE8 VCCCORE50 BA25 AB2 VCCGT11 VCCGT66 F17
AR6 VCCCORE13 VCCCORE46 BA27 AB8 VCCGT13 VCCGT67 F20
AR7 VCCCORE14 VCCCORE47 BB2 AB9 VCCGT14 VCCGT68 G11
AR8 VCCCORE15 VCCCORE51 BB26 AB10 VCCGT15 VCCGT73 G12
AR10 VCCCORE16 VCCCORE52 BC5 AC8 VCCGT12 VCCGT74 G14
VCCCORE10 VCCCORE56 VCCGT16 VCCGT75
n
AR25 BC6 AD9 G15
AR27 VCCCORE11 VCCCORE57 BC7 AE8 VCCGT17 VCCGT76 G17
AT9 VCCCORE12 VCCCORE58 BC9 AE9 VCCGT19 VCCGT77 G18
AT24 VCCCORE19 VCCCORE59 BC10 AE10 VCCGT20 VCCGT78 G20
AT26 VCCCORE17 VCCCORE53 BC26 AF2 VCCGT18 VCCGT79 H5
AU5 VCCCORE18 VCCCORE54 BC27 AF8 VCCGT22 VCCGT87 H6
e
AU6 VCCCORE24 VCCCORE55 BD5 AF10 VCCGT23 VCCGT88 H7
AU7 VCCCORE25 VCCCORE63 BD8 AG8 VCCGT21 VCCGT89 H8
AU8 VCCCORE26 VCCCORE64 BD10 AG9 VCCGT24 VCCGT90 H11
AU9 VCCCORE27 VCCCORE60 BD25 AH9 VCCGT25 VCCGT80 H12
AU24 VCCCORE28 VCCCORE61 BD27 AJ8 VCCGT26 VCCGT81 H14
AU25 VCCCORE20 VCCCORE62 BE9 AJ10 VCCGT28 VCCGT82 H15
AU26 VCCCORE21 VCCCORE69 BE24 AK2 VCCGT27 VCCGT83 H17
L
AU27 VCCCORE22 VCCCORE65 BE25 AK9 VCCGT29 VCCGT84 H18
AV2 VCCCORE23 VCCCORE66 BE26 AL8 VCCGT30 VCCGT85 H20
AV5 VCCCORE30 VCCCORE67 BE27 AL9 VCCGT32 VCCGT86 J7
AV7 VCCCORE32 VCCCORE68 BF2 AL10 VCCGT33 VCCGT95 J8
C AV10 VCCCORE33 VCCCORE70 BF9 AM8 VCCGT31 VCCGT96 J11 C
AV27 VCCCORE29 VCCCORE73 BF24 B3 VCCGT34 VCCGT91 J14
VCCCORE31 VCCCORE71 VCCGT39 VCCGT92
r
AW5 BF26 B4 J17
AW6 VCCCORE39 VCCCORE72 BG27 B6 VCCGT40 VCCGT93 J20
AW7 VCCCORE40 VCCCORE74 B8 VCCGT41 VCCGT94 K2
AW8 VCCCORE41 AN6 B11 VCCGT42 VCCGT98 K11
VCCCORE42 VCC_SENSE VCCCORE_SENSE <46> VCCGT35 VCCGT97
AW9 AN5 B14 L7
VCCCORE43 VSS_SENSE VSSCORE_SENSE <46>Trace Length Match < 25 mils VCCGT36 VCCGT100
AW10 B17 L8
VCCCORE34 SOC_SVID_ALERT# VCCGT37 VCCGT101
o
AA3 B20 L10
VIDALERT# C2 VCCGT38 VCCGT99 M9
BB9 AA1 VR_SVID_CLK C3 VCCGT49 VCCGT102 N7
RSVD3 VIDSCK VR_SVID_CLK <46> VCCGT51 VCCGT104
BC24 C6 N8
AY9 RSVD4 AA2 VR_SVID_DATA C7 VCCGT52 VCCGT105 N9
BB24 RSVD1 VIDSOUT C8 VCCGT53 VCCGT106 N10
RSVD2 Y3 +1.05VS_VCCSTG C11 VCCGT54 VCCGT103 P2
F
RSVD5 C12 VCCGT43 VCCGT107 P8
BG3 C14 VCCGT44 VCCGT108 R9
VCCSTG1 C15 VCCGT45 VCCGT109 T8
W HL-U42_BGA1528 C17 VCCGT46 VCCGT111 T9
C18 VCCGT47 VCCGT112 T10
12 of 20 C20 VCCGT48 VCCGT110 U8
l
D4 VCCGT50 VCCGT114 U10
D7 VCCGT62 VCCGT113 V2
D11 VCCGT63 VCCGT115 V9
SVID ALERT D12 VCCGT55
VCCGT56
VCCGT116
VCCGT117
W8
+1.05V_VCCST D14 W9
Place the PU
a
Y10 VCCGT57 VCCGT118 Y8
resistors close to CPU VCCGT119 VCCGT120
E3 VCCGT_SENSE
VCCGT_SENSE VCCGT_SENSE <46>
1
B D2 VSSGT_SENSE B
VSSGT_SENSE VSSGT_SENSE <46>
RC94
56_0402_5% W HL-U42_BGA1528 Trace Length Match < 25 mils
p
13 of 20
2
SOC_SVID_ALERT# 1 2 (To VR)

VR_ALERT# <46>
RC95 220_0402_5%
SVID DATA
o m +1.05V_VCCST
Place the PU
resistors close to CPU
1
RC96
100_0402_1%
2
C
VR_SVID_DATA
VR_SVID_DATA <46> (To VR)
A A

WHL-U(10/12)Power,SVID
5 4 3 2 1
5 4 3 2 1
CR34
BT5
UC1R
VSS_1 VSS_73
BL7
AE25
BT35
D6
AL32
UC1S
VSS_145
VSS_146
VSS_217
VSS_218
BY25
J18
AU32
N6
B37
UC1T
VSS_290 VSS_362
CF23
V4
v o D
o
BY5 VSS_2 VSS_74 BM33 BT36 VSS_147 VSS_219 BY28 CB3 VSS_291 VSS_363 BE30
CP35 VSS_3 VSS_75 CM5 D8 VSS_148 VSS_220 J21 P10 VSS_292 VSS_364 CF28
CM37 VSS_4 VSS_76 AE27 AL7 VSS_149 VSS_221 AV25 B5 VSS_293 VSS_365 W10
CK37 VSS_5 VSS_77 BM35 D9 VSS_150 VSS_222 BY33 CB33 VSS_294 VSS_366 BE31
AW1 VSS_6 VSS_78 CM9 AM10 VSS_151 VSS_223 J24 P3 VSS_295 VSS_367 CF3
VSS_7 VSS_79 VSS_152 VSS_224 VSS_296 VSS_368
n
CM1 AE30 BU11 AV28 B7 W27
BD6 VSS_8 VSS_80 BM36 E23 VSS_153 VSS_225 BY35 CB4 VSS_297 VSS_369 CF4
AY4 VSS_9 VSS_81 CN13 AM28 VSS_154 VSS_226 J33 P33 VSS_298 VSS_370 W30
B34 VSS_10 VSS_82 AE7 E27 VSS_155 VSS_227 AV3 B9 VSS_299 VSS_371 BF3
E35 VSS_11 VSS_83 BM9 AM33 VSS_156 VSS_228 BY36 CB7 VSS_300 VSS_372 CG33
A4 VSS_12 VSS_84 CN17 BU23 VSS_157 VSS_229 J36 P36 VSS_301 VSS_373 W7
e
AE24 VSS_13 VSS_85 AF27 E29 VSS_158 VSS_230 AV33 BA10 VSS_302 VSS_374 BF33
AE26 VSS_14 VSS_86 BN30 AM35 VSS_159 VSS_231 J6 CC11 VSS_303 VSS_375 CG7
AF25 VSS_15 VSS_87 CN21 BU24 VSS_160 VSS_232 AV36 P4 VSS_304 VSS_376 BF36
AG24 VSS_16 VSS_88 AF3 E31 VSS_161 VSS_233 C1 BA28 VSS_305 VSS_377 Y26
AG26 VSS_17 VSS_89 BN7 BU25 VSS_162 VSS_234 K21 P7 VSS_306 VSS_378 BF4
AH24 VSS_18 VSS_90 CN25 E33 VSS_163 VSS_235 AV4 BA3 VSS_307 VSS_379 CH31
AH25 VSS_19 VSS_91 AF30 AN25 VSS_164 VSS_236 C21 CC20 VSS_308 VSS_380 Y27
L
B2 VSS_20 VSS_92 CN29 BU7 VSS_165 VSS_237 K22 R27 VSS_309 VSS_381 BG25
B36 VSS_21 VSS_93 AF33 E9 VSS_166 VSS_238 AV6 BB3 VSS_310 VSS_382 Y30
C36 VSS_22 VSS_94 BP15 AN28 VSS_167 VSS_239 C25 CC25 VSS_311 VSS_383 BG28
C37 VSS_23 VSS_95 AF36 BV11 VSS_168 VSS_240 K24 R28 VSS_312 VSS_384 CJ11
C CN1 VSS_24 VSS_96 AF4 F12 VSS_169 VSS_241 AV8 BB33 VSS_313 VSS_385 Y33 C
CN2 VSS_25 VSS_97 CN5 AN29 VSS_170 VSS_242 C29 CC28 VSS_314 VSS_386 CJ14
r
CN37 AF7 F15 K25 R29 Y35
CP2 VSS_27 VSS_99 BP25 AN30 VSS_172 VSS_244 AW28 BB36 VSS_316 VSS_388 BH28
D1 VSS_28 VSS_100 CN9 F18 VSS_173 VSS_245 C33 CC31 VSS_317 VSS_389 CJ19
A32 VSS_29 VSS_101 AG10 AN31 VSS_174 VSS_246 K27 R30 VSS_318 VSS_390 Y7
F33 VSS_30 VSS_102 BP3 BV3 VSS_175 VSS_247 AW29 BB4 VSS_319 VSS_391 BH29
A3 VSS_31 VSS_103 CP1 F2 VSS_176 VSS_248 C4 CC7 VSS_320 VSS_392 CJ23
o
BJ7 BP32 AN7 K28 R31 BH32
CJ36 VSS_33 VSS_105 CP11 BV31 VSS_178 VSS_250 AW3 BC25 VSS_322 VSS_394 CJ28
A36 VSS_34 VSS_106 AH27 F21 VSS_179 VSS_251 C9 CD11 VSS_323 VSS_395 BH33
BK10 VSS_35 VSS_107 BP33 AN8 VSS_180 VSS_252 K29 T27 VSS_324 VSS_396 CJ33
CJ4 VSS_36 VSS_108 CP13 BV33 VSS_181 VSS_253 AW30 CD12 VSS_325 VSS_397 BH35
AB27 VSS_37 VSS_109 AH28 F24 VSS_182 VSS_254 CA11 T30 VSS_326 VSS_398 CJ35
BK2 VSS_38 VSS_110 BP4 BV4 VSS_183 VSS_255 K3 BC29 VSS_327 VSS_399 BP19
F
CK1 VSS_39 VSS_111 CP15 F3 VSS_184 VSS_256 AW31 CD14 VSS_328 VSS_400 BR16
AB3 VSS_40 VSS_112 AH29 AP3 VSS_185 VSS_257 CA15 T33 VSS_329 VSS_401 BY18
BK28 VSS_41 VSS_113 BP7 BW11 VSS_186 VSS_258 K30 T35 VSS_330 VSS_402 BY19
AB30 VSS_42 VSS_114 CP19 F4 VSS_187 VSS_259 AY33 BC32 VSS_331 VSS_403 CC16
BK3 VSS_43 VSS_115 AH30 AP33 VSS_188 VSS_260 CA22 CD24 VSS_332 VSS_404 BU16
CK4 VSS_44 VSS_116 CP21 BW15 VSS_189 VSS_261 K31 T36 VSS_333 VSS_405 CC14
l
AB33 VSS_45 VSS_117 AH31 G21 VSS_190 VSS_262 AY35 CD25 VSS_334 VSS_406 BR22
BK33 VSS_46 VSS_118 BR19 AP36 VSS_191 VSS_263 K32 T7 VSS_335 VSS_407 BU20
CK7 VSS_47 VSS_119 CP27 G27 VSS_192 VSS_264 B12 BC8 VSS_336 VSS_408 CD20
AB36 VSS_48 VSS_120 AH33 AP4 VSS_193 VSS_265 K4 CE33 VSS_337 VSS_409 BT14
BK4 VSS_49 VSS_121 BR25 G33 VSS_194 VSS_266 B15 U26 VSS_338 VSS_410 BP12
a
CL2 VSS_50 VSS_122 AH35 AR28 VSS_195 VSS_267 CA25 BD28 VSS_339 VSS_411 CB24
AB4 VSS_51 VSS_123 CP37 G35 VSS_196 VSS_268 K9 CE35 VSS_340 VSS_412 CC24
BK7 VSS_52 VSS_124 AJ25 G36 VSS_197 VSS_269 B18 U7 VSS_341 VSS_413 J5
B CM13 VSS_53 VSS_125 BT15 AT33 VSS_198 VSS_270 CB11 BD33 VSS_342 VSS_414 U24 B
AB7 VSS_54 VSS_126 AJ28 BW24 VSS_199 VSS_271 L27 CE36 VSS_343 VSS_415 BD7
BL25 VSS_55 VSS_127 BT16 G9 VSS_200 VSS_272 B21 V26 VSS_344 VSS_416 AR4
p
CM17 VSS_56 VSS_128 CP9 AT35 VSS_201 VSS_273 L33 BD35 VSS_345 VSS_417 AU4
AC10 VSS_57 VSS_129 AJ7 H21 VSS_202 VSS_274 B23 CE7 VSS_346 VSS_418 AW4
BL28 VSS_58 VSS_130 CR2 AT36 VSS_203 VSS_275 L35 V27 VSS_347 VSS_419 BA6
CM21 VSS_59 VSS_131 AK3 BW7 VSS_204 VSS_276 B25 BD36 VSS_348 VSS_420 BC4
AC27 VSS_60 VSS_132 CR36 H27 VSS_205 VSS_277 CB18 CF11 VSS_349 VSS_421 BE4
BL29 VSS_61 VSS_133 AK33 AT4 VSS_206 VSS_278 L36 V3 VSS_350 VSS_422 BE8
CM25 VSS_62 VSS_134 D21 BY11 VSS_207 VSS_279 B27 BE10 VSS_351 VSS_423 BA4
AC30 VSS_63 VSS_135 AK36 AU10 VSS_208 VSS_280 CB19 CF14 VSS_352 VSS_424 BD4
BL30 VSS_64 VSS_136 BT25 BY15 VSS_209 VSS_281 L6 V30 VSS_353 VSS_425 BG4
m
CM29 VSS_65 VSS_137 D25 H9 VSS_210 VSS_282 B29 BE28 VSS_354 VSS_426 CJ2
BL31 VSS_66 VSS_138 AK4 AU28 VSS_211 VSS_283 CB2 CF19 VSS_355 VSS_427 CJ3
CM31 VSS_67 VSS_139 BT28 BY22 VSS_212 VSS_284 N25 V33 VSS_356 VSS_428 AM5
AD33 VSS_68 VSS_140 AL28 J12 VSS_213 VSS_285 B31 BE29 VSS_357 VSS_429 CM4
BL32 VSS_69 VSS_141 BT33 AU29 VSS_214 VSS_286 CB20 CF2 VSS_358 VSS_430 AC5
CM33 VSS_70 VSS_142 D5 J15 VSS_215 VSS_287 N27 V36 VSS_359 VSS_431 AG5
o
AD35 VSS_71 VSS_143 AL29 VSS_216 VSS_288 CB25 BE3 VSS_360 VSS_432 CR6
VSS_72 VSS_144 VSS_289 VSS_361 VSS_433
W HL-U42_BGA1528 W HL-U42_BGA1528 W HL-U42_BGA1528
17 of 20 18 of 20 19 of 20
5
C 4
Compal Secret Data
3 2
Title
Custom
Date:
WHL-U(11/12)GND
LA-G651P
1
16 of 52
Rev
0.2
A
5 4 3 2 1
D
+1.05VS_VCCIO
RC459 1 @ 2 10K_0402_5% CFG0
CFG0 T4
UC1Q
F37
v o D
o
1 @ 2 CFG3 CFG_0 RSVD_TP5 F34
RC460 1K_0402_5% R4 RSVD_TP4
T3 CFG_1 CP36
CFG3 R3 CFG_2 IST_TRIG CN36
CFG4 J4 CFG_3 RSVD_TP3
CFG_4
n
M4 BJ36
J3 CFG_5 RSVD15 BJ34
M3 CFG_6 RSVD14
R2 CFG_7 BK34
N2 CFG_8 TP_1 BR18
R1 CFG_9 TP_3
e
N1 CFG_10
J2 CFG_11
L2 CFG_12 BT9
J1 CFG_13 RSVD21 BT8
L1 CFG_14 RSVD20
CFG_15 BP8
L3 RSVD18 BP9
L
N3 CFG_16 RSVD19
L4 CFG_18 CR4
N4 CFG_17 RSVD29
CFG_19 CP3
C RSVD26 CR3 C
CFG_RCOMP AB5 RSVD27
CFG_RCOMP
r
W4
ITP_PMODE
CG2
CG1 RSVD25
RSVD24
o
AT3
RSVD12 AU3
RSVD13
H4
H3 RSVD34
RSVD33 AN1
BV24 RSVD8 AN2
F
BV25 RSVD22 RSVD9
RSVD23 AN4
RSVD11 AN3
RSVD10
AL2
G3 RSVD3 AL1
l
G4 VSS_436 RSVD2
VSS_437
AL4
RSVD5 AL3
BK36 RSVD4
a
BK35 RSVD17 BP34
RSVD16 TP1 BP36 SOC_TP2 1 @ 2
W3 TP_2 BP35 RC462 0_0402_5%
B AM4 RSVD35 TP_4 B
RSVD7 C34
AM3 VSS_435
p
RSVD6 A34 Need connect to GND for WHL/CNL
RSVD_TP1 B35
RSVD_TP2
CR35 RSVD28
A35 RSVD28 TP@ T2407 Follow Intel suggetion reserve TP
D34 RSVD1
RSVD30 AH26
1 2 CFG_RCOMP G2 ZVM# AJ27
RC100 49.9_0402_1% G1 RSVD32 MSM#
m
RSVD31 E1
1 2 CFG4 SKTOCC#
RC101 1K_0402_5%
W HL-U42_BGA1528
20 of 20
o
DFX Privacy Strap
1 : Disabled;
Set DFX disable bit in debug interface MSR
CFG3 UC1.G3
C
0 : Enabled; UC1.G4 NC for WHL/CNL
A
Set DFX enable bit in debug interface MSR UC1.C34 Connect to GND for CFL-U43e A
Display Port Presence Strap
1 : Disabled; Compal Secret Data

No Physical Display Port at t ac hed t o E mbedded Dis pl ay port
2017/5/3 2017/6/2 Title
CFG4 Issued Date Deciphered Date
0 : Enabled; THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WHL-U(12/12)CFG,RSVD
An external Display Port device is connected to the Embedded Display Port DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
5 4 3 2 1
D
Rev
0.2
1U_0201_6.3V6M
CD77
52
1 2
1U_0201_6.3V6M
CD32
of
@
1 2 1U_0201_6.3V6M
o

@
10UF * 3 / 1UF * 8
1U_0201_6.3V6M CD88 1 2
18
CD31
@
1 2
LPDDR3 VREF
1U_0201_6.3V6M
Sheet
1U_0201_6.3V6M
CD42 CD87 1 2
1
1 2
v
(10UF * 5 / 1UF * 8)
LA-G651P
1U_0201_6.3V6M 1U_0201_6.3V6M
CD41
1 2 CD86 1 2
Friday, May 18, 2018
1U_0201_6.3V6M
CD40 1U_0201_6.3V6M
@
<LPDDR3_B_CA>
<LPDDR3_A_CA>
1 2
Document Number
o
CD85 1 2
1U_0201_6.3V6M
VDDCA DECAPS
CD39
@
1 2 1U_0201_6.3V6M
1U_0201_6.3V6M CD84 1 2
CD38
1 2 10U_0402_6.3V6M
1U_0201_6.3V6M
n
1
Date:
Title
Size
CD82
@
10U_0402_6.3V6M CD63 1 2
+VREFCA
VDD1 DECAPS
10U_0402_6.3V6M
CD37 1U_0201_6.3V6M
1
10U_0402_6.3V6M CD83
8.2K_0402_1%
8.2K_0402_1%
CD62 1 2
1
2
e
CD36 10U_0402_6.3V6M
10U_0402_6.3V6M 1U_0201_6.3V6M
1
2
RD73
RD78
Update Cap Q'ty to follow Intel 561280_KBL UY PDG Rev2_0
CD81
@
1
+1.2V
2019/2/5
CD61 1 2
+1.2V
CD35
1 2 1 2 10U_0402_6.3V6M
+1.2V
2
2
1
2
L
CD34
5.11_0402_1%
+1.8V_MEM
10U_0402_6.3V6M
2
CD33
RD75
RF@ CD93 RF@

Close to RAM
Close to RAM
10P_0402_50V8J 10P_0402_50V8J
1
Deciphered Date
1
CD94
Compal Secret Data

1U_0201_6.3V6M
1
1 2 CD60 1U_0201_6.3V6M
0.022U_0402_25V7K
24.9_0402_1%
1 2 CD80
RD77
CD10
1 2
330U_D3_2.5VY_R6M
r
1U_0201_6.3V6M 1U_0201_6.3V6M
CD30 CD59 1U_0201_6.3V6M
@
1 2 1 2 CD79
1UF * 12 / 10UF * 5
1 2
+VREF_CA_C
1U_0201_6.3V6M
o
CD29 1U_0201_6.3V6M
+ CD12
1 2 CD58 1U_0201_6.3V6M
1 2 CD78
VTT DECAPS (22UF * 2 / 1UF * 8)
1U_0201_6.3V6M 1 2
1
CD28
@
@
+1.2V
2018/2/5
1 2 1U_0201_6.3V6M
CD57
<CPU>
1U_0201_6.3V6M 1 2
F
CD27
1 2
1U_0201_6.3V6M 10U_0402_6.3V6M
3
3
1U_0201_6.3V6M CD56
@
2
CD26 1 2
@
1 2 CD68
1U_0201_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M
VDD2 DECAPS
CD25 CD55
@
2
1 2 1 2
CD67
Issued Date
1U_0201_6.3V6M
CD24 1U_0201_6.3V6M 10U_0402_6.3V6M
@
1 2
l CD54
2
1 2
1U_0201_6.3V6M CD66
CD23
@
1 2 1U_0201_6.3V6M 10U_0402_6.3V6M
a
<CPU>
<CPU>
CD53
2
1 2
CD65
22U_0603_6.3V6M
1U_0201_6.3V6M 10U_0402_6.3V6M
@
1
CD22 2 CD52
2
1 2
+V_DDR_REFA_C
+V_DDR_REFB_C
+1.2V
+1.2V
p
22U_0603_6.3V6M CD64
+0.6VS
2
CD21
Close to RAM
0.022U_0402_25V7K
CC3869 RF@
0.022U_0402_25V7K
10P_0402_50V8J 1U_0201_6.3V6M
CD51
m
24.9_0402_1%
24.9_0402_1%
2
1 2
4
4
(10UF * 5 / 1UF *12 / 0.1UF *8)
CD11
RD76
1U_0201_6.3V6M 1U_0201_6.3V6M 0.1U_0201_10V6K

RD82
CD9
CD20 CD50
2
1 2 1 2
1
1 2 1 2 CD76
1U_0201_6.3V6M 1U_0201_6.3V6M 0.1U_0201_10V6K
10_0402_1%
10_0402_1%
2
CD19 CD49
2
1 2 1 2
1 RD72
RD80
CD75
o
1U_0201_6.3V6M 1U_0201_6.3V6M 0.1U_0201_10V6K
1
CD18 CD48
2
1 2 1 2
CD74
1 2 1 2 1 2 1 2
+1.2V
+1.2V
RD71
RD74
RD79
RD81
8.2K_0402_1%
8.2K_0402_1%
8.2K_0402_1%
8.2K_0402_1%
10U_0402_6.3V6M 1U_0201_6.3V6M 0.1U_0201_10V6K 1U_0201_6.3V6M
CD47 CD92
@
1
2
1 2 1 2
C
CD17 CD73
@
10U_0402_6.3V6M 1U_0201_6.3V6M 0.1U_0201_10V6K 1U_0201_6.3V6M
+VREFDQ_B
CD46 CD91
@
1
2
1 2 1 2
+VREFDQ_A
CD16 CD72
VDDQ DECAPS
10U_0402_6.3V6M 1U_0201_6.3V6M 0.1U_0201_10V6K 1U_0201_6.3V6M
CD45 CD90
@
1
2
1 2 1 2
CD15 CD71
@
<LPDDR3_B_DQ>
5
5
10U_0402_6.3V6M 1U_0201_6.3V6M 0.1U_0201_10V6K 1U_0201_6.3V6M
<LPDDR3_A_DQ>
CD44 CD89
@
1
2
1 2 1 2
+1.2V
CD14 CD70
10U_0402_6.3V6M 1U_0201_6.3V6M 0.1U_0201_10V6K
CD43
2
1 2
CD13 CD69
@
+1.2V
D
A
5 4 3 2 1
+1.8V_MEM +0.6VS
UD1 @ +1.8V_MEM UD2 @
o
A3 P9 A3 P9 DDR_A_CAA0 RD1 2 CHA@ 1 68_0201_1%
VDD1 DQ0 DDR_A_D46 <7> VDD1 DQ0 DDR_A_D1 <7> DDR_A_CAA1
A4 N9 DDR_A_D43 <7> A4 N9 DDR_A_D7 <7> RD2 2 CHA@ 1 68_0201_1%
A5 VDD1 DQ1 N10 A5 VDD1 DQ1 N10 DDR_A_CAA2 RD3 2 CHA@ 1 68_0201_1%
A6 N11 DDR_A_D40 <7> A6 N11 DDR_A_D5 <7> RD4 2 CHA@ 1 68_0201_1%
A10 VDD1 DQ3 M8 A10 VDD1 DQ3 M8 DDR_A_CAA4 2 1
VDD1 DQ4 DDR_A_D47 <7> CHA_Group{5} VDD1 DQ4 DDR_A_D3 <7> CHA_Group{0} DDR_A_CAA5
RD5 CHA@ 68_0201_1%
U3 M9 DDR_A_D42 <7> U3 M9 DDR_A_D6 <7> RD6 2 CHA@ 1 68_0201_1%
U4 VDD1 DQ5 M10 U4 VDD1 DQ5 M10 DDR_A_CAA6 RD7 2 CHA@ 1 68_0201_1%
D VDD1 DQ6 DDR_A_D45 <7> VDD1 DQ6 DDR_A_D4 <7> DDR_A_CAA7 D
v
U5 M11 DDR_A_D44 <7> U5 M11 DDR_A_D0 <7> RD8 2 CHA@ 1 68_0201_1%
U6 VDD1 DQ7 F11 U6 VDD1 DQ7 F11 DDR_A_CAA8 RD9 2 CHA@ 1 68_0201_1%
+1.2V U10 F10 DDR_A_D38 <7> +1.2V U10 F10 DDR_A_D29 <7> RD10 2 CHA@ 1 68_0201_1%
VDD1 DQ9 F9 VDD1 DQ9 F9 DDR_A_CAB0 RD11 2 CHA@ 1 68_0201_1%
DQ10 DDR_A_D37 <7> DQ10 DDR_A_D31 <7> DDR_A_CAB1
F8 DDR_A_D36 <7> F8 DDR_A_D30 <7> RD12 2 CHA@ 1 68_0201_1%
A8 DQ11 E11 A8 DQ11 E11 DDR_A_CAB2 2 1
VDD2 DQ12 DDR_A_D35 <7> CHA_Group{4} VDD2 DQ12 DDR_A_D25 <7> CHA_Group{3} DDR_A_CAB3
RD13 CHA@ 68_0201_1%
A9 E10 DDR_A_D39 <7> A9 E10 DDR_A_D28 <7> RD14 2 CHA@ 1 68_0201_1%
VDD2 DQ13 VDD2 DQ13 DDR_A_CAB4
o
D4 E9 DDR_A_D33 <7> D4 E9 DDR_A_D26 <7> RD15 2 CHA@ 1 68_0201_1%
D5 VDD2 DQ14 D9 D5 VDD2 DQ14 D9 DDR_A_CAB5 RD16 2 CHA@ 1 68_0201_1%
VDD2 DQ15 DDR_A_D32 <7> VDD2 DQ15 DDR_A_D27 <7> DDR_A_CAB6
D6 T8 DDR_A_D53 <7> D6 T8 DDR_A_D13 <7> RD17 2 CHA@ 1 68_0201_1%
G5 VDD2 DQ16 T9 G5 VDD2 DQ16 T9 DDR_A_CAB7 RD18 2 CHA@ 1 68_0201_1%
VDD2 DQ17 DDR_A_D49 <7> VDD2 DQ17 DDR_A_D9 <7> DDR_A_CAB8
H5 T10 DDR_A_D55 <7> H5 T10 DDR_A_D12 <7> RD19 2 CHA@ 1 68_0201_1%
H6 VDD2 DQ18 T11 H6 VDD2 DQ18 T11 DDR_A_CAB9 RD20 2 CHA@ 1 68_0201_1%
VDD2 DQ19 DDR_A_D54 <7> VDD2 DQ19 DDR_A_D15 <7>
H12 R8 DDR_A_D52 <7> CHA_Group{6} H12 R8 DDR_A_D8 <7> CHA_Group{1}
J5 VDD2 DQ20 R9 J5 VDD2 DQ20 R9
n
J6 R10 DDR_A_D51 <7> J6 R10 DDR_A_D11 <7>
K5 VDD2 DQ22 R11 K5 VDD2 DQ22 R11
K6 C11 DDR_A_D60 <7> K6 C11 DDR_A_D16 <7>
K12 VDD2 DQ24 C10 K12 VDD2 DQ24 C10
L5 C9 DDR_A_D62 <7> L5 C9 DDR_A_D20 <7>
P4 VDD2 DQ26 C8 P4 VDD2 DQ26 C8
DDR_A_D59 <7> DDR_A_D17 <7>
e
P5 VDD2 DQ27 B11 P5 VDD2 DQ27 B11
VDD2 DQ28 DDR_A_D57 <7> CHA_Group{7} VDD2 DQ28 DDR_A_D19 <7> CHA_Group{2}
P6 B10 DDR_A_D56 <7> P6 B10 DDR_A_D23 <7>
U8 VDD2 DQ29 B9 U8 VDD2 DQ29 B9 +0.6VS
U9 B8 DDR_A_D58 <7> U9 B8 DDR_A_D22 <7>
VDD2 DQ31 VDD2 DQ31
+1.2V +1.2V
A11 R2 DDR_A_CAB0 A11 R2 DDR_A_CAA0
VDDQ CA0 DDR_A_CAB1 DDR_A_CAB0 <7> VDDQ CA0 DDR_A_CAA1 DDR_A_CAA0 <7> DDR_A_CS#0
C12 P2 C12 P2 RD21 2 CHA@ 1 80.6_0201_1%
VDDQ CA1 DDR_A_CAB2 DDR_A_CAB1 <7> VDDQ CA1 DDR_A_CAA2 DDR_A_CAA1 <7> DDR_A_CS#1
E8 N2 E8 N2 RD22 2 CHA@ 1 80.6_0201_1%
L
VDDQ CA2 DDR_A_CAB3 DDR_A_CAB2 <7> VDDQ CA2 DDR_A_CAA3 DDR_A_CAA2 <7> DDR_A_ODT0
E12 N3 E12 N3 RD23 2 CHA@ 1 80.6_0201_1%
VDDQ CA3 DDR_A_CAB4 DDR_A_CAB3 <7> VDDQ CA3 DDR_A_CAA4 DDR_A_CAA3 <7> DDR_A_CKE0
G12 M3 G12 M3 RD24 2 CHA@ 1 80.6_0201_1%
H8 F3 H8 F3 RD25 2 CHA@ 1 80.6_0201_1%
H9 E3 H9 E3 RD26 2 CHA@ 1 80.6_0201_1%
H11 E2 H11 E2 RD27 2 CHA@ 1 80.6_0201_1%
C VDDQ CA7 DDR_A_CAB8 DDR_A_CAB7 <7> VDDQ CA7 DDR_A_CAA8 DDR_A_CAA7 <7> C
J9 D2 J9 D2
VDDQ CA8 DDR_A_CAB9 DDR_A_CAB8 <7> VDDQ CA8 DDR_A_CAA9 DDR_A_CAA8 <7>
J10 C2 J10 C2
VDDQ CA9 DDR_A_CAB9 <7> VDDQ CA9 DDR_A_CAA9 <7>
K8 K8
r
K11 VDDQ K11 VDDQ
L12 VDDQ L10 L12 VDDQ L10
VDDQ DQS0 DDR_A_DQS5 <7> VDDQ DQS0 DDR_A_DQS0 <7>
N8 G10 DDR_A_DQS4 <7> N8 G10
VDDQ DQS1 VDDQ DQS1 DDR_A_DQS3 <7>
N12 P10 DDR_A_DQS6 <7> N12 P10
R12 D10 DDR_A_DQS7 <7> R12 D10
U11 U11
VDDQ VDDQ
o
+1.2V L11 +1.2V L11
DQS0# DDR_A_DQS#5 <7> DQS0# DDR_A_DQS#0 <7>
F2 G11 F2 G11
VDDCA DQS1# DDR_A_DQS#4 <7> VDDCA DQS1# DDR_A_DQS#3 <7> +0.6VS
G2 P11 G2 P11
VDDCA DQS2# DDR_A_DQS#6 <7> VDDCA DQS2# DDR_A_DQS#1 <7>
H3 D11 H3 D11
VDDCA DQS3# DDR_A_DQS#7 <7> VDDCA DQS3# DDR_A_DQS#2 <7>
L2 L2 RD28 CHA@
M2 VDDCA M2 VDDCA 37.4_0201_1%
VDDCA L8 VDDCA L8 DDR_A_CLK#0 2 1
DM0 G8 DM0 G8
F
A1 DM1 P8 A1 DM1 P8
A2 NC DM2 D8 A2 NC DM2 D8 RD33 CHA@
A12 NC DM3 A12 NC DM3 37.4_0201_1%
A13 NC A13 NC DDR_A_CLK0 2 1
B1 NC B3 RD29 1 CHA@ 2 243_0402_1% B1 NC B3 RD30 1 CHA@ 2 243_0402_1% +0.6VS
B13 NC ZQ0 B4 RD31 1 CHA@ 2 243_0402_1% B13 NC ZQ0 B4 RD32 1 CHA@ 2 243_0402_1%
C4 NC ZQ1 C4 NC ZQ1 RD34 CHA@
K9 NC K9 NC 37.4_0201_1%
l
R3 NC K3 DDR_A_CKE2 R3 NC K3 DDR_A_CKE0 DDR_A_CLK#1 2 1
NC CKE0 DDR_A_CKE3 DDR_A_CKE2 <7> NC CKE0 DDR_A_CKE1 DDR_A_CKE0 <7>
T1 K4 T1 K4
NC CKE1 DDR_A_CKE3 <7> NC CKE1 DDR_A_CKE1 <7>
T13 T13
U1 NC U1 NC RD35 CHA@
U2 NC L3 DDR_A_CS#0 U2 NC L3 DDR_A_CS#0 37.4_0201_1%
NC CS0# DDR_A_CS#1 NC CS0# DDR_A_CS#1 DDR_A_CS#0 <7> DDR_A_CLK1
U12 L4 U12 L4 2 1
a
NC CS1# NC CS1# DDR_A_CS#1 <7>
U13 U13
NC NC
J3 DDR_A_CLK1 J3 DDR_A_CLK0
CK DDR_A_CLK#1 DDR_A_CLK1 <7> CK DDR_A_CLK#0 DDR_A_CLK0 <7>
B P3 J2 P3 J2 B
VSSCA CK# DDR_A_CLK#1 <7> VSSCA CK# DDR_A_CLK#0 <7>
M4 M4
J4 VSSCA J4 VSSCA
G4 VSSCA J8 DDR_A_ODT0 G4 VSSCA J8 DDR_A_ODT0
VSSCA ODT VSSCA ODT DDR_A_ODT0 <7>
p
G3 G3
F4 VSSCA F4 VSSCA
D3 VSSCA J11 D3 VSSCA J11
VSSCA Vref_DQ +VREFDQ_A VSSCA Vref_DQ +VREFDQ_A
C3 H4 C3 H4 +VREFCA
VSSCA Vref_CA +VREFCA VSSCA Vref_CA
T12 B2 T12 B2
T6 VSSQ VSS B5 T6 VSSQ VSS B5
R6 VSSQ VSS C5 R6 VSSQ VSS C5
VSSQ VSS VSSQ VSS
.047U_0402_16V7K
.047U_0402_16V7K
P12 E4 P12 E4
N6 VSSQ VSS E5 N6 VSSQ VSS E5
VSSQ VSS 1 VSSQ VSS 1
m
M12 F5 M12 F5
VSSQ VSS VSSQ VSS
CD1
CD2
M6 H2 M6 H2
L9 VSSQ VSS J12 L9 VSSQ VSS J12
K10 VSSQ VSS K2 2 K10 VSSQ VSS K2 2
H10 VSSQ VSS L6 +VREFCA H10 VSSQ VSS L6 +VREFCA
G9 VSSQ VSS M5 G9 VSSQ VSS M5
G6 VSSQ VSS N4 +VREFDQ_A G6 VSSQ VSS N4 +VREFDQ_A
VSSQ VSS VSSQ VSS
o
F12 N5 F12 N5
VSSQ VSS VSSQ VSS
.047U_0402_16V7K
.047U_0402_16V7K
F6 R4 F6 R4
E6 VSSQ VSS R5 E6 VSSQ VSS R5
D12 T2 D12 T2
VSSQ VSS VSSQ VSS
CD3 CHA@
CD4 CHA@
C6 T3 C6 T3
B12 VSSQ VSS T4 B12 VSSQ VSS T4
B6 VSSQ VSS T5 2 B6 VSSQ VSS T5 2
VSSQ VSS VSSQ VSS
H9CCNNN8JTMLAR-NTM_FBGA178~D H9CCNNN8JTMLAR-NTM_FBGA178~D
C
A A

LPDDR3_A
5 4 3 2 1
5 4 3 2 1
o
+1.8V_MEM +1.8V_MEM
UD3 @ UD4 @
A3 P9 DDR_B_D42 <7> A3 P9 DDR_B_D17 <7>

A4 VDD1 DQ0 N9 A4 VDD1 DQ0 N9
VDD1 DQ1 DDR_B_D47 <7> VDD1 DQ1 DDR_B_D16 <7>
D
A5 N10 DDR_B_D44 <7> A5 N10 DDR_B_D18 <7> D
VDD1 DQ2 VDD1 DQ2
v
A6 N11 A6 N11 +0.6VS
A10 M8 DDR_B_D43 <7> CHB_Group{5} A10 M8 DDR_B_D22 <7> CHB_Group{2}
U3 VDD1 DQ4 M9 U3 VDD1 DQ4 M9
U4 M10 DDR_B_D40 <7> U4 M10 DDR_B_D21 <7>
U5 VDD1 DQ6 M11 U5 VDD1 DQ6 M11 DDR_B_CAA0 RD36 2 1 68_0201_1%
VDD1 DQ7 DDR_B_D45 <7> VDD1 DQ7 DDR_B_D20 <7> DDR_B_CAA1
U6 F11 DDR_B_D51 <7> U6 F11 DDR_B_D30 <7> RD37 2 1 68_0201_1%
U10 VDD1 DQ8 F10 U10 VDD1 DQ8 F10 DDR_B_CAA2 RD38 2 1 68_0201_1%
+1.2V +1.2V
o
F9 DDR_B_D49 <7> F9 DDR_B_D25 <7> RD39 2 1 68_0201_1%
DQ10 F8 DQ10 F8 DDR_B_CAA4 RD40 2 1 68_0201_1%
DQ11 DDR_B_D53 <7> DQ11 DDR_B_D24 <7> DDR_B_CAA5
A8 E11 DDR_B_D50 <7> CHB_Group{6} A8 E11 DDR_B_D31 <7> CHB_Group{3} RD41 2 1 68_0201_1%
A9 VDD2 DQ12 E10 A9 VDD2 DQ12 E10 DDR_B_CAA6 RD42 2 1 68_0201_1%
D4 E9 DDR_B_D48 <7> D4 E9 DDR_B_D29 <7> RD43 2 1 68_0201_1%
D5 VDD2 DQ14 D9 D5 VDD2 DQ14 D9 DDR_B_CAA8 RD44 2 1 68_0201_1%
D6 T8 DDR_B_D32 <7> D6 T8 DDR_B_D4 <7> RD45 2 1 68_0201_1%
G5 VDD2 DQ16 T9 G5 VDD2 DQ16 T9 DDR_B_CAB0 RD46 2 1 68_0201_1%
n
VDD2 DQ17 DDR_B_D36 <7> VDD2 DQ17 DDR_B_D1 <7> DDR_B_CAB1
H5 T10 DDR_B_D39 <7> H5 T10 DDR_B_D3 <7> RD47 2 1 68_0201_1%
H6 VDD2 DQ18 T11 H6 VDD2 DQ18 T11 DDR_B_CAB2 RD48 2 1 68_0201_1%
H12 R8 DDR_B_D33 <7> CHB_Group{4} H12 R8 DDR_B_D0 <7> CHB_Group{0} RD49 2 1 68_0201_1%
J5 VDD2 DQ20 R9 J5 VDD2 DQ20 R9 DDR_B_CAB4 RD50 2 1 68_0201_1%
J6 R10 DDR_B_D35 <7> J6 R10 DDR_B_D6 <7> RD51 2 1 68_0201_1%
K5 VDD2 DQ22 R11 K5 VDD2 DQ22 R11 DDR_B_CAB6 RD53 2 1 68_0201_1%
DDR_B_D38 <7> DDR_B_D2 <7>
e
K6 VDD2 DQ23 C11 K6 VDD2 DQ23 C11 DDR_B_CAB7 RD52 2 1 68_0201_1%
K12 C10 DDR_B_D60 <7> K12 C10 DDR_B_D13 <7> RD54 2 1 68_0201_1%
L5 VDD2 DQ25 C9 L5 VDD2 DQ25 C9 DDR_B_CAB9 RD55 2 1 68_0201_1%
P4 C8 DDR_B_D63 <7> P4 C8 DDR_B_D10 <7>
P5 VDD2 DQ27 B11 P5 VDD2 DQ27 B11
VDD2 DQ28 DDR_B_D57 <7> CHB_Group{7} VDD2 DQ28 DDR_B_D12 <7> CHB_Group{1}
P6 B10 DDR_B_D61 <7> P6 B10 DDR_B_D8 <7>
U8 VDD2 DQ29 B9 U8 VDD2 DQ29 B9
U9 B8 DDR_B_D62 <7> U9 B8 DDR_B_D11 <7>
VDD2 DQ31 VDD2 DQ31
L
+1.2V +1.2V
A11 R2 DDR_B_CAB0 A11 R2 DDR_B_CAA0
VDDQ CA0 DDR_B_CAB1 DDR_B_CAB0 <7> VDDQ CA0 DDR_B_CAA1 DDR_B_CAA0 <7>
C12 P2 C12 P2
E8 N2 E8 N2
E12 N3 E12 N3
C VDDQ CA3 DDR_B_CAB4 DDR_B_CAB3 <7> VDDQ CA3 DDR_B_CAA4 DDR_B_CAA3 <7> C
G12 M3 G12 M3
VDDQ CA4 DDR_B_CAB5 DDR_B_CAB4 <7> VDDQ CA4 DDR_B_CAA5 DDR_B_CAA4 <7> +0.6VS
H8 F3 H8 F3
H9 E3 H9 E3
r
H11 E2 H11 E2
VDDQ CA7 DDR_B_CAB8 DDR_B_CAB7 <7> VDDQ CA7 DDR_B_CAA8 DDR_B_CAA7 <7> DDR_B_CS#0
J9 D2 J9 D2 RD56 2 1 80.6_0201_1%
VDDQ CA8 DDR_B_CAB9 DDR_B_CAB8 <7> VDDQ CA8 DDR_B_CAA9 DDR_B_CAA8 <7> DDR_B_CS#1
J10 C2 J10 C2 RD57 2 1 80.6_0201_1%
VDDQ CA9 DDR_B_CAB9 <7> VDDQ CA9 DDR_B_CAA9 <7> DDR_B_ODT0
K8 K8 RD58 2 1 80.6_0201_1%
K11 VDDQ K11 VDDQ DDR_B_CKE0 RD59 2 1 80.6_0201_1%
L12 VDDQ L10 L12 VDDQ L10 DDR_B_CKE1 RD60 2 1 80.6_0201_1%
VDDQ DQS0 DDR_B_DQS5 <7> VDDQ DQS0 DDR_B_DQS2 <7> DDR_B_CKE2
N8 G10 DDR_B_DQS6 <7> N8 G10 DDR_B_DQS3 <7> RD61 2 1 80.6_0201_1%
VDDQ DQS1 VDDQ DQS1
o
N12 P10 N12 P10 DDR_B_CKE3 RD62 2 1 80.6_0201_1%
VDDQ DQS2 DDR_B_DQS4 <7> VDDQ DQS2 DDR_B_DQS0 <7>
R12 D10 DDR_B_DQS7 <7> R12 D10 DDR_B_DQS1 <7>
U11 VDDQ DQS3 U11 VDDQ DQS3
VDDQ VDDQ
+1.2V L11 +1.2V L11
DQS0# DDR_B_DQS#5 <7> DQS0# DDR_B_DQS#2 <7>
F2 G11 DDR_B_DQS#6 <7> F2 G11 DDR_B_DQS#3 <7>
G2 VDDCA DQS1# P11 G2 VDDCA DQS1# P11
VDDCA DQS2# DDR_B_DQS#4 <7> VDDCA DQS2# DDR_B_DQS#0 <7>
H3 D11 DDR_B_DQS#7 <7> H3 D11 DDR_B_DQS#1 <7>
F
L2 VDDCA DQS3# L2 VDDCA DQS3#
M2 VDDCA M2 VDDCA
VDDCA L8 VDDCA L8
DM0 G8 DM0 G8 +0.6VS
A1 DM1 P8 A1 DM1 P8
A2 NC DM2 D8 A2 NC DM2 D8 RD66
A12 NC DM3 A12 NC DM3 37.4_0201_1%
A13 NC A13 NC DDR_B_CLK#0 2 1
l
B1 NC B3 RD63 1 2 243_0402_1% B1 NC B3 RD67 1 2 243_0402_1%
B13 NC ZQ0 B4 RD64 1 2 243_0402_1% B13 NC ZQ0 B4 RD65 1 2 243_0402_1%
C4 NC ZQ1 C4 NC ZQ1 RD68
K9 NC K9 NC 37.4_0201_1%
R3 NC K3 DDR_B_CKE2 R3 NC K3 DDR_B_CKE0 DDR_B_CLK0 2 1
NC CKE0 DDR_B_CKE3 DDR_B_CKE2 <7> NC CKE0 DDR_B_CKE1 DDR_B_CKE0 <7> +0.6VS
T1 K4 T1 K4
a
NC CKE1 DDR_B_CKE3 <7> NC CKE1 DDR_B_CKE1 <7>
T13 T13
U1 NC U1 NC RD69
U2 NC L3 DDR_B_CS#0 U2 NC L3 DDR_B_CS#0 37.4_0201_1%
NC CS0# DDR_B_CS#1 NC CS0# DDR_B_CS#1 DDR_B_CS#0 <7> DDR_B_CLK#1
B U12 L4 U12 L4 2 1 B
NC CS1# NC CS1# DDR_B_CS#1 <7>
U13 U13
NC NC
J3 DDR_B_CLK1 J3 DDR_B_CLK0 RD70
CK DDR_B_CLK1 <7> CK DDR_B_CLK0 <7>
p
P3 J2 DDR_B_CLK#1 P3 J2 DDR_B_CLK#0 37.4_0201_1%
VSSCA CK# DDR_B_CLK#1 <7> VSSCA CK# DDR_B_CLK#0 <7> DDR_B_CLK1
M4 M4 2 1
J4 VSSCA J4 VSSCA
G4 VSSCA J8 DDR_B_ODT0 G4 VSSCA J8 DDR_B_ODT0
VSSCA ODT VSSCA ODT DDR_B_ODT0 <7>
G3 G3
F4 VSSCA F4 VSSCA
D3 VSSCA J11 D3 VSSCA J11
VSSCA Vref_DQ +VREFDQ_B VSSCA Vref_DQ +VREFDQ_B
C3 H4 +VREFCA
C3 H4 +VREFCA
VSSCA Vref_CA VSSCA Vref_CA
T12 B2 T12 B2
VSSQ VSS VSSQ VSS
m
T6 B5 T6 B5
R6 VSSQ VSS C5 R6 VSSQ VSS C5
P12 VSSQ VSS E4 P12 VSSQ VSS E4
VSSQ VSS VSSQ VSS
.047U_0402_16V7K
.047U_0402_16V7K
N6 E5 N6 E5
M12 VSSQ VSS F5 M12 VSSQ VSS F5
M6 H2 M6 H2
VSSQ VSS VSSQ VSS
CD5
CD6
L9 J12 L9 J12
VSSQ VSS VSSQ VSS
o
K10 K2 K10 K2
H10 VSSQ VSS L6 2 H10 VSSQ VSS L6 2
G9 VSSQ VSS M5 +VREFCA G9 VSSQ VSS M5 +VREFCA
G6 VSSQ VSS N4 G6 VSSQ VSS N4
F12 VSSQ VSS N5 +VREFDQ_B F12 VSSQ VSS N5 +VREFDQ_B
F6 VSSQ VSS R4 F6 VSSQ VSS R4
VSSQ VSS VSSQ VSS
.047U_0402_16V7K
.047U_0402_16V7K
E6 R5 E6 R5
D12 VSSQ VSS T2 D12 VSSQ VSS T2
C6 T3 C6 T3
VSSQ VSS VSSQ VSS
CD7
CD8
B12 T4 B12 T4
C
B6 VSSQ VSS T5 B6 VSSQ VSS T5
A H9CCNNN8JTMLAR-NTM_FBGA178~D H9CCNNN8JTMLAR-NTM_FBGA178~D A

LPDDR3_B
0.2
5 4 3 2 1
1 2 3 4 5
UV1A
COMMON
1/14 PCI_EXPRESS
Place near Place near BGA Midway GPU & VR
AB6 PEX_WAKE#
balls +1.0VS_DGPU
AA22 AE27
PEX_IOVDD AA22
PLT_RST_VGA# AC7 PEX_IOVDD AB23
PEX_RST#
1U_0201_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
22U_0603_6.3V6M
PEX_IOVDD AC24
10U_0402_6.3V6M
10U_0402_6.3V6M
CLKREQ_PCIE#0_R
CV202
CV205
CV2
CV393
AC6 AD25
CV199
CV204
PEX_CLKREQ# PEX_IOVDD 1 1 1 1 1 1
CV9 DIS@
PEX_IOVDD AE26
AE8 PEX_REFCLK PEX_IOVDD AE27
<10> CLK_PCIE_P0
PCIE CLK AD8 PEX_REFCLK#
<10> CLK_PCIE_N0
2
2 2 2 2 2 2
DIS@
DIS@
DIS@
DIS@
A
CV11 DIS@ 1 2 0.22U_0201_6.3V6M PCIE_CRX_C_DTX_P13 AC9 PEX_TX0
<12> PCIE_CRX_DTX_P13 A
2 0.22U_0201_6.3V6M PCIE_CRX_C_DTX_N13
v
CV12 DIS@ 1 AB9 PEX_TX0#
<12> PCIE_CRX_DTX_N13
AG6 PEX_RX0
<12> PCIE_CTX_C_DRX_P13 AG7 AA10
PEX_RX0# PEX_IOVDDQ
PEX_IOVDDQ AA12 Place near balls Place near BGA Midway GPU & VR
CV13 DIS@ 1 2 0.22U_0201_6.3V6M PCIE_CRX_C_DTX_P14 AB10 PEX_TX1 PEX_IOVDDQ AA13 +1.8VS_DGPU
CV14 DIS@ 1 2 0.22U_0201_6.3V6M PCIE_CRX_C_DTX_N14 AC10 PEX_TX1# PEX_IOVDDQ AA16 AA10 AA16 AB22 AF27
o
PEX_IOVDDQ AA18
AF7 PEX_RX1 PEX_IOVDDQ AA19
<12> PCIE_CTX_C_DRX_P14
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
AE7 PEX_RX1# PEX_IOVDDQ AA20
CV392
CV3
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
PEX_IOVDDQ AA21 1 1 1 1 1 1 1
10U_0402_6.3V6M
10U_0402_6.3V6M
1
1
2 0.22U_0201_6.3V6M PCIE_CRX_C_DTX_P15
CV201 DIS@
CV200 @
CV390 DIS@
CV391 DIS@
CV10 DIS@
CV719 DIS@
CV724 @
PCIE X4 Bus CV15 DIS@ 1 AD11 PEX_TX2 PEX_IOVDDQ AB22
2 0.22U_0201_6.3V6M PCIE_CRX_C_DTX_N15
DIS@ CV198
DIS@ CV203
CV16 DIS@ 1 AC11 PEX_TX2# PEX_IOVDDQ AC23
PEX_IOVDDQ AD24
2
2 2 2 2 2 2 2
@
AE9 AE25
n
PEX_RX2 PEX_IOVDDQ
<12> PCIE_CTX_C_DRX_P15 AF9 AF26
PEX_RX2# PEX_IOVDDQ
<12> PCIE_CTX_C_DRX_N15 AF27
PEX_IOVDDQ
CV17 DIS@ 1 2 0.22U_0201_6.3V6M PCIE_CRX_C_DTX_P16 AC12 PEX_TX3
CV18 DIS@ 1 2 0.22U_0201_6.3V6M PCIE_CRX_C_DTX_N16 AB12 PEX_TX3#
AG9 PEX_RX3
e
<12> PCIE_CTX_C_DRX_P16 AG10
<12> PCIE_CTX_C_DRX_N16 PEX_RX3#
AB13
Near UV1 AC13
PEX_TX4
PEX_TX4#
AF10 PEX_RX4 Place

AE10 PEX_RX4# near ball +1.8VS_DGPU
AD14 NC FOR GF119
L
PEX_TX5
AC14 PEX_TX5# PEX_PLL_HVDD AA8
PEX_PLL_HVDD AA9
NC FOR GM108
AE12 PEX_RX5
0.1U_0201_10V6K
AF12 PEX_RX5#
PEX_SVDD_3V3 AB8 1
B @ T9 B
CV207 DIS@
AC15 PEX_TX6
AB15 PEX_TX6#
r
AG12 2
PEX_RX6
AG13 PEX_RX6#
AB16 PEX_TX7
AC16 PEX_TX7#
AF13 PEX_RX7
o
AE13 PEX_RX7#
AD17 PEX_TX8
AC17 PEX_TX8#
AE15 PEX_RX8
AF15 PEX_RX8#
F
AC18 F2 VDD_SENSE_GPU
PEX_TX9 VDD_SENSE VDD_SENSE_GPU <49>
AB18 PEX_TX9# To POWER
AG15 F1 GND_SENSE_GPU
PEX_RX9 GND_SENSE GND_SENSE_GPU <49>
AG16 PEX_RX9# trace width: 16mils
differential voltage sensing.
AB19
AC19
PEX_TX10 differential signal routing.
l
PEX_TX10#
AF16 PEX_RX10
Reset Control AE16 PEX_RX10#
NC FOR GF117/GK208/GM108
+1.8VS_DGPU_AON
AD20 PEX_TX11
UV12 DIS@ AC20
1.8V AND GATE PEX_TX11#
a
5
NL17SZ08DFT2G_SC70-5
AE18 PEX_RX11
VCC
PCI_RST# 1 AF18
<10,32,34> PCI_RST# IN B PEX_RX11#
C 4 PLT_RST_VGA# C
DGPU_HOLD_RST# 2 OUT Y PLT_RST_VGA# <24>
AC21
GND
(From PCH) <11> DGPU_HOLD_RST# IN A PEX_TX12

1
AB21 PEX_TX12#
p
RV378 DIS@ AG18 PEX_RX12 PEX_TSTCLK_OUT AF22
@ T5
3
10K_0402_5% AG19 PEX_RX12# PEX_TSTCLK_OUT# AE22

@ T6
2
AD23 PEX_TX13
AE23 PEX_TX13#
AF19 PEX_RX13 PEX_PLLVDD AA14

@ T7
AE19 PEX_RX13# PEX_PLLVDD AA15
@ T8
AF24 PEX_TX14
AE24 PEX_TX14#
m
+3VS
CLK_REQ AE21 PEX_RX14
AF21 PEX_RX14#
AD9 GPU_TESTMODE
TESTMODE GPU_TESTMODE <24>
1
AG24 PEX_TX15
RV17 DIS@ AG25 PEX_TX15#
+3VS 10K_0402_5%
o
UV11 DIS@ AG21 PEX_RX15
TC7SH09FU_SSOP5 AG22 PEX_RX15#
2
Open Drain
5
1 AF25 PEX_TERMP
PEX_TERMP
G VCC
<25,49> DGPU_PWROK B GPU_ALL_PGOOD

4
Y GPU_ALL_PGOOD <11>
1
2
<50> +1.35VGS_PGOOD A N17S-G1-A1_FCBGA_595P RV376
+1.8VS_DGPU DIS@ 2.49K_0402_1%
3
DIS@
C 2
1
+1.8VS_DGPU_AON
RV18 DIS@
D 10K_0402_5% D
1
RV68 DIS@
10K_0402_5%
2
QV3B @
2
2N7002KDW_SOT363-6
G
1 6 CLKREQ_PCIE#0_R 1 6
CLKREQ_PCIE#0 <10>
S
QV147B (To SOC)

2N7002KDW_SOT363-6
DIS@
NV(1/5)-PCIE
Size Document Number R ev
VGS(Max) : 0.95 V AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1 2 3 4 5
1 2 3 4 5
UV1G
COMMON
IFPA/B +VGA_CORE UV1H
IFPC +VGA_CORE +VGA_CORE UV1I
IFPD +VGA_CORE
4/14 IFPAB COMMON COMMON
o
5/14 IFPC 6/14 IFPD
IFPC
IFPA_TXC# AC4
AC3 T6 U6 GF119/GK208
IFPA_TXC IFPC_RSET GF119/GK208 IFPD_RSET
AA6 DVI/HDMI DP
IFPAB_RSET DVI/HDMI DP
A IFPA_TXD0# Y3 A
v
Y4 M7 N5 T7 P4
NC FOR GF117/GM108
IFPA_TXD0 IFPC_PLLVDD I2CW_SDA IFPC_AUX# IFPD_PLLVDD I2CX_SDA IFPD_AUX#
N7 N4 P3
NC FOR GF117/GM108
IFPC_PLLVDD I2CW_SCL IFPC_AUX I2CX_SCL IFPD_AUX
V7 R7
NC FOR GF117/GM108
IFPAB_PLLVDD IFPD_PLLVDD
AA2
NC FOR GF117/GM108
IFPA_TXD1#
W7 IFPAB_PLLVDD IFPA_TXD1 AA3 IFPC_L3# N3 IFPD_L3# R5
TXC TXC
NC FOR GF117/GM108
IFPC_L3 N2 IFPD_L3 R4
TXC TXC
o
IFPA_TXD2# AA1 IFPC_L2# R3 IFPD_L2# T5
AB1 TXD0 R2 TXD0 T4
IFPA_TXD2 TXD0 IFPC_L2 TXD0 IFPD_L2
NC FOR GF117/GM108
TXD1 IFPC_L1# R1 TXD1 IFPD_L1# U4
IFPA_TXD3# AA5 TXD1 IFPC_L1 T1 IFPD TXD1 IFPD_L1 U3
IFPA_TXD3 AA4
IFPC_L0# T3 IFPD_L0# V4
TXD2 TXD2
T2 V3
n
TXD2 IFPC_L0 TXD2 IFPD_L0
IFPB_TXC# AB4
IFPB_TXC AB5
GF117 GF117
P6 IFPC_IOVDD GPIO15 C3 R6 IFPD_IOVDD GPIO17 D4
NC NC
W6 IFPA_IOVDD IFPB_TXD4# AB2
IFPB_TXD4 AB3
e
Y6 IFPB_IOVDD
N17S-G1-A1_FCBGA_595P
IFPB_TXD5# AD2 DIS@
IFPB_TXD5 AD3
DIS@
IFPB_TXD6# AD1
IFPB_TXD6 AE1
L
IFPB_TXD7# AD5
IFPB_TXD7 AD4
B Note: UV1K
DAC_A B
GF117 IFPC/D/E/F interface are XVDDs pin for N17S GPU, COMMON
3/14 DACA
r
NC GPIO14 B3 and connect them to NVVDD power for improving
IFPAB NVVDD power rail routing W5 DACA_VDD
GF117/GM108 GF117 GM108/GK208
I2CA_SCL B7
NC NC
N17S-G1-A1_FCBGA_595P I2CA_SDA A7
NC
DIS@ AE2 DACA_VREF TSEN_VREF
AF2 DACA_RSET DACA_HSYNC AE3

NC NC
o
DACA_VSYNC AE4
NC
DACA_RED AG3
NC
DACA_GREEN AF4
NC
+VGA_CORE UV1J
IFPE/F +VGA_CORE
NC DACA_BLUE AF3
F
COMMON
7/14 IFPEF GM108
GK208
GF117
GF119/GK208
DVI-DL DVI-SL/HDMI DP DIS@
I2CY_SDA I2CY_SDA IFPE_AUX# J3
J2
l
I2CY_SCL I2CY_SCL IFPE_AUX
J7 IFPEF_PLLVDD
IFPE_L3# J1
TXC TXC
IFPE_L3 K1
NC FOR GF117/GM108
TXC TXC
K7 IFPEF_PLLVDD
K3
NC FOR GF117/GK208/GM108
IFPE_L2#
X'TAL
a
TXD0 TXD0 K2 UV1M
IFPE_L2
TXD0 TXD0 +1.8VS_DGPU_PLLVDD Place near balls COMMON
K6 IFPEF_RSET IFPE_L1# M3 9/14 XTAL_PLL
TXD1 TXD1
C IFPE_L1 M2 C
TXD1 TXD1
L6 PLLVDD
IFPE_L0# M1 L6 M6 N6 M6 +1.8VS_DGPU_AON
SP_PLLVDD
TXD2 TXD2 N1 RV23 @
IFPE_L0
p
TXD2 TXD2
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
N6 VID_PLLVDD 10K_0402_1%
NC XTAL_OUTBUFF 1 2
IFPE NC FOR GK208 1 1 1
CV31 DIS@
CV34 DIS@
CV60 DIS@
GF119/GK208 GF117/GM108
RV21 DIS@ RV20 DIS@

GPIO18 C2 2 2 2 10K_0402_1% 10K_0402_1%
HPD_E HPD_E
2 1 A10 XTALSSIN XTALOUTBUFF C10 XTAL_OUTBUFF 1 2
NC FOR GF117
C11 XTALIN XTALOUT B10
H6 IFPE_IOVDD
m
GF119/GK208 N17S-G1-A1_FCBGA_595P
J6 IFPF_IOVDD DIS@
1
DVI-DL DVI-SL/HDMI DP
IFPF_AUX# H4 RV22 DIS@
I2CZ_SDA
I2CZ_SCL IFPF_AUX H3 470_0201_5%
YV1 DIS@ SJ10000UI00
27MHZ_10PF_XRCGB27M000F2P18R0
2
o
TXC IFPF_L3# J5
J4 1 3
NC FOR GF117/GM108
TXC IFPF_L3
1 3
K5 NC NC
TXD3 TXD0 IFPF_L2# 2 2
IFPF_L2 K4
TXD3 TXD0 2 4
CV210 DIS@ CV209 DIS@
TXD4 TXD1 IFPF_L1# L4 18P_0402_50V8J 18P_0402_50V8J
IFPF IFPF_L1 L3 1 1
TXD4 TXD1
IFPF_L0# M5
C
TXD5 TXD2
IFPF_L0 M4
TXD5 TXD2
NC FOR GK208
D D
GPIO19 F7
HPD_F
NC FOR GF117
DIS@ Security Classification Compal Secret Data Compal Electronics, Inc.
NV(2/5)-IFP_ABCDEF_DAC_XTAL
1 2 3 4 5
1 2 3 4 5
+1.35VS_VRAM
UV1D UV1F
o
COMMON COMMON
GPU_Decoupling
12/14 FBVDDQ 13/14 GND
Place near BGA Place near balls A2 GND GND M13
B26 FBVDDQ AB17 GND GND M15
H24 J21 M21 W21 L24 C25 FBVDDQ AB20 GND GND M17
E23 FBVDDQ
CAPs @ Power AB24 GND GND N10
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
E26 AC2 N12
@ CV45
@ CV405
@ CV406
CV403
CV404
1 1 1 1 1 1
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
FBVDDQ GND GND
10U_0402_6.3V6M
A A
1
v
F14 AC22 N14
DIS@ CV38
DIS@ CV217
DIS@ CV218
FBVDDQ GND GND
Page
DIS@ CV44
F21 FBVDDQ AC26 GND GND N16
G13 FBVDDQ AC5 GND GND N18
2
2 2 2 2 2 2 G14 AC8 P11
DIS@
DIS@
FBVDDQ GND GND
G15 FBVDDQ AD12 GND GND P13
G18 FBVDDQ A26 GND GND P17
+VGA_CORE P2 NC
o
G20 FBVDDQ UV1E AD16 GND GND P23
G21 FBVDDQ Voltage by GPU SKU COMMON AD18 GND GND P26
L22 FBVDDQ 11/14 NVVDD AD19 GND GND P5 P5 NC
L24 FBVDDQ K10 VDD AD21 GND GND R10
L26 FBVDDQ K12 VDD AD22 GND GND R12
M21 FBVDDQ K14 VDD AE11 GND GND R14
N21 K16 AE14 R16
n
FBVDDQ VDD GND GND
R21 FBVDDQ K18 VDD AE17 GND GND R18
T21 FBVDDQ L11 VDD AE20 GND GND T11
V21 FBVDDQ L13 VDD AB11 GND GND T13
W21 FBVDDQ L15 VDD AF1 GND GND T15
L17 VDD AF11 GND GND T17
M10 VDD AF14 GND GND U10
e
GF117 M12 AF17 U12
GF119
VDD GND GND
Place near balls M14 VDD AF20 GND GND U14
GK208
M16 VDD AF23 GND GND U16
H24 FBVDDQ_AON M18 VDD AF5 GND GND U18
FBVDDQ
L26 E26 G19 G13 G16 H26 FBVDDQ_AON N11 VDD AF8 GND GND U2 U2 NC
FBVDDQ
J21 FBVDDQ_AON N13 VDD AG2 GND GND U23
FBVDDQ
K21 FBVDDQ_AON N15 VDD AG26 GND GND U26
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
FBVDDQ
1
1
N17 AB14 U5
DIS@ CV399
DIS@ CV400
DIS@ CV401
DIS@ CV402
DIS@ CV221
VDD GND GND U5 NC
P10 B1 V11
L
VDD GND GND
P12 VDD B11 GND GND V13
2
2
P18 VDD B20 GND GND Y2
R11 VDD B23 GND GND Y23
B R13 B27 Y26 B
VDD GND GND
R15 VDD B5 GND GND Y5
R17 VDD B8 GND
r
T10 VDD E11 GND
T12 VDD E14 GND
T14 VDD E17 GND
T16 VDD E2 GND
T18 VDD E20 GND
U11 VDD E22 GND
U13 VDD E25 GND
o
Near Ball +1.35VS_VRAM U15 E5
VDD GND
U17 VDD E8 GND
V10 VDD H2 GND
D22 1 DIS@ 2 40.2_0402_1% V12
H2 NC H23
FB_CAL_PD_VDDQ RV41 VDD GND
V14 VDD H25 GND
V16 VDD H5 NC H5 GND
FB_CAL_PU_GND C24 RV42 2 DIS@ 1 40.2_0402_1% V18 VDD K11 GND
K13 GND
F
K15 GND
FB_CALTERM_GND B25 RV43 2 DIS@ 1 60.4_0402_1% N17S-G1-A1_FCBGA_595P K17 GND
DIS@ L10 GND
L12 GND
N17S-G1-A1_FCBGA_595P L14 GND
DIS@ L16 GND
L18 GND
L2 NC L2
l
GND
L23 GND
L25 GND
L5 GND GND AA7
M11 GND GND AB7
a
DIS@
C C
p
+VGA_CORE UV1C
COMMON
14/14 XVDD/VDD33
+1.8VS_DGPU
Under GPU Near GPU
AD10 NC VDD33 G8
AD7 NC GM108 VDD33 G9 G8 G9
+1.8VS_DGPU +1.8VS_DGPU_PLLVDD G10
VDD33
0.1U_0201_10V6K
0.1U_0201_10V6K
4.7U_0402_6.3V6M
3V3_AON
Near GPU Under GPU VDD33 G12 1 1 1
1U_0201_6.3V6M
3V3_AON
1
F11
DIS@ CV220
DIS@ CV211
DIS@ CV219
DIS@ CV216
1 2 F11 3V3AUX_NC
m
4.7U_0402_6.3V6M
LV10 DIS@ 2
2 2 2
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
0.1U_0201_10V6K
SM01000NV00 1 1 1 1 V5 FERMI_RSVD1_NC
CV722 @
CV720 DIS@
CV396 @
CV395 DIS@
HCB1005KF-300T25_2P 1 V6 FERMI_RSVD2_NC
CV394 @
+1.8VS_DGPU_AON
2 2 2 2
2 Under GPU Near GPU
o
CONFIGURABLE
POWER CHANNELS G10 G12
* nc on substrate
0.1U_0201_10V6K
0.1U_0201_10V6K
4.7U_0402_6.3V6M
G1
CV213
1 1 1
1U_0201_6.3V6M
XPWR_G1
1
G2
DIS@ CV397
@ CV214
@ CV212
XPWR_G2
G3 XPWR_G3
G4 XPWR_G4
2
G5 2 2 2
DIS@
XPWR_G5
G6 XPWR_G6
C
G7 XPWR_G7
D V1 XPWR_V1 D
V2 XPWR_V2
** XPWR pins are configurable.

These pins are not connected on the substrate.
W1 XPWR_W1
Therefore, XPWR pins can be assigned as needed, W2 XPWR_W2
W3
to improve Top layer routing, power delivery. W4
XPWR_W3
XPWR_W4
NV(3/5)-POWER
DIS@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
1 2 3 4 5
1 2 3 4 5
+1.8VS_DGPU_AON
UV1N
COMMON GPIO +1.8VS_DGPU_AON
8/14 MISC1
I2CS_SCL D9 I2CS_SCL RV203 1 DIS@ 2 2.2K_0402_5% I2CS SMBUS: 0x9E and 0x9C DGPU_MAIN_EN RV90 1 DIS@ 2 2K_0402_1%
I2CS_SDA
I2CS_SDA D8 RV204 1 DIS@ 2 2.2K_0402_5%
Debug Address: 0x96
A9 I2CC_SCL RV205 1 DIS@ 2 2.2K_0402_5% PSI RV91 1 DIS@ 2 10K_0402_5%
I2CC_SCL I2CC_SDA
I2CC_SDA B9 RV206 1 DIS@ 2 2.2K_0402_5%
VGA_AC_DET RV92 1 DIS@ 2 10K_0402_5%
o
E12 GF117 GPU_EVENT#_D RV72 1 GC6@ 2 10K_0402_5%
THERMDN
C9 I2CB_SCL RV208 1 DIS@ 2 2.2K_0402_5%
NC I2CB_SCL I2CB_SDA GPIO8_OVERT#
F12 THERMDP I2CB_SDA C8 RV207 1 DIS@ 2 2.2K_0402_5% RV69 1 DIS@ 2 100K_0402_5%
NC
GPIO9_ALERT# RV93 1 DIS@ 2 10K_0402_5%
GPU_JTAG_TCK AE5
T231 @ JTAG_TCK
GPU_JTAG_TMS AD6
T232 @ JTAG_TMS
A GPU_JTAG_TDI AE6 A
JTAG_TDI
v
T242 @ GPU_JTAG_TDO
T243 @
AF6 JTAG_TDO
GPU_JTAG_TRST# AG4 C6 GPU_VID0
JTAG_TRST# GPIO0 GPIO0_GC6_FB_EN
To DGPU VR GPU_VID0 <49>
GPIO1 B2 RV202 1 @ 2 0_0402_5%
GPU_EVENT#_D GC6_FB_EN <9,25>
GPIO2 D6 DV1 DIS@ 2 1 RB751V-40_SOD323-2
GPU_EVENT# <9>
GPIO3 C7
F9 DGPU_MAIN_EN GPU_JTAG_TRST# RV94 1 DIS@ 2 10K_0402_5%
GPIO4 DGPU_MAIN_EN <26>
GPIO5 A3
A4 PSI To DGPU VR MEM_VREF RV102 1 DIS@ 2 100K_0402_5%
GK208 GPIO6 PSI <49>
o
GM108 GPIO7 B6
A6 GPIO8_OVERT# GC6_FB_EN RV88 1 GC6@ 2 10K_0402_5%
OVERT GPIO8 GPIO9_ALERT#
GPIO9 F8
C5 MEM_VREF GPU_TESTMODE RV71 1 DIS@ 2 10K_0402_5%
GPIO10 MEM_VREF <27> <21> GPU_TESTMODE
GPIO11 E7
D7 VGA_AC_DET DV2 @ 2 1 RB751V40_SC76-2
GPIO12 AC_PRESENT <10,34>
GPIO13 B4
n
GM108 GK208 GF117 GF119
GPIO16 GPIO16 NC GPIO16 D5

GPIO20 GPIO20 NC GPIO20 E6
GPIO21 GPIO8 GPIO21 C4
NC
GPIO8 NC E9
NC NC
e
DIS@
UV1L
COMMON
EXPOSED STRAP
L
10/14 MISC2
+1.8VS_DGPU_AON
E10 VMON_IN0_NC
F10 VMON_IN1_NC ROM_CS# D12
B B
1
B12 ROM_SI
100K_0402_5%
100K_0402_5%
100K_0402_5%
ROM_SI
A12 ROM_SO
ROM_SO
D1 C12 ROM_SCLK
RV84
RV81
RV80
STRAP0 DIS@ DIS@ DIS@
r
STRAP0 ROM_SCLK
STRAP1 D2 STRAP1
STRAP2 E4 NC FOR
STRAP2
2
STRAP3 E3 GM108
STRAP3
STRAP4 D3 ROM_SI
STRAP4
ROM_SO
ROM_SCLK
STRAP5 C1 STRAP5_NC
1
o
D11
100K_0402_5%
100K_0402_5%
100K_0402_5%
BUFRST#
F6 D10
RV65
RV64
RV381
MULTISTRAP_REF0_GND NC PGOOD @ @ DIS@
+VGA_CORE GF117
GK208 GF117 GF119
2
GM108 GK208
RV6 1 @ 2 100_0402_1% F4 MULTISTRAP_REF1_GND GM108
NC
F5 MULTISTRAP_REF2_GND NC
F
DIS@
Internal Thermal Sensor
RV74 DIS@ RV75 DIS@
Link to PCH SML1
STRAP PLT_RST_VGA# 1 2 10K_0402_5% PLT_RST_VGA# 1 2 10K_0402_5% PU @ PCH SIDE
l
<21> PLT_RST_VGA#
5
+1.8VS_DGPU_AON QV2B DIS@ QV2A DIS@
RAM Config 2N7002KDW_SOT363-6 2N7002KDW_SOT363-6
G
I2CS_SDA 1 6 I2CS_SCL 4 3
EC_SMB_DA2 <8,30,34,36> EC_SMB_CK2 <8,30,34,36>
D
a
1
1
100K_0402_5%
100K_0402_5%
100K_0402_5%
100K_0402_5%
100K_0402_5%
100K_0402_5%
RV398
RV61
RV389
RV382
RV51
RV384
@ @ @ @ @ @
C C
2
RV76 @ RV77 DIS@

PLT_RST_VGA# 1 2 10K_0402_5% PLT_RST_VGA# 1 2 10K_0402_5%
STRAP0
5
p
STRAP1 QV3A @ QV147A DIS@
STRAP2 2N7002KDW_SOT363-6 2N7002KDW_SOT363-6
G
STRAP3 GPIO8_OVERT# 2 1 GPIO8_OVERT#_R 4 3 GPIO9_ALERT# 4 3
GPU_OVERT# <34> GPU_PROHOT# <34,36>
D
STRAP4 RV260 @ 0_0402_5%
STRAP5
1
1
100K_0402_5%
100K_0402_5%
100K_0402_5%
100K_0402_5%
100K_0402_5%
100K_0402_5%
+3VALW +3VS
RV399
RV385
RV387
RV388
RV390
RV383
DIS@ DIS@ DIS@ @ @ @
+3VS
2
1
m
RV106 DIS@ RV108 DIS@ UV10 DIS@
100K_0402_5% 10K_0402_5% NL17SZ08DFT2G_SC70-5
5
2
2
Enable: Vh:2.1V Vl:1V DV4 DIS@ Enable: Vh:1.5V Vl:0.7V
GND VCC
1.8VSDGPU_MAIN 1 RB751S-40_SOD523-2
IN B 4 GPUCORE_EN 1 2
OUT Y VGA_CORE_EN <49>
3
2
IN A
o
D
5 G
2
S RV254 @ RV105 DIS@ 1
DGPU_MAIN_EN 2 G
D
100K_0402_5% 40.2K_0402_1%
3
1 2
RAM_CFG X76 STRAP2 STRAP1 STRAP0 QV7B DIS@
S
QV7A DIS@ CV197 DIS@
1
2N7002KDW_SOT363-6 2N7002KDW_SOT363-6 2 0.1U_0201_10V6K
1
ZZZ RV388 RV390 RV383 UV6 S2G@ UV7 S2G@
0x00(LLL) S2G X76V@ S2G@ S2G@ S2G@ SA000092D10 SA000092D10
DV5 DIS@
0x01(LLH) RB751S-40 SOD-523
1 2
C
1.0VS_DGPU_EN <26,45>
0x02(LHL) <11,26,34> DGPU_PWR_EN
delay 1.33ms
RV103 DIS@
100K_0402_1%
0.1U_0201_10V6K
2
2
D 0x03(LHH) 56K_0402_1% 1 D
RV255 @
RV256 @ 1 2
ZZZ RV382 RV390 RV383 UV6 M2G@ UV7 M2G@ 100K_0402_5%
0x04(HLL) M2G
CV196
X76V@ M2G@ M2G@ M2G@ SA00009TV60 SA00009TV60 @
2
1
ZZZ RV382 RV390 RV384 UV6 H2G@ UV7 H2G@
0x05(HLH) H2G X76V@ H2G@ H2G@ H2G@ SA00009U150 SA00009U150
0x06(HHL)
0x07(HHH)
0x08(LLM) Issued Date 2018/2/5 Deciphered Date 2019/2/5 Title
NV(4/5)-GPIO/Strap
1 2 3 4 5
1 2 3 4 5
For GC6
+1.8VS_DGPU_AON
UV1B
COMMON 1
1.8V OR GATE
o
2/14 FBA CV223 @
<27> FB_A_D[0..31] FB_A_D0 E18 FBA_D0 FB_CLAMP F3 RV5 1 @ 2 100_0402_1% 0.1U_0201_10V6K
FB_A_D1 NC
F18 FBA_D1
FB_A_D2 E16 2 UV23 @
FBA_D2 GF119
5
FB_A_D3 F17 74AUP1G32GW_TSSOP5
FBA_D3
FB_A_D4 D20 GC6_FB_EN 2 SA000054300 DV3 GC6@
FBA_D4
G Vcc
FB_A_D5 <9,24> GC6_FB_EN A GC6_FB_EN
A
D21 FBA_D5 4 2 A
FB_A_D6 Y 1.35V_PWR_EN <50> 1.35V_PWR_EN
v
F20 FBA_D6 1 1
FB_A_D7 <21,49> DGPU_PWROK B DGPU_PWROK
E21 FBA_D7 3
FB_A_D8 E15 FBA_D8
1
FB_A_D9 D15 BAV70W_SOT323-3
FBA_D9
FB_A_D10 F15 RV12
FBA_D10
FB_A_D11 F13 16.5K_0402_5%
FBA_D11
FB_A_D12 C13 GC6@
FBA_D12
FB_A_D13
o
B13 FBA_D13
2
FB_A_D14 E13 FBA_D14
FB_A_D15 D13 RV201 1 2 0_0402_5%
FBA_D15
FB_A_D16 B15 NOGC6@
FBA_D16
FB_A_D17 C16 FBA_D17
FB_A_D18 A13 Stuff RV201 if not support GC6
FBA_D18
FB_A_D19 A15 FBA_D19
FB_A_D20 B18
n
FBA_D20
FB_A_D23 C19
FB_A_D24 B24
FBA_D23
FBA_D24
From DG-07158-001_v05_secured(NVDIA Spec)
e
FB_A_D29 B21 FBA_D29 FB_A_CMD[0..31] <27>
FB_A_D31 C21
<27> FB_A_D[32..63] FBA_D31
FB_A_D32 R22 FBA_D32
FB_A_D33 R24 C27 FB_A_CMD0
FBA_D33 FBA_CMD0
FB_A_D34 T22 C26 FB_A_CMD1
FBA_D34 FBA_CMD1
FB_A_D35 R23 E24 FB_A_CMD2
L
FBA_D35 FBA_CMD2
FB_A_D36 N25 F24 FB_A_CMD3
FBA_D36 FBA_CMD3
FB_A_D37 N26 D27 FB_A_CMD4
FBA_D37 FBA_CMD4
FB_A_D38 N23 D26 FB_A_CMD5
FBA_D38 FBA_CMD5
FB_A_D39 N24 F25 FB_A_CMD6
FBA_D39 FBA_CMD6
FB_A_D40 V23 F26 FB_A_CMD7
FBA_D40 FBA_CMD7
B FB_A_D41 V22 F23 FB_A_CMD8 +1.35VS_VRAM B
FBA_D41 FBA_CMD8
FB_A_D42 T23 G22 FB_A_CMD9
FBA_D42 FBA_CMD9
FB_A_D43 U22 G23 FB_A_CMD10
FBA_D43 FBA_CMD10
r
FB_A_D44 Y24 G24 FB_A_CMD11 FBA_CKE_L FB_A_CMD14 RV2439 1 DIS@ 2 10K_0201_1%
FBA_D44 FBA_CMD11
FB_A_D45 AA24 F27 FB_A_CMD12 FBA_CKE_H FB_A_CMD30 RV2440 1 DIS@ 2 10K_0201_1%
FBA_D45 FBA_CMD12
FB_A_D46 Y22 G25 FB_A_CMD13
FBA_D46 FBA_CMD13
FB_A_D47 AA23 G27 FB_A_CMD14
FBA_D47 FBA_CMD14
FB_A_D48 AD27 G26 FB_A_CMD15 FBA_RST_L FB_A_CMD13 RV2437 1 DIS@ 2 10K_0201_1%
FBA_D48 FBA_CMD15
FB_A_D49 AB25 M24 FB_A_CMD16 FBA_RST_H FB_A_CMD29 RV2438 1 DIS@ 2 10K_0201_1%
FBA_D49 FBA_CMD16
FB_A_D50 AD26 M23 FB_A_CMD17
FBA_D50 FBA_CMD17
o
FB_A_D51 AC25 K24 FB_A_CMD18
FBA_D51 FBA_CMD18
FB_A_D52 AA27 K23 FB_A_CMD19
FBA_D52 FBA_CMD19
FB_A_D53 AA26 M27 FB_A_CMD20
FB_A_D54 W26
FBA_D53
FBA_D54
FBA_CMD20
FBA_CMD21 M26 FB_A_CMD21 GDDR5 design
FB_A_D55 Y25 M25 FB_A_CMD22
FBA_D55 FBA_CMD22
FB_A_D56 R26 K26 FB_A_CMD23
FBA_D56 FBA_CMD23
FB_A_D57 T25 K22 FB_A_CMD24
FBA_D57 FBA_CMD24
FB_A_D58 N27 J23 FB_A_CMD25
FBA_D58 FBA_CMD25
F
FB_A_D59 R27 J25 FB_A_CMD26
FBA_D59 FBA_CMD26
FB_A_D60 V26 J24 FB_A_CMD27
FBA_D60 FBA_CMD27
FB_A_D61 V27 K27 FB_A_CMD28
FBA_D61 FBA_CMD28
FB_A_D62 W27 K25 FB_A_CMD29
FBA_D62 FBA_CMD29
FB_A_D63 W25 J27 FB_A_CMD30
FBA_D63 FBA_CMD30
J26 FB_A_CMD31
FBA_CMD31
<27> FB_A_DBI[3..0] FB_A_DBI0 D19
l
FBA_DQM0
FB_A_DBI1 D14 FBVDDQ_GPU
FBA_DQM1
FB_A_DBI2 C17 FBA_DQM2 GF117/GF119
FB_A_DBI3 C22 +1.35VS_VRAM
<27> FB_A_DBI[7..4] FBA_DQM3 GK208
FB_A_DBI4 P24 FBA_DQM4
FB_A_DBI5 W24 B19
FB_A_DBI6
FBA_DQM5 NC
FBA_CMD32 1.35V
AA25 FBA_DQM6
a
FB_A_DBI7 U25 FBA_CMD34 F22 RV82 1 @ 2 60.4_0402_1%
FBA_DQM7 FBA_DEBUG0
FBA_CMD35 J22 RV83 1 @ 2 60.4_0402_1%
FBA_DEBUG1
<27> FB_A_EDC[3..0] FB_A_EDC0
C E19 FBA_DQS_WP0 C
FB_A_EDC1 C15 FBA_DQS_WP1
FB_A_EDC2 B16 FBA_CLK0 D24 FB_A_CLK0
FBA_DQS_WP2 FB_A_CLK0 <27>
FB_A_EDC3 B22 FBA_CLK0# D25 FB_A_CLK#0
<27> FB_A_EDC[7..4] FBA_DQS_WP3 FB_A_CLK#0 <27>
p
FB_A_EDC4 R25 FBA_CLK1 N22 FB_A_CLK1
FBA_DQS_WP4 FB_A_CLK1 <27>
FB_A_EDC5 W23 FBA_CLK1# M22 FB_A_CLK#1
FBA_DQS_WP5 FB_A_CLK#1 <27>
FB_A_EDC6 AB26 FBA_DQS_WP6
FB_A_EDC7 T26 FBA_DQS_WP7
F19 FBA_WCK01 D18 FB_A_WCK0

FBA_DQS_RN0 FB_A_WCK0 <27>
C14 FBA_WCK01# C18 FB_A_WCK#0
FBA_DQS_RN1 FB_A_WCK#0 <27>
A16 FBA_WCK23 D17 FB_A_WCK1
A22 FBA_WCK23# D16 FB_A_WCK#1
FBA_DQS_RN3 FB_A_WCK#1 <27>
P25 FBA_WCK45 T24 FB_A_WCK2
FB_A_WCK#2
m
W22 FBA_DQS_RN5 FBA_WCK45# U24
FB_A_WCK3 FB_A_WCK#2 <27>
AB27 FBA_DQS_RN6 FBA_WCK67 V24
FB_A_WCK#3 FB_A_WCK3 <27>
T27 FBA_DQS_RN7 FBA_WCK67# V25
FB_A_WCK#3 <27>
GF119
FB_PLLAVDD F16
+1.8VS_PLLAVDD +1.8VS_DGPU
o
NC
FB_PLLAVDD P22
F16 P22 H22 Ball Near GPU DIS@
FB_DLLAVDD H22 LV7 1 2
FB_PLLAVDD
HCB1005KF-300T25_2P
0.1U_0201_10V6K
CV55
0.1U_0201_10V6K
CV52
0.1U_0201_10V6K
CV53
0.1U_0201_10V6K
CV398
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
GF117 1 1 1 SM01000NV00
CV723 DIS@
CV51 @
CV721 @
1 2 1 1
2 2 2
DIS@
DIS@
DIS@
DIS@
C
2 1 2 2
For VRAM DEBUG using
FB_VREF D23
T2401 @ FB_VREF_PROBE
D D
DIS@

NV(5/5)-MEMORY FBA
1 2 3 4 5
5 4 3 2 1
+5VALW +1.8VALW
+1.8VS_DGPU
UV2
+1.8VS to +1.8VS_DGPU 1 14
10U_0402_6.3V6M
VIN1 VOUT1
o
2 13
@ CV324
VIN1 VOUT1 1
1.8VSDGPU_MAIN_EN_R 3 12 CV326 1 2 DIS@ 1200P_0402_50V7K
ON1 CT1
4 11 2
VBIAS GND
DGPU_PWR_EN_18ON 5 10 CV327 1 2 DIS@ 2200P_0402_25V7K
ON2 CT2 +1.8VS_DGPU_AON
D 6 9 D
v
7 VIN2 VOUT2 8
10U_0402_6.3V6M
+1.8VS to +1.8VS_DGPU_AON VIN2 VOUT2
1U_0201_6.3V6M
@ CV325
1
1U_0201_6.3V6M
15
GPAD
1
CV322 DIS@
1U_0201_6.3V6M
CV328 @
CV323 @
G2898KD1U TDFN 14P LOAD SWITCH
2
SA0000BKC00
2
DIS@
<24> DGPU_MAIN_EN
DV9
RV246
1
DIS@
RB751S-40 SOD-523
@
0_0402_5%
1
2 1.8VSDGPU_MAIN_EN_R
+1.8VS_DGPU Discharge
no +1.0VS_DGPU Discharge
e
+3VALW +1.8VS_DGPU +5VALW +1.0VS_DGPU
1
2
DV8 DIS@ CV224 @ RV257 DIS@
RB751S-40 SOD-523 0.1U_0201_10V6K 40.2K_0402_1%
1
2 1 2
RV2008 DIS@ RV2009 DIS@ RV2007 DIS@ RV2006 DIS@
1
100K_0402_5% 10_0603_5% 100K_0402_5% 10_0603_5%
L
RV245 @
2
1K_0402_5%
1 2 DGPU_PWR_EN_18ON
<11,24,34> DGPU_PWR_EN
3
D D
1.8VSDGPU_MAIN_EN#_R 5 QV146B DIS@ 1.0VS_DGPU_EN#_R 5 QV145B DIS@
G 2N7002KDW_SOT363-6 G 2N7002KDW_SOT363-6
C C
SB00000EO00 SB00000EO00
6
S S
DIS@ CV206
D D
0.1U_0201_10V6K
4
2
1.8VSDGPU_MAIN_EN_R 2 QV146A DIS@ 1.0VS_DGPU_EN 2 QV145A DIS@

G <24,45> 1.0VS_DGPU_EN G
RV252 DIS@ 2N7002KDW_SOT363-6 2N7002KDW_SOT363-6
r
100K_0402_1% SB00000EO00 SB00000EO00
2 S S
1
1
F o
B
a l B
mp
A
Compal Secret Data
Title
Size
DGPU_DC/DC Interface
Document Number
LA-G651P
Rev
0.2
A
5 4 3 2 1
5 4 3 2 1
Memory Partition A
UV7 @ MF=0
UV6 @ MF=0 MF=0 MF=1 MF=1 MF=0
MF=0 MF=1 MF=1 MF=0 A4 FB_A_D32

FB_A_EDC4 C2 DQ24 DQ0 A2 FB_A_D33
A4 FB_A_D0 FB_A_EDC5 C13 EDC0 EDC3 DQ25 DQ1 B4 FB_A_D34
FB_A_EDC0 DQ24 DQ0 FB_A_D1 FB_A_EDC6 EDC1 EDC2 DQ26 DQ2 FB_A_D35
o
C2 A2 R13 B2 BYTE4
FB_A_EDC1 C13 EDC0 EDC3 DQ25 DQ1 B4 FB_A_D2 FB_A_EDC7 R2 EDC2 EDC1 DQ27 DQ3 E4 FB_A_D36
FB_A_EDC2 R13 EDC1 EDC2 DQ26 DQ2 B2 FB_A_D3 EDC3 EDC0 DQ28 DQ4 E2 FB_A_D37
FB_A_EDC3 R2 EDC2 EDC1 DQ27 DQ3 E4 FB_A_D4 DQ29 DQ5 F4 FB_A_D38
EDC3 EDC0 DQ28 DQ4 FB_A_D5 BYTE0 DQ30 DQ6 FB_A_D39
E2 D2 F2
DQ29 DQ5 FB_A_D6 <25> FB_A_DBI4 DBI0# DBI3# DQ31 DQ7 FB_A_D40
F4 D13 A11
DQ30 DQ6 FB_A_D7 <25> FB_A_DBI5 DBI1# DBI2# DQ16 DQ8 FB_A_D41
D2 F2 P13 A13
<25> FB_A_DBI0 DBI0# DBI3# DQ31 DQ7 FB_A_D8 <25> FB_A_DBI6 DBI2# DBI1# DQ17 DQ9 FB_A_D42
D13 A11 P2 B11
<25> FB_A_DBI1 DBI1# DBI2# DQ16 DQ8 FB_A_D9 <25> FB_A_DBI7 DBI3# DBI0# DQ18 DQ10 FB_A_D43
D P13 A13 B13 D
<25> FB_A_DBI2 DBI2# DBI1# DQ17 DQ9 FB_A_D10 FB_A_CLK1 DQ19 DQ11 FB_A_D44
v
P2 B11 <25> FB_A_CLK1 J12 E11 BYTE5
<25> FB_A_DBI3 DBI3# DBI0# DQ18 DQ10 FB_A_D11 FB_A_CLK#1 CK DQ20 DQ12 FB_A_D45
B13 BYTE1 <25> FB_A_CLK#1 J11 E13
FB_A_CLK0 J12 DQ19 DQ11 E11 FB_A_D12 FB_A_CMD30 J3 CK# DQ21 DQ13 F11 FB_A_D46
<25> FB_A_CLK0 FB_A_CLK#0 CK DQ20 DQ12 FB_A_D13 CKE# DQ22 DQ14 FB_A_D47
J11 E13 F13
<25> FB_A_CLK#0 FB_A_CMD14 CK# DQ21 DQ13 FB_A_D14 DQ23 DQ15 FB_A_D48
J3 F11 U11
CKE# DQ22 DQ14 F13 FB_A_D15 FB_A_CMD18 H11 DQ8 DQ16 U13 FB_A_D49
DQ23 DQ15 U11 FB_A_D16 FB_A_CMD20 K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 FB_A_D50
FB_A_CMD2 H11 DQ8 DQ16 U13 FB_A_D17 FB_A_CMD19 K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FB_A_D51
FB_A_CMD4 K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 FB_A_D18 FB_A_CMD17 H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 FB_A_D52
FB_A_CMD3 BA1/A5 BA3/A3 DQ10 DQ18 FB_A_D19 BA3/A3 BA1/A5 DQ12 DQ20 FB_A_D53 BYTE6
o
K11 T13 BYTE2 N13
FB_A_CMD1 H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 FB_A_D20 DQ13 DQ21 M11 FB_A_D54
BA3/A3 BA1/A5 DQ12 DQ20 N13 FB_A_D21 FB_A_CMD22 K4 DQ14 DQ22 M13 FB_A_D55
DQ13 DQ21 M11 FB_A_D22 FB_A_CMD27 H5 A8/A7 A10/A0 DQ15 DQ23 U4 FB_A_D56
FB_A_CMD6 K4 DQ14 DQ22 M13 FB_A_D23 FB_A_CMD26 H4 A9/A1 A11/A6 DQ0 DQ24 U2 FB_A_D57
FB_A_CMD11 H5 A8/A7 A10/A0 DQ15 DQ23 U4 FB_A_D24 FB_A_CMD23 K5 A10/A0 A8/A7 DQ1 DQ25 T4 FB_A_D58
FB_A_CMD10 H4 A9/A1 A11/A6 DQ0 DQ24 U2 FB_A_D25 FB_A_CMD25 J5 A11/A6 A9/A1 DQ2 DQ26 T2 FB_A_D59
FB_A_CMD7 K5 A10/A0 A8/A7 DQ1 DQ25 T4 FB_A_D26 A12/RFU/NC DQ3 DQ27 N4 FB_A_D60
FB_A_CMD9 A11/A6 A9/A1 DQ2 DQ26 FB_A_D27 DQ4 DQ28 FB_A_D61 BYTE7
J5 T2 BYTE3 A5 N2
A12/RFU/NC DQ3 DQ27 FB_A_D28 VPP/NC DQ5 DQ29 FB_A_D62
n
N4 U5 M4
A5 DQ4 DQ28 N2 FB_A_D29 VPP/NC DQ6 DQ30 M2 FB_A_D63
U5 VPP/NC DQ5 DQ29 M4 FB_A_D30 DQ7 DQ31
VPP/NC DQ6 DQ30 M2 FB_A_D31 RV117 DIS@ 2 1 1K_0402_1% J1 +1.35VS_VRAM
DQ7 DQ31 RV119 DIS@ 2 1 1K_0402_1% J10 MF
RV116 DIS@ 2 1 1K_0402_1% J1 +1.35VS_VRAM RV121 DIS@ 2 1 121_0402_1% J13 SEN B1
RV118 DIS@ 2 1 1K_0402_1% J10 MF ZQ VDDQ D1
RV120 DIS@ 2 1 121_0402_1% J13 SEN B1 VDDQ F1
ZQ VDDQ FB_A_CMD24 VDDQ
e
D1 J4 M1
VDDQ F1 FB_A_CMD28 G3 ABI# VDDQ P1
FB_A_CMD8 J4 VDDQ M1 FB_A_CMD16 G12 RAS# CAS# VDDQ T1
FB_A_CMD12 G3 ABI# VDDQ P1 FB_A_CMD31 L3 CS# WE# VDDQ G2
FB_A_CMD0 G12 RAS# CAS# VDDQ T1 FB_A_CMD21 L12 CAS# RAS# VDDQ L2
FB_A_CMD15 L3 CS# WE# VDDQ G2 WE# CS# VDDQ B3
FB_A_CMD5 L12 CAS# RAS# VDDQ L2 VDDQ D3
WE# CS# VDDQ B3 VDDQ F3
VDDQ D3 FB_A_WCK#2 D5 VDDQ H3
VDDQ <25> FB_A_WCK#2 FB_A_WCK2 WCK01# WCK23# VDDQ
F3 D4 K3
FB_A_WCK#0 VDDQ <25> FB_A_WCK2 WCK01 WCK23 VDDQ
D5 H3 M3
<25> FB_A_WCK#0 FB_A_WCK0 WCK01# WCK23# VDDQ FB_A_WCK#3 VDDQ
D4 K3 P5 P3
L
<25> FB_A_WCK0 WCK01 WCK23 VDDQ <25> FB_A_WCK#3 FB_A_WCK3 WCK23# WCK01# VDDQ
M3 P4 T3
FB_A_WCK#1 VDDQ <25> FB_A_WCK3 WCK23 WCK01 VDDQ
P5 P3 E5
<25> FB_A_WCK#1 FB_A_WCK1 WCK23# WCK01# VDDQ VDDQ
P4 T3 N5
FB_A_CMD[0..15] <25> FB_A_WCK1 WCK23 WCK01 VDDQ VDDQ
E5 A10 E10
<25> FB_A_CMD[0..15] VDDQ VREFD VDDQ
N5 U10 N10
FB_A_CMD[16..31] A10 VDDQ E10 +FBA_VREFC0 J14 VREFD VDDQ B12
C <25> FB_A_CMD[16..31] VREFD VDDQ VREFC VDDQ C
U10 N10 D12
+FBA_VREFC0 J14 VREFD VDDQ B12 VDDQ F12
FB_A_D[0..63] VREFC VDDQ VDDQ
D12 H12
<25> FB_A_D[0..63] VDDQ FB_A_CMD29 VDDQ
F12 J2 K12
FB_A_EDC[7..0]
r
VDDQ H12 RESET# VDDQ M12
<25> FB_A_EDC[7..0] FB_A_CMD13 VDDQ VDDQ
J2 K12 P12
RESET# VDDQ M12 VDDQ T12
VDDQ P12 VDDQ G13
VDDQ T12 H1 VDDQ L13
VDDQ G13 K1 VSS VDDQ B14
H1 VDDQ L13 B5 VSS VDDQ D14
K1 VSS VDDQ B14 G5 VSS VDDQ F14
RV1 DIS@ RV2 DIS@ B5 VSS VDDQ D14 L5 VSS VDDQ M14
VSS VDDQ VSS VDDQ
o
40.2_0402_1% 40.2_0402_1% G5 F14 T5 P14
FB_A_CLK0 1 2 1 2 FB_A_CLK#0 L5 VSS VDDQ M14 B10 VSS VDDQ T14
T5 VSS VDDQ P14 D10 VSS VDDQ
B10 VSS VDDQ T14 G10 VSS
1 VSS VDDQ VSS
CV4 DIS@ D10 L10 A1
Near to UV6 0.01U_0402_16V7K G10 VSS
VSS
P10 VSS
VSS
VSSQ
VSSQ
C1
L10 A1 T10 E1
2 P10 VSS VSSQ C1 H14 VSS VSSQ N1
T10 VSS VSSQ E1 K14 VSS VSSQ R1
H14 VSS VSSQ N1 +1.35VS_VRAM VSS VSSQ U1
VSS VSSQ VSSQ
F
K14 R1 H2
+1.35VS_VRAM VSS VSSQ U1 G1 VSSQ K2
VSSQ H2 L1 VDD VSSQ A3
RV3 DIS@ RV4 DIS@ G1 VSSQ K2 G4 VDD VSSQ C3
40.2_0402_1% 40.2_0402_1% L1 VDD VSSQ A3 L4 VDD VSSQ E3
FB_A_CLK1 1 2 1 2 FB_A_CLK#1 G4 VDD VSSQ C3 C5 VDD VSSQ N3
L4 VDD VSSQ E3 R5 VDD VSSQ R3
C5 VDD VSSQ N3 C10 VDD VSSQ U3
1 VDD VSSQ VDD VSSQ
CV5 DIS@ R5 R3 R10 C4
Near to UV7 0.01U_0402_16V7K C10 VDD VSSQ U3 D11 VDD VSSQ R4
l
R10 VDD VSSQ C4 G11 VDD VSSQ F5
2 D11 VDD VSSQ R4 L11 VDD VSSQ M5
G11 VDD VSSQ F5 P11 VDD VSSQ F10
L11 VDD VSSQ M5 G14 VDD VSSQ M10
P11 VDD VSSQ F10 L14 VDD VSSQ C11
G14 VDD VSSQ M10 VDD VSSQ R11
L14 VDD VSSQ C11 VSSQ A12
VDD VSSQ R11 VSSQ C12
a
VSSQ A12 VSSQ E12
VSSQ C12 VSSQ N12
VSSQ E12 VSSQ R12
VSSQ N12 170-BALL VSSQ U12
B B
VSSQ R12 VSSQ H13
170-BALL VSSQ U12 SGRAM GDDR5 VSSQ K13
+1.35VS_VRAM VSSQ H13 VSSQ A14
SGRAM GDDR5 VSSQ K13 VSSQ C14
VSSQ A14 VSSQ E14
p
VSSQ VSSQ
1
C14 N14
RV125 DIS@ VSSQ E14 VSSQ R14
549_0402_1% VSSQ N14 VSSQ U14
VSSQ R14 VSSQ
VSSQ U14 K4G80325FB-HC03_FBGA170~D
2
VSSQ
RV200 1 DIS@ 2 931_0402_1% +FBA_VREFC0 K4G80325FB-HC03_FBGA170~D
W=16mils
1
D
1.33K_0402_1%
RV127
820P_0402_25V7
CV158
820P_0402_25V7
CV159
1 1
2 QV50 DIS@ +1.35VS_VRAM Near VRAM Near ball +1.35VS_VRAM Near VRAM Near ball
<24> MEM_VREF
G L2N7002WT1G_SC-70-3
S
m
3
2 2
DIS@
DIS@
DIS@
2
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
CV603
CV604
CV605
CV606
CV607
CV608
CV703
CV704
CV705
CV706
CV707
CV708
DIS@
DIS@
DIS@
DIS@
2 2 1 1 1 1 1 1 2 2 1 1 1 1 1 1
1 1 2 2 2 2 2 2 1 1 2 2 2 2 2 2
Place near pin J14 of each vram
CV601
CV602
CV701
CV702
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
o +1.35VS_VRAM Near ball +1.35VS_VRAM Near ball
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
C
CV609 DIS@
CV610 DIS@
CV611 DIS@
CV612 DIS@
CV613 DIS@
CV614 DIS@
CV615 DIS@
CV616 DIS@
CV617 DIS@
CV618 DIS@
CV709 DIS@
CV710 DIS@
CV711 DIS@
CV712 DIS@
CV713 DIS@
CV714 DIS@
CV715 DIS@
CV716 DIS@
CV717 DIS@
CV718 DIS@
1
1
2
2
A A

N16P_GDDR5_A
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
5 4 3 2 1
5 4 3 2 1
LCD Power Circuit
W=60mils
o
+3VS +LCDVDD_CONN
W=60mils U5 R3208
5 1 +LCDVDD 1 2
IN OUT
v
D D
1U_0201_6.3V6M
C96
0_0805_5%
10P_0402_50V8J
1 1
4.7U_0402_6.3V6M
GND
C128
1
C1220
4 3
<6> PCH_ENVDD EN OC
RF@
EM5203AJ-20 SOT23 5P 2 2
2
SA00008R900
Close to R3208
B+ R3213 1 2 0_0805_5%
no
+LEDVDD
C133
4.7U_0603_25V6K
C53
e
10P_0402_50V8J
1 1
RF@
2 2
JeDP1
L
Close to JEDP1 1
2 1
3 2
4 3
C 5 4 C
6 5
DMIC_CLK EDP_TXN1_C 6
r
C139 1 2 0.1U_0201_10V6K 7
<6> EDP_TXN1 EDP_TXP1_C 7
C138 1 2 0.1U_0201_10V6K 8
<6> EDP_TXP1 8
9
10P_0402_50V8J
C137 1 2 0.1U_0201_10V6K EDP_TXN0_C 10 9

@RF@
1 <6> EDP_TXN0 10
C136 1 2 0.1U_0201_10V6K EDP_TXP0_C 11
C1211
<6> EDP_TXP0 11
12
EDP_AUXP_C 12
o
C135 1 2 0.1U_0201_10V6K 13
2 <6> EDP_AUXP EDP_AUXN_C 13
eDP C134 1 2 0.1U_0201_10V6K 14
EDP_HPD_R <6> EDP_AUXN 14
<6> EDP_HPD R126 1 @ 2 0_0402_5% 15
16 15
17 16
+LCDVDD_CONN W=60mils 18 17
EDP_HPD_R 19 18
F
20 19
<34> BKOFF# 20
21
<6> INVPW M 21
Close to JEDP1 22
23 22
<12> USB20_N5 23
Camera 24
<12> USB20_P5 24
25
l
26 25 31
<33> DMIC_CLK 26 G1
DMIC 27 32
<33> DMIC_DAT 27 G2
+3VS 28 33
29 28 G3 34
30 29 G4 35
a
30 G5
CVILU_CVS3302M1RE-NH
B B
mp Place close to JeDP1
USB20_N5 3
I/O2
ESD@
I/O4
DA5
6 DMIC_DAT
o
2 5
GND VDD
DMIC_CLK 1 4 USB20_P5
I/O1 I/O3
C
RC494 1 2 100K_0402_5%
<6,34> ENBKL EDP_HPD RC495 L30ESDL5V0C6-4_SOT23-6
1 2 100K_0402_5%
PCH_ENVDD RC496 1 2 100K_0402_5%
A A

eDP / Camera
5 4 3 2 1
5 4 3 2 1
HDMI
EMI
EMI
o
CH13 1 2 0.1U_0201_10V6K HDMI_CLKP RH11 1 EMI@ 2 8.2_0402_1% HDMI_L_CLKP HDMI_L_CLKP RH12 1 EMI@ 2 150_0402_1% HDMI_L_CLKN
<6> CPU_DP1_P3
CH14 1 2 0.1U_0201_10V6K HDMI_CLKN RH15 1 EMI@ 2 8.2_0402_1% HDMI_L_CLKN HDMI_L_TX_P0 RH13 1 EMI@ 2 150_0402_1% HDMI_L_TX_N0
<6> CPU_DP1_N3
D D
v
HDMI_L_TX_P1 RH14 1 EMI@ 2 150_0402_1% HDMI_L_TX_N1
HDMI_L_TX_P2 RH16 1 EMI@ 2 150_0402_1% HDMI_L_TX_N2
For HDMI
o
CH15 1 2 0.1U_0201_10V6K HDMI_TX_P0 RH17 1 EMI@ 2 8.2_0402_1% HDMI_L_TX_P0
<6> CPU_DP1_P2 +5VS +5V_Display
CH16 1 2 0.1U_0201_10V6K HDMI_TX_N0 RH18 1 EMI@ 2 8.2_0402_1% HDMI_L_TX_N0 UH11 Close to UH11
<6> CPU_DP1_N2
3
W=40mils
OUT
n
1
CH11
CH21
1 1
10P_0402_50V8J
0.1U_0201_10V6K
IN
1
@ 2
CH12 GND
RF@
0.1U_0201_10V6K 2 2
2 AP2330W-7_SC59-3
e
CH17 1 2 0.1U_0201_10V6K HDMI_TX_P1 RH19 1 EMI@ 2 8.2_0402_1% HDMI_L_TX_P1
<6> CPU_DP1_P1 SA00004ZA00
CH18 1 2 0.1U_0201_10V6K HDMI_TX_N1 RH20 1 EMI@ 2 8.2_0402_1% HDMI_L_TX_N1

<6> CPU_DP1_N1
+3VS
C <6> CPU_DP1_P0 CH19 1 2 0.1U_0201_10V6K HDMI_TX_P2 RH21 1 EMI@ 2 8.2_0402_1% HDMI_L_TX_P2
L C
1
CH20 1 2 0.1U_0201_10V6K HDMI_TX_N2 RH22 1 EMI@ 2 8.2_0402_1% HDMI_L_TX_N2 RH23
<6> CPU_DP1_N0
r
1M_0402_5%
2
G
2
JHDMI1
1 6 HDMI_HPD 19
Near JHDMI1
S
<6> CPU_DP1_HPD HP_DET
D
+5V_Display
18
+5V
o
1
17
QH14A RH24 HDMI_CTRL_DAT 16 DDC/CEC_GND
2N7002KDW_SOT363-6 20K_0402_5% HDMI_CTRL_CLK 15 SDA
RC498 1 2 470_0201_5% 14 SCL
RC499 1 2 470_0201_5% 13 Reserved
2
RC500 1 2 470_0201_5% HDMI_L_CLKN 12 CEC
RC501 1 2 470_0201_5% 11 CK- 23
HDMI_L_CLKP 10 CK_shield GND 22
F
HDMI_L_TX_N0 9 CK+ GND 21
8 D0- GND 20
HDMI_L_TX_P0 7 D0_shield GND
HDMI_L_TX_N1 6 D0+
RC502 1 2 470_0201_5% 5 D1-
RC503 1 2 470_0201_5% HDMI_L_TX_P1 4 D1_shield
RC504 1 2 470_0201_5% HDMI_L_TX_N2 3 D1+
RC505 1 2 470_0201_5% 2 D2-
l
HDMI_L_TX_P2 1 D2_shield
+3VS D2+
LOTES_AHDM0064-P001A
3
D DC232007B00
QH14B 5 ME@
2N7002KDW_SOT363-6 G
a
S
4
B B
CPU_DP1_CTRL_CLK
CH22
1
10P_0402_50V8J
@RF@
2
+3VS +3VS +5V_Display
ESD
m
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
1
1
RH26
RH25
RH27
RH28
QH15A
2N7002KDW_SOT363-6 DH11 @ESD@ DH12 @ESD@ DH13 @ESD@
2
HDMI_CTRL_DAT 9 HDMI_CTRL_DAT HDMI_L_TX_N1 HDMI_L_TX_N1 HDMI_L_TX_N0 HDMI_L_TX_N0

10 1 1 9 10 1 1 9 10 1 1
o
2
HDMI_CTRL_CLK HDMI_CTRL_CLK 8 HDMI_CTRL_CLK HDMI_L_TX_P1 HDMI_L_TX_P1 HDMI_L_TX_P0 HDMI_L_TX_P0

<6> CPU_DP1_CTRL_CLK
1 6 9 2 2 8 9 2 2 8 9 2 2
5
HDMI_HPD HDMI_HPD HDMI_L_TX_N2 HDMI_L_TX_N2 HDMI_L_CLKN HDMI_L_CLKN

7 7 4 4 7 7 4 4 7 7 4 4
HDMI_CTRL_DAT +5V_Display +5V_Display HDMI_L_TX_P2 HDMI_L_TX_P2 HDMI_L_CLKP HDMI_L_CLKP
<6> CPU_DP1_CTRL_DATA
4 3 6 6 5 5 6 6 5 5 6 6 5 5
QH15B 3 3 3 3 3 3
2N7002KDW_SOT363-6
8 8 8
C
L05ESDL5V0NA-4_SLP2510P8-10-9 L05ESDL5V0NA-4_SLP2510P8-10-9 L05ESDL5V0NA-4_SLP2510P8-10-9
A A

HDMI
Custom 0.2
5 4 3 2 1
5 4 3 2 1
UCM trace
VBUS Discharge
EC_SMB_DA2_R R3239 1 2 0_0402_5% +USBC_VBUS
I2C_1_SDA <11>
R3240 1 @ 2 0_0402_5% EC_SMB_DA2 <8,24,34,36>
1
EC_SMB_CK2_R R3241 1 2 0_0402_5% R168
I2C_1_SCL <11>
@ 100_1206_5%
R3242 1 @ 2 0_0402_5%
EC_SMB_CK2 <8,24,34,36>
2
D D
1
D
VBUS_DSCHG 2 Q9 @
G IRLML2030TRPBF_SOT23-3
SB00001J300
1
S
3
R3203
100K_0402_5%
@
2
+5VALW
n
R3234 1 @ 2 0_0603_5%
+LDO_3V3_5455 +5VALW
10U_0402_6.3V6M
10U_0402_6.3V6M
1 1
C158
C310
@ @ +USBC_VBUS
Close to Pin10 Dead battery function Cfig. pin.
2 2
e
Tie to GND to disable dead battery ‘ Rd’ .
1
MUX
1
Floating to enable dead battery ‘ Rd’ R169 R221 @
R303
590K_0402_1%
200K_0402_1% 10K_0402_5%
+LDO_3V3_5455 U16 DB_CFG R157 1 2 0_0402_5% SD034590380
2
+3.3V_IN_5455
2
10 Realtek
VCON_IN 20 C168 1 2 220P_0402_50V8J VMON_5455 LOC_PWR_MON
25
RTS5455 DB_CFG
C167 5V_IN 9
L
PD_CC1 <31>
1
2 1 26 CC1 11
LDO_3V3 CC2 PD_CC2 <31>
2
C169 1 2 220P_0402_50V8J R3202
4.7U_0402_6.3V6M R302
USB3_CRX_C_MTX_P3 10K_0402_1%
<12> USB3_CRX_MTX_P3 C170 1 2 0.22U_0201_6.3V6M 39 ISP Channel via CCs R222 10K_0402_5%
C171 1 2 0.22U_0201_6.3V6M USB3_CRX_C_MTX_N3 40 SSRX_1P/2N 10K_0402_5%
<12> USB3_CRX_MTX_N3
2
SSRX_1N/2P 15 USB3_DP2_MTX_DRX_P2 C2193 1 2 0.1U_0201_10V6K
USB3_DP2_MTX_C_DRX_P2 <31>
1
C USB3_CTX_C_MRX_P3 C_TX2_1P/2N USB3_DP2_MTX_DRX_N2 C
From USB3 C173 1 2 0.22U_0201_6.3V6M 41 14 C2194 1 2 0.1U_0201_10V6K
<12> USB3_CTX_MRX_P3 USB3_CTX_C_MRX_N3 SSTX_1P/2N C_TX2_1N/2P USB3_DP2_MTX_C_DRX_N2 <31>
C175 1 2 0.22U_0201_6.3V6M 42
<12> USB3_CTX_MRX_N3 SSTX_1N/2P
19 USB3_DP2_MRX_DTX_P2 C2204 1 2 0.33U_0201_6.3V6M
r
CPU_DP2_P0_C C_RX2_1P/2N USB3_DP2_MRX_DTX_N2 USB3_DP2_MRX_C_DTX_P2 <31>
C300 1 2 0.1U_0201_10V6K 35 18 C2203 1 2 0.33U_0201_6.3V6M USB3_DP2_MRX_C_DTX_N2 <31>
<6> CPU_DP2_P0 CPU_DP2_N0_C DP0_1P/2N C_RX2_1N/2P
C301 1 2 0.1U_0201_10V6K 36 10Gps 3:2 MUX 0314_Add
<6> CPU_DP2_N0 DP0_1N/2P Connect 'LOC_PWR' net to local power for F/W to
CPU_DP2_P1_C USB3_DP2_MTX_DRX_P1 decide if C port can become provider via PR_SWAP.
C302 1 2 0.1U_0201_10V6K 43 13 C2195 1 2 0.1U_0201_10V6K
USB3_DP2_MTX_C_DRX_P1 <31> Leave floating if no local power exists in the
<6> CPU_DP2_P1 CPU_DP2_N1_C DP1_1P/2N C_TX1_1P/2N USB3_DP2_MTX_DRX_N1
C303 1 2 0.1U_0201_10V6K 44 12 C2196 1 2 0.1U_0201_10V6K USB3_DP2_MTX_C_DRX_N1 <31> system or in the application that 545x can only
<6> CPU_DP2_N1 DP1_1N/2P C_TX1_1N/2P
From DP C304 1 2 0.1U_0201_10V6K CPU_DP2_P2_C 45
be powered on by local power.
<6> CPU_DP2_P2 CPU_DP2_N2_C DP2_1P/2N USB3_DP2_MRX_DTX_P1
C305 1 2 0.1U_0201_10V6K 46 17 C2202 1 2 0.33U_0201_6.3V6M USB3_DP2_MRX_C_DTX_P1 <31>
<6> CPU_DP2_N2
o
DP2_1N/2P C_RX1_1P/2N 16 USB3_DP2_MRX_DTX_N1 C2201 1 2 0.33U_0201_6.3V6M
CPU_DP2_P3_C C_RX1_1N/2P USB3_DP2_MRX_C_DTX_N1 <31>
C306 1 2 0.1U_0201_10V6K 37
<6> CPU_DP2_P3 CPU_DP2_N3_C DP3_1P/2N
C307 1 2 0.1U_0201_10V6K 38
<6> CPU_DP2_N3 DP3_1N/2P
DP2_AUXP_SBU1
C2179 1 2 0.1U_0201_10V6K CPU_DP2_AUXP_C 1 3
<6> CPU_DP2_AUXP CPU_DP2_AUXN_C AUX_P/MGPIO4 SBU1/MGPIO6 DP2_AUXP_SBU1 <31>
<6> CPU_DP2_AUXN C2180 1 2 0.1U_0201_10V6K 2 4 DP2_AUXN_SBU2 <31> DP2_AUXN_SBU2
AUX_N/MGPIO5 Low Speed MUX SBU2/MGPIO7
TO SOC 34
F
<6> CPU_DP2_HPD HPD
1
R163 R165
1
5 7 1M_0402_5% 1M_0402_5%
R171 H_DP/DCI_DATA/MGPIO2 C_DP/BB_DP VBUS_DSCHG
6 BC1.2 Switch 8 @ @
100K_0402_5% H_DM/DCI_CLK/MGPIO3 C_DM/BB_DM
2
EC_SMB_DA2_R 31 30
EC_SMB_CK2_R 32 SM_SDA/GPIO6 I2C_SCL/GPIO7 29
2
33 SM_SCL/GPIO5 I2C_SDA/GPIO8 28
<14,34> PD_INT# SM_INT/GPIO4 I2C_INT/GPIO9 27
l
I2C_EN/GPIO10 USBC_EN <31>
24 22
REXT MGPIO8/ IMON VMON_5455
21
MGPIO9/ VMON LOC_PWR_MON
47 23
1
R164 E-PAD MGPIO10/ LOC_PWR_MON

6.2K_0402_1%
a
RTS5455-GR_QFN46_6P5X4P5
2
B B
+LDO_3V3_5455
100K_0402_5%
R113 2 1
@
R3228 1 2 220K_0201_1%
USB3_DP2_MRX_C_DTX_P2
USB3_DP2_MRX_C_DTX_N2
CPU_DP2_AUXN_C
@
R3229 1 2 220K_0201_1%
m
CPU_DP2_AUXP_C
R3204
2
@
R3232 1 2 220K_0201_1%
+LDO_3V3_5455 USB3_DP2_MRX_C_DTX_P1
USB3_DP2_MRX_C_DTX_N1
@
R3233 1 2 220K_0201_1%
1
100K_0402_5%
R3216 1 @ 2 750k_0201_1%
USB3_CRX_C_MTX_P3
USB3_CRX_C_MTX_N3
R3217 1 @ 2 750k_0201_1%
R3219 1 @ 2 750k_0201_1%
USB3_CTX_C_MRX_P3
USB3_CTX_C_MRX_N3
R3218 1 @ 2 750k_0201_1%
R3221 1 2 750k_0201_1%
C
@
CPU_DP2_P0_C
CPU_DP2_N0_C
R3220 1 @ 2 750k_0201_1%
A A
R3223 1 @ 2 750k_0201_1%
CPU_DP2_P1_C
CPU_DP2_N1_C
R3222 1 @ 2 750k_0201_1%
R3225 1 @ 2 750k_0201_1%
CPU_DP2_P2_C
CPU_DP2_N2_C
R3224 1 @ 2 750k_0201_1%
R3227 1 @ 2 750k_0201_1%
CPU_DP2_P3_C
CPU_DP2_N3_C
R3226 1 @ 2 750k_0201_1%
2018/2/5
Compal Secret Data
2019/2/5 Title
Size
Type-C_RTS5455
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
5 4 3 2 1
5 4 3 2 1
+USBC_VBUS +USBC_VBUS L5 EMI@

1 2 USB20_P3_R
<12> USB20_P3 1 2
JUSBC1 4 3 USB20_N3_R
<12> USB20_N3 4 3
A1 B12
o
GND_A1 GND_B12 DLM0NSN900HY2D_4P
<30> USB3_DP2_MTX_C_DRX_P1 A2 B11 USB3_DP2_MRX_C_DTX_P1 <30>
A3 TX1+ RX1+ B10
<30> USB3_DP2_MTX_C_DRX_N1 TX1- RX1- USB3_DP2_MRX_C_DTX_N1 <30>
@ C311 1 2 0.47U_0402_25V6K A4 B9 @ C312 1 2 0.47U_0402_25V6K
VBUS_A4 VBUS_B9 D44 ESD@
A5 B8 USB3_DP2_MTX_C_DRX_P2 1 1 10 9 USB3_DP2_MTX_C_DRX_P2
D <30> PD_CC1 CC1 SBU2 DP2_AUXN_SBU2 <30> D
3
USB20_P3_R A6 B7 USB20_N3_R USB3_DP2_MTX_C_DRX_N2 2 2 9 8 USB3_DP2_MTX_C_DRX_N2
USB20_N3_R A7 D+_A6 D-_B7 B6 USB20_P3_R DT245
Bottom
D-_A7 D+_B6 USB3_DP2_MTX_C_DRX_P1 4 4 7 USB3_DP2_MTX_C_DRX_P1
TOP
7
<30> DP2_AUXP_SBU1 A8 B5 PD_CC2 <30>

SBU1 CC2 ESD@ USB3_DP2_MTX_C_DRX_N1 5 5 6 USB3_DP2_MTX_C_DRX_N1
6
C313 1 2 0.47U_0402_25V6K A9 B4 C314 1 2 0.47U_0402_25V6K L30ESD24VC3-2_SOT23-3
1
@ VBUS_A9 VBUS_B4 @ 3 3
o
A10 B3
<30> USB3_DP2_MRX_C_DTX_N2 RX2- TX2- USB3_DP2_MTX_C_DRX_N2 <30>
<30> USB3_DP2_MRX_C_DTX_P2 A11 B2 USB3_DP2_MTX_C_DRX_P2 <30>
8
RX2+ TX2+
A12 B1
GND_A12 GND_B1 AZ1045-04F_DFN2510P10E-10-9
SC300001Y00
1 4
GND1 GND4
n
2 5
3 GND2 GND5 6 D46 ESD@
GND3 GND6 USB3_DP2_MRX_C_DTX_P2 1 1 9 USB3_DP2_MRX_C_DTX_P2
10
USB3_DP2_MRX_C_DTX_N2 2 2 9 8 USB3_DP2_MRX_C_DTX_N2
JAE_DX07SL24JJ2
USB3_DP2_MRX_C_DTX_P1 4 4 7 USB3_DP2_MRX_C_DTX_P1
ME@ 7
e
USB3_DP2_MRX_C_DTX_N1 5 5 6 6 USB3_DP2_MRX_C_DTX_N1
3 3
AZ1045-04F_DFN2510P10E-10-9
L
SC300001Y00
ESD for USBC1 Lines and Control

lines
C C
o r USB20_P3_R 3
1
I/O2
GND
I/O1
ESD@
I/O4
VDD
I/O3
D45
6
4
+5VALW
USB20_N3_R
F
L30ESDL5V0C6-4_SOT23-6
l
+5VALW ILIM_R
+USBC_VBUS
1
3A/Active High R3243
a
W=80mils 2.2K_0402_5%
D52
U65
6 1 DP2_AUXP_SBU1 1 1 9 DP2_AUXP_SBU1
10
2
IN OUT
B
R3245 1 2 0_0402_5% DP2_AUXN_SBU2 2 2 9 8 DP2_AUXN_SBU2 B
ILIM_R 5 2
1 1
10P_0402_50V8J
0.1U_0201_10V6K
SET GND PD_CC1 4 4 7 PD_CC1

C2177 RF@
1 1 1 1 7
470P_0402_50V7K
22U_0603_6.3V6M
22U_0603_6.3V6M
100U_1206_6.3V6M
1
D
p
1
4 3 2 PD_CC2 5 5 6 PD_CC2
C2175
6
2 2 <30> USBC_EN EN FLAG ILIM_select <34>
R3244 G
C2174
AP22615AWU-7 TSOT26 2 2 2 2 3 3
C2176
C2207
C2208
2.2K_0402_5%
1
@ S
3
Q145 @ 8
2
R2029
100K_0402_5% 2N7002KW_SOT323-3
AZ1045-04F_DFN2510P10E-10-9
2
ESD@
ILIM = 6800/ RSET SC300001Y00
m
ILIM_select = L , ILIM = 3 A
ILIM_select = F , ILIM = 1.5 A
Issued Date
Compal Secret Data
Deciphered Date
Title
Size
Type-C_RTS5455_CONN
Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
Date: Friday, May 18, 2018
LA-G651P
Sheet 31 of 52
5 4 3 2 1
A B C D E F G H
SSD(Key M) +3VS
100 MIL
+3VS_SSD
+3VS_SSD
0.01U_0402_16V7K
0.1U_0201_10V6K
R3210 1 2 0_0805_5%
10U_0402_6.3V6M
10U_0402_6.3V6M
1 1
1 1
C92
10P_0402_50V8J
1
C1176
C1177
C1178
C1179
o
@ 2 2
RF@
2 2
2
@
JSSD1
1 2
Near JSSD1 3 GND 3.3VAUX 4
5 GND 3.3VAUX 6
1 <12> PCIE_CRX_DTX_N9 PERn3 N/C 1
7 8
v
<12> PCIE_CRX_DTX_P9 PERp3 N/C
9 10
C2182 1 2 0.22U_0201_6.3V6MPCIE_CTX_C_DRX_N9 11 GND DAS/DSS# 12
<12> PCIE_CTX_DRX_N9 PETn3 3.3VAUX
C2181 1 2 0.22U_0201_6.3V6MPCIE_CTX_C_DRX_P9 13 14
<12> PCIE_CTX_DRX_P9 PETp3 3.3VAUX
15 16
17 GND 3.3VAUX 18
<12> PCIE_CRX_DTX_N10 PERn2 3.3VAUX
19 20
<12> PCIE_CRX_DTX_P10 PERp2 N/C
21 22
C2185 1 2 0.22U_0201_6.3V6MPCIE_CTX_C_DRX_N10 23 GND N/C 24
<12> PCIE_CTX_DRX_N10 PETn2 N/C
2 0.22U_0201_6.3V6MPCIE_CTX_C_DRX_P10
o
C2186 1 25 26
<12> PCIE_CTX_DRX_P10 PETp2 N/C
27 28
29 GND N/C 30
SSD PCIE <12> PCIE_CRX_DTX_N11 PERn1 N/C
31 32
33 PERp1 N/C 34
<12> PCIE_CTX_DRX_N11 PETn1 N/C
C2184 1 2 0.22U_0201_6.3V6MPCIE_CTX_C_DRX_P11 37 38
<12> PCIE_CTX_DRX_P11 PETp1 DEVSLP
39 40
41 GND N/C 42
n
<12> PCIE_CRX_DTX_N12 PERn0/SATA B+ N/C
43 44
<12> PCIE_CRX_DTX_P12 PERp0/SATA B- N/C
45 46
<12> PCIE_CTX_DRX_N12
C2187 1 2 0.22U_0201_6.3V6MPCIE_CTX_C_DRX_P12 49 PETn0/SATA A- N/C 50 PCI_RST#
<12> PCIE_CTX_DRX_P12 PETp0/SATA A+ PERST#
51 52
GND CLKREQ# CLKREQ_PCIE#4 <10>
53 54
<10> CLK_PCIE_N4 REFCLKn PEWake#
55 56
<10> CLK_PCIE_P4 REFCLKp N/C
e
57 58
GND N/C
67 68
69 N/C SUSCLK 70
71 PEDET 3.3VAUX 72
73 GND 3.3VAUX 74
75 GND 3.3VAUX
GND
77 76
MTG77 MTG76
L
LOTES_APCI0146-P008A
SP07001GE00
ME@
2 2
NGFF WLAN /BT(Key E) +3VS_WLAN +3VS_WLAN
r NGFF Wireless LAN / BT (Key E) [PCIE+USB/CNVi]

@RF@ CC3870
o
10P_0402_50V8J
10P_0402_50V8J
0.01U_0402_16V7K
CC3871 RF@
1 1 1
CW7 CNVi@
1
CW8
1
CW1
1
CW2
1 1 For Power consumption Measurement
CW6 CNVi@ 0.1U_0201_10V6K 0.01U_0402_16V7K 0.1U_0201_10V6K
CNVi@ CW3
4.7U_0402_6.3V6M CNVi@ 4.7U_0402_6.3V6M CNVi@ +3VS +3VS_WLAN
2 2 2 2 2 2 2 2
NONCNVi@
RW46 1 2 0_0603_5%
Close to KEY E pin72,74 Close to KEY E pin2,4
F
+3VALW
422.18mA
Jefferson Peak:1360mA@peak current
Thunder_Peak_2:1100mA@peak current RW47 1 @ 2 0_0603_5%
+3VS_WLAN The connectivity module power supply pin shall be

CNVi Module PIN Def i ne connected directly to thr rail DSW.
JWLAN1 From
GND 1 2 +3P3A 567240_Intel_Wireless_AC_9560_Jefferson_Peak_EPS_Rev1.1
GND_1 3.3VAUX_2
USB_D+ 3 4
l
<12> USB20_P10 USB_D+ 3.3VAUX_4 +3P3A
BT <12> USB20_N10 USB_D- 5 USB_D- LED1#
6 LED#1
GND 7 8 PCM_CLK
CNV_CRX_DTX_N1 RW6 1 2 0_0201_5% CNV_CRX_R_DTX_N1 GND_7 PCM_CLK CNV_RF_RESET#_R
<9> CNV_CRX_DTX_N1 CNV_CRX_DTX_P1
@ WGR_D1N 9 10 RF_RESET_B RW7 1 CNVi@ 2 33_0201_5% CNV_RF_RESET# <9>
<9> CNV_CRX_DTX_P1 RW8 1 @ 2 0_0201_5% CNV_CRX_R_DTX_P1 WGR_D1P 11
SDIO_CLK PCM_SYNC 12 PCM_IN
SDIO_CMD PCM_OUT CLKREQ_CNV#_R
CNV_CRX_DTX_N0 CNV_CRX_R_DTX_N0 GND 13 SDIO_DAT0 PCM_IN
14 CLKREQ0 RW9 1 CNVi@ 2 33_0201_5%
CLKREQ_CNV# <9>
<9> CNV_CRX_DTX_N0 RW10 1 @ 2 0_0201_5% WGR_D0N 15 16 LED2#
CNV_CRX_DTX_P0 RW11 1 2 0_0201_5% CNV_CRX_R_DTX_P0 SDIO_DAT1 LED2#
<9> CNV_CRX_DTX_P0 @ WGR_D0P 17 18 GND/LNA_EN
a
SDIO_DAT2 GND_18
CLK_CNV_CRX_DTX_N GND 19 20 UART WAKE# CNV_BRI_CRX_R_DTX RW44 1 NONCNVi@
2 0_0201_5%
UART0_RX <11,35>
RW12 1 @ 2 0_0201_5% CLK_CNV_CRX_R_DTX_N WGR_CLKN 21 SDIO_DAT3 UART_WAKE 22 BRI_RSP RW39 1 CNVi@ 2 22_0402_5% PCH EDS : M.2 CNV Mode Select
<9> CLK_CNV_CRX_DTX_N CLK_CNV_CRX_DTX_P SDIO_WAKE UART_TX CNV_BRI_CRX_DTX <11>
RW14 1 @ 2 0_0201_5% CLK_CNV_CRX_R_DTX_P WGR_CLKP 23
<9> CLK_CNV_CRX_DTX_P SDIO_RST RW45 1 NONCNVi@
2 0_0201_5% GPP_F6/CNV_RGI_DT
3
Near JWLAN1 32 RGI_DT
CNV_RGI_CTX_R_DRX RW40 1 CNVi@ 2 75_0402_5%
UART0_TX <11,35>
CNV_RGI_CTX_DRX <11> Active Low
3
UART_RX CNV_RGI_CRX_R_DTX
PCIE_CTX_C_DRX_P8 GND 33 GND_33 UART_RTS
34 RGI_RSP CNV_BRI_CTX_R_DRX
RW16 1 CNVi@ 2 22_0402_5%
CNV_RGI_CRX_DTX <11> 0 = Integrated CNVi enable.
CC116 1 2 0.1U_0201_10V6K PETp0 35 36 BRI_DT RW33 1 CNVi@ 2 75_0402_5% CNV_BRI_CTX_DRX <11>
<12> PCIE_CTX_DRX_P8 PCIE_CTX_C_DRX_N8 PET_RX_P0 UART_CTS CNVi_PWR_EN
CC117 1 2 0.1U_0201_10V6K PETn0 37 38 Clink RESET 1 = Integrated CNVi disable. +1.8VALW
<12> PCIE_CTX_DRX_N8 PET_RX_N0 CLink_RST EC_TX <34,35>
GND 39 40
p
GND_39 CLink_DATA Clink DATA EC_RX <34,35>
<12> PCIE_CRX_DTX_P8 PERp0 41 PER_TX_P0 CLink_CLK
42 Clink CLK WLAN_COEX3 RW41 CNV_RGI_CTX_R_DRX RC449 +3VS_WLAN +3VALW
WLAN <12> PCIE_CRX_DTX_N8 PERn0 43 44 COEX3 1 @ 2 0_0201_5%
COEX3 <9>
1 2 20K_0201_5%
2
PER_TX_N0 COEX3 WLAN_COEX2 RW42
GND 45 GND_45 COEX2
46 COEX_RXD WLAN_COEX1 RW43
1 @ 2 0_0201_5%
COEX2 <9> CNV_BRI_CTX_R_DRX RC3940 1
G
<10> CLK_PCIE_P2 REFCLKP047 REFCLK_P0 COEX1
48 COEX_TXD 1 @ 2 0_0201_5%
COEX1 <9>
@ 2 20K_0201_5% QWL1
<10> CLK_PCIE_N2 REFCLKN049 REFCLK_N0 SUSCLK(32KHz)
50 C_P32K SUSCLK <10>
1 3
1 RW23 EC_TX
S
CLKREQ_PCIE#2_R GND 51 GND_51 PERST0#
52 PERST0# PCI_RST# <10,21,34> 100K_0402_5% 2
<10> CLKREQ_PCIE#2 RWL158 1 2 0_0402_5% CLKREQ0#53 54 W_DISABLE2# @
WAKE#_R WLBT_OFF# <9>
<34> EC_PCIE_WAKE# RWL162 1 @ 2 0_0402_5% PEWake0#55 CLKREQ0# W_DISABLE2# 56 W_DISABLE1# 71.5K_0402_1% 1 CNVi@ 2 RW35 CLKREQ_CNV# PJ2301 1P SOT23-3
PEWAKE0# W_DISABLE1# WL_OFF# <12>
CNV_CTX_DRX_N1 GND 57 GND_57 I2C_DAT
58 A4WP_I2C_DATA SB00000T900
RW26 1 @ 2 0_0201_5% CNV_CTX_R_DRX_N1 WT_D1N 59 60 A4WP_I2C_CLK
<9> CNV_CTX_DRX_N1 CNV_CTX_DRX_P1 RSVD/PCIE_RX_P1 I2C_CLK
RW27 1 @ 2 0_0201_5% CNV_CTX_R_DRX_P1 WT_D1P 61 62 A4WP_IRQ#
<9> CNV_CTX_DRX_P1 RSVD/PCIE_RX_N1 I2C_IRQ CLKIN_XTAL
CNV_CTX_DRX_N0 GND 63 64 REFCLK0 CLKIN_XTAL <10>
RW29 1 @ 2 0_0201_5% CNV_CTX_R_DRX_N0 WT_D0N 65
GND_63 RSVD_64 66 PERST1#
m
<9> CNV_CTX_DRX_N0 CNV_CTX_DRX_P0 RSVD/PCIE_TX_P1 RSVD_66
RW30 1 @ 2 0_0201_5% CNV_CTX_R_DRX_P0 WT_D0P 67 68 CLKREQ1#
<9> CNV_CTX_DRX_P0 RSVD/PCIE_TX_N1 RSVD_68
CLK_CNV_CTX_DRX_N GND 69 GND_69 RSVD_70
70 PEWake1#
RW31 1 @ 2 0_0201_5% CLK_CNV_CTX_R_DRX_N WT_CLKN71 72 +3P3A
<9> CLK_CNV_CTX_DRX_N CLK_CNV_CTX_DRX_P RSVD_71 3.3VAUX_72
RW32 1 @ 2 0_0201_5% CLK_CNV_CTX_R_DRX_P WT_CLKP73 74 +3P3A
<9> CLK_CNV_CTX_DRX_P RSVD_73 3.3VAUX_74 +3VALW
GND 75 GND_75 76 GND Need to stuff for CNVi power sequence control Imax : 2.0 A +3VS_WLAN
77 GND1
GND GND2 Imax : 2.0 A
o
LOTES_APCI0147-P007A
1U_0201_6.3V6M
SP07001GF00 1
+3VS_WLAN
CC3861 CNVi@
ME@ CC3863
CNVi@ 0.1U_0201_10V6K
Note: The real behavior of BT_DISABLE are UC13
2
1 2
BT_DISABLE=LOW, BT=OFF 5 VOUT
BT_DISABLE=HIGH, BT=ON VIN
2
CNVi_PWR_EN 1 CNVi@ 2 CNVi_PWR_EN_R 4 GND
<34> CNVi_PWR_EN EN
RC3937 0_0402_5%
1U_0201_6.3V6M
3 RC3943 1 2 10K_0402_5%
C
@
/OC
CC3864 CNVi@
EM5203AJ-20 SOT23-5
CNVi@
2
4 4
I (Max) : 2.0 A(+3VS_WLAN)
RDS(Typ) : 70 mohm
V drop : 0.14 V

NGFF SSD/WLAN
Custom 0.2
A B C D E F G H
A B C D E
ALC3240 Head Phone Input

place close audio codec
+3VDD_CODEC
VREF
+5VS
1U_0201_6.3V6M
2
Place near Pin34 1 1
1U_0402_16V6K
@
o
+5VS_PVDD RA1 2 1 0_0805_5% RA51
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
100K_0402_1%
CA27
CA94
0.1U_0201_10V6K
0.1U_0201_10V6K
+3VDD_CODEC 2 2
2 1 2 1
1
+1.8VS PLUG_IN_R RA13 1 2 200K_0402_1%
CA3
PLUG_IN <37>
CA1
CA2
CA32
@ 1 2 1 2
1 2 1
v
AGND
CA17
4.7U_0402_6.3V6M
1 CPVEE
Audio Combo Jack
29
34
39
Place near Pin39 1 1
1U_0402_16V6K
1U_0201_6.3V6M
1
UA1 @
PVDD1
PVDD2
CPVDD
DVDD
o
33_0402_5% 2 1 RA12 HDA_SDIN0_AUDIO 7
CA20
CA95
<9> HDA_SDIN0
<9> HDA_SDOUT_R 4 SDATA-IN
SDATA-OUT HPOUT-L(PORT-I-L)
25
26
HP_OUTL
HP_OUTR Headphone 2 2
EXT_MIC_SLEEVE EMI@ RA19 2 1 BLM15BD121SN1D_2P
EMI
SM010009U00
HPOUT-R(PORT-I-R) W=40mils EXT_MIC_RING2 EMI@ RA20 2 1 BLM15BD121SN1D_2P SM010009U00
HGNDB <37>
W=40mils
EMI PC_BEEP 11
5
PCBEEP
VREF
22
27
VREF
HP_OUTL
HP_OUTR
EMI@ RA22 1
EMI@ RA23 1
2 47_0402_5%
2 47_0402_5%
HGNDA
HPOUT_R
<37>
HPOUT_L <37>
<37>
Place RA10 & CA12 on AGND moat <9> HDA_BIT_CLK_R CPVEE SD028470A80
BCLK CPVEE
n
SD028470A80
22P_0402_50V8J @EMI@ CA12 33_0402_5% 2 @EMI@ 1 RA10
CA33 @EMI@
CA34 @EMI@
CA35 @EMI@
CA36 @EMI@
For Universal Audio Jack
470P_0402_50V7K
470P_0402_50V7K
470P_0402_50V7K
470P_0402_50V7K
2
2
RA6 1 2 2.2K_0402_5% EXT_MIC_RING2 13 17 LINE1-R
wide 40MIL 1 2 2.2K_0402_5% EXT_MIC_SLEEVE 14 MIC2-L(PORT-F-L)/RING LINE1-R(PORT-C-R) 18 LINE1-L
EMI CA96 1 2 1U_0201_6.3V6M
1 1 1 1
RA26
RA27
10K_0402_5%
10K_0402_5%
MIC2-R(PORT-F-R)/SLEEVE LINE1-L(PORT-C-L)
AGND
RA7 CA19 1 2 2.2U_0201_6.3V6M 15 24 @ @

MIC2-CAP LINE1-VREFO-L PLUG_IN_R +LINE1-VREFO-R
23 12 LINE1-L CA21 1@ 2 1U_0402_16V6K
+MIC2-VREFO
e
MIC2-VREFO HP/ LINE1-JD(JD1) 2 2 2 2
External DMIC
1
SPK_L2+ 35 2 DMIC_DAT_R 0_0402_5% 2 @ 1 RA14 LINE1-R CA22 1@ 2 1U_0402_16V6K
SPK_L1- 36 SPK-OUT-LP GPIO0/DMIC-DATA12 3 DMIC_CLK_R LA1 1 2 DMIC_DAT <28>
SPK_R1- 37 SPK-OUT-LN GPIO1/DMIC-CLK EMI@ BLM15EG221SN1D_2P DMIC_CLK <28> CA97 1 2 1U_0201_6.3V6M AGND AGND AGND AGND AGND AGND
SPK_R2+ 38 SPK-OUT-RN 8
SPK-OUT-RP DVDD-IO +IOVDD_CODEC
AGND AGND
RA29 1 2 4.7K_0402_5%
2.2U_0201_6.3V6M 1 2 CA26 2 1
LDO1 21 28 @ +LINE1-VREFO-R RA32 1 2 4.7K_0402_5%
2.2U_0201_6.3V6M 1 2 CA16 LDO2 32 LDO1-CAP CBN 30 CA15 CA98
LDO2-CAP CBP
L
LDO3 6 1U_0402_16V6K 1U_0201_6.3V6M
2.2U_0201_6.3V6M 1 2 CA13 LDO3-CAP 1 2
40 EC_MUTE#_R 1 2
PDB EC_MUTE# <34>
10 0_0402_5% @ RA11 2 1
VD33STB
9 DC DET 41 @
Speaker
AVDD1
AVDD2
AVSS1
AVSS2
<9> HDA_SYNC_R SYNC THERMAL PAD RA8 10K_0402_5%
2 2
20
33
19
31
16
r
+1.8VS_codec
o
AGND +3VALW
+5VDDA_CODEC +1.8VS
Moat
RA5 1 2
@ 0_0402_5%
CA8 1 2 1U_0201_6.3V6M
AGND
F
Place near Pin33
+3VS to +3VDD_CODEC +5VS to +5VDDA_CODEC +3VS to +IOVDD_CODEC
l
EMI
SPEAK 4 ohm: 40MIL
a
SPEAK 8 ohm: 20MIL JSPK1
SPK_R1- 1
+3VS +3VDD_CODEC +5VS +5VDDA_CODEC +3VS +IOVDD_CODEC SPK_R2+ 2 1
2
3 3
RA4 2 1 0_0603_5%
@ @ 3
G1
1U_0201_6.3V6M
RA2 2 1 0_0603_5% RA3 2 1 0_0603_5% 4
1000P_0402_50V7K
1000P_0402_50V7K
0.1U_0201_10V6K
1U_0201_6.3V6M
G2
p
@
CA93
1 1
10P_0402_50V8J
0.1U_0201_10V6K
CA11
ACES_50278-00201-001
CA7
@RF@ CC91
1 1 1 1
10P_0402_50V8J
0.1U_0201_10V6K
1
CA4
SP02000EZ10
EMI@ CA30
EMI@ CA31
Place RA4 on AGND moat 1
CA5
CA6
ME@
@RF@
2 2
2
2 2 2 2
Place near Pin8 2
Place near Pin1 JSPK2
SPK_L2+ R3247 1 2 0_0603_5% SPK_L2+_R 1
SPK_L1- R3246 1 2 0_0603_5% SPK_L1-_R 2 1
AGND 2
Place near Pin20
1000P_0402_50V7K
1000P_0402_50V7K
m
3
4 G1
1 1 G2
EMI@ CA28
EMI@ CA29
ACES_50278-00201-001
SP02000EZ10
2 2 ME@
o
ESD protection needs to be placed near connector side
PC Beep At least one R-Short short close to UA1
RA42 1 2 0_0402_5% ESD SPK_R2+
SPK_R1-
SPK_L2+_R
SPK_L1-_R
place close to audio codec
@
RA43 1 2 0_0402_5%
C
3
2
RA40 1 2 47K_0402_5% BEEP_N CA37 1 2 0.1U_0201_10V6K PC_BEEP
EC Beep <34> BEEP#
L03ESDL5V0CC3-2_SOT23-3
L03ESDL5V0CC3-2_SOT23-3
@ DA3 DA4
RA41 1 2 47K_0402_5% RA44 1 2 0_0402_5% @ESD@ @ESD@
APU Beep <9> HDA_SPKR
100P_0402_50V8J
CA40 @ESD@
4 1 @ 4
1
RA45 1 2 0_0402_5%
RA39
27K_0402_5% @
2
Moat
1
GND AGND
2
update from 4K7 to 27K
AGND
HD Audio Codec_ALC3240
C 0.2
A B C D E
+3VL +3VL
o
L20
1 2 R189 1 @ 2 0_0603_5%
+3VALW_EC +EC_VCCA
BLM15AX601SN1D_2P
SM01000KL00 +3VALW_EC
1 1 1
0.1U_0201_10V6K
C180
0.1U_0201_10V6K
C181
C184 +5VALW
v
0.1U_0201_10V6K
2 2 2 +EC_VCCA
L21 USB_EN# R194 1 2 10K_0402_5%
1 2
BLM15AX601SN1D _2P
111
125
SM01000KL00
22
33
96
67
9
U11 +3VALW
ECAGND
VCC_LPC
VCC
VCC
VCC
VCC
AVCC
VCC0
o
EC_MUTE# R198 1 @ 2 10K_0402_5%
1 21 LID_SW# R1665 1 2 100K_0402_5%

<14,30> PD_INT# GATEA20/GPIO00 EC_VCCST_PG/GPIO0F VCCST_PWRGD <10>
2 23
KBRST#/GPIO01 BEEP#/GPIO10 BEEP# <33> KB_MUTLI_KEY
3 26 RC507 2 1 10K_0402_5%
<8> SERIRQ SERIRQ EC_FAN_PWM/GPIO12 EC_FAN_PWM1 <36>
4 PWM Output 27
<8> LPC_FRAME# LPC_FRAME# AC_OFF/GPIO13 ILIM_select <31>
5
<8> LPC_AD3 LPC_AD3
7
EMI <8> LPC_AD2
8 LPC_AD2 63 EC_SPI_CS0# R3235 1 2 100K_0402_5%
n
<8> LPC_AD1 LPC_AD1 VCIN1_BATT_TEMP/AD0/GPIO38 VCIN1_BATT_TEMP <40,41>
@EMI@ @EMI@ 10 LPC & MISC 64
<8> LPC_AD0 LPC_AD0 VCIN1_BATT_DROP/AD1/GPIO39
2 1 R190 2 1 65
ADP_I/AD2/GPIO3A ADP_I <41>
C186 22P_0402_50V8J 10_0402_1% 12 AD Input 66 Follow ENE suggestion for Auto load
<8> CLK_LPC_EC CLK_PCI_EC AD_BID/AD3/GPIO3B CUST_TEMP3 <36>
13 75
<10,21,32> PCI_RST# EC_RST# PCIRST#/GPIO05 AD4/GPIO42 GPU_OVERT# <24>
1 2 37 76
+3VALW_EC R192 @ 47K_0402_5% 20 EC_RST# AD5/GPIO43 CUST_TEMP2 <36>
<6> EC_SCI# EC_SCI#/GPIO0E +3VALW
2 38
<8> PM_CLKRUN# CLKRUN#/GPIO1D
e
C187 68
DA0/GPIO3C NOVO# <35>
0.1U_0201_10V6K DA Output 70
1 EN_DFAN1/DA1/GPIO3D TP_DISABLE# <35>
KSI0 55 71
@ KSI0/GPIO30 DA2/GPIO3E DGPU_PWR_EN <11,24,26>
KSI1 56 72
KSI1/GPIO31 DA3/GPIO3F USB_EN# <37>
KSI2 57
KSI3 58 KSI2/GPIO32 83 EC_PCIE_WAKE# R212 2 @ 1 4.7K_0402_5%
KSI4 59 KSI3/GPIO33 EC_MUTE#/PSCLK1/GPIO4A 84
KSI5 60 KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B 85 PBTN_OUT# R195 2 @ 1 10K_0402_5%
KSI6 61 KSI5/GPIO35 PSCLK2/GPIO4C 86
PS2 Interface
KSI7
KSO0
62
39
KSI6/GPIO36
KSI7/GPIO37
PSDAT2/GPIO4D
TP_CLK/GPIO4E
87
88
USB_CHG_ILIM_SEL <37> ESD
L
KSO1 40 KSO0/GPIO20 TP_DATA/GPIO4F
<35> KSO[0..15] KSO1/GPIO21 1
KSO2 41 @ESD@
KSO3 42 KSO2/GPIO22 97 C197
<35> KSI[0..7] KSO3/GPIO23 ENKBL/GPXIOA00 ENBKL <6,28>
KSO4 43 98 0.1U_0201_10V6K
KSO4/GPIO24 WOL_EN/GPXIOA01 SYS_PWROK <10> 2
KSO5 44 99
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 ME_EN <9>
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH1/GPXIOD00 VCIN0_PH1 <40>
KSO8 47 KSO7/GPIO27
KSO8/GPIO28 SPI Device Interface
KSO9 48 119
KSO9/GPIO29 MISO/GPIO5B EC_SPI_MISO <8>
KSO10 49 120
r
KSO10/GPIO2A MOSI/GPIO5C EC_SPI_MOSI <8>
KSO11 50 SPI Flash ROM SPICLK/GPIO58 126
KSO11/GPIO2B EC_SPI_CLK <8>
KSO12 51 128
KSO12/GPIO2C SPICS#/GPIO5A EC_SPI_CS0# <8> VCIN1_BATT_TEMP
KSO13 52 1 2
KSO14 53 KSO13/GPIO2D C189 100P_0402_50V8J
KSO15 54 KSO14/GPIO2E 73 VCIN1_AC_IN 1 2
KSO15/GPIO2F EC_CIR_RX/AD6/GPIO40 CUST_TEMP1 <36>
81 74 C190 100P_0402_50V8J
<35> KB_MUTLI_KEY KSO16/GPIO48 SYS_PWROK/AD7/GPIO41
82 89
<24,36> GPU_PROHOT# KSO17/GPIO49 GPIO50 EC_MUTE# <33>
+3VALW_EC 90 SUSP# R1664 1 @ 2 100K_0402_5%
BATT_CHG_LED#/GPIO52 BATT_CHG_LED# <37>
91
o
CAPS_LED#/GPIO53 CAPS_LED# <35>
R201 77 GPIO 92 BKOFF# R3238 1 2 100K_0402_5%
EC_SMB_CK1 <40,41> EC_SMB_CK1 EC_SMB_CLK1/GPIO44 PWR_LED#/GPIO54 PWR_LED# <35,37>
1 2 78 93
<40,41> EC_SMB_DA1 EC_SMB_DAT1/GPIO45 BATT_LOW_LED#/GPIO55 BATT_LOW_LED# <37>
2.2K_0402_5% 79 95
<8,24,30,36> EC_SMB_CK2 EC_SMB_CLK2/GPIO46 SYSON/GPIO56 SYSON <13,43,44>
R202 80 121
EC_SMB_DA1 <8,24,30,36> EC_SMB_DA2 EC_SMB_DAT2/GPIO47 VR_ON/GPIO57 VR_ON <46>
1 2 127
DPWROK_EC/GPIO59 AC_PRESENT <10,24>
2.2K_0402_5% SM Bus
6 100
<10> PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 EC_RSMRST# <10>
14 101
<37> USB_CHG_CTL1 GPIO07 GPXIOA04 3V/5VALW_PG <37,38,42,44>
15 102
F
<10> EC_CLEAR_CMOS# GPIO08 VCIN1_ADP_PROCHOT/GPXIOA05
+3VS 16 103
<37> USB_CHG_CTL3 GPIO0A VCOUT1_PROCHOT#/GPXIOA06 VCOUT1_PROCHOT# <41>
17 104 +3VS
<37> USB_CHG_EN GPIO0B VCOUT0_MAIN_PWR_ON/GPXIOA07 VCOUT0_MAIN_PWR_ON <42>
18 105
<37> USB_CHG_CTL2 GPIO0C BKOFF#/GPXIOA08 BKOFF# <28>
19 GPIO GPO 106
<37> USB_CHG_STATUS# AC_PRESENT/GPIO0D GPXIOA09
25 107
GPU_PROHOT# <35> KB_BL_PWM PWM2/GPIO11 PCH_PWR_EN/GPXIOA10 CNVi_PWR_EN <32> EC_FAN_SPEED1
RC3944 1 DIS@ 2 10K_0402_5% 28 108 RC508 2 1 10K_0402_5%
<36> EC_FAN_SPEED1 FAN_SPEED1/GPIO14 PWR_VCCST_PG/GPXIOA11 EC_PCIE_WAKE# <32>
29
30 FANFB1/GPIO15 GPU_OVERT# RC509 2 DIS@ 1 10K_0402_5%
<32,35> EC_TX EC_TX/GPIO16
31 110
<32,35> EC_RX VCIN1_AC_IN <41>
l
32 EC_RX/GPIO17 VCIN1_AC_IN/GPXIOD01 112 PD_INT# RC506 2 1 10K_0402_5%
<10> PCH_PWROK PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON <42>
34 114 ON/OFF# <35,36>
36 SUSP_LED#/GPIO19 ON/OFF#/GPXIOD03 115
<46> VR_PWRGD NUM_LED#/GPIO1A GPI LID_SW#/GPXIOD04 LID_SW# <37>
116
SUSP#/GPXIOD05 SUSP# <13,38,43>
117
GPXIOD06 118 PECI1 2
PECI/GPXIOD07 H_PECI <6>
122 R208 43_0402_1%
<10> PBTN_OUT# PBTN_OUT#/GPIO5D
123 124 +3VALW_EC +3VL
a
<10,41> PM_SLP_S4# PM_SLP_S4#/GPIO5E V18R/VCC_IO2
1
AGND
4.7U_0402_6.3V6M
ON/OFF# R3236 1 2 100K_0402_5%
GND
GND
GND
GND
GND
C192
KB9022QD_LQFP128_14X14 2
11
24
35
94
113
69
SA000075S30
ECAGND
Keyboard BackLight_SELECT
mp PROHOT#
ESD PCI_RST# PCH_PWROK VR_PWRGD VCCST_PWRGD SYSON
0.1U_0201_10V6K
ESD@
C193 @ESD@
C188
100P_0402_50V8J
C2178 ESD@
100P_0402_50V8J
C123 ESD@
100P_0402_50V8J
C124 @ESD@
0.1U_0201_10V6K
o
1 1 1 1 1
Funct i on KBL_ID
@ 2 2 2 2 2
KBL 1 VCOUT1_PROCHOT# R204 1 2 0_0402_5%
NO KBL 0 @
<46> VR_HOT#
R205 1 2 0_0402_5% H_PROCHOT# <6>
Pin 13 Pin 32 Pin 36 Pin 21 Pin 95
PH on KB side
C
KB_BL_PWM 1
@
C191
1
47P_0402_50V8J
R325 2
10K_0402_5%
NOKBL@ Issued Date 2018/2/5 Deciphered Date 2019/2/5 Title
EC KB9022QD
2
Custom 0.2
GTW-0902-00-ASSY-V1.pdf PD4SB_BL_KB_Darfon_2D_X07_20170731
Finger printer Keyboard

JFP1
1
<11,32> UART0_RX 1 KSI[0..7]
2
<11,32> UART0_TX 2 KSI[0..7] <34>
3
<32,34> EC_TX 3
4 9 KSO[0..15]
<32,34> EC_RX 5 4 GND 10 KSO[0..15] <34>
o
6 5 GND
<12> USB20_P6 6 ME@
7
<12> USB20_N6 8 7 SP011509010
+3VS 8 ACES_51510-0320N-P01
ACES_51580-00841-P01
SP01002GM00 +5VS 34
ME@ GND 33
GND
v
R263 2 1 470_0201_5% CAPS_LED#_R 32
31 32
<34> CAPS_LED# 31
CFP166 KSO15 30
0.1U_0201_10V6K KSO10 29 30
29
C1378
KSO11 28
KSO14 27 28
1 27
ESD@ KSO13 26
o
DFP6 @ESD@ KSO12 25 26
25
0.1U_0201_10V6K
PESD5V0U2BT_SOT23-3 KSO3 24
2 KSO6 23 24
1
KSO8 22 23
KSO7 21 22
KSO4 20 21
KSO2 19 20
19
n
KSI0 18
ESD KSO1
KSO5
KSI3
17
16
15
18
17
16
KSI2 14 15
14
Touch Pad
KSO0 13
KSI5 12 13
e
KSI4 11 12
KSO9 10 11
KSI6 9 10
+3VS +3VS 9
KSI7 8
@ KSI1 7 8
CTP163 6 7
0.1U_0201_10V6K 5 6
4 5
4
1
3
3
L
R280 2
<34> KB_MUTLI_KEY 1 2
4.7K_0402_5%
JTP1 1
1
2
2 1 JKB1
<11> I2C_0_SCL 2
3
<11> I2C_0_SDA 4 3
<9> TP_INT# 4
<34> TP_DISABLE# 5
6 5
r
7 6
8 G1
G2
SP01002DQ00
JXT_FP201CH-006G10M
ME@
PWR Button
o
3
2
1 1
@ @ @ESD@ SN111005800
CTP164 CTP165 DTP5 SKRBAAE010_4P
100P_0402_50V8J 100P_0402_50V8J PACDN042Y3R_SOT23-3
2 2 2 SW2 1
<34,36> ON/OFF#
1
Keyboard Backlight
ESD
l
PN 510-004411-01 Rev 1
F Novo Button
4 3
a +3VL
2
p
+5VS R172
100K_0402_5%
+5VALW ME@
SW1 ON/OFF#
1
KBL@ SP01001UE00
QKBL121 ACES_50524-00401-P01 NOVO# 1 2 NOVO#
<34> NOVO#
1
4 6
+5VS_KBL 3 4 G2 5
S
KBL@ 3 1
RKBL1 2 3 G1 3 4
1 2
2
10K_0402_5% ME2301DC-G_SOT23-3
KBL@ CKBL908
ESD
0.1U_0201_10V6K
1
G
1 2
10U_0402_6.3V6M
m
2
RKBL5 TCHC2QR_2P D23

JKBL1
CKBL906
<34> KB_BL_PWM 1 2 ESD@
30K_0402_1% 2 1 L03ESDL5V0CC3-2_SOT23-3
1
1
KBL@ KBL@
CKBL907 @
0.01U_0402_16V7K
2
Co PWR LED
<34,37>
Issued Date
PWR_LED#
2018/2/5
Compal Secret Data
Deciphered Date
Power (White) (TOP)
1
LED2
LTW-C193TS5-C_WHITE
SC50000BB10
2019/2/5
2 R173 1
Title
Size
C
2 412_0402_1%
KB/KBL/LED/TP/FP Conn.
Document Number
+VL

Rev
0.2
5 4 3 2 1
Thermal Sensor
+3VS
2
R390
0_0402_5%
Close to UTS1 CPU Close to GPU
o
REMOTE1+
1
UTS1 EX_THM@ 1
1
+3V_Thermal 1 8 EC_SMB_CK2 C
1 VDD SCL EC_SMB_CK2 <8,24,30,34>
EX_THM@ EX_THM@ CTS2 2 QTS1 EX_THM@
CTS1 REMOTE1+ 2 7 EC_SMB_DA2 100P_0402_50V8J B MMST3904-7-F_SOT323-3
D+ SDA EC_SMB_DA2 <8,24,30,34> 2 E
2200P_0402_50V7K
3
2 REMOTE1- 3 6 REMOTE1-
D D- ALERT# GPU_PROHOT# <24,34> D
v
+3V_Thermal RTS340 1 2 4.7K_0402_5% 4 5
EX_THM@ T_CRIT# GND
NCT7718W_MSOP8
SMB Address: 1001100x

REMOTE1+/-:
o
Trace width/space:10/10 mil
Trace length:<8"
THERMISTOR
e n
CHARGER GPU CHOKE
L CPU CHOKE
+EC_VCCA +EC_VCCA +EC_VCCA
C C
1
R364 R365 DIS@ R368
r
16.5K_0402_1% 16.5K_0402_1% 16.5K_0402_1%
2
<34> CUST_TEMP1 <34> CUST_TEMP2 <34> CUST_TEMP3
o
1
1
R366 R367 DIS@ R369
100K +-1% 0402 B25/50 4250K 100K +-1% 0402 B25/50 4250K 100K +-1% 0402 B25/50 4250K
SL200002H00 SL200002H00 SL200002H00
2
2
F
ECAGND ECAGND ECAGND
add. thermistors_by JC
B
FAN
a l ON/OFF# SHORT PADS

BOT Side 1
J1
2
SHORT PADS
J2
ON/OFF# <34,35>
CPU
H1
HOLEA
H2
HOLEA
H3
HOLEA
VGA
H4
HOLEA
H5
HOLEA
FAN
H6
HOLEA
Shielding Clip
Larger
CLIP10
HOLEA
CLIP11
HOLEA
CLIP12
HOLEA
CLIP13
HOLEA
CLIP14
HOLEA
CLIP15
HOLEA
CLIP16
HOLEA
B
p 1
1
TOP Side 1 2 @ @ @ @ @ @ @
1
SHORT PADS
+5VS H_3P3 H_3P3 H_3P3 H_3P3 H_3P3 H_3P3
JFAN1
R3214 1 @ 2 0_0603_5% +5VS_FAN1 4 6
<34> EC_FAN_SPEED1
3
2
4 GND
3 GND
5 LASER BARCODE H7
HOLEA
H8
HOLEA
H9
HOLEA
H10
HOLEA
H11
HOLEA
H15
HOLEA
H16
HOLEA Smaller
1 2
<34> EC_FAN_PWM1 1
1 ZZZ1 @ ZZZ3 @ CLIP1 CLIP2 CLIP3 CLIP4 CLIP5 CLIP6 CLIP7 CLIP8 CLIP9
10U_0402_6.3V6M
m
JXT_FP202DH-004M10M HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1
CF162
SP010022U00
ME@
2 @ @ @ @ @ @ @ @ @
1
H_3P8 H_3P2 H_2P5 H_2P5 H_3P8 H_2P5 H_4P5
BARCODE_8X8 BARCODE_12X4
o
CLIP17
H17 H18 H19 H20 HOLEA
ZZZ2 @ ZZZ4 @ HOLEA HOLEA HOLEA HOLEA
FD1 FD2 FD3 FD4
@
1
1
1
1
1
BARCODE_20X4 BARCODE_10X10
H_5P0X2P5N H_5P0X2P5N H_2P5N H_6P0N
C IRON SHEET
H25
@
A
1
MB_SUP_BRK_25X5

FAN / Thermal Senser
C 0.2
5 4 3 2 1
5 4 3 2 1
+VL +5VALW_USBCH +5VALW
USB Charger ESD USB3_CRX_L_DTX_N29

10
ESD@ D7
1 1
USB3_CRX_L_DTX_N2 CHR_USB20_P2_R 3
ESD@ D9
6
L59 I/O2 I/O4
USB3_CRX_L_DTX_P28 2USB3_CRX_L_DTX_P2
1 R215 2 2 1 3 2
D
1 1 9
o
1 0_0603_5% BLM15PX331SN1D_2P Q28 C453
USB3_CTX_L_DRX_N27 4USB3_CTX_L_DRX_N2
4
ME2301DC-G_SOT23-3
C454 L60 4.7U_0402_6.3V6M 7 2 5 +5V_CHGUSB
4.7U_0402_6.3V6M @ 2 1 GND VDD
Down USB charger Iout ripple
G
2
2 USB3_CTX_L_DRX_P26 5USB3_CTX_L_DRX_P2
BLM15PX331SN1D_2P 6 5
must under 20mA on DC S5 2
CHR_USB20_N2_R
3 3 1 4
I/O1 I/O3
+5VALW +VL 8
L30ESDL5V0C6-4_SOT23-6
10U_0402_6.3V6M
10U_0402_6.3V6M
22U_0603_6.3V6M
47U_0805_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
47U_0805_6.3V6M
R130
1 1 1 2
v
1
1
AZ1045-04F_DFN2510P10E-10-9
C224
C225
C226
C227
C239
C238
C228
100K_0402_5%
2N7002KW_SOT323-3
1
D
2
2
D
2 2 @ D
2 1
R339 C90
3V/5VALW_PG_R G
@ @
@ @
<34,38,42,44> 3V/5VALW_PG
1 @
0_0402_5%
2
Q29 S 2
0.1U_0201_10V6K
USB3.0_Port
3
2
EMI
o
@
C457
0.1U_0201_10V6K
1
Intel_PCH_USB2.0
+5VALW_USBCH +5V_CHGUSB L12 EMI@
+3VL CHR_USB20_N2 1
1 2
2 CHR_USB20_N2_R
USB3.0 CONN (for charger)
CHR_USB20_P2 CHR_USB20_P2_R
1
1
10K_0402_5%
10K_0402_5%
4 3
n
4 3
DLM0NSN900HY2D_4P
W=80mils
RC510
RC511
+5V_CHGUSB
80mil
2
U12
1 12
9 IN OUT 10 CHR_USB20_P2 JUSB1
<34> USB_CHG_STATUS# STATUS# DP_IN CHR_USB20_N2
13 11 Intel_PCH_USB3.0 1 10
FAULT# DM_IN CHR_USB20_N2_R VBUS GND
e
<34> USB_CHG_ILIM_SEL 4 2 2 11
ILIM_SEL DM_OUT USB20_N2 <12> CHR_USB20_P2_R D- GND
<34> USB_CHG_EN
5
EN DP_OUT
3
USB20_P2 <12>
USB3.0 With USB2.0 For Charge USB3_CRX_L_DTX_N2
3
D+ GND
12
6 15 R3211 1 2 2.7M_0402_1% R223 2 1 0_0402_5% 4 13
<34> USB_CHG_CTL1 CTL1 ILIM_LO <12> USB3_CRX_DTX_N2 USB3_CRX_L_DTX_N2 GND GND
7 16 R3212 1 2 24.9K_0402_1% 5
<34> USB_CHG_CTL2 CTL2 ILIM_HI USB3_CRX_L_DTX_P2 STDA_SSRX-
<34> USB_CHG_CTL3 8 14 6
CTL3 GND 17 R224 2 1 0_0402_5% USB3_CRX_L_DTX_P2 7 STDA_SSRX+
T-PAD <12> USB3_CRX_DTX_P2 USB3_CTX_L_DRX_N2 8 GND
USB3_CTX_L_DRX_P2 9 STDA_SSTX-
100U_1206_6.3V6M
TPS2546RTER_QFN16_3X3 1 1 1 1 STDA_SSTX+
1
10K_0402_5%
22U_0603_6.3V6M
22U_0603_6.3V6M
SA000064O00
10P_0402_50V8J
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
C195
C2210
C2211
SANTA_375145-1
RF@ C2212
2 2 2 2 ME@
RC512
1 1 1
L
2
C2189
C2190
C2192
C156
0.1U_0201_10V6K
2 2 2 1 2 USB3_CTX_C_DRX_N2 R225 2 1 0_0402_5% USB3_CTX_L_DRX_N2
<12> USB3_CTX_DRX_N2
Near JUSB1 C157
0.1U_0201_10V6K
1 2 USB3_CTX_C_DRX_P2 R226 2 1 0_0402_5% USB3_CTX_L_DRX_P2
<12> USB3_CTX_DRX_P2
C C
Place TX AC coupling Cap (C156,157). Close to connector
To I/O Board
o r I/O CONN
F
+USB3_VCCA
+VL
2A/Active Low +3VALW

SP01001AO00
ME@
l
+5VALW +USB3_VCCA ACES_51522-02601-001
U20 W=80mils
W=80mils 1 28
5 OUT 27 GND
IN 2 LID_SW# 26 GND
GND <34> LID_SW# 26
<34> USB_EN# 4 25
EN 3 USB3_CTX_DRX_N1 24 25
OCB <12> USB3_CTX_DRX_N1 USB3_CTX_DRX_P1 24
1 23
<12> USB3_CTX_DRX_P1 23
a
C196 G524B2T11U_SOT23-5 USB3.0 22
USB3_CRX_DTX_N1 22
C2213
0.1U_0201_10V6K SA00007BW00 21
<12> USB3_CRX_DTX_N1 USB3_CRX_DTX_P1 21
10P_0402_50V8J
100U_1206_6.3V6M
@ C178
1 1 1 1 20
2 <12> USB3_CRX_DTX_P1 20
22U_0603_6.3V6M
22U_0603_6.3V6M
19
USB20_N1_R 19
@ C2205
@ C179
B 18 B
USB20_P1_R 17 18
2 2 2 2 16 17
RF@
15 16
14 15
13 14
p
12 13
BATT_CHG_LED# 11 12
<34> BATT_CHG_LED# BATT_LOW_LED# 11
10
<34> BATT_LOW_LED# PWR_LED# 10
Near JIO1 <34,35> PWR_LED# 9
Intel_PCH_USB2.0 EMI <33> HGNDA HGNDA

HPOUT_R
HGNDA 8
7
6
9
8
7
<33> HPOUT_R 6
AGND 5
L16 EMI@ HPOUT_L 4 5
1 2 USB20_N1_R Audio Jack <33> HPOUT_L
3 4
<33> HGNDB HGNDB
<12> USB20_N1 1 2 2 3
HGNDB
PLUG_IN 1 2
USB20_P1_R <33> PLUG_IN 1
4 3
<12> USB20_P1 4 3 JIO1
DLM0NSN900HY2D_4P
m
AGND
5
Co 4 3
Compal Secret Data
2
Title
Size
Custom
Date:
USB3 / IO Board
Document Number
1
LA-G651P
Friday, May 18, 2018 Sheet 37 of 52
Re v
0.2
A
A B C D E
o
+3VS
+3VALW J4
2 1
2 1
+VL JUMP_43X79
0.1U_0201_10V6K
CC60
1 1
6.8P_0402_50V8C
1 1
0.1U_0201_10V6K
C212
@RF@
1
C205
@ +3VALW to +3VS 2 2
2
U13
1 14
2 VIN1 VOUT1 13 +3VALW_3VS
Close to J4
o
VIN1 VOUT1
3 12 C383 1 2 S CER CAP 1000P 50V K X7R 0402
ON1 CT1 SE074102K80
4 11
<13,34,43> SUSP# VBIAS GND
5 10 C386 1 2 220P_0402_50V7K +5VS
+5VALW ON2 CT2 J5
+5VALW_5VS
n
6 9 2 1
7 VIN2 VOUT2 8 2 1
VIN2 VOUT2 JUMP_43X79
0.1U_0201_10V6K
0.1U_0201_10V6K
15
CC162
1 1 1
6.8P_0402_50V8C
GPAD
C214
C218
@RF@
@ G2898KD1U TDFN 14P LOAD SWITCH
SA0000BKC00
e
2 2 2
+5VALW to +5VS Close to J5
r L 2
For +1.8VALW Discharge For +0.6VS Discharge
F o
+5VALW
+1.8VALW
a l +0.6VS
1
+5VALW
1
R2005
@ 22_0603_5% R228
1
3 3
@
1
R2004 470_0402_5%
2
@ 100K_0402_5% R230
2
p
@
100K_0402_5%
2
D D
2
1.8VALW_PWR_EN# 5 SUSP 5 @
G Q143B @ G Q144B
2N7002KDW_SOT363-6 2N7002KDW_SOT363-6
S S
4
4
6
D D
2 SUSP# 2 @
<34,37,42,44> 3V/5VALW_PG G G
Q143A @ Q144A
2N7002KDW_SOT363-6 2N7002KDW_SOT363-6
S S
m
1
Compal Secret Data
Title
Size
Document Number
DC to DC
Rev
4
C 0.2
A B C D E
5 4 3 2 1
D
ACES_50278-00401-001
G2
6
5
PF101
7A_32VDC_0437007.WRML
+19V_VIN
v o D
o
G1 4 APDIN 1 2 +19V_APDIN 1 2
4 3
3 2 EMI@ PL102
2
1000P_0402_50V7K
1000P_0402_50V7K
100P_0402_50V8J
100P_0402_50V8J
1 S SUPPRE_ 5A Z80 20M 0805
1
n
@ JDCIN1
1
EMI@ PC101
EMI@ PC102
EMI@ PC103
EMI@ PC104
2
2
C
L e C
o r
F
2
+CHGRTC
l
PR106
45.3K_0603_1%
PR108
1.5K_0603_5%
1
1 2 +3VLP
a
PD302
3
B
+RTCBATT 1 +RTCBATT_R B
LRB715FT1G_SOT323-3
mp
A
5
Co 4
Compal Secret Data
3 2
B
Title
Size
Date:
PWR- DCIN / Vin Detector
Document Number

1
39 of 54
Rev
2.0
A
5 4 3 2 1
EMI@ PL201
CONN@ VMB2 VMB S SUPPRE_ 5A Z80 20M 0805
PF201 1 2
JBAT1 F1206HB12V024TM 12A 24V UL FAST
SUYIN_125022HB008M200ZL
1 1 2
1 2 BATT+
EMI@ PL202
2 3 EC_SMCA S SUPPRE_ 5A Z80 20M 0805
o
3 4 EC_SMDA 1 2
4 5 TH
5 6
6
1
7
7
1
100_0402_1%
100_0402_1%
8
8 9 PC201 EMI@ PC202 EMI@
D GND 0.01U_0402_25V7K D
v
10 1000P_0402_50V7K
2
GND
PR201
PR202
11
2
GND 12
GND
o
EC_SMB_CK1 <34,41>
EC_SMB_DA1 <34,41>
1 2
+3VLP
n
PR203 200K_0402_1%
1 2
PR205 10K_0402_5%
VCIN1_BATT_TEMP <34,41> PH201 under CPU botten side :
CPU thermal protection at 93 +-3 degree C
e
+RTCBATT_R
Recovery at 56 +-3 degree C
L
+EC_VCCA
16.5K_0402_1%
1
PR206
C C
2
<34> VCIN0_PH1
1
o
PH201
100K +-1% 0402 B25/50 4250K
2
l F ECAGND
p a B
o m
A
5
C 4
Compal Secret Data
3 2
Title
Custom
Date:
PWR- BATTERY CONN/OTP
SKL
1
Sheet 40 of 54
R ev
2.0
A
A B C D
0x3CH <BIT9> PSYS current gain **Design Notes**

Rs1 = 10mΩ and Rs2 = 5mΩ o r Rs 1 = 10m Ω a nd R s2 = 10Ω
m For 45W/65W /90W system, 2S/3S/4S battery
BIT0 = 1.14uA/W Maximum Charging current 3.5A
BIT1 = 0.285uA/W Maximum Battery discharge power 55W
========================================================= #Register Setting
Rs1 = 20mΩ and Rs2 = 10mΩ or Rs1 = 20mΩ and Rs2 = 20m Ω
BIT0 = 2.28uA/W 1. 0X3DH bit10 set 0 (default 1) to enable turbo boost
BIT1 = 0.57uA/W function
2. Disable turbo when AC only
#Circuit Design
o
1. ACLIM and CCLIM are devider voltage control.
Ipsys = KPSYS  
x ( VAD P x IAD P + VBA T
R_Psys = 1.2V / Ipsys
x IBA
T )
Protection for reverse input 2. Use 7X7 choke and 3X3 H/L side MOSFET
Charge current 3A
KPSYS = 1.14uA/W Vgs = 20V Power loss : 1.79W (H/S=0.227W,L/S=1.2738W,Choke=0.297W)
adapter wattage = 45W Vds = 60V Power density : 0.61 (23X16)
1
D
Battery wattage = 40Wh Id = 250mA 2 #Protect function
1
PQ301 1
Ipsys = 1.14 x (45+40) = 96.9uA
v
R_Psys = 1.2V / 96.9uA = 12.3K-ohm.
G 2N7002KW_SOT323-3 1. ACOVP : VCC voltage > 24V
===================================== max Power loss 0.22W for 90W;0.12W for 65W system;0.05W for 45W 2. SMBus timeout : 0X3DH bit15 set 0 (default 0) to enable
S
175s(default).
3
adapter wattage = 65W CSR rating: 1W
Battery wattage = 40Wh VCSIP-VCSIN spec < 81mV 3. ACOC : OX3CH bit4 set1 release adapter limit function
Ipsys = 1.14 x (65+40) = 119.7uA (default:Enable).
R_Psys = 1.2V / 96.9uA = 10K-ohm. Rds(on) = 15.8mohm max 4. CHGOCP : based on charge current setting
o
1 2 1 2
Vgs = 20V 5. BATOVP : 4.6V/Cell
PR301 PR302 Vds = 30V 6. BATLOWV : No.
1M_0402_1% 3M_0402_5% ID = 10.5A (Ta=70C) B+ 7. TSHUT : 150C
EMB04N03H_EDFN5X6-8-5
PQ302 +19V_P1 PQ303
Need check the SOA for inrush AON7506_DFN33-8-5 PR303
1 1 +19V_P2 0.01_1206_1%
n
2 2
5 3 3 5 1 4
+19V_VIN
PC205 @EMI@
EMI@
2 3
2200P_0402_25V7K
10U_0603_25V6M
0.1U_0402_25V7K
10U_0603_25V6M
4
1
1
CSIN_CHG_R
CSIP_CHG_R
PC204
Module model information
PC203
e
PC206
2
2
2
ISL95520_Hybrid_Boost_V2.mdd
1
Co-lay jump and ISN choke.
2_0402_5%
1
PR305
0_0402_5%
@ PR304
1
L
PR306
2
392K_0402_1% ASGATE_CHG_R
2
PC207
2
1 2 PQ304
4.02K_0402_1%
4.02K_0402_1%
2 AON7506_DFN33-8-5 2
1
0.1U_0402_25V6
1
2
r
5 3
PR309
PR729 and PR732 are ACDET set t i ng base on your proj ect to set. 100_0402_1%
4
PR307
PR308
1 2 BATT+ Rds(on) = 32mohm max
Vgs = 20V
o
0.22U_0402_16V7K Vds = 30V
1
CMSRC_CHG PC209 ID = 8A (Ta=70C) @ PC210

2200P_0402_50V7K
48.7K_0402_1%
1
PC208
PR310
1
ASGATE_CHG 1 2
2
BGATE_CHG
2
OPCN_CHG 2
0.1U_0402_25V7K
CSIN_CHG
CSIP_CHG
OPCP_CHG
VBAT_CHG
F
Rds(on) = 32mohm max
1 VDD_CHG
Vgs = 20V
Vds = 30V Support max charge 3.5A
5
ID = 8A (Ta=70C) PQ305
Power loss: 0.245W
PU301 CSR rating: 1W
100K_0402_1%
support Turbo boost : 2200P
32
31
30
29
28
27
26
25
no support Turbo boost : 0.1u S IC ISL88739AHRZ-T QFN 32P CHARGER VCSPP-VCSON spec < 81mV
AON7408L_DFN8-5
PR311
7X7X3
l CSIP
CSIN
ASGATE
CMSRC
OPCN
QPCP
VBAT
BGATE
PC211 4
@ PR312 0_0603_5% 0.47U_0603_25V7K
Isat: 6.5A
ACIN_CHG 1 24 BST_CHG 1 2 BST_CHG_R 1 2 DCR: 28mohm
2
ACIN BOOT PR315

2 23 UG_CHG 0.01_1206_1%
PL302
BATT+
3
2
1
<34> VCIN1_AC_IN PR313
ACOK UGATE
0_0402_5%
a
1 2 3 22 LX_CHG 3 2 +17.4V_BATT_CHG 1 4
1
158K_0402_1%
<34,40> EC_SMB_DA1 SDA PHASE

PR314
PR318 1 2 0_0402_5% 4 21 LG_CHG 4 1 2 3
4.7_1206_5%
<34,40> EC_SMB_CK1 SCL LGATE
RF@ PR317
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
5
5 20 VDDP_CHG PQ306
3
PROCHOT# VDDP 4.7UH_5.5A _20%_7X7X3_M 3
2
AON7752_DFN3X3EP8-5
PR320 0_0402_5% AMON_ISL95520 PR319 4.7_0402_5%
1
1 2 6 19 VDD_CHG 1 2
PC212
PC213
PC214
@ PC225
@ PC226
<34> ADP_I AMON VDD
1U_0201_6.3V6M
1U_0402_6.3V7K
p
1U_0201_6.3V6M
1U_0402_6.3V7K
2
PR321 1 2 0_0402_5% BMON_ISL95520 7 18
@ PC11222
2
1
1
PC216
2
@ PC11221
BMON DCIN 4
PC215
680P_0402_50V7K
8 17
BATGONE
PC217
PSYS NTC
1
1
2
2
2
CCLIM
ACLIM
COMP
PROG
AGND
CSON
CSOP
PR323
FSET
1
PC219 @ 100K_0402_1%
3
2
1
2
1
RF@
PC218 1000P_0402_25V8J
PD102
33
10
11
12
13
14
15
16
1000P_0402_25V8J Follow adapter and PR324 10_1206_5% 3
+19V_VIN
2
battery wattage in 1 2 1
3
Close to Vsys current source. 2 PQ307
m
1
2
EC.
FSET_CHG
PC220
VF = 0.38V
1U_0603_25V6
Base on CPU Core VR design. LMUN5113T1G_SOT323-3
2
PR326
0_0402_5%
The resistor is pop on CPU VR schematic.
1
@PR3360
0_0402_5% LRB715FT1G_SOT323-3
1
PR325
10K_0402_1%
2
1
VDD_CHG
VDD=5V
1
2
BA
1
CCLIM_CHG
2
200K_0402_1%
<10,34> PM_SLP_S4#
1
<34> VCOUT1_PROCHOT# ACLIM_CHG

A31 connect to BA
PR328
PR329
200K_0402_1%
PROG_CHG CSOP_CHG 1 2 CSOP_CHG_R Other team connect to bat t
PQ311
conn
3
COMP_CHG PR331 2_0402_5% LTC015EUBFS8TL_UMT3F
2
1
100_0402_1%
@ PR332 Fs=729KHZ ~ +/- 15% PC221 BA

1
C
0_0402_5%
76.8K_0402_1% 0.1U_0402_25V6
2
1 2
PR333
@ PR334
1
CSON_CHG 1 2 CSON_CHG_R
560P_0402_50V7K
1
@ @ PR336
PR335
PC222
150K_0402_1%
PQ310 0_0402_5%
76.8K_0402_1%
2
1
D
2
1
4
VCIN1_AC_IN
2 PR338 Turn off Charger IC on battery only.
4
0.022U_0402_25V7K
2
PR337
G 115K_0402_1% @ Depend on customer design for

1
VCIN1_BATT_TEMP <34,40>
S system power consumption.
3
L2N7002WT1G_SC70-3 BATGONE(BATT_TEMP)
2
logic high: above 2.4V

2
2
PC223
(Rs1 = 10mΩ and Rs2 = 5mΩ or Rs1 = 20mΩ and Rs2 = 10mΩ) . Hybrid boost power mode logic low: under 0.8V
2
CC_LIM = VccLIM / 64 x Rs2 Cell = 4s(1:1)

============================================================= PC224
10P_0402_25V8J
(Rs1 = 10mΩ and Rs2 = 10mΩ or Rs1 = 20mΩ and Rs2 = 20mΩ) .
1
CC_LIM = VccLIM / 32 x Rs2

=============================================================
Issued Date 2017/11/09 2018/11/09 Title
AC_LIM = Vac_LIM / 32 x Rs1 Adapter current limimed:
For U22(45W)_adp: Battery current limimed by CCLIm ~ 5.7A(115K).
Deciphered Date
PWR_CHARGER
PR337=53.6k Adapter current limimed by ACLIm ~ 3.3A(53.6K). AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
For U23e(65W) and DIS_adp: (PR779 and PQ741 are for change ACLIm when AC in) DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-F971P 2.0
PR337=76.8k MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A B C D
A B C D E

SY8286B_V1.mdd
o
keep short pad,
snubber is for EMI only.
B+ PU401
1 1
v
EMI@ PL902 SY8286BRAC_QFN20_3X3 @ PR402 PC402
0_0402_5% 0.1U_0402_25V7K
+19VB_3V BST_3V BST_3V_R
2200P_0402_50V7K
1 2 1 2 1 2 Use 7x7x3 size when the layout space is enough.
10P_0402_25V8J
10U_0603_25V6M
S SUPPRE_ 5A Z80 20M 0805
EMI@ PC401
EMI@ PC403
0.1U_0402_25V6
@RF@ PC11147
1
PL401
PC404
1.5UH_6A_20%_5X5X3_M
BS
IN
IN
IN
IN
o
2
2
LX_3V6 20 LX_3V 1 4
LX LX +3VALWP
7 19 2 3
4.7_1206_5%
GND LX
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10P_0402_25V8J
RF@ PR403
1
@RF@ PC11154
8 18
+3VLP GND GND 3.3V LDO 150mA~300mA
PC405
PC406
PC407
PC408
n
9 17
2
PG LDO +3VLP
4.7U_0402_6.3V6M
1
10 16
PC409
@
1 3V_SN2
NC NC
1
Check pull up resistor of SPOK at HW side
OUT
EN2
EN1
21
NC
FF
2
GND
680P_0603_50V7K
PR401
PC410 RF@
100K_0402_5%
11
12
13
14
15
2
Vout is 3.234V~3.366V
<34,37,38,44> 3V/5VALW_PG
2
ENLDO_3V5V PC411 PR404
1000P_0402_25V8J 1K_0402_1%
L
5V_3V_EN 3V_FB 1 2 3V_FB_1 1 2
EN1 and EN2 dont't be floating.

EN :H>0.8V ; L<0.4V Fsw : 600K Hz
2 2
r
SY8286C_V2_single.mdd
SY8286C_V2_dual.mdd @ PJP402
1 2
keep short pad, +3VALWP 1 2 +3VALW
o
2 Cell battery : Cin=10uF*2pcs snubber is for EMI only. JUMP_43X118
3 Cell ~ 4 Cell battery : Cin=10uF*1pcs
B+ +19VB_5V @ PJP403
@ PR405 PC412 JUMP_43X39
EMI@ PL903 PU402 SY8288CRAC_QFN20_3X3 1 2
0_0402_5% 0.1U_0402_25V7K
1 2 +19VB_5V BST_5V1 2 BST_5V_R 1 2 +3VLP 1 2 +3VL
1
F
BS
IN
IN
IN
IN
LX_5V 6
2200P_0402_50V7K
10U_0603_25V6M
10U_0603_25V6M
0.1U_0402_25V6
20
LX LX PL402
10P_0402_25V8J
7 19 LX_5V 1 4
@RF@ PC11146
+5VALWP
l
GND LX
1
1
PC413
PC414
EMI@ PC415
EMI@ PC416
8 18 2 3
GND GND PC417
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
2
1
9 17 VCC_5V 1 2
RF@ PR407
PG VCC 3.3UH_6.3A_20%_7X7X3_M
PC422
PC418
PC423
PC419
PC420
PC421
PR406
4.7_1206_5%
499K_0402_1% 10 16
a
2
2
1 2 ENLDO_3V5V NC NC 4.7U_0402_6.3V6M
B+ OUT
LDO
EN2
EN1
21
FF
GND
1
150K_0402_1%
2
PR408
3 3
11
12
13
14
15
1
+5VLP
4.7U_0402_6.3V6M
1 5V_SN
PC11155 3V/5VALW_PG
p
1U_0201_6.3V6M 1 5V LDO 150mA~300mA
2
680P_0603_50V7K
PC424
ENLDO_3V5V
RF@ PC425
2
2
5V_3V_EN
PR410
Vout is 4.998V~5.202V
2.2K_0402_5%
1 2
<34> EC_ON EN1 and EN2 dont't be floating. PC426 PR412
TDC=6A Iocp=10A
m
EN :H>0.8V ; L<0.4V 1000P_0402_25V8J 1K_0402_1%
1 2 5V_FB 1 2 5V_FB_1 1 2
<34> VCOUT0_MAIN_PWR_ON PR411
0_0402_5%
5V_3V_EN
o
1M_0402_1%
4.7U_0402_6.3V6M
1
1
PR413
PC427
2
2
@ PJP405
C
1 2
+5VALWP 1 2 +5VALW
JUMP_43X118
4 @ PJP406 4
JUMP_43X39
1 2
+5VLP 1 2 +VL

PWR- 3VALW/5VALW-SY8286B&C
A B C D E
A B C D E
Pin19 need pull separate from +1.35VP. 0.675Volt +/- 5%

If you have +1.35V and +0.675V sequence question, TDC 0.7A
EMI@ PL501 you can change from +1.35VP to +1.35VS.
B+ Peak Current 1A
o
1 2 +19VB_DDR PR501
2.2_0603_5%
BST_DDR_R 1 2 BST_DDR
10P_0402_25V8J
2200P_0402_50V7K
10U_0603_25V6M
10U_0603_25V6M
0.1U_0402_25V6
+1.2VP
RF@ PC11148
1
@EMI@ PC501
EMI@ PC502
PC503
PC504
UG_DDR +0.6VSP
2
1 1
v
LX_DDR
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
PC505
PC11212
0.1U_0402_25V7K
PC506
PC507
16
17
18
19
20
PU501
2
BOOT
VTT
VLDOIN
PHASE
UGATE
21 @
PQ501 PAD
1
AONH36334_DFN3X3A8-10 LG_DDR
o
15 1
LGATE VTTGND
D1
D1
D1
G1
14 2
10 9 PR502 PGND VTTSNS
PL502 D1 D2/S1 8.06K_0402_1%
4 1 LX_DDR 1 2 CS_DDR 13 3
+1.2VP PC508 CS RT8207PGQW_WQFN20_3X3 GND
G2
S2
S2
S2
3 2 1U_0402_10V6K
2VDDP_DDR12 VTTREF_DDR
n
1 4
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
8
PR504 VDDP VTTREF
1UH_6.6A_20%_5X5X3_M
1
5.1_0603_5%
PC509
PC510
PC511
PC512
PC513
PC514
1 2 VDD_DDR 11 5
+5VALW VDD VDDQ +1.2VP
1
PGOOD
2
2
PC516
+5VALW PR505
TON
1
RF@ PR503 0.033U_0402_16V7K
FB
S5
S3
2
4.7_1206_5% PC517 1 2
e
1U_0402_10V6K 5.1_0603_5%
1 2
10
6
SNB_1.2VP
RF@ PC515
FB_DDR
EN_DDR
TON_DDR
680P_0402_50V7K
EN_0.6VSP
PR507
2
1 2 +1.2VP
PR508 470K_0402_1%
+19VB_DDR 1 2
6.04K_0402_1%
1
L
PR509
PR510 0_0402_5% 10K_0402_1%
1 2
<13,34,44> SYSON
2
MOSFET: 3x3 DFN
1
@ PC518
2 H/S Rds(on): 27mohm(Typ), 34mohm(Max) 0.1U_0402_10V7K 2
Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C
2
L/S Rds(on): 19mohm(Typ), 23.5mohm(Max)
r
Mode Level +0.675VSP VTTREF_1.35V @ PR511
Idsm: 11A@Ta=25C, 8.8A@Ta=70C 0_0402_1%
S5 L off off 1 2 @ PJ501
S3 L off on Choke: 7x7x3 <13,34,38> SUSP# +1.2VP 1 2 +1.2V
1 2
S0 H on on Rdc=6.7mohm(Typ), 7.4mohm(Max) JUMP_43X118
PR518
Note: S3 - sleep ; S5 - power off Switching Frequency:540kHz 1 2
<7> DDR_VTT_PG_CTRL
Ipeak=8A
o
1
0_0402_5%
Iocp~9.6A @ PC519
OVP: 113%~120% 0.1U_0402_10V7K PJ503 @
2
VFB=0.75V, Vout=1.203V 1 2
+0.6VSP 1 2 +0.6VS
JUMP_43X39
l F
a
3 3
mp
4
Compal Secret Data
Deciphered Date 2017/6/2 Title
Size
Custom
+1.2VP/+0.6VSP/+2.5VP
Document Number
SKL
Re v
2.0
4

A B C D E
A B C D
+3VALW +5VALW
Ultra Low Dropout 0.23V(typical) at 3A Output Current
1U_0402_6.3V7K
PC601
1
JUMP_43X79
o
2
2
@ PJ701
2
1 1
PU601
v
1
PC602 G9661MF11U_SO8
10U_0402_6.3V6M
PR601 4 5
2
0_0402_5% 3 VPP
VIN
NC
VO
6 +1.8VALWP
1
1 2 2 7
12.4K_0402_1%
0.01U_0402_25V7K
GND
<34,37,38,42> 3V/5VALW_PG VEN ADJ
1
1 8
o
POK GND
PR603
PC603
22U_0603_6.3V6M
1
1
Rup
0.1U_0402_16V7K
1
PC604
PR604
PJP602
2
2
PC605
1M_0402_5%
@
2
1 2
2
@ PR3345 +1.8VALWP 1 2 +1.8VALW
2
n
100K_0402_5%
JUMP_43X39
10K_0402_1%
1
PR605
Rdown
e
2
+3VALW
PGOOD <45>
Vout=0.8V* (1+Rup/Rdown)
+3VALW +5VALW
r L 2
o
1U_0402_6.3V7K
1
PC11203
1
F
JUMP_43X79
2
@ PJ702
2
2
l
PU904
1
PC11206 G9661MF11U_SO8
10U_0402_6.3V6M
4 5
2
PR3351 0_0402_5% 3 VPP

VIN
NC
VO
6 +1.8VP_MEM
1
1 2 2 7
12.4K_0402_1%
0.01U_0402_25V7K
GND
a
<13,34,43> SYSON VEN ADJ
1
1 8
POK GND
PR3354
PC11205
22U_0603_6.3V6M
1
Rup
0.1U_0402_16V7K
2
@ PC11202
1
PR3353
2
3 3
PC11204
1M_0402_5%
2
p 2
PJP904
2
@
1
10K_0402_1% 1 2
+1.8VP_MEM 1 2 +1.8V_MEM
PR3352
JUMP_43X39
Rdown
2
o m Vout=0.8V* (1+Rup/Rdown)
=0.8*(1+(12.7/10))
Vout=1.816V
C A B
Compal Secret Data
Deciphered Date
C
2017/6/2 Title

Custom
Date:
+1.8V_PRIM

D
Sheet 44 of 54
R ev
2.0
4
5 4 3 2 1
v o D
o
SY8286_V1_single.mdd
SY8286_V1_dual.mdd
n
+19VB_1.05V keep short pad, RF@ PR702 RF@ PC702
snubber is for EMI only. 4.7_1206_5% 680P_0603_50V7K
1 2 SNUB_1.05V 1 2
e
PU701
@ PJP701
+19VB_1.05V
B+ 1
1 2
2 2
IN PG
9 @ PR703
0_0402_5%
PC704
0.1U_0402_25V7K
Use 7x7x3 size when the layout space is enough.
10U_0603_25V6M
10P_0402_25V8J
0.1U_0402_25V6
3 1 BST_1.05V 1 2 BST_1.05V_R 1 2
@RF@ PC11149
2200P_0402_50V7K
JUMP_43X79 IN BS PL701
1
EMI@ PC701
EMI@ PC703
PC705
4 6 LX_1.05V 1 2
IN LX +1.05VALWP
2
5 19 1UH_MMD-05AHN1R0M-X2L_8A_20%
15K_0402_1%
330P_0402_50V7K
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
IN LX
1
L
1
7 20
PR704
PC706
PC707
PC708
PC709
PC710
GND LX
8 14 FB_1.05V R1
2
GND FB
PR701
2
18 17 LDO_3V
0_0402_5% GND VCC
1U_0402_6.3V7K
EN_1.05V
1U_0402_6.3V7K
C 2 1 11 10 C
PC11213
PC711
<44> PGOOD EN NC
FB=0.6V
1
ILMT_1.05V 13 12
r
2
2
ILMT NC
1
@ PC712
PR705 15 16 PR706
1M_0402_1%
0.1U_0402_25V6 +3VALW BYP NC Vout=0.6V* (1+R1/R2) R2 20K_0402_1%
2
LDO_3V
21 =0.6*(1+(15/20))
2
PAD
1U_0402_6.3V7K
2
EN :H>0.8V ; L<0.4V SY8286RAC_QFN20_3X3

Vout=1.05V
PC713
o
@ PJP702
EN pin don't floating
2
JUMP_43X118
2
If have pull down resistor at HW side, PR707 @
+1.05VALWP
1
1 2
2
+1.05VALW
please delete PR601. 0_0402_5%
1
The current limit is set to 6A, 9A or 12A when this pin

is pull low, floating or pull high.
l F
B
p
+3VALW +5VALW
a
B
1
1U_0402_6.3V7K
PC11208
1
@VGA@ PJ703
JUMP_43X39
2
2
2
VGA@ PU905
m
1
VGA@ PC11211 G9661MF11U_SO8

PR3356 10U_0402_6.3V6M
4 5
0_0402_5%
2
3 VPP
VIN
NC
VO
6 +1.0VS
1
1 2 2 7
10K_0402_1%
GND
<24,26> 1.0VS_DGPU_EN
0.01U_0402_25V7K
VGA@ PR3359
VEN ADJ
1
1 8
POK GND
VGA@ PC11209
22U_0603_6.3V6M
1
o
Rup
0.1U_0402_16V7K
VGA@ PR3358
VGA@ PC11207
@VGA@ PJP905
2
1M_0402_5%
VGA@ PC11210
2
1 2
2
+1.0VS 1 2 +1.0VS_DGPU
2
JUMP_43X39
38.3K_0402_1%
VGA@ PR3357
Rdown
C
2
A A
Vout=0.8V* (1+Rup/Rdown)
=0.8*(1+(10/38.3))
Vout=1.008V
+1.0VS
C 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Z_SKL
5 4 3 2 1
1 2 3 4 5

Close IC
PRZ1 and PRZ22 are for debug only. RT3602AE_U22_RU42_colay_V1A.mdd for IC portion
VCCSSA_SENSE and VSSSA_SENSE need other resistor at HW side.
RT3602AE_U22_RU42_colay_V1B.mdd for SW portion
o
RT3602_VREF Vref=0.6V +VCCSA @ PRZ1 PRZ8 PRZ10
100_0402_1% 10K_0402_1% 100K_0402_1% PCZ3
1 2 VCCSA_SENSE_R 1 2 1 2 0.1U_0402_50V7K
1
6.19K_0402_1%
6.19K_0402_1%
19.1K_0402_1%
PRZ15
1 2 1 2
2
1
1
<13> VCCSA_SENSE
1 2 ISENSE1P_SA_R1 <47>
<47> ISENSE1N_SA
@ PCZ200 PCZ5 390P_0402_50V7K PCZ6 68P_0402_50V8J
PRZ2
PRZ3
PRZ4
0_0402_5% 0.1U_0402_25V6
2
A @ PCZ1 @ PRZ16 A
FB_SA FB_SA
v
0.1U_0402_10V6K 10K_0402_1% @ PCZ4
1
1 2 1 2 0.47U_0402_25V6K
@ PCZ203 1 2
1
0.1U_0402_25V6
6.19K_0402_1%
6.19K_0402_1%
19.1K_0402_1%
0.47U_0402_25V6K
2
PRZ94
Close IC RT3602_VREF
PRZ6
PRZ11
PCZ193
1
0_0402_5% 1 2 1 2
PRZ5
1 2
<13> VSSSA_SENSE PRZ13 PRZ14
2
RT3602_SET1
2
1
@ PRZ22 28K_0402_1% 0_0402_5%
RT3602_SET2 1 2 @ PCZ199
RT3602_SET3 Close IC
o
0.1U_0402_25V6
RT3602_VREF 3.9_0402_1%
2
1
100_0402_1% PRZ95
PRZ24
VR_PSYS 0_0402_5%
PRZ23 +3VS
1
<15> VSSCORE_SENSE 1 2 100K_0402_1%
10K_0402_1%
1.37K_0402_1%
1.37K_0402_1%
9.09K_0402_1%
1 2
Close CORE1 choke
PRZ18
PRZ19
PRZ20
2
@
PRZ17
PRZ21
@ PHZ1 PRZ26 1 2
VR_PWRGD <34> EN
2
1
PRZ107 100K_0402_1%_B25/50 4250K 0_0402_5% PRZ25 High: > 0.7V
@ PCZ7 1 2PHZ1_R1 1 2 PHZ1_R 1 2 100_0402_1% 0_0402_5%
n
0.1U_0402_25V6
RGND_MAIN 1 2
VR_ON
Low: < 0.3V
<34>
2
RT3602_VREF
1
1
43.2K_0402_1%
1.37K_0402_1%
1.37K_0402_1%
9.09K_0402_1%
+1.05V_VCCST
IMON_SA
PRZ29
PRZ30
1 2 IMON_CORE_R 1 2
RT3602_EN
PRZ28
VSEN_CORE
RGND_MAIN
FB_SA
PRZ33 PRZ35
COMP_SA
RGND_SA
VR_PSYS
24K_0402_1% 732_0402_1% @ PCZ206
2
1
@ PCZ204 @ PCZ201 0.1U_0402_25V6
PCZ194
110_0402_1%
0.1U_0402_25V6
1
1
0.1U_0402_25V6 0.1U_0402_25V6 1 2
75_0402_1%
100_0402_1%
45.3_0402_1%
1
@ PCZ9
PRZ37
e
2
@ PCZ8 @ PRZ40 0.1U_0402_10V6K
PUZ1
2
0.1U_0402_10V6K 10K_0402_1% 1 2
49
48
47
46
45
44
43
42
41
40
39
38
37
PRZ36
PRZ38
PRZ39
RT3602AJGQW_WQFN48_6X6
2
1 2 1 2 @
Close IC
2
PRZ43 PRZ45
GND
RGND_MAIN
VSEN_MAIN
EN
PSYS
FB_SA
RGND_SA
COMP_SA
ISENN_SA
ISENP_SA
IMON_SA
VR_READY
VREF06/PSET
10K_0402_1% 31.6K_0402_1% VR_SVID_CLK <15>
@ VSEN_CORE 1 2 1 2 <47> IMON_CORE VR_ALERT# <15>
+VCCCORE PRZ41
IMON_CORE VR_SVID_DATA <15>
100_0402_1% PCZ12 82P_0402_50V8J 1 36 PWM_SA <47>
1 2 1 2 1 2 2 RT3602_SET1 IMON_MAIN PWM_SA 35 VR_HOT# <34>
FB_CORE SET1 DRVEN DRVEN_CPU <47>
PRZ47 3 34 1 2
0_0402_5% PCZ13 4 COMP_CORE FB_MAIN VCLK 33 PRZ98 49.9_0402_1% RT3602_VREF
<47> ISENSE1N_CORE
1 2 PCZ11 150P_0402_50V8J 0.1U_0402_50V7K 5 RT3602_SET2 COMP_MAIN ALERT 32 PRZ99 1 210_0402_1% PRZ48
<15> VCCCORE_SENSE Ra RT3602_SET3 SET2 VDIO
L
1 2 6 31 1
PRZ100 2
100_0402_1% 23.7K_0402_1% PRZ49 0_0402_5%
SET3 VR_HOT IMON_GT
1
U42@ PRZ106 7 30 1 2 1 2
@ PCZ196 1 2 1 2 ISEN1N_MAIN 8 ISEN1N_MAIN IMON_AUXI 29 @ PCZ15 0.47U_0402_25V6K
Close IC
U42@ 0_0402_5% 9 ISEN2N_MAIN ISENP_AUXI 28 1 2
0.1U_0402_25V6
2
PCZ16 0.1U_0402_50V7K 10 ISEN2P_MAIN ISENN_AUXI 27 VSEN_GT

<47> ISENSE2N_CORE TSEN_CORE 11 ISEN1P_MAIN VSEN_AUXI COMP_GT
26 PRZ50
RT3602_VIN 12 TSEN_MAIN COMP_AUXI ISENSE1P_GT_R1 <47>
25 0_0402_5%
Rb VIN RGND_AUXI ISENSE1N_GT <47>
PWM2_MAIN
PWM1_MAIN
DRVEN_SET
B 1 2 B
TSEN_AUXI
PWM_AUXI
+5VALW VSEN_GT
RGND_AUXI
U22@ PRZ105 10K_0402_1% 1 2 1 2 VCCGT_SENSE <15>
FB_AUXI
0.22U_0402_25VAK
1
1
PCZ18
2.2_0805_1%
<47> ISENSE2P_CORE_R1
0.1U_0402_25V6 PRZ56 @ PRZ59
PRZ41 and PRZ21 are for debug only. PRZ54
VCC
10K_0402_1% 100_0402_1% +VCC_GT
NC
NC
NC
NC
NC
37.4K_0402_1%
Rc
PRZ53
PCZ19
r
2
VCCCORE_SENSE and VSSCORE_SENSE need other resistor +5VALW
1 2 1 2 1 2 1 2
U22@ PRZ104 10K_0402_1%
at HW side.
13
14
15
16
17
18
19
20
21
22
23
24
1
<47> ISENSE1P_CORE_R1
1 2 1 2 @ PCZ198
DRVEN_SET
RT3602_VREF
TSEN_GT
FB_GT
PRZ51 PRZ52
Ra Rb/Rc 0.1U_0402_25V6
RT3602_VCC
2
110K_0402_1% 1.65K_0402_1% PCZ20 82P_0402_50V8J PCZ21
TSEN_CORE_R 1 2 1 2 270P_0402_50V7K
+19VB_CPU
PHZ2
U22 N/A Stuff
1
1 2 1 2 1 2
8.06K_0402_1%
o
@ PCZ202
1
FB_GT
@ PRZ61 @ PCZ22 0.1U_0402_25V6
6.49K_0402_1% 6.49K_0402_1%
100K_0402_1%_B25/50 4250K
2
10K_0402_1% 0.1U_0402_10V6K
U42 Stuff N/A
PRZ64
PRZ63
<47>
PWM_GT
Close CORE1 MOSFET
<47>
<47>
PWM_CORE2
PWM_CORE1
+5VALW PRZ65
Close IC
2
8.2_0402_1%
1 2
8.06K_0402_1%
PRZ93
1
U22@ PRZ68 1 2
PRZ68
VSSGT_SENSE <15>
PRZ67
1K_0402_1%
1
F
0_0402_5%
1
+5VALW PCZ23
2
1
4.7U_0402_6.3V6M PRZ66
TSEN_CORE_R TSEN_GT_R
2
110K_0402_1% @ PCZ197 @ PRZ60
1
100K_0402_1%_B25/50 4250K
0.1U_0402_25V6 100_0402_1%
2
1
2
1
@ PRZ72
8.66K_0402_1%
11.8K_0402_1%
PRZ71
10K_0402_5%
U22@ PRZ71
PRZ70
1
71.5K_0402_1%
PHZ3
2
DRVEN_SET PRZ69
2
l
1.65K_0402_1%
2
1
PRZ75
8.66K_0402_1%
11.8K_0402_1%
PRZ74
10K_0402_5%
Close GT MOSFET
PRZ73
TSEN_GT_R
PRZ59 and PRZ60 are for debug only.
2
2
VCCGT_SENSE and VSSGT_SENSE need other resistor
a
at HW side.
C
Set DRVEN output function at PS4. Set to 5V DRVEN C
is floating, and set to GND DRVEN is low at PS4.
mp
D
Compal Secret Data
Deciphered Date 2019/09/01 Title
Size
CPU_CORE
Document Number Re v
0.2
D

1 2 3 4 5
5 4 3 2 1
o
PUZ2
PUZ3
15 14
16 VSWH VSWH 13 15 14
VSWH VSWH 16 VSWH VSWH 13
17 12 VSWH VSWH
18 VSWH VSWH 11 +19VB_CPU 17
VSWH VSWH
12
19 VSWH VSWH 10 @ 18 11 +19VB_CPU
PJZ1 VSWH VSWH
20 VSWH PGND 9 PCZ28 B+ 19
VSWH PGND
10
21 VSWH VIN 8 0.1U_0402_25V6 1 2 20 9 PCZ208
VSWH VIN 1 2 21 VSWH VIN 8 0.1U_0402_25V6
D 22 7 1 2 VSWH VIN D
+5VALW GL VSWH 22 7 1 2
v
PRZ108 23 6 GL VSWH
10U_0603_25V6M
10U_0603_25V6M
JUMP_43X118 +5VALW
33U_D1_25VM_R6M
33U_D1_25VM_R6M
33U_D1_25VM_R6M
2200P_0402_50V7K
PGND NC PRZ111 23 6
PCZ37
PCZ34
1 2 24 5 2 1
@EMI@ PCZ29
EMI@ PCZ30
PCZ31
PCZ32
1 1 1
10U_0603_25V6M
10U_0603_25V6M
PGND NC
2200P_0402_50V7K
0.1U_0402_25V6
PVCC BOOT 1 2 24 5 2 1
@EMIU42@ PCZ36
EMIU42@ PCZ33
25 4 PVCC BOOT
0.1U_0402_25V6
1
1
5.1_0402_1% 26 NC NC 3 + + + 25 4
PCZ215
PCZ216
PCZ217
PRZ76 NC NC
1
NC VCC 2.2_0603_5% 5.1_0402_1% 26 3
27 2 NC VCC DRVEN_CPU PRZ109 2.2_0603_5%
28 GL FCCM 1 27 2
1
GL FCCM
2
AGND PWM 2 2 2 28 1
2
PCZ207 PCZ210 AGND PWM
1U_0402_10V6K AOZ5038QI_QFN31_5X5 1U_0402_10V6K
2
2
AOZ5038QI_QFN31_5X5
o
<46> PWM_CORE1 Rdc=0.9mohm +VCCCORE Rdc=0.9 mohm
<46> DRVEN_CPU PLZ1
<46> PWM_CORE2 +VCCCORE
PLZ2
1 4
1 4
ISENSE1P_CORE 2 3 ISENSE2P_CORE 2 3
330U_B2_2.5VM_R9M
@EMI@ PRZ82
330U_D1_2VY_R9M
+5VALW
4.7_1206_5%
2
1
1 1
@EMI@ PRZ84
+5VALW
4.7_1206_5%
2
1
1 PRZ80 2
1M_0402_1%
0.15UH_NA__35A_20%
n
PRZ110
1M_0402_1%
PRZ113
+ + 1 2 0.15UH_NA__35A_20%
PCZ211
PCZ213
PRZ114
5.1_0402_1%
Can be closed to choke 5.1_0402_1%
2 2
1CORE1_SNUB 2
1
PCZ42
1CORE2_SNUB 2
PCZ40 0.1U_0402_25V6 PRZ87 PRZ103 U42@ PCZ43
ISENSE1P_CORE_R PCZ209
1U_0402_10V6K 1 2 1 2 1 2 619_0603_1% 619_0603_1% 0.1U_0402_25V6
2
2
1U_0402_10V6K 2 ISENSE2P_CORE_R
2
1 1 2 1 2
47P_0402_50V8J
PCZ219
47P_0402_50V8J
PRZ85 PRZ102 PRZ88
PCZ218
e
PRZ90
1
619_0603_1% 619_0603_1% 536_0402_1%
1
1 2 536_0402_1%
@EMI@ PCZ44
IMON_CORE
1 2
@EMI@ PCZ45
<46>
680P_0603_50V7K
IMON_CORE
680P_0603_50V7K
Can be closed to choke
2
ISENSE2N_CORE <46>
ISENSE1N_CORE <46>
ISENSE2P_CORE_R1 <46>
L
ISENSE1P_CORE_R1 <46>
C C
r
+19VB_CPU VCC_CORE
FSW=450kHz VCC_GT VCC_SA
Choke=0.15uH FSW=450kHz FSW=600kHz
DCR=0.9mohm +/- 5% Choke=0.15uH DCR=6.2 mohm +/- 5%
DCR=0.9 mohm +/- 5%
PCG5
PCG6
10U_0603_25V6M
10U_0603_25V6M
2200P_0402_50V7K
PCG3
PCG4
U22
0.1U_0402_25V6
U22
1
o
LL=2.4 mohm U22 LL=10.3 mohm
LL=3.1 mohm TDC=4A
EMI@
@EMI@
TDC=21A
2
ICCMAX=32A TDC=18A ICCMAX=4.5A
OCP=40A ICCMAX=31A OCP=9.5A
PUZ4
OCP=39A
15 14 U42 U42
16 VSWH VSWH 13
Rdc=0.9 mohm +VCC_GT U42 LL=10.3 mohm
PLG1 LL=2.4 mohm
F
17 VSWH VSWH 12
18 VSWH VSWH 11 GT_LX 1 4 TDC=42A LL=3.1 mohm TDC=
VSWH VSWH
19
20 VSWH PGND
10
9 ISENSE1P_GT 2 3 ISENSE1N_GT ICCMAX=64A TDC=12A ICCMAX=6A
PCG2
VSWH VIN ICCMAX=31A OCP=9.5A
330U_D1_2VY_R9M
21 8 0.1U_0402_25V6
@EMI@ PRG4 1 OCP=70A
4.7_1206_5%
VSWH VIN
1
+5VALW PRZ112
22
23 GL VSWH
7
6 PRG2
2 1
0.15UH_NA__35A_20% +
OCP=39A
PCZ212
1 2 24 PGND NC 5 1 2
25 PVCC BOOT 4 2.2_0603_5%
5.1_0402_1% 26 NC NC 3 2
2
27 NC VCC 2 DRVEN_CPU PRG6 PRG9 PCG8
l
1
28 GL FCCM 1 604_0402_1% 604_0402_1% 0.1U_0402_25V6

PCZ214 AGND PWM 1 2 ISENSE1P_GT_R 1 2 1 2
1GT_SNUB
1U_0402_10V6K
2
AOZ5038QI_QFN31_5X5 PRG7 PRG8

330_0402_1% 255_0402_1%
Can be closed to choke 1 2 1 2
@EMI@ PCG9
AVGT1_R
680P_0603_50V7K
a
2
1 2
Close GT choke
+5VALW
<46> PWM_GT PHG1
1K_0402_5%_TSM0B102J3652RE
B
1 PRG1 2 VCC_GT ISENSE1N_GT <46> B
5.1_0402_1%
1
p
ISENSE1P_GT_R1 <46>
PCG1
1U_0402_10V6K
2
+19VB_CPU
m
10U_0603_25V6M
10U_0603_25V6M
2200P_0402_50V7K
PRA2
@EMI@ PCA6
PCA2
0.1U_0402_25V6
2.2_0603_5%
SA_BST SA_BST_R
1
1 2
PCA4
PCA5
1
EMI@
2
PCA3
PUA1
0.1U_0402_25V6
2
4 3 SA_UG
BOOT UGATE
o
5 2 SA_LX
<46> PWM_SA PWM PHASE
1
+5VALW DRVEN_CPU 1 6 PQA1 Rdc=6.2 mohm

G1
D1
D1
D1
EN PGND AONH36334_DFN3X3A8-10 +VCCSA

1 2 VCC_SA 8 7 PLA1
VCC LGATE 9 9 10
GND D2/S1 D1 1 4
PRA1 5.1_0402_1%
ISENSE1P_SA 2 3
RT9610CGQW_WDFN8_2X2
1
@EMI@ PRA4
G2
S2
S2
S2
4.7_1206_5%
1
PCA1
1U_0402_10V6K 0.47UH_MHCI05012B-R47M-R8A_7A_20%
2
SA_LG
Can be closed to choke
C
2
PCA7
0.1U_0402_25V6
ISENSE1P_SA_R
1 SA_SNUB
1 2 1 2 1 2
PRA6 PRA9 PRA7 PRA8

A 422_0603_1% 422_0603_1% 280_0402_1% 300_0402_1% A
1 2 1 2
@EMI@ PCA8
AVCCSA_R
680P_0402_50V7K
Close SA choke
2
1 2
PHA1
1K_0402_5%_TSM0B102J3652RE ISENSE1N_SA <46>
ISENSE1P_SA_R1 <46>
3650K

CPU Power stage
Size Document Number Re v
5 4 3 2 1
A
B
C
D
+VCCCORE
@RF@ PC11150
10P_0402_25V8J
5
5
2 1
2 1 2 1 2 1 2 1
2
1
PC2086 PC2076 PC2031 PC2021 PC2001

1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
2
1
PC2087 PC2077 PC2032 PC2022 PC2002

2 1 2 1 2 1 2 1
2
1
C
PC2088 PC2078 PC2033 PC2023 PC2003
2 1 2 1 2 1 2 1
2
1
PC2089 PC2079 PC2034 PC2024 PC2007

2 1 2 1 2 1 2 1
2 1
PC2080 PC2035 PC2025 PC2008
PC2090 1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M
1U_0201_6.3V6M 2 1 2 1 2 1 2 1
o
PC2081 PC2036 PC2026 PC2010
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M
2 1 2 1 2 1 2 1
PC2082 PC2037 PC2027 PC2011

1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M
2 1 2 1 2 1 2 1
VCC_CORE Place on CPU Back Side @ V09
PC2083 PC2038 PC2028 PC2012

1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M
2 1 2 1 2 1
2
1
PC2084 PC2039 PC2029 PC1367

1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
4
4
m
PC2085 PC2040 PC2030 PC1368
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M
2 1
+VCCSA
22U_0603 * 12 pcs+10U_0402*26 pcs +1U_0201*35 pcs
PC1369
2 1 10U_0402_6.3V6M
2 1 2 1
PC11171
10U_0402_6.3V6M PC11168 PC1370
2 1 10U_0402_6.3V6M 10U_0402_6.3V6M
p
2 1 2 1
@ PC11169
RF@ PC11152 10U_0402_6.3V6M PC11167 PC11156
10P_0402_25V8J 2 1 10U_0402_6.3V6M 10U_0402_6.3V6M
+VCCSA
2 1 2 1 2 1
@ PC11170
10U_0402_6.3V6M PC11166 PC11157
2 1 10U_0402_6.3V6M 10U_0402_6.3V6M
2
1
2 1 2 1
a
PC1391 PC2103
22U_0603_6.3V6M 10U_0402_6.3V6M PC11165 PC11158
2 1 10U_0402_6.3V6M 10U_0402_6.3V6M
2
1
2
1
2 1
+VCCCORE
2
1
PC1392 PC2104 PC1352

22U_0603_6.3V6M 10U_0402_6.3V6M PC1361 22U_0603_6.3V6M PC11159
l 22U_0603_6.3V6M 10U_0402_6.3V6M
2
1
2
1
2
1
2 1 2 1
PC1394 PC1397 PC1359
22U_0603_6.3V6M 22U_0603_6.3V6M PC1362 22U_0603_6.3V6M PC11160
2 1 10U_0402_6.3V6M 10U_0402_6.3V6M
2
1
2 1 2 1
PC1398 PC1360
10U_0402_6.3V6M PC1363 22U_0603_6.3V6M PC11161
10U_0402_6.3V6M 10U_0402_6.3V6M
2
1
2 1 2 1
22U_0603 * 6
PC1396 2 1
22U_0603_6.3V6M PC1364 PC11162
PC2111 10U_0402_6.3V6M 10U_0402_6.3V6M
1U_0201_6.3V6M 2 1 2 1
3
3
2 1
2
1
PC1365 PC11226
PC1393 PC2112 10U_0402_6.3V6M 10U_0402_6.3V6M
22U_0603_6.3V6M 1U_0201_6.3V6M 2 1
F
2
1
2 1 2 1
PC1366 PC11227
PC2105 PC2113 22U_0603_6.3V6M 10U_0402_6.3V6M
10U_0402_6.3V6M 1U_0201_6.3V6M 2 1
2
1
2 1 2 1
PC2004 PC11223
PC2106 PC2114 22U_0603_6.3V6M 10U_0402_6.3V6M
10U_0402_6.3V6M 1U_0201_6.3V6M 2 1 2 1
Issued Date
2 1 2 1
PC2005 PC11225
o VCC_SA Place on CPU Back Side.
PC11172 PC2115 10U_0402_6.3V6M 10U_0402_6.3V6M
10U_0402_6.3V6M 1U_0201_6.3V6M 2 1
2
1
2 1 2 1
PC2006 PC11224
PC11173 PC2116 22U_0603_6.3V6M 10U_0402_6.3V6M
10U_0402_6.3V6M 1U_0201_6.3V6M 2 1
2 1
r
PC2009
PC2117 10U_0402_6.3V6M
1U_0201_6.3V6M 2 1
PC11163
10U_0402_6.3V6M
2016/6/2
2 1
PC11164
10U_0402_6.3V6M
+VCC_GT
pcs+10U_0402*10 pcs+ 1U_0201 * 7 pcs

L
2
2
+VCC_GT
Compal Secret Data
@RF@ PC11151 2 1 2 1 2 1
Deciphered Date
10P_0402_25V8J
2 1 PC2061 PC11178 PC1323
1U_0201_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M
2 1 2 1 2 1
2
1
2
1
2
1
PC2062 PC11179 PC2042

e
PC1301 PC1311 PC1321 1U_0201_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M

22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 2 1 2 1 2 1
2
1
2
1
PC2063 PC11180 PC2043

2
1
PC1312 PC1302 1U_0201_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M

PC1304 22U_0603_6.3V6M 22U_0603_6.3V6M 2 1 2 1 2 1
2017/6/2
22U_0603_6.3V6M
2
1
2
1
PC2064 PC11181 PC2044

2 1
PC1313 PC1303 1U_0201_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M

22U_0603_6.3V6M 22U_0603_6.3V6M 2 1 2 1 2 1
PC2041 2 1
n
2
1
10U_0402_6.3V6M PC2065 @ PC11182 PC2045

PC1314 PC1322 1U_0201_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M
2 1 22U_0603_6.3V6M 10U_0402_6.3V6M 2 1 2 1 2 1
2 1
C
2
1
@ PC1324 PC2066 PC11183 PC2046

VCC_GT Place on CPU Back Side.
10U_0402_6.3V6M PC1315 PC1305 1U_0201_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M

Size
Title
Date:
10U_0402_6.3V6M 22U_0603_6.3V6M 2 1 2 1 2 1
2
1
2
1
PC2067 PC11184 PC2047

2 1 PC1316 PC1306 1U_0201_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M
22U_0603_6.3V6M 22U_0603_6.3V6M 2 1 2 1 2 1
o
@ PC11174
2
1
2
1
10U_0402_6.3V6M PC2068 PC11185 PC2048

2 1 PC1317 PC1307 1U_0201_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M
22U_0603_6.3V6M 22U_0603_6.3V6M 2 1 2 1 2 1
Document Number
@ PC11175
2
1
2
1
10U_0402_6.3V6M PC2069 PC11186 PC2049

PC1318 PC1308 1U_0201_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M
22U_0603_6.3V6M 22U_0603_6.3V6M 2 1 2 1 2 1
1
1
2
1
2
1
PC2070 PC11187 PC2050

v
PC1319 PC1309 1U_0201_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M

22U_0603_6.3V6M 22U_0603_6.3V6M 2 1 2 1 2 1
2
1
2
1
PC2071 PC11189 PC2051

PC1320 PC1310 1U_0201_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M
Sheet
22U_0603_6.3V6M 22U_0603_6.3V6M 2 1 2 1 2 1
2 1 2 1
PC2072 PC11188 PC2052
48
PC11176 PC11177 1U_0201_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M

10U_0402_6.3V6M 10U_0402_6.3V6M 2 1 2 1 2 1
o
of
PC2073 PC11190 PC2053

1U_0201_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M
54
22U_0603 * 20pcs10U_0402*38 pcs +1U_0201*8pcs+ 0.47U_0201*4 pcs
PWR-PROCESSOR_DECOUPLING
Rev
2.0
A
B
C
D
5 4 3 2 1
D
R1, R2, R3, R4, R5, C are
based on VGA type to set.
OpenVReg Configurations:(PSI pin)
Operation phase Number
1 phase with DEM
PSI Voltage setting
0V to 0.4V
v o D
o
Vboot=Vvref*Rref2/(Rref1+Rref2+Rboot) 1 phase with CCM 0.7V to 0.88V
PL801 VGA_EMI@
Rt=Rrefadj // (Rboot+Rref2) 2 phase with DEM 1.08V to 1.35V VGA_B+
2 1
Vmin= Vvref*[Rref2/(Rref2+Rboot)]*[Rt/(Rref1+Rt)] 2 phase with CCM 1.6V to 5.5V B+
VGA_EMI@ PC804
10U_0603_25V6M
10U_0603_25V6M
0.1U_0402_25V6
n
2200P_0402_50V7K
@VGA_EMI@PC805
Vmax=Vvref*Rref2/[(Rref1//Rrefadj)+Rboot+Rref2] +1.8VS_DGPU_AON
1
VGA@ PC802
VGA@ PC803
DH1_VGA
Vout=Vmin+N*Vstep
1
PWM VID and Output voltage control
2
Vstep=(Vmax-Vmin)/Nmax @VGA@ PR41
1.Boot mode VGA@
e
10K_0402_1%
2.Standby mode (don't support) PQ801
1
VGA@PR3 3.Normal mode AON6962_DFN5X6D-8-7
2
1 2
D1
G1
<24> PSI
10K_0402_1%
VGA@ PL802
1
0_0402_5% 0.22UH_PCMB061HR22MS4R305_14A_20% +VGA_CORE
@VGA@ PR42
PR2 LX1_VGA
7 1 4
2 1 D2/S1
VGA_CORE_EN <24>
2 3
L
1
1
VGA@PR7
G2
2
S2
S2
S2
VGA@ PR4 0_0402_5%
330U_B2_2.5VM_R9M
330U_B2_2.5VM_R9M
330U_B2_2.5VM_R9M
R2 20.5K_0402_1%
High: >1.2V
1SNUB_VGA1
@VGA_EMI@
<24> GPU_VID0 1 2 1 1 1
Low: <0.55V PR811
5
DL1_VGA 6
R3 VGA@
NVVDDS_PSI_R
PR10 4.7_1206_5% + + +
VGA@ PC810
VGA@ PC809
VGA@ PC811
R1
NVVDDS_EN
0_0402_5% NVVDDS_VID
2
2
4.32K_0402_1%
C 1 2 1 2 DH1_VGA C
VGA_B+ 2 2 2
16.5K_0402_1%
VGA@ PR6 2.2_0603_5% PC812 @VGA_EMI@

1
r
10U_0603_25V6M
VGA@PR8
10U_0603_25V6M
680P_0402_50V7K
0.01U_0402_16V7K
BST1_NVVDDS 2BST1_NVVDDS-R
1
4700P_0402_50V7K
VGA@PR20
R4 6.19K_0402_1% 1 VGA@
2
VGA@ PC813
VGA@ PC814
1 PR813
1
1
DH2_VGA
@VGA@PC19
REFADJ_NVVDDS
PU1 9.1K_0402_1%
1
VGA@
VGA@ PC9
1 2
1
RT8816AGQW_WQFN20_3X3 PC8
2
2
2 VGA@
309_0402_1%
C 0.1U_0402_25V6
VID
PSI
EN
UGATE1
BOOT1
2
o
PQ802
VGA@ PR21
1
AON6962_DFN5X6D-8-7
R5 6 20 LX1_VGA Rocset
D1
G1
REFADJ PHASE1
2
VGA@ PL803
RGND_NVVDDS
REFIN_NVVDDS 7 19 DL1_VGA VGA@ LX2_VGA
+VGA_CORE
7 1 4
REFIN LGATE1 PR14 D2/S1
+VGA_CORE
1
1_0402_1% 2 3
F
VREF_NVVDDS 8 18 PVCC_NVVDDS 1 2 @VGA_EMI@ EDP-Continuous 26A
G2
+5VALW
S2
S2
S2
SNUB_VGA2
VREF PVCC
VGA@ PR816 EDP-Peak 45A
1
1
PC10 Close Vref pin VGA@ 0.22UH_PCMB061HR22MS4R305_14A_20%
VGA@PR13 4.7_1206_5% OCP min 54A
6
0.1U_0402_25V6 1 2 TON_NVVDDS9 17 DL2_VGA PC16
TON LGATE2
2
VGA@ PR26 2.2U_0603_16V6K
RGND_NVVDDS2
2
VGA_B+ 1 2 432K_0402_1% Rton LX2_VGA
OCSET_NVVDDSOCSET/SS
2.2_0805_5% 10 16
l
RGND PHASE2
1
DL2_VGA
UGATE2
1
RGND_NVVDDS
PGOOD
PC818 @VGA_EMI@
BOOT2
VSNS
VGA@ PC28 680P_0402_50V7K

GND
1U_0603_25V6K VGA@
2
2
VGA@PR15 PC22
<21> GND_SENSE_GPU 1 2 0.1U_0402_25V6
21
11
12
13
14
15
0_0402_5%
a
VGA@ PR16 PR9
Remark: 1 2 BST2_NVVDDS
1 2BST2_NVVDDS-R
DH2_VGA
1. Switching frequency setting:(Ton pin) 10_0402_5% VGA@ 2.2_0603_5%

1000P_0402_50V7K
36K_0402_1%
Fsw=(Vin-0.5)/(2*Vin*Rton*3.2p)
1
0.01U_0402_16V7K
B B
=352Khz 1 Current Limit threshold setting
VGA@ PR24
1
@VGA@ PC18
@VGA@ PC17
Rocset= (Ivalley * Rds(on) * 12) / Icoset
p
For debug only, PR17
HW side need other resister 10K_0402_5%
2
2 1 2
VGA@ PR19 +3VS
10_0402_5%
1 2
+VGA_CORE DGPU_PWROK <21,25> +VGA_CORE
original
0.1U_0402_25V 4pcs
Css
<21> VDD_SENSE_GPU 1 2
@VGA@ PR18
PC831
PC832
PC833
PC834
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0_0402_1%
1
m
2
2
@VGA_RF@
@VGA_RF@
@VGA_RF@
@VGA_RF@
4.7U_0402_6.3V 4pcs
10U_0603_6.3V 13pcs
o
+VGA_CORE Near GPU Core 4.7U_0402_6.3V 12pcs
1U_0402_16V 5pcs
GB4-128 package
10U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
VGA@ PC837
VGA@ PC839
VGA@ PC838
VGA@ PC840
10U_0402_6.3V6M
VGA@ PC886
VGA@ PC887
10U_0402_6.3V6M
10U_0402_6.3V6M
VGA@ PC883
VGA@ PC885
10U_0402_6.3V6M
VGA@ PC884
+VGA_CORE Under GPU Core

1
1
1
1
1
C
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
2
2
2
2
2
1U_0402_16V6K 4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
1U_0402_16V6K 4.7U_0402_6.3V6M
1U_0402_16V6K 4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
VGA@ PC824
VGA@ PC826
VGA@ PC827
PC848
VGA@ PC822
VGA@ PC823
VGA@ PC825
VGA@ PC828
VGA@ PC829
VGA@ PC830
PC849
PC851
1
A A
VGA@
2
2
VGA@
VGA@
10U_0402_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
VGA@ PC880
PC871
PC872
PC875
PC876
VGA@ PC878
PC879
PC881
VGA@ PC882
22U_0603_6.3V6M
10U_0402_6.3V6M
22U_0603_6.3V6M
PC874
PC877
PC873
1
1
1
1U_0402_16V6K
1U_0402_16V6K
VGA@ PC843
VGA@ PC844
VGA@ PC845
VGA@ PC846
VGA@
VGA@ PC847
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
2
2
2
Security Classification Compal Secret Data

Title
Issued Date 2016/6/2 Deciphered Date 2017/6/2
2
NVIDIA VGA_CORE
5 4 3 2 1
5 4 3 2 1
v o D

SY8286_V1_single.mdd
no
e
SY8286_V1_dual.mdd
+3VS Confirm HW side
B+_1.35V
1
keep short pad, @VGA_EMI@ PR902 @VGA_EMI@ PC902
PR901 VGA@ 4.7_1206_5% 680P_0603_50V7K
L
snubber is for EMI only. 1 2 SNUB_1.35V 1 2
VGA@ 100K_0402_5%
@VGA@ PJP901 PU901 @VGA@
2
+1.35VGS_PGOOD <21>
B+ 1
1 2
2 2
IN PG
9 PR903
0_0402_5%
PC905 VGA@
0.1U_0402_25V7K
Use 7x7x3 size when the layout space is enough.
10U_0603_25V6M
0.1U_0402_25V6
3 1 BST_1.35V 1 2 BST_1.35V_R
1 2
2200P_0402_50V7K
JUMP_43X79 IN BS VGA@ PL901
1
VGA_EMI@ PC901
@VGA_EMI@ PC904
VGA@ PC903
C LX_1.35V C
4
IN LX
6 1 4
+1.35VGSP
2
2
VGA@ PD1301 5 19 2 3
330P_0402_50V7K
r
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
IN LX
1 2
12.4K_0402_1%
PR904
1
7 20
VGA@ PC906
VGA@ PC907
VGA@ PC908
VGA@ PC909
VGA@ PC910
GND LX 1UH_MMD-05AHN1R0M-X2L_8A_20%
RB751V-40_SOD323-2 FB_1.35V
8 14 R1
2
GND FB
2
18 17 LDO_3V_1.35V
PR905 16.5K_0402_1% GND VCC
VGA@
1
1 2 EN_1.35V 11 10
<25> 1.35V_PWR_EN
o
EN NC PC911 FB=0.6V
1
ILMT_1.35V 13 12 4.7U_0402_6.3V6M
2
1
ILMT NC PR907 VGA@

@VGA@ PR906 PC912 VGA@ 15 16
1M_0402_1% 0.22U_0402_16V7K
+3VALW BYP NC Vout=0.6V* (1+R1/R2) R2 10K_0402_1%
2
LDO_3V_1.35V
21 =0.6*(1+(12.7/10)) @ PJP902
2
PAD JUMP_43X118
2
1U_0402_6.3V7K
EN :H>0.8V ; L<0.4V SY8286RAC_QFN20_3X3 1 2
Vout=1.362V +1.35VGSP 1 2 +1.35VS_VRAM
1
PC913
F
1
@VGA@
2
If have pull down resistor at HW side, PR908

please delete PR601. 0_0402_5%
2
l
If have pull down resistor at HW side, pls delete PR702
p a B
o m
A
5
C 4 3
Compal Secret Data
2
Deciphered Date
2017/6/2 Title
Size
Custom
Date:
PWR-CPU_CORE/CPU_CORE_NB
Document Number
ISL62771 Module
1
Sheet 50 of 54
Rev
2.0
A

Lenovo - S530-13 (ELZ02) Compal LA-G651P R02 180517A

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Lenovo - S530-13 (ELZ02) Compal LA-G651P R02 180517A

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A B C D E

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Friday, May 18, 2018 Sheet

BOM Structure Table USB 2.0 Port Table

S5 S4/ Battery only

Full ON HIGH HIGH HIGH HIGH ON ON ON ON

SOURCE VGA BATT CHARGER Thermal Touch Pad PCH TypeC-Mux

Security Classification Compal Secret Data

G3->S0 S0->S3/DS3 S0/ DS3 ->S0 S0->S5

Security Classification Compal Secret Data Compal Electronics, Inc.

1 2 H_PROCHOT#_R Y4 PECI PROC_TDI Y5 SOC_XDP_TDO SOC_XDP_TDI RC12 1 CMC@ 2 51_0402_5%

1 = eSPI is selected for EC

EC_SPI_CLK RC473 1 EMI@ 2 33_0402_5% SOC_SPI_0_CLK_R

Security Classification Compal Secret Data Compal Electronics, Inc.

RC3945 HDA_SYNC BN34

BL36 HDA_SDI0/I2S0_RXD GPP_G2/SD3_DATA1 CM35

DGPU GPU_EVENT# RC464 1 2 0_0402_5% SOC_GPP_C10

RC33 1 @ 2 2.2K_0402_5% HDA_SPKR 9 of 20

SPKR (Internal Pull Down):

TOP Swap Override

0 = Disable TOP Swap mode. ==> Default

XCLK_BIASREF RC110 1 2 60.4_0402_1%

BD3 CJ1 XCLK_BIASREF

RC53 1 2 60.4_0402_1% EC_VCCST_PG

Security Classification Compal Secret Data Compal Electronics, Inc.

GSPI0_MOSI (Internal Pull Down):

0 = Disable No Reboot mode. ==> Default

DGPU_PRSNT# 10K_0402_5% 2 UMA@ 1 R73

10K_0402_5% 2 DIS@ 1 R74

Place close to PCH

CNV_RGI_CRX_DTX RC3939 1 @ 2 20K_0201_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

v oUSB2/3 (re-driver) (I/O SB)

Security Classification Compal Secret Data Compal Electronics, Inc.

+1.8VALW AK24 3.679A

RON(Max) : 6.2 mohm BE7

+1.05VS_VCCIO change package of 1U from 0201 to 0402

Close to CPU Underneath CPU Underneath CPU Close to CPU

+1.05VALW TO +1.05VS_VCCSTG CPU C10 Save Power +1.2V TO +VCCPLL_OC

UC8 @ UC9 @ 0.1U_0201_10V6K @ @ 1

2 2 VIN1 <9> SOC_C10_GATE# A VCC @ VIN2 RC456

Security Classification Compal Secret Data Compal Electronics, Inc.

BW18 +3VL_RTC +RTCBATT

CC169 CC171 BW19

2 2 +1.8VALW CA14 VCCPRIM_1P05_12 BR23

BV16 VCCPRIM_CORE3 VCCA_XTAL_1P05

1 CB14 Close to CP5 Close to BP14

@ Close to BT24 CB15

CC79 Internal LDO CC18

2 VCCDSW_1P05 VCCPRIM_1P8_3 CD18

BR24 When CNVi is not used in the design:

close to BP20 K12

Security Classification Compal Secret Data Compal Electronics, Inc.

SOC_SVID_ALERT# 1 2 (To VR)

Security Classification Compal Secret Data Compal Electronics, Inc.

W HL-U42_BGA1528 W HL-U42_BGA1528 W HL-U42_BGA1528

RC459 1 @ 2 10K_0402_5% CFG0

Display Port Presence Strap