Microelectronics Journal 73 (2018) 75–85

Contents lists available at ScienceDirect

Microelectronics Journal
journal homepage: w w w . e l s e v i e r . c o m / l o c a t e / m e j o

Design and analysis of 2T2M hybrid CMOS-Memristor based RRAM

Noha Shaarawy a , Ahmed Emara b , Ahmed M. El-Naggar a , Mohammed E. Elbtity a ,
Maged Ghoneima c , Ahmed G. Radwan d,a,*
a Nanoelectronics Integrated Systems Center (NISC), Nile University, Egypt
b
Mentor Graphics, Egypt
c
Mechatronics Engineering Department, Ain-Shams University, Egypt
d Engineering Mathematics and Physics Department, Cairo University, Egypt

A R T I C L E I N F O A B S T R A C T

Keywords: In this paper, a Static Noise Margin (SNM) analysis for 2T2M RRAM cell is investigated. The proposed analysis
1T2M is done using mathematical formulation and verified by SPICE simulations. The analysis is tested for both, write
2T2M
and read modes. Moreover, the analysis is applied to diverse types of RRAM cells, and a comparison between
Memristor
the performance of such cells is discussed. Additionally, the effect of the exponential memristor model on the
RAM
RRAM
memristor behaviour in terms of switching speed and the range of the memristor resistance are discussed in
SNM detail. The circuits design and simulations were carried out using TSMC 130 nm CMOS technology and Cadence
Virtuoso tool. Finally, comparison between different RAM technologies is briefly presented.

1. Introduction charge at nanoscale, these memories are facing challenges to be scaled

Random Access Memory plays an essential role in today’s comput-
ing systems. The performance and the functionality of any computer
system are greatly affected by the memory subsystem [1]. According to
the International Technology Roadmap for Semiconductors (ITRS) [2],
CMOS-based memories occupy 90% of the SoC area.
Power consumption, capacity, noise margin, long data retention
time and read/write speed are the main characteristics of the memory.
It is always required to have a low power consumption, high capacity,
high read/write speed and long write/read cycling endurance memory.
Unfortunately, it is almost impossible to obtain all of these ideal char-
acteristics in the same memory technology and this is the cause of the
memory wall (bottleneck) issues [3,4]. Thus, there are a lot of technolo-
gies that have been proposed to get one or more of these ideal charac-
teristics such as Static Random Access (SRAM) [5], Dynamic Random
Access Memory (DRAM) [6], FLASH (NOR or NAND) [7], Spin-Transfer
Torque Magentoresistive Random Access Memory (STT-MRAM) [8],
Phase Change Random Access Memory (PCRAM) [9], Ferroelectric Ran-
dom Access Memory (FeRAM) [10], Magnetic Random Access Memory
(MRAM) [11], and Resistive Random Access Memory (RRAM) [12].
SRAM, DRAM and Flash (also called Silicon-based) memories are
working based on charge storing mechanism. Due to ease of losing the
down to beyond 10 nm. Therefore, currently new memory architec-
tures based on other technologies that could go beyond CMOS limits
are under research and development. Memristor-based memory tech-
nology, referred to as Resistive Random Access Memory (RRAM), is
one of the new memory technologies that is expected to replace these
conventional silicon-based memories [13,14]. The nonvolatile charac-
teristics of the RRAM cells make it an attractive replacement for systems
that require low power and high performance such as, instant-on com-
puters. Taking the advantage of memristor in keeping its state, the RAM
will boot-up instantly without the need to wait for loading the data from
the hard drive [15]. Existing research on memristor technology mainly
focuses improving its reliability, fabrication processes and integration
with CMOS based design [16].
In 1971, Leon Chua introduced the memristor as the fourth circuit
element besides the other three fundamental elements which are; the
resistor (R), inductor (L) and capacitor (C) [17,18]. HP labs success-
fully manufactured the first physical device in 2008 [19] based on bipo-
lar TiO2 thin film technology. Accordingly, the usage of the memristor
technology started to be explored for different applications. In Ref. [20],
a memristive device that is controlled through a threshold voltage is
introduced and implemented on SPICE. This device is following the tun-
neling distance modulation during switching. In addition, the concept

* Corresponding author. Engineering Mathematics and Physics Department, Cairo University, Egypt.
E-mail addresses: noha.a.shaarawy@gmail.com (N. Shaarawy), ahmed.emara.01@gmail.com (A. Emara), a.elnaggar@nu.edu.eg (A.M. El-Naggar), elbtity@azhar.edu.eg
(M.E. Elbtity), m_ghoneima@ieee.org (M. Ghoneima), agradwan@nu.edu.eg (A.G. Radwan).

https://doi.org/10.1016/j.mejo.2018.01.001
Received 17 January 2017; Received in revised form 29 December 2017; Accepted 4 January 2018
Available online 3 February 2018
0026-2692/© 2018 Elsevier Ltd. All rights reserved.
N. Shaarawy et al.
of the memcapacitor-based relaxation oscillators is established in Ref.
[21] through using two series memcapacitors which is viable for both
capacitor and memcapacitor. Moreover, a family of Memristor-based
Reactance-Less Oscillators (MRLOs) is proposed in Ref. [22]. These
MRLOs do not need any reactive components (i.e capacitors or induc-
tors) as the oscillation is generated via the memristor device through
exploiting its resistance storage property. More applications are valid
such as neuromorphic systems [23], oscillatory systems [24–26], binary
adders [27–29] and memories [30,31]. A fabricated RRAM based on
CMOS process was presented in Ref. [32].
Since Chua introduced the memristor, many models were intro-
duced to emulate this new device. The main advantage of the memristor
is that it ables to keep its most recent state for a long time even when
the power supply is disconnected [18]. As a result, the RRAM cells are
expected to consume lower power than the conventional 6T SRAM cell
during sleep mode. On the other hand, stability is considered one of the
primary restrictions in nano-scale memory design [33]. So, it has been
a major focus of recent research. In order to analyze a non-standard bit
cell, such as the RRAM cells, many of the conventional metrics cannot
be directly applied and need to be redefined.
In this paper, a novel SNM of RRAM cells is presented. Although, the
dynamic properties of memristor on the storage cell has a great impact
on the cell stability, the study of the RRAM SNM was not discussed
previously in published works based on memristive RRAM. This paper
presents a definition and analytical method for calculating RRAM SNM.
The introduced analytical method is applied to the 2T2M memristor
based storage cell architecture. In order to verify the proposed analy-
sis, it is compared with the simulation results. Moreover, the proposed
Stability analysis is applied to different RRAM cells to compare their
stability performance.
This paper is organized as follows; Section 2 illustrates the main con-
cept of the resistive switching mechanisms. In Section 3, the exponen-
tial model is described and its parameters are studied to find the effects
of these parameters on the memristor response. Section 4 presents the
proposed RRAM cell. Also, other RRAM cells are described. In section
5, the static noise margin has been analyzed analytically based on the
proposed RRAM cell. In section 6, the proposed static noise margin sim-
ulation analysis is applied on different types of RRAM cells presented
in section 4. Finally, the conclusion is presented in section 7.
2. Resistive Random Access Memory (RRAM)
Resistive Random Access Memory (RRAM) is a two-terminal device
with a switching element sandwiched between two electrodes [35].
Depending on the programming voltage applied on the memristor ter-
minals, the switching medium is turned from a high-resistance state to
a low-resistance state and vice verse.
Fig. 1. Different types of switching characteristics (a) unipolar Switching with abrupt resistance change, (b) bipolar Switching with abrupt resistance change and (c) bipolar switching
with analog resistance change [34].
76
Microelectronics Journal 73 (2018) 75–85
The resistive switching characteristics can be divided into two types:
unipolar switching and bipolar switching. If the device can be inter-
changed between high-resistance and low-resistance states with one
polarity of the applied voltage, then the device is called unipolar switch-
ing device. Whereas, if the device has to be switched from a high-
resistance state to a low-resistance state and vice verse with differ-
ent polarities of the applied voltage, then the device is called bipo-
lar switching device. Regardless of the switching type (i.e, unipolar,
bipolar), the switching operation from high-resistance state to low-
resistance state is named as SET process and the opposite process is
named as RESET process.
In bipolar switching, the switching direction depends on the polar-
ity of the applied voltage. Accordingly, the device switches from high-
Resistance state to low-resistance state by applying a voltage with a
polarity of VSET . After switching, the device resistance becomes low
and the ON-state can retain its state even if the applied voltage is dis-
connected. On the other hand, the device can be switched off by apply-
ing VRESET with opposite polarity of VSET (i.e, The polarity of VRESET is
opposite to that of VSET ).
In contrast, the SET process in unipolar switching devices only
depends on the magnitude of the applied voltage and does not depend
on its polarity. As a result, the thermal effects are commonly involved
during the unipolar switching process [34]. A current compliance has
to be applied in unipolar devices during the SET process in order to
limit the current of the ON-state and the thermal generation. However,
this current compliance is removed during the RESET process and the
devices are switched to high-resistance state by having a large current.
In most researched unipolar cases, the set voltage Vth2 (VSET ) is larger
than the reset voltage Vth1 (VRESET ), whereas the set current is smaller
than the reset current. Generally, unipolar devices suffer from limited
endurance cycles because of the high current of the ON-state and the
heating process. In addition, the operation window between set and
reset voltages can be limited and accidental reset can occur.
The drawback of the unipolar resistive switching is that VRESET could
overlap with VSET as a result of having same polarities. Obviously, this
kind of trouble cannot exist in bipolar resistive switching since the VSET
and VRESET voltages have opposite polarities.
Both of the unipolar and bipolar switching devices can follow the
abrupt mechanism or the analog mechanism [36]. In the abrupt mech-
anism, the switching between OFF-state and ON-state is sharp and fast,
as shown in Fig. 1 (a,b), respectively, which makes the devices suitable
for digital memory applications. By using this abrupt mechanism in the
digital memories, the read disturb that occurs in the storage cells during
the read operation is significantly reduced down to a manageable level.
However, these kinds of switching devices can be also analog, which
means that many states can exist between the ON-state and OFF-state
(continuous switching), as shown in Fig. 1 (c). This type of switch-
N. Shaarawy et al.
Fig. 2. Voltage vs. Current in the Exponential Memristor Model, 2 MHz sinusoidal 1.4v input source, 𝛽 = 0.001, 𝛼 = 2, n = 4, 𝛾 = 4, and a = 25 (a) I–V Curve and (b) Memristor
Internal state x.
ing mechanism is suitable for analog applications and specific types of
memories.
The exponential model, used in this paper, is a bipolar switching
device with analog mechanism. The bipolar switching is used to avoid
the problems of the unipolar switching illustrated in this section. In
addition, the analog mechanism has been used instead of the abrupt
mechanism to be able to use our 2T2M cell [37] as a multi-bit storage
element, in multi-bit cells, the regions between the On-state and OFF-
state are needed to store different bits-combinations, as a future work.
3. Exponential memristor model
A memristive system can be described by
v = R(x, t)i,
dx
= f (x, i, t), (1b)
dt
where Equation (1a) describes the I–V characteristic of the memris-
tor, whereas Equation (1b) specifies the memristor internal state x. In
this section, the exponential model, which is used in the 2T2M cell, is
described and analyzed.
3.1. Exponential model
The existing memristor models discussed till this moment still ignore
the effects of the non-linearity of the electric fields. The exponential
memristor model given by Lehtonen et al. [38] works on capturing a
large effect of the electric field. This model multiplies the drift equation
by a function that depends on the applied voltage on the memristor.
The exponential model is defined by the following two equations:
I = xn 𝛽 sinh(𝛼V) + 𝜒(exp(𝛾V) − 1),
dx
= a sinh(bv)f (x, i), (2b)
dt
where Equation (2a) fits the measured IV characteristic of exponen-
tial memristor model where 𝛽, 𝛼, 𝛾 and 𝜒 are fitting constants, and n
is a free parameter. The IV hysteresis loop acts like a p-n junction
(the exponential part) during the OFF state, whereas in the “ON”state
it follows a tunneling process (sinh part). Also, the internal state Equa-
tion (2b) has a nonlinear dependency on the voltage and the window
function f (x, i), as well. In Fig. 2, one can easily notice the memristor
hysteresis loop, and the unsymmetrical response in charging and dis-
charging the device. The exponential model was adopted in this work
in Verilog-A to speed up simulations, and ease the configuration of the
memristor parameters.
Microelectronics Journal 73 (2018) 75–85
3.2. Exponential memristor model analysis
In the exponential model, the internal state x exhibits a nonlinear
response with the applied voltage across the memristor.
In this paper, the effect of 𝛽, 𝜒 and a on the characteristics of the
exponential model are investigated by simulations. The 𝛽 is inversely
proportional with RON . As 𝛽 increases, the current passing through the
memristor increases, therefore, the value of RON decreases as shown
in Fig. 3(a). Similarly, ROFF is determined by the 𝜒 parameter. As 𝜒
increases, the current passing through the memristor to switch it off
increases, thus, the value of ROFF decreases, as shown in Fig. 3(b).
Finally, the parameter a controls the switching speed of the memristor
model in which the a parameter is directly proportional to this speed,
as shown in Fig. 4.
(1a)
4. Memristor based memory cells
There are two main RRAM memory architectures which are: the
grid RRAM architecture and the crossbar RRAM architecture. Unlike
grid RRAM, the crossbar structure does not have access transistors in its
cell architecture and that makes it attractive due to its intensive small
area. Although crossbar RRAM structure has advantage in terms of the
size, it faces many issues in terms of switching time, access time, and
reliability [39]. These problems are caused by the wire resistance and
sneak currents which leads to IR drop issue [40]. Moreover, this issue
totes some constraints on writing time, memory array size, and oper-
ating voltages. Furthermore, several techniques have been proposed
to solve the IR drop issue such as those presented in Refs. [41] and
[42].
On the other hand, the grid RRAM architecture (which we study
(2a) here) features more energy efficiency as well as superiority in access
time. However this architecture presents higher size and hence higher
cost. The previous aforementioned techniques do not apply for this
type of RRAM architecture. Different memristor based grid RRAM
architectures are shown in Fig. 5. This section illustrates different
memristor-based concepts for building RRAM cells.
Generally, the RRAM cells can overcome some disadvantages of the
conventional 6T SRAM cell such as low density and high power con-
sumption. Although the basic idea of the 2T2M RRAM cell was intro-
duced in Ref. [37], but more circuit simulations are introduced in this
paper to give a better illustration for the cell. Moreover, the effects
of the exponential model’s parameters, discussed in section 3, on the
behaviour of the 2T2M cell are explored. In addition, both of the 1T1M
[30] and 1T2M [43] RRAM cells, shown in Fig. 5 (a,b), will be explained
briefly in this section and also in section 6.
77
N. Shaarawy et al.
Fig. 3. The effect of both 𝛽 and 𝜒 parameters on the behaviour of the exponential model (a) 𝛽 is proportional inversely with the Ron , and (b) The 𝜒 is proportional inversely with the
ROFF .
Fig. 4. The effect of the a parameter on the behaviour of the exponential model: a param-
eter is directly proportional to the speed of the internal state x.
4.1. 2T2M cell
In Ref. [37], the 2T2M cell was implemented using the exponential
model, as this model is an accurate description for the memristor device
due to its nonlinear dependence on the electric field. The 2T2M cell
consists of two access transistors and two memristors that are connected
opposite to each other, as shown in Fig. 5(c). Both of the write and read
operations are explained in details in Ref. [37].
Fig. 5. Different topologies of memristor based RRAM cells: (a) 1T1M Cell, (b) 1T2M Cell and (c) 2T2M Cell.
78
Microelectronics Journal 73 (2018) 75–85
The 2T2M RRAM cell is expected to shrink the overall area of the
memory module by almost 50%, compared to the conventional 6T
SRAM cell. This shrink is due to using only 2 transistors in 2T2M cell
while 6T-SRAM uses 6 transistors, the small size of the memristor in
the range of 10 nm or less, and also the possibility of implementing the
memristor on the top layer above metal layer during fabrication as pre-
sented in Ref. [44]. In addition, the 2T2M RRAM cell requires a fewer
number of periodical data refreshing cycles compared to [30].
As illustrated in Ref. [37], the read operation is done by discharging
both of the precharged BL & BLB. Therefore, the RC constant of the
memristor is significantly smaller in case of ON-state. As a result, the
difference between the two states could be read in a very short time. By
this way, the read stability could be enhanced and the rate of needed
data refresh cycles could be reduced.
The required interface signals for accessing the array are also com-
patible with the conventional CMOS-based memory, where address,
read/write enable, data in, and data out are the main signals. The com-
plete 2T2M RRAM module is shown in Fig. 6(a). The array contains a
Control Unit block, which includes all control signals to trigger mem-
ory, as well as the Peripheral circuits are shown in details in Fig. 6(b)
to input the data, and sense the output data of the array. The main
purpose of the controller circuit of NEG_M1 & NEG_M2 is to decrease
the difference voltage applied on the memristor devices during the read
operation, hence the state drift of the memristor will be decreased (per-
formance increases).
In this paper, more circuit simulations which clarify the effects of
the exponential model’s parameters on the behaviour of the 2T2M cell
N. Shaarawy et al.
Fig. 6. (a) Proposed Memory Array architecture (node (x) refers to NEG_M2 and node (y) refers to NEG_M1) and (b) Detailed schematic of the Peripheral CIRCUIT showing the logic
used in read and write access.
are introduced. As discussed in section 3, the 𝛽 parameter is inversely
proportional with RON . Thus, 𝛽 parameter has effect only on the mem-
ristor devices that are “ON”. By assuming that a logic ‘1’ is written to
the cell, the memristor device (M2) that is connected to the BLB node,
“ON” device, is the one which is effected by the 𝛽 parameter. As a
result, as 𝛽 increases, the RC constant decreases, causing the BLB node
is discharged at a faster rate during read operation. Therefore, the volt-
age difference between the BL and BLB nodes increases, as shown in
Fig. 7(a and b). On the other hand, the 𝜒 parameter is inversely propor-
tional with ROFF . Thus, 𝜒 parameter has effect only on the memristor
devices that are OFF. By assuming that a logic ‘1’ is written to the cell,
the memristor device (M1) connected to the BL node, OFF device, is the
one which is effected by the 𝜒 parameter. As a result, as 𝜒 increases,
the RC constant decreases, hence the BL node is discharged at a faster
rate during read operation. Therefore, the voltage difference between
the BL and BLB node decreases, as shown in Fig. 7(c and d).
4.2. 1T2M cell
A 1T2M RRAM cell was introduced in Ref. [43]. Such cell consists
of two memristors connected back-to-back, representing the storage ele-
ments, and one access transistor as illustrated in Fig. 5(b). The advan-
tage of a 1T2M memory cell is the compact area, which allows for
denser memories on the same area. In addition, as a 1T2M stores data
in a differential form, resulting in high read noise margin, such cell was
reported to store multi-bit information on the same cell eliminating the
need for special voltage supplies required for multi-bit decoding [45].
4.3. 1T1M cell
A 1T1M cell [30] comprises one memristor and one access tran-
sistor, as shown in Fig. 5(a). The small unit cell size allows for more
memory cells to be integrated on the same chip area. In write mode,
the access transistor is enabled, and the word on data line is stored in
the memristor. In the read mode, the bit line is compared to a constant
voltage reference to decode the output word. Although the 1T1M cell
has a relatively small area, it uses a constant reference supply in read
operation. Hence, read reliability across process corners is altered. In
this paper, the proposed static noise margin analysis is applied on the
1T1M cell. The results of both WNM and RNM have been compared
versus the other cells as will be discussed later in section 6.
79
Microelectronics Journal 73 (2018) 75–85
5. Mathematical analysis of noise margin
In this paper, the static noise margin for RRAM cells is defined and
analyzed. Both of the analytical analysis and simulation results are pre-
sented. The analytical analysis is dependent on the cell architecture
i.e. each cell architecture must be dealt with certain analytical model.
The analytical analysis based on the 2T2M cell architecture [37] is pre-
sented.
5.1. The proposed static noise margin definition
SNM is the maximum noise that the memory cell can afford before
changing its stored data. While writing to the memristor is a straightfor-
ward operation, reading is more challenging as there are a lot of issues
during the read operation of the memristor devices such as; sneak path
and state drift [46]. As a result, the read stability is a critical limitation
for RRAM cells based on memristor. In this paper, the noise margin
for memristor cells in write, read and hold modes are defined and ana-
lyzed. This technique of definition is different from that of 6T SRAM
since RRAM cells do not involve positive feedback circuitry to store
data. Thus, the traditional measurement of SNM in 6T-SRAM cells is
not applicable in RRAM cells.
A Write Noise Margin (WNM), is the maximum noise voltage that
can be applied on the terminals of an RRAM cell during a write opera-
tion, causing the internal state x of the memristor to change by a certain
amount, while preserving the stored data decoded in a consequent read
operation. Furthermore, Read Noise Margin (RNM) is the maximum
noise voltage that the memristor can tolerate during a read operation,
without damaging the stored data. On the other hand, Hold Noise Mar-
gin (HNM) is the maximum current that can pass through the memristor
during sleep mode without damaging its stored data.
5.2. Write Noise Margin
For the cell shown in Fig. 5(c), the 2T2M cell has two branches,
each of which has one memristor. The first branch operates in the “ON”
state while the other one operates in the “OFF” state. However, only
the “ON” state memristor is affected by the noise signals as the “OFF”
state memristor has a very big resistance, ROFF , and hence the added
noise voltage cannot produce enough current that changes the inter-
nal state x of the “OFF” memristor device. Consequently, to calculate,
N. Shaarawy et al.
Fig. 7. The effect of the exponential model’s parameter on the 2T2M cell’s behaviour using cadence tools at Vdd = 1.4 V, 𝛼 = 6, 𝛾 = 11.5 and n = 4 (a) Writing logic ‘1’ through
different values of 𝛽 parameter, (b) Reading logic ‘1’ through different values of 𝛽 parameters (BLB node is discharged in faster rate), (c) Writing logic ‘1’ through different values of 𝜒
parameter, (d) Reading logic ‘1’ through different values of 𝜒 parameter (BL node is discharged in faster rate).
analytically, the static noise margin of the 2T2M cell, the cell circuit
diagram can be approximated to the one shown in Fig. 8, where there
is only one memristor in “ON” state. Fig. 8(a) shows a simplified cir-
cuit of the 2T2M cell during the write operation of a logic ‘1’. In this
analysis, the exponential memristor model, described in quation (2a), is
used. T1 operates in the linear region as (vds < vgs − vth ). The WNM can
be found analytically by solving Kirchhoffs equation, and applying the
limiting conditions on the noise tolerance. In the 2T2M cell, in order to
accomplish a correct write operation, the value of the internal state x
of the “ON” memristor must be equal to or greater than certain thresh-
old value. This threshold is defined as the minimum value of state that
causes the “ON” memristor resistance to permit the flow of electrons
(current), which in turn results in a voltage drop of ∼0.1 V (between
the BL and BLB), which is the trigger for the sensing amplifier. Based
on the simulated model and its design parameters, the threshold value
for the memristor state x was found to be 0.2.
∑
k
x(i) = [f (x)a sinh(b ∗ va (i))], (3a)
i=0
Im (i) = xn (i)𝛽 sinh(va (i)) + 𝜒(𝛼 exp(𝛾va (i)) − 1), (3b)
1
Ra = , (3c)
k(vgs − vth)
Im Ra + va (i) = vi − vn , (3d)
vi = vdd − vth , (3e)
80
Microelectronics Journal 73 (2018) 75–85
vgs = vdd − va , (3f)
In Equation (3a), the discrete form of the internal state x of the expo-
nential model depends non-linearly on the voltage level, where a is a
constant, f (x) is a window function, and g(va ) is a polynomial function.
For simplicity, the window function f (x) is assumed to be equal to 1.
Equation (3b) is the discrete form of the measured I–V characteristic
of memristor represented by Equation (2a) in Ref. [47]. Equation (3c)
represents an approximation for the internal resistance of the transis-
tor (T1) in the linear region. Equation (3d) is Kirchhoffs equation for
the simplified circuit in Fig. 8(a). Equations (3e) and (3f) represent the
value of the vi and the vgs of the circuit in Fig. 8(a), respectively. In order
to calculate the maximum noise vn at a certain value of vdd , the value of
x(i) [x(0) = 0.05] is gotten and substituted in Equation (3b). After that,
Equations (3b) and (3d) are solved to get the value of va (i). Such iter-
ation is repeated through the whole period of the write operation with
appropriate time step [dt = 1e-10]. If the value of the calculated x(i) is
lower than 0.2 at any point of the write operation, then the obtained
value of vn is bigger than the maximum noise tolerance for the cell. The
results of the analytical WNM (Write Noise Margin) is compared to the
WNM simulation results in section 6.
5.3. Read Noise Margin
Similar to the analysis done for the WNM, the 2T2M cell circuit dia-
gram can also be reduced to one memristor during the read operation.
Fig. 8(b) shows a simplified circuit during the read operation of logic
N. Shaarawy et al. Microelectronics Journal 73 (2018) 75–85

Fig. 8. 2T2M Approximated circuit (a) During

Write operation and (b) During Read operation.

dvi v (t + 1) − vi (t)
‘0’. The memristor in Fig. 8(b) is the one which has the same polarity of Ic = −c = −c i , (4c)
the input voltage. T1 operates in saturation region as (vds ≥ vgs − vth ). dt dt
The RNM can be found analytically by solving the Kirchhoffs equation
vgs = 1.4 − va , (4d)
and putting the limit condition of the noise tolerance. In the 2T2M cell,
to prevent the loss of the stored data, the value of the internal state x of
the “ON” memristor shouldn’t be decreased lower than 0.2 as explained vds = vi − vn − va , (4e)
in section 5.2.

I = IC = Im = Ids , (4a) vi (0) = 1.4 (4f)

Equation (4a) represents the Kirchhoffs equation of the simplified

Ids = k2 (vgs − vth )2 (1 + vds ), (4b) circuit shown in Fig. 8(b). Equation (4b) represents the current Ids∣sat

Fig. 9. (a) 1T1M WNM analysis circuit, (b) 1T2M WNM analysis circuit and (c) 2T2M WNM analysis circuit.

Fig. 10. (a) 1T1M RNM analysis circuit, (b) 1T2M RNM analysis circuit and (c) 2T2M RNM analysis circuit.

81
N. Shaarawy et al.
Fig. 11. (a) 1T1M HNM analysis circuit, (b) 1T2M HNM analysis circuit and (c) 2T2M HNM analysis circuit.
Fig. 12. SNM Analytical analysis Vs. Simulation analysis of the 2T2M cell through differ-
ent values of Vdd (a) Write Noise Margin Analysis and (b) Read Noise Margin Analysis.
of T1 in the saturation region. Equation (4c) shows the behaviour of
the alternating current as a function of time during the discharging of
a capacitor C. Finally, Equations (4d) and (4e) represent the value of
the voltages vgs and vds of the circuit in Fig. 8(b), respectively. In order
to calculate the maximum vn at a certain value of vdd , the initial value
of x(t) [x(0) = 0.05] is assumed and its value is substituted in Equa-
tion (3b). After that, Equations (4b) and (3b) are equalized based on
the Kirchhoffs law to find the current value of va (t) [vi (0) = 1.4]. After
finding the value of va (t), Equations (3b) and (4c) are solved to get the
value of vi (t + 1). To ensure stability, convergence, and accuracy, the
82
Microelectronics Journal 73 (2018) 75–85
Fig. 13. Write Noise Margin Analysis is applied on both the 1T1M, 1T2M, 2T2M cell
through different values of power supplies.
whole process is repeated through the whole period of the read oper-
ation with an appropriate time step [dt = 1e-10]. If the value of the
calculated x(t) reduces lower than 0.2 at any point of the read opera-
tion, then, the current value of vn is greater than that of the maximum
noise tolerance for the cell. The results of the analytical RNM analysis
is compared with the RNM simulation results in section 6.
6. Simulation analysis of noise margin
6.1. Architecture of simulation analysis
The proposed noise margin definition will be applied on the three
RRAM cells explained in section 4. The noise source polarity will be set
so as to oppose the applied voltages on the BL & BLB in the different
modes. Hence, in write mode, the noise source will be added to the BL
& BLB nodes in order to decrease the effective voltage difference on the
memristor terminals. Accordingly, the change in the memristor inter-
nal state will be altered. Similarly, in read mode, the noise source will
be added to increase the effective voltage difference on the memristor
terminals. As a result, the memristor internal state will change faster
than normal, leading to a destructive read operation. Fig. 9 shows the
effective circuit of the three cells in write mode.
In 1T1M [30], 1T2M [43] and 2T2M [37] cells, writing a logic ‘1’
is much slower than writing a logic ‘0’, as the effective voltage passed
to the memristor devices is a weak ‘1’ due the NMOS device threshold
voltage. Hence, noise added to a write ‘1’ operation will dominate the
WNM results. As a result, noise analysis will be carried out in a write
‘1’ mode. For a 2T2M and 1T2M cells, noise sources are introduced on
both the BL & BLB. On the other hand, in 1T1M, the noise source is
only introduced on the BLB terminal as the other terminal, BL, is the
same bus of the data (DL). Therefore, this bus will be constant during
the write mode. Accordingly, the effective voltage difference on the
memristor devices is lowered. Thus, the internal memristor state will
not be fully changed.
N. Shaarawy et al. Microelectronics Journal 73 (2018) 75–85

Fig. 14. (a) Read Noise Margin Analysis is applied on both 1T1M, 1T2M, and 2T2M cell through different values of power supplies., (b) The effect of the noise on the internal state x on
the memristor.

In read mode, the noise source will be added in order to create a
destructive read operation stimulus. Fig. 10 shows the effective circuit
of three cells in read mode. Similar to the WNM configuration, in a
1T1M, 2T2M, and 1T2M cells, the noise sources are introduced on the
BL & BLB lines.
The HNM is measured by adding positive current to the RON mem-
ristor, or negative current to the ROFF memristor (The worst case), as
shown in Fig. 11. So, measuring the HNM of the cell is the same in case
of storing a logic ‘0’ or logic a ‘1’.
6.2. Results of static noise margin analysis
The defined noise margin was applied on the three RRAM cell,
based on the exponential model. The analysis was simulated by Cadence
Virtuoso tools, 130-nm TSMC CMOS process technology, 27◦ C tem-
perature, and exponential memristor model where Vdd = 1.4V, 𝛼 = 6,
𝛽 = 15, 𝛾 = 11.5, 𝜒 = 0.001 and n = 4.
In this paper, the proposed analytical analysis of the static noise
margin is applied on the 2T2M cell [37] and the results of the analytical
analysis are compared with the results of the simulation analysis. The
comparison between the analytical results and the simulation results of
the WNM is shown in Fig. 12(a). Based on the Fig. 12(a), the average
error percent between the analytical results and the simulation results
of the WNM is within 5%. On the other hand, the results of the RNM of
both of the analytical and simulation analysis are compared versus each
other as shown in Fig. 12(b). The average error percent between the
analytical analysis and the simulation analysis as cleared in Fig. 12(b)
is within 7%.
WNM analysis is applied during a write of logic ‘1’ operation. Fig. 13
shows the simulation results for the three cells in such mode. Based on
Equation (2a) of the memristor exponential model shown in section
3.2, the power supply value is the most effective factor on a memristor
performance. Accordingly, the proposed WNM analysis is simulated in
different Vdd levels to study the effect of the power supply on the WNM
for each cell. As shown in Fig. 13, in write mode, as the power supply
level increases, the immunity of the three RRAM cells for noise on BL
& BLB increases. Hence, increasing power supply level enhances the
stability of the RRAM cells in write mode. In addition, the 1T2M cell
has the highest WNM relative to both of the 2T2M, and 1T1M because
the current noise, which is caused by the noise source, is divided on the
two memristor devices as shown in Fig. 5(b). Therefore, the effective
noise on each memristor is lower than the effective noise in case of
2T2M, and 1T1M cell.
In Fig. 14(a), the RNM results are shown. In a 1T2M and 2T2M cells,
writing a logic ıís similar to a read operation. Thus, the worst case in
read mode is to read a logic ‘0’, as it tends to invert the stored data in

Table 1
A comparison between different memory technologies denotes that information is not available in cited papers.
Cell Write Read WNM RNM Internal Retention Endurance Needed Non-volatility
Size Operation Operation (V) (V) State Refresh
(F 2 ) Time Time Distortion Cycles
SRAM >100 [48] ∼1 ns ∼1 ns X 0.5 Y N/A N/A >1E16 N/A No
DRAM 20–50 [48] ∼10 ns ∼10 ns N/A N/A N/A 32–64 ms [49] >1E16 Every 32–64 ms [49] No
(1T1C)
Flash <4 [2,50] 100 μs–1 ms ∼10 μs N/A N/A N/A >10y >1E4 ** Yes
(NAND)
Flash ∼10 [2,51] 10 us–1 ms ∼50 ns N/A N/A N/A >10y >1E5 ** Yes
(NOR)
STT-MRAM 6–50 [48] <5 ns <10 ns ** ** N/A >10y >1E15 ** Yes
PCRAM 4 ∼ 20 ∼50 ns <10 ns ** ** N/A >10y >1E9 ** Yes
[52,53]
RRAM ∼16–17 5 ns 0.8 ns X Y Z >10y 1E6 -1E12 Every 10,000 Read Yes
(1T1M) (Predicted) CyclesZ
RRAM ∼16–17 5 ns 2 ns 2X 2Y 5Z >10y 1E6 Every 24,000 Read Yes
(1T2M) (Predicted) Cycles
RRAM ∼35–50 5 ns 0.5 ns 1.5X Y Z >10y 1E6 Every 32,000 Read Yes
(2T2M) (Predicted) Cycles
FeRAM 15 ∼50 ns 20–80 ns ** ** N/A >10y 1E12 ** Yes

83
N. Shaarawy et al.
the memristor device. Hence, the RNM analysis is applied during a read
of logic ‘0’. In contrast to 1T2M and 2T2M cells, in a 1T1M cell, the
RNM analysis is applied during a read of logic ‘1’, as it’s considered to
be the worst case in a read operation. Similar to the WNM, the proposed
RNM analysis is simulated during different power supply levels Vdd . As
shown in Fig. 14(b), the distortion in the memristor internal state x
increases with the increase in the power supply level.
During read mode, the 1T1M and 2T2M cells can tolerate high value
of the power supply without damaging the stored data into the memris-
tor device, unlike the 1T2M cell whose internal state x is totally dam-
aged when Vdd is raised above 1.6 V. As a result, the 1T2M cell has
a restriction on the value of the power supply. As shown in Fig. 14,
the value of the noise that the cell can afford during the read mode
increases, as long as the internal state of the memristor doesn’t get
exposed to a great damage. Table 1 shows the performance compar-
ison between different emerging technologies in terms of cell size,
read/write time, volatility, endurance and retention.
7. Conclusion
In this paper, a novel stability analysis for RRAM cells was pro-
posed. The analysis was used to test the 2T2M RRAM cells, along with
other RRAM cells. Due to the low mobility of the memristor, 2T2M are
much slower than conventional 6T SRAM cells. However, this latency
is inversely proportional to the applied voltage. In addition, analytic
expression for the SNM of 2T2M RRAM cell has been driven through
both of the write and read modes. Moreover, a new easy and quick;
simulation method of SNM has been developed. Finally, the proposed
analytical approach, showed a great match with simulation results.
References
[1] H.-S.P. Wong, S. Salahuddin, Memory leads the way to better computing, Nat.
Nanotechnol. 10 (3) (2015) 191–194.
[2] International Technology Roadmap for Semiconductors, [Online] http://www.itrs.
net/, 2015.
[3] S.A. McKee, Reflections on the memory wall, in: Conf. Computing Frontiers, 2004.
[4] B. Jacob, The memory system: you can’t avoid it, you can’t ignore it, you can’t
fake it, in: The Memory System: You Can’t Avoid it, You Can’t Ignore it, You Can’t
Fake it, 2009.
[5] E. Ebrahimi, M. Guthaus, J. Renau, Timing Speculative Sram, 2017.
[6] D. Lee, Y. Kim, G. Pekhimenko, S.M. Khan, V. Seshadri, K.K.-W. Chang, O. Mutlu,
Adaptive-latency dram: optimizing dram timing for the common-case, in: 2015
IEEE 21st International Symposium on High Performance Computer Architecture
(HPCA), 2015, pp. 489–501.
[7] L.M. Grupp, J.D. Davis, S. Swanson, The bleak future of nand flash memory, in:
Proceedings of the 10th USENIX Conference on File and Storage Technologies
(FAST’12), Berkeley, CA, USA, 2012, p. 2.
[8] M. Alioto, STT-MRAM memories for IoT applications: Challenges and
opportunities at circuit level and above, in: International Symposium on VLSI
Technology, Systems and Application (VLSI-TSA), Hsinchu, 2017, p. 1, https://
doi.org/10.1109/VLSI-TSA.2017.7942448.
[9] Y.H. Lee, et al., High performance low A/R poly PN diode for 20nm node PCRAM
cell switch, in: 45th European Solid-State Device Research Conference (ESSDERC),
Graz, 2015, pp. 122–125, https://doi.org/10.1109/ESSDERC.2015.7324728.
[10] S. Ducharme, T.J. Reece, C.M. Othon, R.K. Rannow, Ferroelectric Polymer
Langmuirblodgett Films for Nonvolatile Memory Applications, 2017.
[11] W. Kang, L. Chang, Y. Zhang, W. Zhao, Voltage-controlled mram for working
memory: perspectives and challenges, Design, in: Automation & Test in Europe
Conference & Exhibition (DATE), 2017, 2017, pp. 542–547.
[12] A.A. Bagheri-Soulla, M.B. Ghaznavi-Ghoushchi, An rram-based mlc design
approach, Microelectron. J. 64 (2017) 9–18.
[13] J. Chang, L. Chang, A. Dupret, C. Kim, F. Hamzaoglu, T. Yoshikawa, F2: memory
trends: from big data to wearable devices, in: IEEE International Solid-state
Circuits Conference - (ISSCC) Digest of Technical Papers, 2015, pp. 1–2.
[14] E. DeIonno, A.L. White, Reliability considerations and radiation testing of
memristor devices, in: Aerospace Conference, IEEE, 2015.
[15] M. Hopkin, Found: the missing circuit element, Nature (2008) https://doi.org/10.
1038/news.2008.789.
[16] P. Pouyan, E. Amat, A. Rubio, Reliability challenges in design of memristive
memories, in: CMOS Variability (VARI), 2014 5th European Workshop on, IEEE,
2014, pp. 1–6.
[17] A.G. Radwan, M.E. Fouda, On the Mathematical Modeling of Memristor,
Memcapacitor, and Meminductor, Springer, 2015.
[18] L.O. Chua, S.M. Kang, Memristive devices and systems, Proc. IEEE 64 (2) (1976)
209–223.
84
Microelectronics Journal 73 (2018) 75–85
[19] D.B. Strukov, G.S. Snider, D.R. Stewart, R.S. Williams, The missing memristor
found, Nature 453 (2008) 80–83, https://doi.org/10.1038/nature06932.
[20] I. Vourkas, A. Batsos, G.C. Sirakoulis, Spice modeling of nonlinear memristive
behavior, Int. J. Circ. Theor. Appl. 43 (2015) 553565.
[21] M.E. Fouda, A.G. Radwan, Resistive-less memcapacitor-based relaxation oscillator,
Int. J. Circ. Theor. Appl. 43 (2015) 959965.
[22] M.A. Zidan, H. Omran, C. Smith, A. Syed, A.G. Radwan, K.N. Salama, A family of
memristor-based reactance-less oscillators, Int. J. Circ. Theor. Appl. vol. 42 (2013)
1103–1122, https://doi.org/10.1002/cta.1908.
[23] Y.V. Pershin, M. Di Ventra, Experimental demonstration of associative memory
with memristive, neural networks, Neural Network. 2010 453 (2010) 881–886.
[24] A. Talukdar, A.G. Radwan, K.N. Salama, Nonlinear dynamics of memristor based
3rd order oscillatory system, Microtecnic 43 (2012) 169–175.
[25] A. Talukdar, A.G. Radwan, K.N. Salama, Generalized model for memristor-based
wien family oscillators, Microtecnic 42 (2011) 1032–1038.
[26] M.A. Zidan, H.A.H. Fahmy, M.M. Hussain, K.N. Salama, Memristor-based memory:
the sneak paths problem and solutions, Microtecnic 44 (2013) 176–183.
[27] A.A. El-Slehdar, A.H. Fouad, A.G. Radwan, Memristor-based balanced ternary
adder, in: 25th International Conference on Microelectronics (ICM), 2013.
[28] A.A. El-Slehdar, A.H. Fouad, A.G. Radwan, Memristor-based redundant binary
adder, in: International Conference on Engineering and Technology (ICET), 2014.
[29] A.A. El-Slehdar, A.H. Fouad, A.G. Radwan, Memristor based n-bits redundant
binary adder, Microelectron. J. 46 (2015) 207–213.
[30] B. Mohammad, D. Homouz, H. Elgabra, Robust hybrid memristor-cmos memory:
modeling and design, IEEE Trans. Very Large Scale Integr. Syst. 21 (11) (2013)
2069–2079, https://doi.org/10.1109/TVLSI.2012.2227519.
[31] S.S. Sarwar, S.A. Saqueb, F. Quaiyum, A.M.H.U. Rashid, Memristor-based
Nonvolatile Random Access Memory: Hybrid Architecture for Low Power Compact
Memory Design, Access, IEEE 1, 2013, pp. 29–34, https://doi.org/10.1109/
ACCESS.2013.2259891.
[32] C.-F. Liao, M.-Y. Hsu, Y.-D. Chih, J. Chang, Y.-C. King, C.J. Lin, Zero static-power
4t SRAM with self-inhibit resistive switching load by pure CMOS logic process, in:
2016 IEEE International Electron Devices Meeting (IEDM), IEEE, 2016.
[33] S. Wen, Z. Zeng, T. Huang, Exponential stability analysis of memristor-based
recurrent neural networks with time-varying delays, Neurocomputing 97 (2012)
233–240.
[34] U. Russo, D. Ielmini, C. Cagli, A.L. Lacaita, Self-accelerated thermal dissolution
model for reset programming in unipolar resistive-switching memory (rram)
device, IEEE Trans. Electron. Dev. 56 (2009) 193–200.
[35] W. Hiatt, T. Hickmott, Bistable switching in niobium oxide diodes, Appl. Phys.
Lett. 6 (1965) 106–108.
[36] J.J. Yang, I.H. Inoue, T. Mikolajick, C.S. Hwang, Metal oxide memories based on
thermochemical and valence change mechanisms, MRS Bull. 37 (2012) 131–137.
[37] N. Shaarawy, M. Ghoniema, A.G. Radwan, 2t2m memristor based memory cell for
higher stability rram module, in: (ISCAS), 2015 IEEE International Symposium on
Circuits and Systems, 2015, pp. 1418–1421, https://doi.org/10.978-1-4799-
8391-9/ISCAS.2015.
[38] E. Lehtonen, Modeling the HP Memristor with SPICE, 2010. [Online] http://www.
neurdon.com/2010/07/23/modeling-the-hp-memristor-with-spice/.
[39] C. Xu, D. Niu, N. Muralimanohar, R. Balasubramonian, T. Zhang, S. Yu, Y. Xie,
Overcoming the challenges of crossbar resistive memory architectures, in: 2015
IEEE 21st International Symposium on High Performance Computer Architecture
(HPCA), 2015, pp. 476–488.
[40] J. Reuben, R. Ben-Hur, N. Wald, N. Talati, A.H. Ali, P.-E. Gaillardon, S. Kvatinsky,
Memristive Logic: a Framework for Evaluation and Comparison, 2017.
[41] Y. Zhang, D. Feng, J. Liu, W. Tong, B. Wu, C. Fang, A novel reram-based main
memory structure for optimizing access latency and reliability, in: 2017 54th
ACM/EDAC/IEEE Design Automation Conference (DAC), 2017, pp. 1–6.
[42] N. Talati, S. Gupta, P. Mane, Logic Design within Memristive Memories Using
Memristor Aided Logic (Magic), 2016.
[43] A. Emara, M. Ghoneima, M. El-Dessouky, Differential 1t2m memristor memory cell
for single/multi-bit rram modules, in: Computer Science and Electronic
Engineering Conference (CEEC), 2014 6th, 2014, pp. 69–72, https://doi.org/10.
1109/CEEC.2014.6958557.
[44] P.F. Chiu, M.F. Chang, C.W. Wu, C.H. Chuang, S.S. Sheu, Y.S. Chen, M.J. Tsai, Low
store energy, low vddmin, 8t2r nonvolatile latch and sram with vertical-stacked
resistive memory (memristor) devices for low power mobile applications, IEEE J.
Solid State Circ. 47 (6) (2012) 1483–1496, https://doi.org/10.1109/JSSC.2012.
2192661.
[45] A. Emara, M. Ghoneima, A reference-less multilevel memristor based rram module,
in: 2015 IEEE 58th International Midwest Symposium on Circuits and Systems
(MWSCAS), 2015, pp. 1–4, https://doi.org/10.1109/MWSCAS.2015.7282147.
[46] M.A. Zidan, H.A.H. Fahmy, M.M. Hussain, K.N. Salama, Memristor-based memory:
the sneak paths problem and solutions, Microelectron. J. 44 (2) (2013) 176–183.
[47] J.J. Yang, M.D. Pickett, X.M. Li, D.A.A. Ohlberg, D.R. Stewart, R.S. Williams,
Memristive switching mechanism for metal/oxide/metal nanodevices, Nat.
Nanotechnol. 3 (2008) 429–433.
[48] M.T. Chang, P. Rosenfeld, S.L. Lu, B. Jacob, Technology comparison for large
last-level caches (L3 Cs): Low-leakage SRAM, low write-energy STT-RAM, and
refresh-optimized eDRAM, in: IEEE 19th International Symposium on High
Performance Computer Architecture (HPCA), Shenzhen, 2013, pp. 143–154,
https://doi.org/10.1109/HPCA.2013.6522314.
[49] S. Liu, K. Pattabiraman, T. Moscibroda, B.G. Zorn, Flikker: saving dram
refresh-power through critical data partitioning, ACM SIGPLAN Not. 47 (4) (2012)
213–224.
N. Shaarawy et al.
[50] C.W. Oh, N.Y. Kim, S.H. Kim, Y.L. Choi, S.I. Hong, H.J. Bae, J.B. Kim, K.S. Lee,
Y.S. Lee, N.M. Cho, et al., 4-bit double sonos memories (dsms) using single-level
and multi-level cell schemes, in: Electron Devices Meeting, 2006. IEDM’06,
International, IEEE, 2006, pp. 1–4.
[51] R. Muralidhar, R. Steimle, M. Sadd, R. Rao, C. Swift, E. Prinz, J. Yater, L. Grieve, K.
Harber, B. Hradsky, et al., A 6 v embedded 90 nm silicon nanocrystal nonvolatile
memory, in: IEEE International Electron Devices Meeting 2003, Washington, DC,
USA, 2003, pp. 26.2.1–26.2.4, https://doi.org/10.1109/IEDM.2003.1269353.
85
Microelectronics Journal 73 (2018) 75–85
[52] J. Oh, J.H. Park, Y. Lim, H. Lim, Y. Oh, J.S. Kim, J. Shin, Y.J. Song, K. Ryoo, D.
Lim, et al., Full integration of highly manufacturable 512mb pram based on 90nm
technology, in: Electron Devices Meeting, 2006. IEDM’06, International, IEEE,
2006, pp. 1–4.
[53] F. Pellizzer, A. Benvenuti, B. Gleixner, Y. Kim, B. Johnson, M. Magistretti, T.
Marangon, A. Pirovano, R. Bez, G. Atwood, A 90nm phase change memory
technology for stand-alone non-volatile memory applications, in: VLSI Technology,
2006. Digest of Technical Papers. 2006 Symposium on, IEEE, 2006, pp. 122–123.