SPACE SYSTEM S

RF System-in-Package (RF-SiP)
Enabling Next Generation RF-SiP Through Flip Chip

Sean Thorne
Business Development Manager
Space Systems
Cobham Advanced Electronic Solutions

November 4, 2020
Semiconductor Package Technology
The Road to System-in-Package (SiP)

courtesy D. Sheldon, JPL

November 4, 2020
Microwave Journal
2
Webinar Series
 Next Generation Package Technology
Cobham Advanced Package Technology Roadmap for Space/High Rel

QML Non-QML
Legacy Advanced Next Generation
Performance Requirements

System-in-
Package (SiP)

Organic
Class Y
Class Y
Non-hermetic
QML-V
Hermetic

<– 2013 2013-2018 2019 –> Next Generation

Stacked Die Wirebond Flip Chip Fine Pitch Flip Chip Interposer, TSV
Ceramic Leaded Ceramic CGA Organic BGA (2D) 2.1D 2.5D 3D

Package Technology For Space/High Rel

November 4, 2020
Microwave Journal
3
Webinar Series
RF System-in-Package Technology (RF-SiP)
2.1D System-in-Package Technology Example

courtesy EE Times, M. Maxfield

• 2.1D RF-SiP technology provides a path to true heterogeneous

integration solutions
– Heterogeneous die integrated through organic substrate
– Si, SiGe, GaAs and GaN device technologies
– Advanced organic build-up substrate technology with fine lines and spaces
– Advanced flip chip assembly technologies
– Solder bump or Copper pillar flip chip interconnects with underfill

November 4, 2020
Microwave Journal
4
Webinar Series
RF System-in-Package Technology (RF-SiP)
Advantages of Using Flip Chip Technology

• Heterogeneous Integration
– Flip chip assembly of beam forming transmit and receive die, amplifiers and filters
– High density channel footprint to achieve smaller form factor for higher frequency
arrays
• Performance
– Lower parasitic & insertion losses
– Higher speed enabled by short flip chip interconnects and direct connections to
array elements (fewer transitions),
– Smaller variation part to part and within a part due to manufacturing techniques
• Manufacturability
– RF devices designed for flip chip assembly using Cobham design rules for
manufacturing of high reliability products
– Automated assembly using qualified Cobham material sets and assembly processes
following QML flows for space applications per MIL-PRF-38535
• Reliability
– Physics-of-Failure approach to understanding SiP mechanical reliability
– Material set optimized to enhance overall system reliability based on die type,
substrate type and use conditions
November 4, 2020
Microwave Journal
5
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RF System-in-Package Technology (RF-SiP)
Process: Wafer Bumping

• Solder bumped & Cu pillar bumped wafers through assembly with underfill
• Silicon, Silicon-Germanium, Gallium-Arsenic, Gallium-Nitride wafers
• 75mm to 300mm wafer diameters, Full thickness to 50µm thickness

November 4, 2020
Microwave Journal
6
Webinar Series
RF System-in-Package Technology (RF-SiP)
Process: RF Flip Chip Assembly & Underfill

• Flip chip assembly of RF device through underfill

– Flux dip, placement, and solder reflow profile or TCB bonding
– Capillary flow dispense process for underfill and staking options

GaN Cu Pillar
Flip Chip Attach

Pre and Post Underfill Staking Option

November 4, 2020
Microwave Journal
7
Webinar Series
RF System-in-Package Technology (RF-SiP)
Underfill Dielectric Characterization

November 4, 2020
Microwave Journal
8
Webinar Series
Physics-of-Failure Reliability Assessment
Solder Fatigue Modeling using FEA

• Finite Element Analysis used to predict thermal cycle solder fatigue life

FC150 Organic Flip Chip Assembly - Condition B Hysteresis Curve

10000

9000
Predicted
8000 Weibull Life = 2,136 cycles
7000

Equivalent Stress
6000

5000

4000

3000

2000

Test Condition = Condition B

1000
-55/125°C temperature range
15 minute ramps 0
0.000 0.001 0.002 0.003 0.004 0.005
Equivalent Creep Strain

November 4, 2020
Microwave Journal
9
Webinar Series
Physics-of-Failure Reliability Assessment
GaN Flip Chip Reliability Study

• Daisy Chain Test Vehicle and Experimental Matrix

– GaN daisy chain test vehicles, 3x3mm and 6x6mm to represent RF device footprints
– Test board designed and procured with multiple solder mask sizes
– Optimized flip chip assembly with and without underfill
– Experimental matrix defined; initial focus on solder bump and effect of underfill by
die size
– Test vehicle assembly complete; temperature cycle testing in progress

November 4, 2020
Microwave Journal
10
Webinar Series
RF System-in-Package Technology (RF-SiP)
Summary

• Package assembly technology plays a critical role in advancing RF

solutions for next generation products
• Flip chip assembly technology enables advanced RF-SiP solutions
across the following areas
– Heterogeneous Integration (HI)
– Enhanced Performance (lower parasitics, reduced losses)
– Manufacturability (repeatability and automation)
• Flip chip technology implementation requires planning and
characterized processes
– Wafer bumping of thin III-V semiconductor wafers
– Flip chip assembly/inspection techniques
– Underfill characterization for IC/MMIC performance
– Product reliability assessments/analysis leveraging a Physics-of-Failure approach
 Understanding underfill performance with various substrate materials (adhesion, CTE
mismatch) through experimental data and validated reliability prediction methodologies
 Underfill material characteristics suitability to the program requirements (outgassing,
glass transition temperature, dielectric constant/loss tangent)
– Early engagement between chip/system design, packaging and manufacturing
November 4, 2020
Microwave Journal
11
Webinar Series
 SPACE SYSTEM S

ACKNOWLEDGEMENTS
Scott Popelar, Development Engineer Chief
Julie Hook, Principal Process Engineer Technician

QUESTIONS