Physical Address

= Segment Address x 10H + Offset Address

8086 does not have a RAM or ROM inside it. However, it has internal
registers for storing intermediate and final results and interfaces with
memory located outside it through the System Bus. 
In case of 8086, it is a 16-bit Integer processor in a 40 pin, Dual Inline
Packaged IC. 
The internal architecture of Intel 8086 is divided into 2 units: The Bus
Interface Unit (BIU), and The Execution Unit (EU). These are explained
as following below.

1. The Bus Interface Unit (BIU):

It provides the interface of 8086 to external memory and I/O devices via
the System Bus. It performs various machine cycles such as memory
read, I/O read etc. to transfer data between memory and I/O devices. 
BIU performs the following functions- 
 It generates the 20 bit physical address for memory access.
 It fetches instructions from the memory.
 It transfers data to and from the memory and I/O.
 Maintains the 6 byte prefetch instruction queue(supports
pipelining).
BIU mainly contains the 4 Segment registers, the Instruction Pointer, a
prefetch queue and an Address Generation Circuit. 
Address Generation Circuit: 
 The BIU has a Physical Address Generation Circuit.
 It generates the 20 bit physical address using Segment and Offset
addresses using the formula: 
 
Physical Address
= Segment Address x 10H + Offset Address

The main components of the EU are General purpose registers, the ALU,
Special purpose registers, Instruction Register and Instruction Decoder
and the Flag/Status Register. 
1. Fetches instructions from the Queue in BIU, decodes and executes
arithmetic and logic operations using the ALU.
2. Sends control signals for internal data transfer operations within
the microprocessor.
3. Sends request signals to the BIU to access the external module.
4. It operates with respect to T-states (clock cycles) and not machine
cycles.

3 answer:
Wait states are extra clock pulses pulses inserted when the processor is
accessing slow memory or I/O devices.The WAIT state plays a significant
role in preventing CPU speed incompatibilities. The 8088/8086 allow
approximately 3 clock pulses for a memory read or memory write. ... The
circuit shown adds 1 wait state in each memory read or write cycle.
In response to request by an event in external hardware.READY input of 8086 is set
LOWAs long as READY is held low, wait states (Tw) are inserted between T3 and
T4For a write cycle, data maintained on the bus

Purpose: to extend the duration of the bus cycle, so slower memory devices can be
used

So, Wait states can be used to reduce the energy consumption of

a processor, by allowing the main processor clock to either slow down or
temporarily pause during the wait state if the CPU has no other work to do

Answer:1

Because it has instructions that can write single bytes, it thus needs two
separate write enables (even and odd) so it can write to a 16-bit word and
only write one of the two bytes. So the memory must be organized as two
separate "banks", each of which is one byte wide, that can be written
independently