Professional Documents
Culture Documents
PIC18F2455/2550/4455/4550 Data Sheet
PIC18F2455/2550/4455/4550 Data Sheet
Data Sheet
28/40/44-Pin, High-Performance,
Enhanced Flash, USB Microcontrollers
with nanoWatt Technology
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
MCLR/VPP/RE3 1 28 RB7/KBI3/PGD
RA0/AN0 2 27 RB6/KBI2/PGC
RA1/AN1 3 26 RB5/KBI1/PGM
RA2/AN2/VREF-/CVREF 4 25 RB4/AN11/KBI0
RB3/AN9/CCP2(1)/VPO
PIC18F2455
PIC18F2550
RA3/AN3/VREF+ 5 24
RA4/T0CKI/C1OUT/RCV 6 23 RB2/AN8/INT2/VMO
RA5/AN4/SS/HLVDIN/C2OUT 7 22 RB1/AN10/INT1/SCK/SCL
VSS 8 21 RB0/AN12/INT0/FLT0/SDI/SDA
OSC1/CLKI 9 20 VDD
OSC2/CLKO/RA6 10 19 VSS
RC0/T1OSO/T13CKI 11 18 RC7/RX/DT/SDO
RC1/T1OSI/CCP2(1)/UOE 12 17 RC6/TX/CK
RC2/CCP1 13 16 RC5/D+/VP
VUSB 14 15 RC4/D-/VM
40-Pin PDIP
MCLR/VPP/RE3 1 40 RB7/KBI3/PGD
RA0/AN0 2 39 RB6/KBI2/PGC
RA1/AN1 3 38 RB5/KBI1/PGM
RA2/AN2/VREF-/CVREF 4 37 RB4/AN11/KBI0/CSSPP
RA3/AN3/VREF+ 5 36 RB3/AN9/CCP2(1)/VPO
RA4/T0CKI/C1OUT/RCV 6 35 RB2/AN8/INT2/VMO
RA5/AN4/SS/HLVDIN/C2OUT 7 34 RB1/AN10/INT1/SCK/SCL
RE0/AN5/CK1SPP 8 33 RB0/AN12/INT0/FLT0/SDI/SDA
PIC18F4455
PIC18F4550
RE1/AN6/CK2SPP 9 32 VDD
RE2/AN7/OESPP 10 31 VSS
VDD 11 30 RD7/SPP7/P1D
VSS 12 29 RD6/SPP6/P1C
OSC1/CLKI 13 28 RD5/SPP5/P1B
OSC2/CLKO/RA6 14 27 RD4/SPP4
RC0/T1OSO/T13CKI 15 26 RC7/RX/DT/SDO
RC1/T1OSI/CCP2(1)/UOE 16 25 RC6/TX/CK
RC2/CCP1/P1A 17 24 RC5/D+/VP
VUSB 18 23 RC4/D-/VM
RD0/SPP0 19 22 RD3/SPP3
RD1/SPP1 20 21 RD2/SPP2
RC1/T1OSI/CCP2(1)/UOE
NC/ICPORTS(2)
RC2/CCP1/P1A
44-Pin TQFP
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
RD3/SPP3
RD2/SPP2
RD1/SPP1
RD0/SPP0
VUSB
44
43
42
41
40
39
37
36
35
34
38
RC7/RX/DT/SDO 1 33 NC/ICRST(2)/ICVPP(2)
RD4/SPP4 2 32 RC0/T1OSO/T13CKI
RD5/SPP5/P1B 3 31 OSC2/CLKO/RA6
RD6/SPP6/P1C 4 30 OSC1/CLKI
RD7/SPP7/P1D 5 PIC18F4455 29 VSS
VSS 6 28 VDD
VDD 7
PIC18F4550 27 RE2/AN7/OESPP
RB0/AN12/INT0/FLT0/SDI/SDA 8 26 RE1/AN6/CK2SPP
RB1/AN10/INT1/SCK/SCL 9 25 RE0/AN5/CK1SPP
RB2/AN8/INT2/VMO 10 24 RA5/AN4/SS/HLVDIN/C2OUT
RB3/AN9/CCP2(1)/VPO 11 23 RA4/T0CKI/C1OUT/RCV
12
13
14
15
16
17
18
19
20
21
22
RB4/AN11/KBI0/CSSPP
RA2/AN2/VREF-/CVREF
NC/ICCK(2)/ICPGC(2)
NC/ICDT(2)/ICPGD(2)
RB5/KBI1/PGM
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RB6/KBI2/PGC
RB7/KBI3/PGD
RA3/AN3/VREF+
RC1/T1OSI/CCP2(1)/UOE
RC0/T1OSO/T13CKI
RC2/CCP1/P1A
44-Pin QFN
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
RD3/SPP3
RD2/SPP2
RD1/SPP1
RD0/SPP0
VUSB
44
43
42
41
40
39
37
36
35
34
38
RC7/RX/DT/SDO 1 33 OSC2/CLKO/RA6
RD4/SPP4 2 32 OSC1/CLKI
RD5/SPP5/P1B 3 31 VSS
RD6/SPP6/P1C 4 30 VSS
RD7/SPP7/P1D 5 PIC18F4455 29 VDD
VSS 6 28 VDD
PIC18F4550 27 RE2/AN7/OESPP
VDD 7
VDD 8 26 RE1/AN6/CK2SPP
RB0/AN12/INT0/FLT0/SDI/SDA 9 25 RE0/AN5/CK1SPP
RB1/AN10/INT1/SCK/SCL 10 24 RA5/AN4/SS/HLVDIN/C2OUT
RB2/AN8/INT2/VMO 11 23 RA4/T0CKI/C1OUT/RCV
12
13
14
15
16
17
18
19
20
21
22
RB4/AN11/KBI0/CSSPP
RB3/AN9/CCP2(1)/VPO
RA2/AN2/VREF-/CVREF
RB5/KBI1/PGM
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
NC
RB6/KBI2/PGC
RB7/KBI3/PGD
RA3/AN3/VREF+
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
8
Instruction State Machine
Decode & Control Signals
Control
PRODH PRODL
PORTC
8 x 8 Multiply RC0/T1OSO/T13CKI
3 8 RC1/T1OSI/CCP2(3)/UOE
(2) Internal RC2/CCP1
OSC1 Power-up
Oscillator BITOP W
Timer 8 RC4/D-/VM
Block 8 8
OSC2(2) Oscillator RC5/D+/VP
INTRC Start-up Timer RC6/TX/CK
Oscillator Power-on 8 8 RC7/RX/DT/SDO
T1OSI
Reset
8 MHz ALU<8>
T1OSO Oscillator Watchdog
Timer
8
Single-Supply Brown-out
MCLR(1) Reset
Programming
In-Circuit Fail-Safe
VDD, VSS Debugger Clock Monitor
PORTE
USB Voltage Band Gap
VUSB
Regulator Reference
MCLR/VPP/RE3(1)
BOR Data
EEPROM Timer0 Timer1 Timer2 Timer3
HLVD
ADC
Comparator CCP1 CCP2 MSSP EUSART USB
10-Bit
Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer
to Section 2.0 “Oscillator Configurations” for additional information.
3: RB3 is the alternate pin for CCP2 multiplexing.
Address PORTC
ROM Latch
Instruction Bus <16> Decode RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(4)/UOE
IR RC2/CCP1/P1A
RC4/D-/VM
RC5/D+/VP
8 RC6/TX/CK
Instruction State Machine RC7/RX/DT/SDO
Decode & Control Signals
Control
PRODH PRODL
PORTD
8 x 8 Multiply
VDD, VSS 3 8
Internal
Oscillator Power-up RD0/SPP0:RD4/SPP4
OSC1(2) Timer BITOP W
Block 8 8 8 RD5/SPP5/P1B
OSC2(2) Oscillator RD6/SPP6/P1C
INTRC RD7/SPP7/P1D
Start-up Timer
T1OSI Oscillator 8 8
Power-on
T1OSO 8 MHz
Oscillator Reset ALU<8>
Watchdog 8
ICPGC(3) Single-Supply Timer
Programming Brown-out
ICPGD(3) Reset PORTE
In-Circuit RE0/AN5/CK1SPP
ICPORTS(3) Debugger Fail-Safe RE1/AN6/CK2SPP
Clock Monitor Band Gap RE2/AN7/OESPP
ICRST(3)
Reference MCLR/VPP/RE3(1)
MCLR(1) USB Voltage
Regulator
VUSB
BOR Data
EEPROM Timer0 Timer1 Timer2 Timer3
HLVD
Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer
to Section 2.0 “Oscillator Configurations” for additional information.
3: These pins are only available on 44-pin TQFP packages under certain conditions. Refer to Section 25.9 “Special ICPORT Features
(Designated Packages Only)” for additional information.
4: RB3 is the alternate pin for CCP2 multiplexing.
PIC18F2455/2550/4455/4550
PLL Prescaler
101 (4 MHz Input Only)
Primary Oscillator ÷5 0
MUX
100 96 MHz ÷2
OSC2 ÷4
1
011 PLL
Sleep ÷3
010
OSC1 ÷2 001 FSEN
÷1 000
HSPLL, ECPLL, 1
USB
XTPLL, ECPIO Peripheral
CPUDIV
÷6 ÷4 0
PLL Postscaler
11
÷4
CPUDIV 10
÷3
01
Oscillator Postscaler
÷4 ÷2
11 00
÷3
10 CPU
XT, HS, EC, ECIO
÷2 01
1
÷1
0 Primary
00 Clock IDLEN
FOSC3:FOSC0
Secondary Oscillator Peripherals
MUX
T1OSO
T1OSC
T1OSCEN
Enable
T1OSI Oscillator
OSCCON<6:4> 8 MHz
111
4 MHz
Internal 110 Clock
INTOSC Postscaler
8 MHz 100
Source 8 MHz 500 kHz FOSC3:FOSC0 OSCCON<1:0>
011
(INTOSC) 250 kHz
INTRC 010
Source 125 kHz
001 Clock Source Option
1 31 kHz for other Modules
31 kHz (INTRC) 000
0
OSCTUNE<7>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2.2.5.4 Compensating for INTOSC Drift an interrupt occurs, the internally clocked timer is read
and both timers are cleared. If the internally clocked
It is possible to adjust the INTOSC frequency by
timer value is greater than expected, then the internal
modifying the value in the OSCTUNE register. This has
oscillator block is running too fast. To adjust for this,
no effect on the INTRC clock source frequency.
decrement the OSCTUNE register.
Tuning the INTOSC source requires knowing when to
Finally, a CCP module can use free-running Timer1 (or
make the adjustment, in which direction it should be
Timer3), clocked by the internal oscillator block and an
made and in some cases, how large a change is
external event with a known period (i.e., AC power
needed. When using the EUSART, for example, an
frequency). The time of the first event is captured in the
adjustment may be required when it begins to generate
CCPRxH:CCPRxL registers and is recorded for use
framing errors or receives data with errors while in
later. When the second event causes a capture, the
Asynchronous mode. Framing errors indicate that the
time of the first event is subtracted from the time of the
device clock frequency is too high; to adjust for this,
second event. Since the period of the external event is
decrement the value in OSCTUNE to reduce the clock
known, the time difference between events can be
frequency. On the other hand, errors in data may sug-
calculated.
gest that the clock speed is too low; to compensate,
increment OSCTUNE to increase the clock frequency. If the measured time is much greater than the calcu-
lated time, the internal oscillator block is running too
It is also possible to verify device clock speed against
fast; to compensate, decrement the OSCTUNE register.
a reference clock. Two timers may be used: one timer
If the measured time is much less than the calculated
is clocked by the peripheral clock, while the other is
time, the internal oscillator block is running too slow; to
clocked by a fixed reference source, such as the
compensate, increment the OSCTUNE register.
Timer1 oscillator. Both timers are cleared but the timer
clocked by the reference generates interrupts. When
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
T1OSI 1 2 3 n-1 n
CPU
Clock
Peripheral
Clock
Program
Counter PC PC + 2 PC + 4
FIGURE 3-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
T1OSI
OSC1
TOST(1) TPLL(1)
1 2 n-1 n
PLL Clock
Output
Clock(2)
Transition
CPU Clock
Peripheral
Clock
Program PC PC + 2 PC + 4
Counter
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2: Clock transition typically occurs within 2-4 TOSC.
3.2.3 RC_RUN MODE This mode is entered by setting SCS1 to ‘1’. Although
it is ignored, it is recommended that SCS0 also be
In RC_RUN mode, the CPU and peripherals are
cleared; this is to maintain software compatibility with
clocked from the internal oscillator block using the
future devices. When the clock source is switched to
INTOSC multiplexer; the primary clock is shut down.
the INTOSC multiplexer (see Figure 3-3), the primary
When using the INTRC source, this mode provides the
oscillator is shut down and the OSTS bit is cleared. The
best power conservation of all the Run modes while still
IRCF bits may be modified at any time to immediately
executing code. It works well for user applications
change the clock speed.
which are not highly timing sensitive or do not require
high-speed clocks at all times. Note: Caution should be used when modifying a
If the primary clock source is the internal oscillator single IRCF bit. If VDD is less than 3V, it is
block (either INTRC or INTOSC), there are no distin- possible to select a higher clock speed
guishable differences between the PRI_RUN and than is supported by the low VDD.
RC_RUN modes during execution. However, a clock Improper device operation may result if
switch delay will occur during entry to and exit from the VDD/FOSC specifications are violated.
RC_RUN mode. Therefore, if the primary clock source
is the internal oscillator block, the use of RC_RUN
mode is not recommended.
INTRC 1 2 3 n-1 n
CPU
Clock
Peripheral
Clock
Program
Counter PC PC + 2 PC + 4
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
INTOSC
Multiplexer
OSC1
TOST(1) TPLL(1)
1 2 n-1 n
PLL Clock
Output
Clock(2)
Transition
CPU Clock
Peripheral
Clock
Program PC PC + 2 PC + 4
Counter
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2: Clock transition typically occurs within 2-4 TOSC.
CPU
Clock
Peripheral
Clock
Sleep
Program
Counter PC PC + 2
OSC1
TOST(1) TPLL(1)
PLL Clock
Output
CPU Clock
Peripheral
Clock
Program PC PC + 2 PC + 4 PC + 6
Counter
Q1 Q2 Q3 Q4 Q1
OSC1
CPU Clock
Peripheral
Clock
Program PC PC + 2
Counter
FIGURE 3-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Q1 Q2 Q3 Q4
OSC1
TCSD
CPU Clock
Peripheral
Clock
Program
Counter PC
Wake Event
TABLE 3-2: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Microcontroller Clock Source Clock Ready Status
Exit Delay
Before Wake-up After Wake-up Bit (OSCCON)
XT, HS
Primary Device Clock XTPLL, HSPLL OSTS
None
(PRI_IDLE mode) EC
INTOSC(3) IOFS
XT, HS TOST(4)
XTPLL, HSPLL TOST + trc(4) OSTS
T1OSC or INTRC(1)
EC TCSD(2)
INTOSC(3) TIOBST(5) IOFS
XT, HS TOST(4)
XTPLL, HSPLL TOST + trc(4) OSTS
INTOSC(3)
EC TCSD(2)
INTOSC(3) None IOFS
XT, HS TOST(4)
None XTPLL, HSPLL TOST + trc(4) OSTS
(Sleep mode) EC TCSD(2)
INTOSC(3) TIOBST(5) IOFS
Note 1: In this instance, refers specifically to the 31 kHz INTRC clock source.
2: TCSD (parameter 38, Table 28-12) is a required delay when waking from Sleep and all Idle modes and runs
concurrently with any other required delays (see Section 3.4 “Idle Modes”).
3: Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
4: TOST is the Oscillator Start-up Timer period (parameter 32, Table 28-12). trc is the PLL lock time-out
(parameter F12, Table 28-9); it is also designated as TPLL.
5: Execution continues during TIOBST (parameter 39, Table 28-12), the INTOSC stabilization period.
External Reset
MCLRE
MCLR
( )_IDLE
Sleep
WDT
Time-out
OST/PWRT
OST 1024 Cycles
Chip_Reset
10-Bit Ripple Counter R Q
OSC1
32 μs 65.5 ms
PWRT
INTRC(1) 11-Bit Ripple Counter
Enable PWRT
Enable OST(2)
Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin.
2: See Table 4-2 for time-out situations.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent
Power-on Resets may be detected.
2: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to
‘1’ by software immediately after POR).
VDD
MCLR
INTERNAL POR
TPWRT
OST TIME-OUT
INTERNAL RESET
FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
OST TIME-OUT
INTERNAL RESET
FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
OST TIME-OUT
INTERNAL RESET
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 4-7: TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PLL TIME-OUT
INTERNAL RESET
TABLE 4-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION
FOR RCON REGISTER
FIGURE 5-1: PROGRAM MEMORY MAP AND STACK FOR PIC18F2455/2550/4455/4550 DEVICES
PIC18FX455 PIC18FX550
PC<20:0> PC<20:0>
CALL, RCALL, RETURN, 21 CALL, RCALL, RETURN, 21
RETFIE, RETLW, CALLW, RETFIE, RETLW, CALLW,
ADDULNK, SUBULNK ADDULNK, SUBULNK
Stack Level 1 Stack Level 1
• •
• •
• •
Stack Level 31 Stack Level 31
High Priority Interrupt Vector 0008h High Priority Interrupt Vector 0008h
Low Priority Interrupt Vector 0018h Low Priority Interrupt Vector 0018h
On-Chip
Program Memory On-Chip
Program Memory
5FFFh
6000h
User Memory Space
7FFFh
8000h
1FFFFFh 1FFFFFh
200000h 200000h
11111
11110
Top-of-Stack Registers 11101 Stack Pointer
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2 Internal
Q3 Phase
Clock
Q4
PC PC PC + 2 PC + 4
OSC2/CLKO
(RC mode)
Execute INST (PC – 2)
Fetch INST (PC) Execute INST (PC)
Fetch INST (PC + 2) Execute INST (PC + 2)
Fetch INST (PC + 4)
Note: All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
5.2.4 TWO-WORD INSTRUCTIONS used by the instruction sequence. If the first word is
skipped for some reason and the second word is
The standard PIC18 instruction set has four two-word
executed by itself, a NOP is executed instead. This is
instructions: CALL, MOVFF, GOTO and LSFR. In all
necessary for cases when the two-word instruction is
cases, the second word of the instructions always has
preceded by a conditional instruction that changes the
‘1111’ as its four Most Significant bits; the other 12 bits
PC. Example 5-4 shows how this works.
are literal data, usually a data memory address.
The use of ‘1111’ in the 4 MSbs of an instruction Note: See Section 5.5 “Program Memory and
specifies a special form of NOP. If the instruction is the Extended Instruction Set” for
executed in proper sequence, immediately after the information on two-word instruction in the
first word, the data in the second word is accessed and extended instruction set.
When a = 0:
BSR<3:0> Data Memory Map
The BSR is ignored and the
00h 000h Access Bank is used.
= 0000 Access RAM 05Fh
Bank 0 060h The first 96 bytes are
FFh GPR 0FFh general purpose RAM
00h 100h (from Bank 0).
= 0001
Bank 1 GPR The remaining 160 bytes are
FFh 1FFh Special Function Registers
= 0010 00h 200h (from Bank 15).
Bank 2 GPR
FFh When a = 1:
2FFh
= 0011 00h 300h The BSR specifies the bank
Bank 3 GPR used by the instruction.
FFh 3FFh
00h 400h
= 0100 Bank 4 GPR(1)
FFh 4FFh
= 0101 00h 500h
Bank 5 GPR(1)
FFh 5FFh
= 0110 00h 600h
Bank 6 GPR(1)
Access Bank
FFh 6FFh
= 0111 00h 700h 00h
Bank 7 GPR(1) Access RAM Low
5Fh
FFh 7FFh Access RAM High 60h
00h 800h (SFRs) FFh
= 1000
Bank 8
Unused
to Read as 00h
= 1110
Bank 14
FFh EFFh
00h Unused F00h
= 1111 F5Fh
Bank 15
SFR F60h
FFh FFFh
Note 1: These banks also serve as RAM buffer for USB operation. See Section 5.3.1 “USB RAM” for more
information.
BSR(1)
Data Memory From Opcode(2)
7 0 000h 00h 7 0
0 0 0 0 0 0 1 1 Bank 0 1 1 1 1 1 1 1 1
FFh
100h 00h
Bank 1
Bank Select(2) 200h FFh
00h
Bank 2
300h FFh
00h
Bank 3
through
Bank 13
FFh
E00h
00h
Bank 14
F00h FFh
00h
Bank 15
FFFh FFh
Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to
the registers of the Access Bank.
2: The MOVFF instruction embeds the entire 12-bit address in the instruction.
5.3.3 ACCESS BANK however, the instruction is forced to use the Access
Bank address map; the current value of the BSR is
While the use of the BSR, with an embedded 8-bit
ignored entirely.
address, allows users to address the entire range of
data memory, it also means that the user must always Using this “forced” addressing allows the instruction to
ensure that the correct bank is selected. Otherwise, operate on a data address in a single cycle without
data may be read from or written to the wrong location. updating the BSR first. For 8-bit addresses of 60h and
This can be disastrous if a GPR is the intended target above, this means that users can evaluate and operate
of an operation but an SFR is written to instead. on SFRs more efficiently. The Access RAM below 60h
Verifying and/or changing the BSR for each read or is a good place for data values that the user might need
write to data memory can become very inefficient. to access rapidly, such as immediate computational
results or common program variables. Access RAM
To streamline access for the most commonly used data
also allows for faster and more code efficient context
memory locations, the data memory is configured with
saving and switching of variables.
an Access Bank, which allows users to access a
mapped block of memory without specifying a BSR. The mapping of the Access Bank is slightly different
The Access Bank consists of the first 96 bytes of when the extended instruction set is enabled (XINST
memory (00h-5Fh) in Bank 0 and the last 160 bytes of Configuration bit = 1). This is discussed in more detail
memory (60h-FFh) in Block 15. The lower half is known in Section 5.6.3 “Mapping the Access Bank in
as the “Access RAM” and is composed of GPRs. The Indexed Literal Offset Mode”.
upper half is where the device’s SFRs are mapped.
These two areas are mapped contiguously in the 5.3.4 GENERAL PURPOSE
Access Bank and can be addressed in a linear fashion REGISTER FILE
by an 8-bit address (Figure 5-5). PIC18 devices may have banked memory in the GPR
The Access Bank is used by core PIC18 instructions area. This is data RAM which is available for use by all
that include the Access RAM bit (the ‘a’ parameter in instructions. GPRs start at the bottom of Bank 0
the instruction). When ‘a’ is equal to ‘1’, the instruction (address 000h) and grow upwards towards the bottom
uses the BSR and the 8-bit address included in the of the SFR area. GPRs are not initialized by a
opcode for the data memory address. When ‘a’ is ‘0’, Power-on Reset and are unchanged on all other
Resets.
OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0100 q000 52, 32
HLVDCON VDIRMAG — IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 0-00 0101 52, 279
WDTCON — — — — — — — SWDTEN --- ---0 52, 298
(2)
RCON IPEN SBOREN — RI TO PD POR BOR 0q-1 11q0 52, 44
TMR1H Timer1 Register High Byte xxxx xxxx 52, 133
TMR1L Timer1 Register Low Byte xxxx xxxx 52, 133
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 52, 129
TMR2 Timer2 Register 0000 0000 52, 136
PR2 Timer2 Period Register 1111 1111 52, 136
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 52, 135
SSPBUF MSSP Receive Buffer/Transmit Register xxxx xxxx 52, 194,
202
SSPADD MSSP Address Register in I2C™ Slave mode. MSSP Baud Rate Reload Register in I2C™ Master mode. 0000 0000 52, 202
SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 52, 194,
203
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 52, 195,
204
SSPCON2 GCEN ACKSTAT ACKDT/ ACKEN/ RCEN/ PEN/ RSEN/ SEN 0000 0000 52, 205
ADMSK5(7) ADMSK4(7) ADMSK3(7) ADMSK2(7) ADMSK1(7)
ADRESH A/D Result Register High Byte xxxx xxxx 52, 268
ADRESL A/D Result Register Low Byte xxxx xxxx 52, 268
ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 52, 259
ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0qqq 52, 260
ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 52, 261
CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 53, 142
CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 53, 142
CCP1CON P1M1(3) P1M0(3) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 53, 141,
149
CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx 53, 142
CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx 53, 142
CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 53, 141
BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 0100 0-00 53, 240
ECCP1DEL PRSEN PDC6(3) PDC5(3) PDC4(3) PDC3(3) PDC2(3) PDC1(3) PDC0(3) 0000 0000 53, 158
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(3) PSSBD0(3) 0000 0000 53, 159
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 53, 275
CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 53, 269
TMR3H Timer3 Register High Byte xxxx xxxx 53, 139
TMR3L Timer3 Register Low Byte xxxx xxxx 53, 139
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 53, 137
SPBRGH EUSART Baud Rate Generator Register High Byte 0000 0000 53, 241
SPBRG EUSART Baud Rate Generator Register Low Byte 0000 0000 53, 241
RCREG EUSART Receive Register 0000 0000 53, 250
TXREG EUSART Transmit Register 0000 0000 53, 247
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 53, 238
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 53, 239
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Note 1: Bit 21 of the TBLPTRU allows access to the device Configuration bits.
2: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
3: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
4: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
5: RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’.
6: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
7: I2C Slave mode only.
UCFG UTEYE UOEMON — UPUEN UTRDIS FSEN PPB1 PPB0 00-0 0000 55, 166
UADDR — ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 -000 0000 55, 170
UCON — PPBRST SE0 PKTDIS USBEN RESUME SUSPND — -0x0 000- 55, 164
USTAT — ENDP3 ENDP2 ENDP1 ENDP0 DIR PPBI — -xxx xxx- 55, 168
UEIE BTSEE — — BTOEE DFN8EE CRC16EE CRC5EE PIDEE 0--0 0000 55, 182
UEIR BTSEF — — BTOEF DFN8EF CRC16EF CRC5EF PIDEF 0--0 0000 55, 181
UIE — SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE -000 0000 55, 180
UIR — SOFIF STALLIF IDLEIF TRNIF ACTVIF UERRIF URSTIF -000 0000 55, 178
UFRMH — — — — — FRM10 FRM9 FRM8 ---- -xxx 55, 170
UFRML FRM7 FRM6 FRM5 FRM4 FRM3 FRM2 FRM1 FRM0 xxxx xxxx 55, 170
SPPCON(3) — — — — — — SPPOWN SPPEN ---- --00 55, 187
SPPEPS(3) RDSPP WRSPP — SPPBUSY ADDR3 ADDR2 ADDR1 ADDR0 00-0 0000 55, 191
SPPCFG(3) CLKCFG1 CLKCFG0 CSEN CLK1EN WS3 WS2 WS1 WS0 0000 0000 55, 188
SPPDATA(3) DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 0000 0000 55, 192
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Note 1: Bit 21 of the TBLPTRU allows access to the device Configuration bits.
2: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
3: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
4: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
5: RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’.
6: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
7: I2C Slave mode only.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register.
2: For Borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the
source register.
000h
When a = 0 and f ≥ 60h:
The instruction executes in 060h
Direct Forced mode. ‘f’ is inter- 080h Bank 0
preted as a location in the 100h
Access RAM between 060h 00h
and 0FFh. This is the same as Bank 1 60h
the SFRs or locations F60h to through
Bank 14 Valid range
0FFh (Bank 15) of data for ‘f’
memory.
FFh
F00h Access RAM
Locations below 60h are not
Bank 15
available in this addressing F60h
mode.
SFRs
FFFh
Data Memory
BSR
When a = 1 (all values of f): 000h 00000000
Bank 0
The instruction executes in
080h
Direct mode (also known as
Direct Long mode). ‘f’ is inter- 100h
preted as a location in one of
the 16 banks of the data 001001da ffffffff
Bank 1
memory space. The bank is through
designated by the Bank Select Bank 14
Register (BSR). The address
can be in any implemented F00h
bank in the data memory Bank 15
F60h
space.
SFRs
FFFh
Data Memory
Instruction: TBLRD*
Program Memory
Table Pointer(1)
Table Latch (8-bit)
TBLPTRU TBLPTRH TBLPTRL
TABLAT
Program Memory
(TBLPTR)
Instruction: TBLWT*
Program Memory
Holding Registers
Table Pointer(1) Table Latch (8-bit)
TBLPTRU TBLPTRH TBLPTRL TABLAT
Program Memory
(TBLPTR)
Note 1: Table Pointer actually points to one of 32 holding registers, the address of which is determined by
TBLPTRL<4:0>. The process for physically writing data to the program memory array is discussed in
Section 6.5 “Writing to Flash Program Memory”.
6.2 Control Registers The FREE bit, when set, will allow a program memory
erase operation. When FREE is set, the erase
Several control registers are used in conjunction with operation is initiated on the next WR command. When
the TBLRD and TBLWT instructions. These include the: FREE is clear, only writes are enabled.
• EECON1 register The WREN bit, when set, will allow a write operation.
• EECON2 register On power-up, the WREN bit is clear. The WRERR bit is
• TABLAT register set in hardware when the WREN bit is set and cleared
• TBLPTR registers when the internal programming timer expires and the
write operation is complete.
6.2.1 EECON1 AND EECON2 REGISTERS Note: During normal operation, the WRERR is
The EECON1 register (Register 6-1) is the control read as ‘1’. This can indicate that a write
register for memory accesses. The EECON2 register is operation was prematurely terminated by
not a physical register; it is used exclusively in the a Reset or a write operation was
memory write and erase sequences. Reading attempted improperly.
EECON2 will read all ‘0’s.
The WR control bit initiates write operations. The bit
The EEPGD control bit determines if the access will be cannot be cleared, only set, in software; it is cleared in
a program or data EEPROM memory access. When hardware at the completion of the write operation.
clear, any subsequent operations will operate on the
data EEPROM memory. When set, any subsequent Note: The EEIF interrupt flag bit (PIR2<4>) is set
operations will operate on the program memory. when the write is complete. It must be
cleared in software.
The CFGS control bit determines if the access will be
to the Configuration/Calibration registers or to program
memory/data EEPROM memory. When set,
subsequent operations will operate on Configuration
registers regardless of EEPGD (see Section 25.0
“Special Features of the CPU”). When clear, memory
selection access is determined by EEPGD.
Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error
condition.
TABLE 6-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Example Operation on Table Pointer
TBLRD*
TBLPTR is not modified
TBLWT*
TBLRD*+
TBLPTR is incremented after the read/write
TBLWT*+
TBLRD*-
TBLPTR is decremented after the read/write
TBLWT*-
TBLRD+*
TBLPTR is incremented before the read/write
TBLWT+*
TABLE ERASE
TBLPTR<21:6>
Program Memory
TABLAT
Write Register
8 8 8 8
Program Memory
Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error
condition.
TMR1IF GIE/GIEH
TMR1IE
TMR1IP IPEN
INT1IF
Additional Peripheral Interrupts INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and
allow the bit to be cleared.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding
enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding
enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: This bit is reserved on 28-pin devices; always maintain this bit clear.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: This bit is reserved on 28-pin devices; always maintain this bit clear.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: This bit is reserved on 28-pin devices; always maintain this bit clear.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’. See Register 4-1 for additional information.
2: The actual Reset value of POR is determined by the type of device Reset. See Register 4-1 for additional
information.
RA0/AN0 RA0 0 OUT DIG LATA<0> data output; not affected by analog input.
1 IN TTL PORTA<0> data input; disabled when analog input enabled.
AN0 1 IN ANA A/D input channel 0 and Comparator C1- input. Default configuration
on POR; does not affect digital output.
RA1/AN1 RA1 0 OUT DIG LATA<1> data output; not affected by analog input.
1 IN TTL PORTA<1> data input; reads ‘0’ on POR.
AN1 1 IN ANA A/D input channel 1 and Comparator C2- input. Default configuration
on POR; does not affect digital output.
RA2/AN2/ RA2 0 OUT DIG LATA<2> data output; not affected by analog input. Disabled when
VREF-/CVREF CVREF output enabled.
1 IN TTL PORTA<2> data input. Disabled when analog functions enabled;
disabled when CVREF output enabled.
AN2 1 IN ANA A/D input channel 2 and Comparator C2+ input. Default configuration
on POR; not affected by analog output.
VREF- 1 IN ANA A/D and comparator voltage reference low input.
CVREF x OUT ANA Comparator voltage reference output. Enabling this feature disables
digital I/O.
RA3/AN3/ RA3 0 OUT DIG LATA<3> data output; not affected by analog input.
VREF+ 1 IN TTL PORTA<3> data input; disabled when analog input enabled.
AN3 1 IN ANA A/D input channel 3 and Comparator C1+ input. Default configuration
on POR.
VREF+ 1 IN ANA A/D and comparator voltage reference high input.
RA4/T0CKI/ RA4 0 OUT DIG LATA<4> data output; not affected by analog input.
C1OUT/RCV 1 IN ST PORTA<4> data input; disabled when analog input enabled.
T0CKI 1 IN ST Timer0 clock input.
C1OUT 0 OUT DIG Comparator 1 output; takes priority over port data.
RCV x IN TTL External USB transceiver RCV input.
RA5/AN4/SS/ RA5 0 OUT DIG LATA<5> data output; not affected by analog input.
HLVDIN/C2OUT 1 IN TTL PORTA<5> data input; disabled when analog input enabled.
AN4 1 IN ANA A/D input channel 4. Default configuration on POR.
SS 1 IN TTL Slave select input for SSP (MSSP module).
HLVDIN 1 IN ANA High/Low-Voltage Detect external trip point input.
C2OUT 0 OUT DIG Comparator 2 output; takes priority over port data.
OSC2/CLKO/ OSC2 x OUT ANA Main oscillator feedback output connection (all XT and HS modes).
RA6 CLKO x OUT DIG System cycle clock output (FOSC/4); available in EC, ECPLL and
INTCKO modes.
RA6 0 OUT DIG LATA<6> data output. Available only in ECIO, ECPIO and INTIO
modes; otherwise, reads as ‘0’.
1 IN TTL PORTA<6> data input. Available only in ECIO, ECPIO and INTIO
modes; otherwise, reads as ‘0’.
Legend: OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
RB0/AN12/ RB0 0 OUT DIG LATB<0> data output; not affected by analog input.
INT0/FLT0/
1 IN TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared.
SDI/SDA
Disabled when analog input enabled.(1)
AN12 1 IN ANA A/D input channel 12.(1)
INT0 1 IN ST External interrupt 0 input.
FLT0 1 IN ST Enhanced PWM Fault input (ECCP1 module); enabled in software.
SDI 1 IN ST SPI data input (MSSP module).
SDA 1 OUT DIG I2C™ data output (MSSP module); takes priority over port data.
1 IN I2C/SMB I2C data input (MSSP module); input type depends on module setting.
RB1/AN10/ RB1 0 OUT DIG LATB<1> data output; not affected by analog input.
INT1/SCK/
1 IN TTL PORTB<1> data input; weak pull-up when RBPU bit is cleared.
SCL Disabled when analog input enabled.(1)
AN10 1 IN ANA A/D input channel 10.(1)
INT1 1 IN ST External interrupt 1 input.
SCK 0 OUT DIG SPI clock output (MSSP module); takes priority over port data.
1 IN ST SPI clock input (MSSP module).
SCL 0 OUT DIG I2C clock output (MSSP module); takes priority over port data.
1 IN I2C/SMB I2C clock input (MSSP module); input type depends on module setting.
RB2/AN8/ RB2 0 OUT DIG LATB<2> data output; not affected by analog input.
INT2/VMO 1 IN TTL PORTB<2> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.(1)
AN8 1 IN ANA A/D input channel 8.(1)
INT2 1 IN ST External interrupt 2 input.
VMO 0 OUT DIG External USB transceiver VMO data output.
RB3/AN9/ RB3 0 OUT DIG LATB<3> data output; not affected by analog input.
CCP2/VPO
1 IN TTL PORTB<3> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.(1)
AN9 1 IN ANA A/D input channel 9.(1)
(2)
CCP2 0 OUT DIG CCP2 Compare and PWM output.
1 IN ST CCP2 Capture input.
VPO 0 OUT DIG External USB transceiver VPO data output.
RB4/AN11/ RB4 0 OUT DIG LATB<4> data output; not affected by analog input.
KBI0/CSSPP
1 IN TTL PORTB<4> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.(1)
AN11 1 IN ANA A/D input channel 11.(1)
KBI0 1 IN TTL Interrupt-on-pin change.
CSSPP(4) 0 OUT DIG SPP chip select control output.
RB5/KBI1/ RB5 0 OUT DIG LATB<5> data output.
PGM
1 IN TTL PORTB<5> data input; weak pull-up when RBPU bit is cleared.
KBI1 1 IN TTL Interrupt-on-pin change.
PGM x IN ST Single-Supply Programming mode entry (ICSP™). Enabled by LVP
Configuration bit; all other pin functions disabled.
Legend: OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
I2C/SMB = I2C/SMBus input buffer, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is
overridden for this option)
Note 1: Configuration on POR is determined by PBADEN Configuration bit. Pins are configured as analog inputs when
PBADEN is set and digital inputs when PBADEN is cleared.
2: Alternate pin assignment for CCP2 when CCP2MX = 0. Default assignment is RC1.
3: All other pin functions are disabled when ICSP™ or ICD operation is enabled.
4: 40/44-pin devices only.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0); otherwise,
read as ‘0’.
2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are
implemented only when PORTE is implemented (i.e., 40/44-pin devices).
3: Unimplemented in 28-pin devices; read as ‘0’.
RE0/AN5/ RE0 0 OUT DIG LATE<0> data output; not affected by analog input.
CK1SPP 1 IN ST PORTE<0> data input; disabled when analog input enabled.
AN5 1 IN ANA A/D input channel 5; default configuration on POR.
CK1SPP 0 OUT DIG SPP clock 1 output (SPP enabled).
RE1/AN6/ RE1 0 OUT DIG LATE<1> data output; not affected by analog input.
CK2SPP 1 IN ST PORTE<1> data input; disabled when analog input enabled.
AN6 1 IN ANA A/D input channel 6; default configuration on POR.
CK2SPP 0 OUT DIG SPP clock 2 output (SPP enabled).
RE2/AN7/ RE2 0 OUT DIG LATE<2> data output; not affected by analog input.
OESPP 1 IN ST PORTE<2> data input; disabled when analog input enabled.
AN7 1 IN ANA A/D input channel 7; default configuration on POR.
OESPP 0 OUT DIG SPP enable output (SPP enabled).
MCLR/VPP/ MCLR —(1) IN ST External Master Clear input; enabled when MCLRE Configuration bit
RE3 is set.
VPP — (1) IN ANA High-voltage detection, used for ICSP™ mode entry detection.
Always available regardless of pin mode.
RE3 — (1) IN ST PORTE<3> data input; enabled when MCLRE Configuration bit is
clear.
Legend: OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input
Note 1: RE3 does not have a corresponding TRISE<3> bit. This pin is always an input regardless of mode.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
FOSC/4 0
1
Sync with Set
1 Internal TMR0L TMR0IF
Programmable Clocks on Overflow
T0CKI pin 0
Prescaler
T0SE (2 TCY Delay)
T0CS 8
3
T0PS2:T0PS0
8
PSA Internal Data Bus
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale.
FOSC/4 0
1
Sync with Set
Internal TMR0
1 TMR0L High Byte TMR0IF
T0CKI pin Programmable 0 Clocks on Overflow
Prescaler 8
T0SE (2 TCY Delay)
T0CS 3 Read TMR0L
T0PS2:T0PS0
Write TMR0L
PSA
8
8
TMR0H
8
8
Internal Data Bus
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
TMR1 Set
Clear TMR1 TMR1L TMR1IF
High Byte
(CCP Special Event Trigger) on Overflow
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
TMR1 Set
Clear TMR1 TMR1L TMR1IF
High Byte
(CCP Special Event Trigger) on Overflow
8
Read TMR1L
Write TMR1L
8
8
TMR1H
8
8
Internal Data Bus
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
4 1:1 to 1:16
T2OUTPS3:T2OUTPS0 Set TMR2IF
Postscaler
2
T2CKPS1:T2CKPS0 TMR2 Output
(to PWM or MSSP)
TMR2/PR2
Reset Match
1:1, 1:4, 1:16
FOSC/4 TMR2 Comparator PR2
Prescaler
8 8
8
Internal Data Bus
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
Read TMR1L
Write TMR1L
8
8
TMR3H
8
8
Internal Data Bus
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: These bits are not implemented on 28-pin devices and are read as ‘0’.
TABLE 15-2: INTERACTIONS BETWEEN CCP1 AND CCP2 FOR TIMER RESOURCES
CCP1 Mode CCP2 Mode Interaction
Capture Capture Each module can use TMR1 or TMR3 as the time base. The time base can be different
for each CCP.
Capture Compare CCP2 can be configured for the Special Event Trigger to reset TMR1 or TMR3
(depending upon which time base is used). Automatic A/D conversions on trigger event
can also be done. Operation of CCP1 could be affected if it is using the same timer as a
time base.
Compare Capture CCP1 be configured for the Special Event Trigger to reset TMR1 or TMR3 (depending
upon which time base is used). Operation of CCP2 could be affected if it is using the
same timer as a time base.
Compare Compare Either module can be configured for the Special Event Trigger to reset the time base.
Automatic A/D conversions on CCP2 trigger event can be done. Conflicts may occur if
both modules are using the same time base.
Capture PWM(1) None
Compare PWM(1) None
PWM(1) Capture None
(1)
PWM Compare None
PWM(1) PWM Both PWMs will have the same frequency and update rate (TMR2 interrupt).
Note 1: Includes standard and Enhanced PWM operation.
TMR3H TMR3L
Set CCP1IF
T3CCP2 TMR3
CCP1 pin Enable
Prescaler and CCPR1H CCPR1L
÷ 1, 4, 16 Edge Detect
TMR1
T3CCP2 Enable
4 TMR1H TMR1L
CCP1CON<3:0> Set CCP2IF
4
Q1:Q4
4
CCP2CON<3:0>
T3CCP1 TMR3H TMR3L
T3CCP2
TMR3
Enable
CCP2 pin
Prescaler and CCPR2H CCPR2L
÷ 1, 4, 16 Edge Detect
TMR1
Enable
T3CCP2
TMR1H TMR1L
T3CCP1
Compare Output S Q
Comparator
Match Logic
R
TRIS
4 Output Enable
CCP1CON<3:0>
0 TMR1H TMR1L 0
Compare Output S Q
Comparator
Match Logic
R
TRIS
4 Output Enable
CCPR2H CCPR2L
CCP2CON<3:0>
Duty Cycle
TMR2 = PR2
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
TRISD<4>
CCPR1H (Slave)
P1B P1B
Output TRISD<5>
Comparator R Q
Controller
P1C
P1C
TMR2 (Note 1)
S TRISD<6>
P1D P1D
Comparator
Clear Timer, TRISD<7>
set CCP1 pin and
latch D.C.
PR2 ECCP1DEL
Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time
base.
P1A Active
P1D Modulated
P1A Inactive
P1D Inactive
P1A Modulated
Delay(1) Delay(1)
10 (Half-Bridge) P1B Modulated
P1A Active
P1D Modulated
P1A Inactive
P1D Inactive
Relationships:
• Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
• Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)
• Delay = 4 * TOSC * (ECCP1DEL<6:0>)
Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 16.4.6 “Programmable Dead-Band Delay”).
PIC18FX455/X550 FET
Driver +
P1A V
-
Load
FET
Driver
+
P1B V
-
V-
Half-Bridge Output Driving a Full-Bridge Circuit
V+
PIC18FX455/X550
FET FET
Driver Driver
P1A
Load
FET FET
Driver Driver
P1B
V-
Forward Mode
Period
P1A(2)
Duty Cycle
P1B(2)
P1C(2)
P1D(2)
(1) (1)
Reverse Mode
Period
Duty Cycle
P1A(2)
P1B(2)
P1C(2)
P1D(2)
(1) (1)
Note 1: At this time, the TMR2 register is equal to the PR2 register.
Note 2: Output signal is shown as active-high.
PIC18FX455/X550 QC
FET QA FET
Driver Driver
P1A
Load
P1B
FET FET
Driver Driver
P1C
QB QD
V-
P1D
16.4.5.1 Direction Change in Full-Bridge Mode Figure 16-9 shows an example where the PWM direc-
tion changes from forward to reverse at a near 100%
In the Full-Bridge Output mode, the P1M1 bit in the
duty cycle. At time t1, the outputs, P1A and P1D,
CCP1CON register allows the user to control the
become inactive, while output P1C becomes active. In
forward/reverse direction. When the application firm-
this example, since the turn-off time of the power
ware changes this direction control bit, the module will
devices is longer than the turn-on time, a shoot-through
assume the new direction on the next PWM cycle.
current may flow through power devices, QC and QD,
Just before the end of the current PWM period, the (see Figure 16-7) for the duration of ‘t’. The same
modulated outputs (P1B and P1D) are placed in their phenomenon will occur to power devices, QA and QB,
inactive state, while the unmodulated outputs (P1A and for PWM direction change from reverse to forward.
P1C) are switched to drive in the opposite direction.
If changing PWM direction at high duty cycle is required
This occurs in a time interval of (4 TOSC * (Timer2
for an application, one of the following requirements
Prescale Value) before the next PWM period begins.
must be met:
The Timer2 prescaler will be either 1, 4 or 16,
depending on the value of the T2CKPS1:T2CKPS0 bits 1. Reduce PWM for a PWM period before
(T2CON<1:0>). During the interval from the switch of changing directions.
the unmodulated outputs to the beginning of the next 2. Use switch drivers that can drive the switches off
period, the modulated outputs (P1B and P1D) remain faster than they can drive them on.
inactive. This relationship is shown in Figure 16-8.
Other options to prevent shoot-through current may
Note that in the Full-Bridge Output mode, the ECCP exist.
module does not provide any dead-band delay. In gen-
eral, since only one output is modulated at all times,
dead-band delay is not required. However, there is a
situation where a dead-band delay might be required.
This situation occurs when both of the following
conditions are true:
1. The direction of the PWM output changes when
the duty cycle of the output is at or near 100%.
2. The turn-off time of the power switch, including
the power device and driver circuit, is greater
than the turn-on time.
P1A (Active-High)
P1B (Active-High)
DC
P1C (Active-High)
(Note 2)
P1D (Active-High)
DC
Note 1: The direction bit in the CCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle.
2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals
of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D signals
are inactive at this time.
P1A(1)
P1B(1) DC
P1C(1)
P1D(1) DC
tON(2)
External Switch C(1)
tOFF(3)
t = tOFF – tON(2, 3)
Potential
Shoot-Through Current(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PWM Activity
Dead Time Dead Time Dead Time
Shutdown Event
ECCPASE bit
PWM Activity
Dead Time Dead Time Dead Time
Shutdown Event
ECCPASE bit
ECCPASE
Cleared by Firmware
PIC18FX455/X550 Family
External
UOE(1) Transceiver
USB Control and VM(1) USB Bus
Configuration VP(1)
RCV(1)
USB VMO(1)
SIE VPO(1)
SPP7:SPP0
1 Kbyte CK1SPP
USB RAM CK2SPP
CSSPP
OESPP
Note 1: This signal is only available if the internal transceiver is disabled (UTRDIS = 1).
2: The internal pull-up resistors should be disabled (UPUEN = 0) if external pull-up resistors are used.
3: Do not enable the internal regulator when using an external 3.3V supply.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: If UTRDIS is set, the UOE signal will be active independent of the UOEMON bit setting.
2: The UPUEN, UTRDIS and FSEN bits should never be changed while the USB module is enabled. These
values must be preconfigured prior to enabling the module.
3: This bit is only valid when the on-chip transceiver is active (UTRDIS = 0); otherwise, it is ignored.
There are 6 signals from the module to communicate The VPO and VMO signals are outputs from the SIE to
with and control an external transceiver: the external transceiver. The RCV signal is the output
• VM: Input from the single-ended D- line from the external transceiver to the SIE; it represents
the differential signals from the serial bus translated
• VP: Input from the single-ended D+ line
into a single pulse train. The VM and VP signals are
• RCV: Input from the differential receiver used to report conditions on the serial bus to the SIE
• VMO: Output to the differential line driver that can’t be captured with the RCV signal. The
• VPO: Output to the differential line driver combinations of states of these signals and their
• UOE: Output enable interpretation are listed in Table 17-1 and Table 17-2.
Data Bus
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: This bit is only valid for endpoints with available Even and Odd BD registers.
REGISTER 17-4: UEPn: USB ENDPOINT n CONTROL REGISTER (UEP0 THROUGH UEP15)
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: This bit must be initialized by the user to the desired value prior to enabling the USB module.
2: This bit is ignored unless DTSEN = 1.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Available
as
EP15 IN Odd Data RAM
Descriptor
4FFh 4FFh 4FFh 4FFh
Maximum Memory Maximum Memory Maximum Memory Maximum Memory
Used: 128 bytes Used: 132 bytes Used: 256 bytes Used: 248 bytes
Maximum BDs: Maximum BDs: Maximum BDs: 6 Maximum BDs:
32 (BD0 to BD31) 33 (BD0 to BD32) 4 (BD0 to BD63) 62 (BD0 to BD61)
Mode 3
Mode 0 Mode 1 Mode 2
Endpoint (Ping-Pong on all other EPs,
(No Ping-Pong) (Ping-Pong on EP0 OUT) (Ping-Pong on all EPs)
except EP0)
SOFIF
SOFIE
BTSEF
BTSEE TRNIF USBIF
TRNIE
BTOEF
BTOEE
IDLEIF
DFN8EF IDLEIE
DFN8EE UERRIF
CRC16EF UERRIE
CRC16EE
CRC5EF STALLIF
STALLIE
CRC5EE
PIDEF
PIDEE ACTVIF
ACTVIE
URSTIF
URSTIE
Control Transfer(1)
1 ms Frame
Note 1: The control transfer shown here is only an example showing events that can occur for every transaction. Typical control transfers
will spread across multiple frames.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: Once an Idle state is detected, the user may want to place the USB module in Suspend mode.
2: Clearing this bit will cause the USTAT FIFO to advance (valid only for IN, OUT and SETUP tokens).
3: This bit is typically unmasked only following the detection of a UIDLE interrupt event.
4: Only error conditions enabled through the UEIE register will set this bit. This bit is a status bit only and
cannot be set or cleared by the user.
C:
UCONbits.SUSPND = 0;
while (UIRbits.ACTVIF) { UIRbits.ACTVIF = 0; }
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Device
Configuration
Interface Interface
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
FOSC/4
OESPP
CSSPP
CK1SPP
CK2SPP
FIGURE 18-3: TIMING FOR USB WRITE ADDRESS AND DATA (4 WAIT STATES)
USB Clock
OESPP
CSSPP
CK1SPP
CK2SPP
FIGURE 18-4: TIMING FOR USB WRITE ADDRESS AND READ DATA (4 WAIT STATES)
USB Clock
OESPP
CSSPP
CK1SPP
CK2SPP
Endpoint
Byte 0 Byte 1 Byte 2 Byte 3 Byte n
Address
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 RDSPP: SPP Read Status bit (Valid when SPPCON<SPPOWN> = 1, USB)
1 = The last transaction was a read from the SPP
0 = The last transaction was not a read from the SPP
bit 6 WRSPP: SPP Write Status bit (Valid when SPPCON<SPPOWN> = 1, USB)
1 = The last transaction was a write to the SPP
0 = The last transaction was not a write to the SPP
bit 5 Unimplemented: Read as ‘0’
bit 4 SPPBUSY: SPP Handshaking Override bit
1 = The SPP is busy
0 = The SPP is ready to accept another read or write request
bit 3-0 ADDR3:ADDR0: SPP Endpoint Address bits
1111 = Endpoint Address 15
• •
• •
0001
0000 = Endpoint Address 0
SS Edge
Select
2
Clock Select
SSPM3:SSPM0
SMP:CKE
4
2 (
TMR2 Output
2
)
Edge
Select
SCK Prescaler TOSC
4, 16, 64
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by
writing to the SSPBUF register.
2: When enabled, these pins must be properly configured as input or output.
3: Bit combinations not specifically listed here are either reserved or implemented in I2C™ mode only.
SDO SDI
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
SCK Modes
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Input
Sample
(SMP = 1)
SSPIF
Next Q4 Cycle
SSPSR to after Q2↓
SSPBUF
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDI bit 0
(SMP = 0)
bit 7 bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 Cycle
SSPSR to
SSPBUF after Q2↓
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDI
(SMP = 0) bit 7 bit 0
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag Next Q4 Cycle
after Q2↓
SSPSR to
SSPBUF
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
SDI
(SMP = 0) bit 7 bit 0
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 Cycle
after Q2↓
SSPSR to
SSPBUF
Note: Only port I/O names are used in this diagram for
the sake of brevity. Refer to the text for a full list of
multiplexed functions.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: When enabled, the SDA and SCL pins must be properly configured as input or output.
2: Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
2: If the I2C module is active, these bits may not be set (no spooling) and the SSPBUF may not be written (or
writes to the SSPBUF are disabled).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: If the I2C module is active, this bit may not be set (no spooling) and the SSPBUF may not be written (or
writes to the SSPBUF are disabled).
DS39632C-page 210
Receiving Address R/W = 0 Receiving Data ACK Receiving Data ACK
SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SSPIF (PIR1<3>)
Bus master
terminates
transfer
BF (SSPSTAT<0>)
Preliminary
Cleared in software
SSPBUF is read
PIC18F2455/2550/4455/4550
SSPOV (SSPCON1<6>)
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
SDA A7 A6 A5 X A3 X X ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SSPIF (PIR1<3>)
Bus master
terminates
(RECEPTION, 7-BIT ADDRESS)
transfer
BF (SSPSTAT<0>)
Preliminary
Cleared in software
SSPBUF is read
SSPOV (SSPCON1<6>)
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
CKP
(CKP does not reset to ‘0’ when SEN = 0)
Note 1: x = Don’t care (i.e., address bit can be either a ‘1’ or a ‘0’).
2: In this example, an address equal to A7.A6.A5.X.A3.X.X will be Acknowledged and cause an interrupt.
I2C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01011
PIC18F2455/2550/4455/4550
DS39632C-page 211
FIGURE 19-10:
DS39632C-page 212
Receiving Address R/W = 1 Transmitting Data Transmitting Data
ACK ACK
SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S
Data in SCL held low P
sampled while CPU
responds to SSPIF
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
Cleared in software Cleared in software
Preliminary
From SSPIF ISR From SSPIF ISR
SSPBUF is written in software SSPBUF is written in software
PIC18F2455/2550/4455/4550
CKP
Receive First Byte of Address Receive Second Byte of Address Receive Data Byte Receive Data Byte
R/W = 0 ACK
Bus master
terminates
SSPIF (PIR1<3>) transfer
BF (SSPSTAT<0>)
SSPOV is set
Preliminary
because SSPBUF is
still full. ACK is not sent.
UA (SSPSTAT<1>)
DS39632C-page 213
FIGURE 19-12:
DS39632C-page 214
Clock is held low until Clock is held low until
update of SSPADD has update of SSPADD has
taken place taken place
Receive First Byte of Address Receive Second Byte of Address Receive Data Byte Receive Data Byte
R/W = 0 ACK
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
Bus master
terminates
SSPIF (PIR1<3>) transfer
BF (SSPSTAT<0>)
SSPOV (SSPCON1<6>)
SSPOV is set
Preliminary
because SSPBUF is
still full. ACK is not sent.
PIC18F2455/2550/4455/4550
UA (SSPSTAT<1>)
CKP
(CKP does not reset to ‘0’ when SEN = 0)
Note 1: x = Don’t care (i.e., address bit can be either a ‘1’ or a ‘0’).
I2C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01001
2: In this example, an address equal to A9.A8.A7.A6.A5.X.A3.A2.X.X will be Acknowledged and cause an interrupt.
3: Note that the Most Significant bits of the address are not affected by the bit masking.
Bus master
terminates
Clock is held low until Clock is held low until transfer
update of SSPADD has update of SSPADD has Clock is held low until
Receive First Byte of Address R/W = 0 Receive Second Byte of Address Receive First Byte of Address R/W = 1 Transmitting Data Byte ACK
SDA 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 1 1 1 0 A9 A8 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S Sr P
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
Preliminary
Dummy read of SSPBUF Write of SSPBUF Completion of
contents of SSPSR to clear BF flag BF flag is clear
to clear BF flag initiates transmit data transmission
at the end of the
UA (SSPSTAT<1>) third address sequence clears BF flag
DS39632C-page 215
PIC18F2455/2550/4455/4550
19.4.4 CLOCK STRETCHING 19.4.4.3 Clock Stretching for 7-Bit Slave
Both 7-Bit and 10-Bit Slave modes implement Transmit Mode
automatic clock stretching during a transmit sequence. 7-Bit Slave Transmit mode implements clock stretch-
The SEN bit (SSPCON2<0>) allows clock stretching to ing by clearing the CKP bit after the falling edge of the
be enabled during receives. Setting SEN will cause ninth clock if the BF bit is clear. This occurs regardless
the SCL pin to be held low at the end of each data of the state of the SEN bit.
receive sequence. The user’s ISR must set the CKP bit before transmis-
sion is allowed to continue. By holding the SCL line
19.4.4.1 Clock Stretching for 7-Bit Slave low, the user has time to service the ISR and load the
Receive Mode (SEN = 1) contents of the SSPBUF before the master device can
In 7-Bit Slave Receive mode, on the falling edge of the initiate another transmit sequence (see Figure 19-10).
ninth clock at the end of the ACK sequence if the BF Note 1: If the user loads the contents of SSPBUF,
bit is set, the CKP bit in the SSPCON1 register is setting the BF bit before the falling edge of
automatically cleared, forcing the SCL output to be the ninth clock, the CKP bit will not be
held low. The CKP bit being cleared to ‘0’ will assert cleared and clock stretching will not occur.
the SCL line low. The CKP bit must be set in the user’s
ISR before reception is allowed to continue. By holding 2: The CKP bit can be set in software
the SCL line low, the user has time to service the ISR regardless of the state of the BF bit.
and read the contents of the SSPBUF before the
19.4.4.4 Clock Stretching for 10-Bit Slave
master device can initiate another receive sequence.
This will prevent buffer overruns from occurring (see Transmit Mode
Figure 19-15). In 10-Bit Slave Transmit mode, clock stretching is
controlled during the first two address sequences by
Note 1: If the user reads the contents of the
the state of the UA bit, just as it is in 10-Bit Slave
SSPBUF before the falling edge of the
Receive mode. The first two addresses are followed
ninth clock, thus clearing the BF bit, the
by a third address sequence which contains the high-
CKP bit will not be cleared and clock
order bits of the 10-bit address and the R/W bit set to
stretching will not occur.
‘1’. After the third address sequence is performed, the
2: The CKP bit can be set in software UA bit is not set, the module is now configured in
regardless of the state of the BF bit. The Transmit mode and clock stretching is controlled by
user should be careful to clear the BF bit the BF flag as in 7-Bit Slave Transmit mode (see
in the ISR before the next receive Figure 19-13).
sequence in order to prevent an overflow
condition.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA DX DX – 1
SCL
Master device
CKP asserts clock
Master device
deasserts clock
Write
SSPCON1
DS39632C-page 218
Clock is not held low
because Buffer Full (BF) bit is
clear prior to falling edge Clock is held low until Clock is not held low
of ninth clock CKP is set to ‘1’ because ACK = 1
SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SSPIF (PIR1<3>)
Bus master
terminates
transfer
BF (SSPSTAT<0>)
Preliminary
Cleared in software
SSPBUF is read
PIC18F2455/2550/4455/4550
SSPOV (SSPCON1<6>)
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
CKP
CKP
If BF is cleared written
prior to the falling to ‘1’ in
edge of the ninth clock, software
CKP will not be reset BF is set after falling
to ‘0’ and no clock edge of the ninth clock,
stretching will occur CKP is reset to ‘0’ and
clock stretching occurs
I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)
SSPIF (PIR1<3>)
Bus master
terminates
Cleared in software Cleared in software Cleared in software transfer
Cleared in software
BF (SSPSTAT<0>)
SSPOV is set
Preliminary
because SSPBUF is
still full. ACK is not sent.
UA (SSPSTAT<1>)
DS39632C-page 219
PIC18F2455/2550/4455/4550
19.4.5 GENERAL CALL ADDRESS If the general call address matches, the SSPSR is
SUPPORT transferred to the SSPBUF, the BF flag bit is set (eighth
bit) and on the falling edge of the ninth bit (ACK bit), the
The addressing procedure for the I2C bus is such that
SSPIF interrupt flag bit is set.
the first byte after the Start condition usually
determines which device will be the slave addressed by When the interrupt is serviced, the source for the
the master. The exception is the general call address interrupt can be checked by reading the contents of the
which can address all devices. When this address is SSPBUF. The value can be used to determine if the
used, all devices should, in theory, respond with an address was device specific or a general call address.
Acknowledge. In 10-bit mode, the SSPADD is required to be updated
The general call address is one of eight addresses for the second half of the address to match and the UA
reserved for specific purposes by the I2C protocol. It bit is set (SSPSTAT<1>). If the general call address is
consists of all ‘0’s with R/W = 0. sampled when the GCEN bit is set, while the slave is
configured in 10-Bit Address mode, then the second
The general call address is recognized when the Gen-
half of the address is not necessary, the UA bit will not
eral Call Enable (GCEN) bit is enabled (SSPCON2<7>
be set and the slave will begin receiving data after the
set). Following a Start bit detect, 8 bits are shifted into
Acknowledge (Figure 19-17).
the SSPSR and the address is compared against the
SSPADD. It is also compared to the general call
address and fixed in hardware.
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S
SSPIF
BF (SSPSTAT<0>)
Cleared in software
SSPBUF is read
SSPOV (SSPCON1<6>) ‘0’
GCEN (SSPCON2<7>)
‘1’
Internal SSPM3:SSPM0
Data Bus SSPADD<6:0>
Read Write
SSPBUF Baud
Rate
Generator
SDA Shift
Clock Arbitrate/WCOL Detect
SDA In Clock
SSPSR
(hold off clock source)
MSb LSb
Receive Enable
Acknowledge
Generate
SCL
SSPM3:SSPM0 SSPADD<6:0>
SDA DX DX – 1
BRG decrements on
Q2 and Q4 cycles
BRG
03h 02h 01h 00h (hold off) 03h 02h
Value
SCL
TBRG
S
Set S (SSPSTAT<3>)
Write to SSPCON2
occurs here. SDA = 1,
At completion of Start bit,
SDA = 1, SCL = 1 hardware clears RSEN bit
SCL (no change). and sets SSPIF
Sr = Repeated Start
DS39632C-page 228
Write SSPCON2<0> SEN = 1, ACKSTAT in
Start condition begins SSPCON2 = 1
From slave, clear ACKSTAT bit SSPCON2<6>
SEN = 0
Transmitting Data or Second Half
Transmit Address to Slave R/W = 0 of 10-bit Address ACK
SDA A7 A6 A5 A4 A3 A2 A1 ACK = 0 D7 D6 D5 D4 D3 D2 D1 D0
Preliminary
BF (SSPSTAT<0>)
SEN
PEN
R/W
I 2C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
Write to SSPCON2<4>
to start Acknowledge sequence
SDA = ACKDT (SSPCON2<5>) = 0
Write to SSPCON2<0> (SEN = 1),
begin Start Condition ACK from master, Set ACKEN, start Acknowledge sequence,
Master configured as a receiver SDA = ACKDT = 0 SDA = ACKDT = 1
SEN = 0 by programming SSPCON2<3> (RCEN = 1)
Bus master
ACK is not sent terminates
transfer
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
Data shifted in on falling edge of CLK Set SSPIF at end
of receive Set SSPIF interrupt
Set SSPIF interrupt at end of Acknow-
Set SSPIF interrupt ledge sequence
at end of receive
at end of Acknowledge
SSPIF sequence
Set P bit
Cleared in software Cleared in software Cleared in software Cleared in software (SSPSTAT<4>)
SDA = 0, SCL = 1 Cleared in
Preliminary
while CPU software and SSPIF
responds to SSPIF
BF
(SSPSTAT<0>) Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
SSPOV
ACKEN
I 2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
PIC18F2455/2550/4455/4550
DS39632C-page 229
PIC18F2455/2550/4455/4550
19.4.12 ACKNOWLEDGE SEQUENCE 19.4.13 STOP CONDITION TIMING
TIMING A Stop bit is asserted on the SDA pin at the end of a
An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Enable bit, PEN
Acknowledge Sequence Enable bit, ACKEN (SSPCON2<2>). At the end of a receive/transmit, the
(SSPCON2<4>). When this bit is set, the SCL pin is SCL line is held low after the falling edge of the ninth
pulled low and the contents of the Acknowledge data bit clock. When the PEN bit is set, the master will assert
are presented on the SDA pin. If the user wishes to gen- the SDA line low. When the SDA line is sampled low,
erate an Acknowledge, then the ACKDT bit should be the Baud Rate Generator is reloaded and counts down
cleared. If not, the user should set the ACKDT bit before to ‘0’. When the Baud Rate Generator times out, the
starting an Acknowledge sequence. The Baud Rate SCL pin will be brought high and one TBRG (Baud Rate
Generator then counts for one rollover period (TBRG) Generator rollover count) later, the SDA pin will be
and the SCL pin is deasserted (pulled high). When the deasserted. When the SDA pin is sampled high while
SCL pin is sampled high (clock arbitration), the Baud SCL is high, the P bit (SSPSTAT<4>) is set. A TBRG
Rate Generator counts for TBRG. The SCL pin is then later, the PEN bit is cleared and the SSPIF bit is set
pulled low. Following this, the ACKEN bit is automatically (Figure 19-26).
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into an inactive state 19.4.13.1 WCOL Status Flag
(Figure 19-25). If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
19.4.12.1 WCOL Status Flag contents of the buffer are unchanged (the write doesn’t
If the user writes the SSPBUF when an Acknowledge occur).
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
SCL 8 9
SSPIF
Cleared in
Set SSPIF at the software
end of receive Cleared in
software Set SSPIF at the end
of Acknowledge sequence
Note: TBRG = one Baud Rate Generator period.
SDA ACK
P
TBRG TBRG TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup Stop condition
SDA
BCLIF
SDA
SCL
Set SEN, enable Start SEN cleared automatically because of bus collision.
condition if SDA = 1, SCL = 1 MSSP module reset into Idle state.
SEN
SDA sampled low before
Start condition. Set BCLIF.
S bit and SSPIF set because
BCLIF SDA = 0, SCL = 1.
SSPIF and BCLIF are
cleared in software
SSPIF
TBRG TBRG
SDA
FIGURE 19-30: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S Set SSPIF
Less than TBRG TBRG
SCL S
SCL pulled low after BRG
time-out
SEN
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
BCLIF ‘0’
SSPIF
SDA = 0, SCL = 1, Interrupts cleared
set SSPIF in software
SDA
SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
RSEN
BCLIF
Cleared in software
S ‘0’
SSPIF ‘0’
TBRG TBRG
SDA
SCL
S ‘0’
SSPIF
PEN
BCLIF
P ‘0’
SSPIF ‘0’
SDA
PEN
BCLIF
P ‘0’
SSPIF ‘0’
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: SREN/CREN overrides TXEN in Sync mode with the exception that SREN has no effect in Synchronous
Slave mode.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
0.3 — — — — — — — — — — — —
1.2 — — — 1.221 1.73 255 1.202 0.16 129 1201 -0.16 103
2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2403 -0.16 51
9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9615 -0.16 12
19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 — — —
57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 — — —
115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 — — —
0.3 — — — — — — — — — — — —
1.2 — — — — — — — — — — — —
2.4 — — — — — — 2.441 1.73 255 2403 -0.16 207
9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9615 -0.16 51
19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19230 -0.16 25
57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55555 3.55 8
115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — —
0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 300 -0.04 1665
1.2 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 1201 -0.16 415
2.4 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 2403 -0.16 207
9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9615 -0.16 51
19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19230 -0.16 25
57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55555 3.55 8
115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — —
0.3 0.300 0.04 832 300 -0.16 415 300 -0.16 207
1.2 1.202 0.16 207 1201 -0.16 103 1201 -0.16 51
2.4 2.404 0.16 103 2403 -0.16 51 2403 -0.16 25
9.6 9.615 0.16 25 9615 -0.16 12 — — —
19.2 19.231 0.16 12 — — — — — —
57.6 62.500 8.51 3 — — — — — —
115.2 125.000 8.51 1 — — — — — —
0.3 0.300 0.00 33332 0.300 0.00 16665 0.300 0.00 8332 300 -0.01 6665
1.2 1.200 0.00 8332 1.200 0.02 4165 1.200 0.02 2082 1200 -0.04 1665
2.4 2.400 0.02 4165 2.400 0.02 2082 2.402 0.06 1040 2400 -0.04 832
9.6 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 9615 -0.16 207
19.2 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 19230 -0.16 103
57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57142 0.79 34
115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 117647 -2.12 16
0.3 0.300 0.01 3332 300 -0.04 1665 300 -0.04 832
1.2 1.200 0.04 832 1201 -0.16 415 1201 -0.16 207
2.4 2.404 0.16 415 2403 -0.16 207 2403 -0.16 103
9.6 9.615 0.16 103 9615 -0.16 51 9615 -0.16 25
19.2 19.231 0.16 51 19230 -0.16 25 19230 -0.16 12
57.6 58.824 2.12 16 55555 3.55 8 — — —
115.2 111.111 -3.55 8 — — — — — —
BRG Clock
RCIF bit
(Interrupt)
Read
RCREG
Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
BRG Clock
ABDEN bit
ABDOVF bit
FFFFh
BRG Value XXXXh 0000h 0000h
When operating in Asynchronous mode, the EUSART Note 1: The TSR register is not mapped in data
module consists of the following important elements: memory so it is not available to the user.
• Baud Rate Generator 2: Flag bit TXIF is set when enable bit TXEN
• Sampling Circuit is set.
• Asynchronous Transmitter To set up an Asynchronous Transmission:
• Asynchronous Receiver 1. Initialize the SPBRGH:SPBRG registers for the
• Auto-Wake-up on Break signal appropriate baud rate. Set or clear the BRGH
• 12-Bit Break Character Transmit and BRG16 bits, as required, to achieve the
• Auto-Baud Rate Detection desired baud rate.
• Pin State Polarity 2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
20.2.1 EUSART ASYNCHRONOUS 3. If the signal from the TX pin is to be inverted, set
TRANSMITTER the TXCKP bit.
4. If interrupts are desired, set enable bit TXIE.
The EUSART transmitter block diagram is shown in
Figure 20-3. The heart of the transmitter is the Transmit 5. If 9-bit transmission is desired, set transmit bit
(Serial) Shift Register (TSR). The Shift register obtains TX9. Can be used as address/data bit.
its data from the Read/Write Transmit Buffer register, 6. Enable the transmission by setting bit TXEN
TXREG. The TXREG register is loaded with data in which will also set bit TXIF.
software. The TSR register is not loaded until the Stop 7. If 9-bit transmission is selected, the ninth bit
bit has been transmitted from the previous load. As should be loaded in bit TX9D.
soon as the Stop bit is transmitted, the TSR is loaded 8. Load data to the TXREG register (starts
with new data from the TXREG register (if available). transmission).
9. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TRMT SPEN
BRG16 SPBRGH SPBRG
TX9
Baud Rate Generator TX9D
Write to TXREG
Word 1
BRG Output
(Shift Clock)
TX (pin)
Start bit bit 0 bit 1 bit 7/8 Stop bit
Word 1
TXIF bit
(Transmit Buffer 1 TCY
Reg. Empty Flag)
Write to TXREG
Word 1 Word 2
BRG Output
(Shift Clock)
TX (pin)
Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0
RX9
RXDTP SPEN
8
RCIE
RCIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word
causing the OERR (Overrun) bit to be set.
RX/DT Line
RCIF
Cleared due to user read of RCREG
Note 1: The EUSART remains in Idle while the WUE bit is set.
RX/DT Line
Note 1
RCIF
Cleared due to user read of RCREG
Sleep Command Executed Sleep Ends
Note 1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur before the oscillator is ready. This
sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.
Write to TXREG
Dummy Write
BRG Output
(Shift Clock)
Break
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
SENDB sampled here Auto-Cleared
SENDB
(Transmit Shift
Reg. Empty Flag)
RC7/RX/DT/
SDO pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7
Word 1 Word 2
RC6/TX/CK pin
(TXCKP = 0)
RC6/TX/CK pin
(TXCKP = 1)
Write to
TXREG Reg Write Word 1 Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
RC7/RX/DT/SDO
pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
RC6/TX/CK pin
(TXCKP = 0)
RC6/TX/CK pin
(TXCKP = 1)
Write to
bit SREN
SREN bit
CREN bit ‘0’ ‘0’
RCIF bit
(Interrupt)
Read
RXREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
AN6(2)
AN5(2)
AN12
AN10
AN11
PCFG3:
AN9
AN8
AN4
AN3
AN2
AN1
AN0
PCFG0
0000(1) A A A A A A A A A A A A A
0001 A A A A A A A A A A A A A
0010 A A A A A A A A A A A A A
0011 D A A A A A A A A A A A A
0100 D D A A A A A A A A A A A
0101 D D D A A A A A A A A A A
0110 D D D D A A A A A A A A A
0111(1) D D D D D A A A A A A A A
1000 D D D D D D A A A A A A A
1001 D D D D D D D A A A A A A
1010 D D D D D D D D A A A A A
1011 D D D D D D D D D A A A A
1100 D D D D D D D D D D A A A
1101 D D D D D D D D D D D A A
1110 D D D D D D D D D D D D A
1111 D D D D D D D D D D D D D
A = Analog input D = Digital I/O
Note 1: The POR value of the PCFG bits depends on the value of the PBADEN Configuration bit. When
PBADEN = 1, PCFG<3:0> = 0000; when PBADEN = 0, PCFG<3:0> = 0111.
2: AN5 through AN7 are available only on 40/44-pin devices.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D
clock starts. This allows the SLEEP instruction to be executed before starting a conversion.
CHS3:CHS0
1100
AN12
1011
AN11
1010
AN10
1001
AN9
1000
AN8
0111
AN7(1)
0110
AN6(1)
0101
AN5(1)
0100
AN4
VAIN
(Input Voltage) 0011
10-Bit AN3
Converter
A/D 0010
AN2
0001
VCFG1:VCFG0 AN1
VDD(2) 0000
AN0
X0
VREF+ X1
Reference 1X
Voltage VREF- 0X
VSS(2)
Note 1: Channels AN5 through AN7 are not available on 28-pin devices.
2: I/O pins have diode protection to VDD and VSS.
1022 LSB
0.5 LSB
1 LSB
1.5 LSB
2 LSB
2.5 LSB
3 LSB
1023 LSB
1022.5 LSB
1023.5 LSB
• Set GIE bit
3. Wait the required acquisition time (if required).
4. Start conversion:
Analog Input Voltage
• Set GO/DONE bit (ADCON0 register)
VSS
FIGURE 21-5: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 TAD1
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Automatic
Acquisition Conversion starts Discharge
Time (Holding capacitor is disconnected)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Two Common Reference Comparators Two Common Reference Comparators with Outputs
CM2:CM0 = 100 CM2:CM0 = 101
A VIN- A VIN-
RA0/AN0 RA0/AN0
VIN+ C1 C1OUT VIN+ C1 C1OUT
RA3/AN3/ A RA3/AN3/ A
VREF+ VREF+
RA4/T0CKI/C1OUT*/
A VIN- RCV
RA1/AN1
C2 C2OUT RA1/AN1 A VIN-
RA2/AN2/ D VIN+
VREF-/CVREF RA2/AN2/ D VIN+ C2 C2OUT
VREF-/CVREF
RA5/AN4/SS/HLVDIN/C2OUT*
One Independent Comparator with Output Four Inputs Multiplexed to Two Comparators
CM2:CM0 = 001 CM2:CM0 = 110
A VIN- A
RA0/AN0 RA0/AN0
CIS = 0 VIN-
RA3/AN3/ A VIN+ C1 C1OUT RA3/AN3/ A CIS = 1
VIN+ C1 C1OUT
VREF+ VREF+
RA4/T0CKI/C1OUT*/RCV RA1/AN1 A
CIS = 0 VIN-
RA2/AN2/ A CIS = 1
D VIN- VIN+ C2 C2OUT
RA1/AN1 VREF-/CVREF
RA2/AN2/ D VIN+ C2 Off (Read as ‘0’)
CVREF
VREF-/CVREF From VREF Module
A = Analog Input, port reads zeros always D = Digital Input CIS (CMCON<3>) is the Comparator Input Switch
* Setting the TRISA<5:4> bits will disable the comparator outputs by configuring the pins as inputs.
MULTIPLEX
+
Port pins
- To RA4 or
RA5 pin
D Q Bus
CxINV Data
Read CMCON EN
D Q Set
CMIF
bit
EN CL
From
other
Reset Comparator
VDD
VT = 0.6V RIC
RS < 10k
Comparator
AIN Input
CPIN ILEAKAGE
VA VT = 0.6V ±500 nA
5 pF
VSS
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
CVRSS = 1
VREF+
VDD
CVRSS = 0 8R
CVR3:CVR0
CVREN R
16-to-1 MUX
R
16 Steps
CVREF
R
R
R
CVRR 8R
CVRSS = 1
VREF-
CVRSS = 0
PIC18FXXXX
CVREF
R(1)
Module
+
Voltage RA2 CVREF Output
–
Reference
Output
Impedance
Note 1: R is dependent upon the voltage reference configuration bits, CVRCON<5> and CVRCON<3:0>.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: See Table 28-6 in Section 28.0 “Electrical Characteristics” for specifications.
VDD
HLVDL3:HLVDL0 HLVDCON
Register
HLVDEN VDIRMAG
HLVDIN
16-to-1 MUX
Set
HLVDIF
HLVDEN
Internal Voltage
Reference
BOREN 1.2V Typical
VDD
VHLVD
HLVDIF
Enable HLVD
TIRVST
IRVST
HLVDIF cleared in software
Internal Reference is stable
CASE 2:
VDD
VHLVD
HLVDIF
Enable HLVD
TIRVST
IRVST
Internal Reference is stable
HLVDIF cleared in software
VHLVD
VDD
HLVDIF
Enable HLVD
IRVST TIRVST
CASE 2:
VHLVD
VDD
HLVDIF
Enable HLVD
IRVST TIRVST
300000h CONFIG1L — — USBDIV CPUDIV1 CPUDIV0 PLLDIV2 PLLDIV1 PLLDIV0 --00 0000
300001h CONFIG1H IESO FCMEN — — FOSC3 FOSC2 FOSC1 FOSC0 00-- 0101
300002h CONFIG2L — — VREGEN BORV1 BORV0 BOREN1 BOREN0 PWRTEN --01 1111
300003h CONFIG2H — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN ---1 1111
300005h CONFIG3H MCLRE — — — — LPT1OSC PBADEN CCP2MX 1--- -011
300006h CONFIG4L DEBUG XINST ICPRT(3) — — LVP — STVREN 100- -1-1
300008h CONFIG5L — — — — CP3(1) CP2 CP1 CP0 ---- 1111
300009h CONFIG5H CPD CPB — — — — — — 11-- ----
30000Ah CONFIG6L — — — — WRT3(1) WRT2 WRT1 WRT0 ---- 1111
30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 111- ----
30000Ch CONFIG7L — — — — EBTR3(1) EBTR2 EBTR1 EBTR0 ---- 1111
30000Dh CONFIG7H — EBTRB — — — — — — -1-- ----
3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx(2)
3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0001 0010(2)
Legend: x = unknown, u = unchanged, - = unimplemented. Shaded cells are unimplemented, read as ‘0’.
Note 1: Unimplemented in PIC18FX455 devices; maintain this bit set.
2: See Register 25-13 and Register 25-14 for DEVID values. DEVID registers are read-only and cannot be programmed by
the user.
3: Available only on PIC18F4455/4550 devices in 44-pin TQFP packages. Always leave this bit clear in all other devices.
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
Note 1: The microcontroller and USB module both use the selected oscillator as their clock source in XT, HS and
EC modes. The USB module uses the indicated XT, HS or EC oscillator as its clock source whenever the
microcontroller uses the internal oscillator.
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
Note 1: Available only on PIC18F4455/4550 devices in 44-pin TQFP packages. Always leave this bit clear in all
other devices.
Legend:
R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
Legend:
R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
Legend:
R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
Legend:
R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
Note 1: This bit is read-only in normal execution mode; it can be written only in Program mode.
Legend:
R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
Legend:
R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
Legend:
R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
Legend:
R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
Note 1: These values for DEV10:DEV3 may be shared with other devices. The specific device is always identified
by using the entire DEV10:DEV0 bit sequence.
SLEEP
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
INTOSC
Multiplexer
OSC1
TOST(1) TPLL(1)
1 2 n-1 n
PLL Clock
Output
Clock
Transition
CPU Clock
Peripheral
Clock
Program PC PC + 2 PC + 4 PC + 6
Counter
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
Sample Clock
Device Oscillator
Clock Failure
Output
CM Output
(Q)
Failure
Detected
OSCFIF
000000h
Boot Block Boot Block CPB, WRTB, EBTRB
0007FFh
000800h
Block 0 Block 0 CP0, WRT0, EBTR0
001FFFh
002000h
Block 1 Block 1 CP1, WRT1, EBTR1
003FFFh
004000h
Block 2 Block 2 CP2, WRT2, EBTR2
005FFFh
006000h
Unimplemented
Block 3 CP3, WRT3, EBTR3
Read ‘0’s
007FFFh
008000h
Unimplemented Unimplemented
Read ‘0’s Read ‘0’s (Unimplemented Memory Space)
1FFFFFh
WRT2, EBTR2 = 11
005FFFh
006000h
WRT3, EBTR3 = 11
007FFFh
Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0.
TABLAT register returns a value of ‘0’.
005FFFh
006000h
WRT3, EBTR3 = 11
007FFFh
Literal operations
15 8 7 0
OPCODE k (literal) MOVLW 7Fh
Control operations
CALL, GOTO and Branch operations
15 8 7 0
OPCODE n<7:0> (literal) GOTO Label
15 12 11 0
1111 n<19:8> (literal)
15 8 7 0
OPCODE S n<7:0> (literal) CALL MYFUNC
15 12 11 0
1111 n<19:8> (literal)
S = Fast bit
15 11 10 0
OPCODE n<10:0> (literal) BRA MYFUNC
15 8 7 0
OPCODE n<7:0> (literal) BC MYFUNC
BYTE-ORIENTED OPERATIONS
ADDWF f, d, a Add WREG and f 1 0010 01da ffff ffff C, DC, Z, OV, N 1, 2
ADDWFC f, d, a Add WREG and Carry bit to f 1 0010 00da ffff ffff C, DC, Z, OV, N 1, 2
ANDWF f, d, a AND WREG with f 1 0001 01da ffff ffff Z, N 1,2
CLRF f, a Clear f 1 0110 101a ffff ffff Z 2
COMF f, d, a Complement f 1 0001 11da ffff ffff Z, N 1, 2
CPFSEQ f, a Compare f with WREG, skip = 1 (2 or 3) 0110 001a ffff ffff None 4
CPFSGT f, a Compare f with WREG, skip > 1 (2 or 3) 0110 010a ffff ffff None 4
CPFSLT f, a Compare f with WREG, skip < 1 (2 or 3) 0110 000a ffff ffff None 1, 2
DECF f, d, a Decrement f 1 0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
DECFSZ f, d, a Decrement f, Skip if 0 1 (2 or 3) 0010 11da ffff ffff None 1, 2, 3, 4
DCFSNZ f, d, a Decrement f, Skip if Not 0 1 (2 or 3) 0100 11da ffff ffff None 1, 2
INCF f, d, a Increment f 1 0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
INCFSZ f, d, a Increment f, Skip if 0 1 (2 or 3) 0011 11da ffff ffff None 4
INFSNZ f, d, a Increment f, Skip if Not 0 1 (2 or 3) 0100 10da ffff ffff None 1, 2
IORWF f, d, a Inclusive OR WREG with f 1 0001 00da ffff ffff Z, N 1, 2
MOVF f, d, a Move f 1 0101 00da ffff ffff Z, N 1
MOVFF fs, fd Move fs (source) to 1st word 2 1100 ffff ffff ffff None
fd (destination) 2nd word 1111 ffff ffff ffff
MOVWF f, a Move WREG to f 1 0110 111a ffff ffff None
MULWF f, a Multiply WREG with f 1 0000 001a ffff ffff None 1, 2
NEGF f, a Negate f 1 0110 110a ffff ffff C, DC, Z, OV, N
RLCF f, d, a Rotate Left f through Carry 1 0011 01da ffff ffff C, Z, N 1, 2
RLNCF f, d, a Rotate Left f (No Carry) 1 0100 01da ffff ffff Z, N
RRCF f, d, a Rotate Right f through Carry 1 0011 00da ffff ffff C, Z, N
RRNCF f, d, a Rotate Right f (No Carry) 1 0100 00da ffff ffff Z, N
SETF f, a Set f 1 0110 100a ffff ffff None 1, 2
SUBFWB f, d, a Subtract f from WREG with 1 0101 01da ffff ffff C, DC, Z, OV, N
borrow
SUBWF f, d, a Subtract WREG from f 1 0101 11da ffff ffff C, DC, Z, OV, N 1, 2
SUBWFB f, d, a Subtract WREG from f with 1 0101 10da ffff ffff C, DC, Z, OV, N
borrow
SWAPF f, d, a Swap nibbles in f 1 0011 10da ffff ffff None 4
TSTFSZ f, a Test f, skip if 0 1 (2 or 3) 0110 011a ffff ffff None 1, 2
XORWF f, d, a Exclusive OR WREG with f 1 0001 10da ffff ffff Z, N
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as an input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if
assigned.
3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
BIT-ORIENTED OPERATIONS
BCF f, b, a Bit Clear f 1 1001 bbba ffff ffff None 1, 2
BSF f, b, a Bit Set f 1 1000 bbba ffff ffff None 1, 2
BTFSC f, b, a Bit Test f, Skip if Clear 1 (2 or 3) 1011 bbba ffff ffff None 3, 4
BTFSS f, b, a Bit Test f, Skip if Set 1 (2 or 3) 1010 bbba ffff ffff None 3, 4
BTG f, d, a Bit Toggle f 1 0111 bbba ffff ffff None 1, 2
CONTROL OPERATIONS
BC n Branch if Carry 1 (2) 1110 0010 nnnn nnnn None
BN n Branch if Negative 1 (2) 1110 0110 nnnn nnnn None
BNC n Branch if Not Carry 1 (2) 1110 0011 nnnn nnnn None
BNN n Branch if Not Negative 1 (2) 1110 0111 nnnn nnnn None
BNOV n Branch if Not Overflow 1 (2) 1110 0101 nnnn nnnn None
BNZ n Branch if Not Zero 1 (2) 1110 0001 nnnn nnnn None
BOV n Branch if Overflow 1 (2) 1110 0100 nnnn nnnn None
BRA n Branch Unconditionally 2 1101 0nnn nnnn nnnn None
BZ n Branch if Zero 1 (2) 1110 0000 nnnn nnnn None
CALL n, s Call subroutine 1st word 2 1110 110s kkkk kkkk None
2nd word 1111 kkkk kkkk kkkk
CLRWDT — Clear Watchdog Timer 1 0000 0000 0000 0100 TO, PD
DAW — Decimal Adjust WREG 1 0000 0000 0000 0111 C
GOTO n Go to address 1st word 2 1110 1111 kkkk kkkk None
2nd word 1111 kkkk kkkk kkkk
NOP — No Operation 1 0000 0000 0000 0000 None
NOP — No Operation 1 1111 xxxx xxxx xxxx None 4
POP — Pop top of return stack (TOS) 1 0000 0000 0000 0110 None
PUSH — Push top of return stack (TOS) 1 0000 0000 0000 0101 None
RCALL n Relative Call 2 1101 1nnn nnnn nnnn None
RESET Software device Reset 1 0000 0000 1111 1111 All
RETFIE s Return from interrupt enable 2 0000 0000 0001 000s GIE/GIEH,
PEIE/GIEL
RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None
RETURN s Return from Subroutine 2 0000 0000 0001 001s None
SLEEP — Go into Standby mode 1 0000 0000 0000 0011 TO, PD
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as an input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if
assigned.
3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
LITERAL OPERATIONS
ADDLW k Add literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N
ANDLW k AND literal with WREG 1 0000 1011 kkkk kkkk Z, N
IORLW k Inclusive OR literal with WREG 1 0000 1001 kkkk kkkk Z, N
LFSR f, k Move literal (12-bit) 2nd word 2 1110 1110 00ff kkkk None
to FSR(f) 1st word 1111 0000 kkkk kkkk
MOVLB k Move literal to BSR<3:0> 1 0000 0001 0000 kkkk None
MOVLW k Move literal to WREG 1 0000 1110 kkkk kkkk None
MULLW k Multiply literal with WREG 1 0000 1101 kkkk kkkk None
RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None
SUBLW k Subtract WREG from literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N
XORLW k Exclusive OR literal with WREG 1 0000 1010 kkkk kkkk Z, N
DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS
TBLRD* Table Read 2 0000 0000 0000 1000 None
TBLRD*+ Table Read with post-increment 0000 0000 0000 1001 None
TBLRD*- Table Read with post-decrement 0000 0000 0000 1010 None
TBLRD+* Table Read with pre-increment 0000 0000 0000 1011 None
TBLWT* Table Write 2 0000 0000 0000 1100 None
TBLWT*+ Table Write with post-increment 0000 0000 0000 1101 None
TBLWT*- Table Write with post-decrement 0000 0000 0000 1110 None
TBLWT+* Table Write with pre-increment 0000 0000 0000 1111 None
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as an input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if
assigned.
3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
Note: All PIC18 instructions may take an optional label argument, preceding the instruction mnemonic, for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
Q1 Q2 Q3 Q4 If No Jump:
Example: Q1 Q2 Q3 Q4
HERE BRA Jump
Decode Read Process Write
Before Instruction
register ‘f’ Data register ‘f’
PC = address (HERE)
After Instruction
PC = address (Jump) Example: BSF FLAG_REG, 7, 1
Before Instruction
FLAG_REG = 0Ah
After Instruction
FLAG_REG = 8Ah
Description: Clears the contents of the specified Encoding: 0000 0000 0000 0100
register. Description: CLRWDT instruction resets the
If ‘a’ is ‘0’, the Access Bank is selected. Watchdog Timer. It also resets the
If ‘a’ is ‘1’, the BSR is used to select the postscaler of the WDT. Status bits, TO
GPR bank (default). and PD, are set.
If ‘a’ is ‘0’ and the extended instruction
Words: 1
set is enabled, this instruction operates
in Indexed Literal Offset Addressing Cycles: 1
mode whenever f ≤ 95 (5Fh). See Q Cycle Activity:
Section 26.2.3 “Byte-Oriented and
Q1 Q2 Q3 Q4
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details. Decode No Process No
operation Data operation
Words: 1
Cycles: 1 Example: CLRWDT
Q Cycle Activity: Before Instruction
Q1 Q2 Q3 Q4 WDT Counter = ?
Decode Read Process Write After Instruction
register ‘f’ Data register ‘f’ WDT Counter = 00h
WDT Postscaler = 0
TO = 1
Example: CLRF FLAG_REG,1
PD = 1
Before Instruction
FLAG_REG = 5Ah
After Instruction
FLAG_REG = 00h
Q1 Q2 Q3 Q4 Q Cycle Activity:
Decode Read Process Write to Q1 Q2 Q3 Q4
register ‘f’ Data destination Decode Read Process Write to
If skip: register ‘f’ Data destination
Q1 Q2 Q3 Q4 If skip:
No No No No Q1 Q2 Q3 Q4
operation operation operation operation No No No No
If skip and followed by 2-word instruction: operation operation operation operation
Q1 Q2 Q3 Q4 If skip and followed by 2-word instruction:
No No No No Q1 Q2 Q3 Q4
operation operation operation operation No No No No
No No No No operation operation operation operation
operation operation operation operation No No No No
operation operation operation operation
Example: HERE DECFSZ CNT, 1, 1
GOTO LOOP Example: HERE DCFSNZ TEMP, 1, 0
CONTINUE ZERO :
NZERO :
Before Instruction
PC = Address (HERE) Before Instruction
After Instruction TEMP = ?
CNT = CNT – 1 After Instruction
If CNT = 0; TEMP = TEMP – 1,
PC = Address (CONTINUE) If TEMP = 0;
If CNT ≠ 0; PC = Address (ZERO)
PC = Address (HERE + 2) If TEMP ≠ 0;
PC = Address (NZERO)
Words: 1 C register f
Cycles: 1
Words: 1
Q Cycle Activity:
Cycles: 1
Q1 Q2 Q3 Q4
Decode Read Process Write to Q Cycle Activity:
register ‘f’ Data destination Q1 Q2 Q3 Q4
Decode Read Process Write to
Example: RLNCF REG, 1, 0 register ‘f’ Data destination
Before Instruction
REG = 1010 1011 Example: RRCF REG, 0, 0
After Instruction Before Instruction
REG = 0101 0111 REG = 1110 0110
C = 0
After Instruction
REG = 1110 0110
W = 0111 0011
C = 0
After Instruction Q1 Q2 Q3 Q4
TO = 1† Decode Read Process Write to
PD = 0 register ‘f’ Data destination
Example 1: SUBFWB REG, 1, 0
† If WDT causes wake-up, this bit is cleared.
Before Instruction
REG = 3
W = 2
C = 1
After Instruction
REG = FF
W = 2
C = 0
Z = 0
N = 1 ; result is negative
Example 2: SUBFWB REG, 0, 0
Before Instruction
REG = 2
W = 5
C = 1
After Instruction
REG = 2
W = 3
C = 1
Z = 0
N = 0 ; result is positive
Example 3: SUBFWB REG, 1, 0
Before Instruction
REG = 1
W = 2
C = 0
After Instruction
REG = 0
W = 2
C = 1
Z = 1 ; result is zero
N = 0
ADDFSR Add Literal to FSR ADDULNK Add Literal to FSR2 and Return
Syntax: ADDFSR f, k Syntax: ADDULNK k
Operands: 0 ≤ k ≤ 63 Operands: 0 ≤ k ≤ 63
f ∈ [ 0, 1, 2 ] Operation: FSR2 + k → FSR2,
Operation: FSR(f) + k → FSR(f) (TOS) → PC
Status Affected: None Status Affected: None
Encoding: 1110 1000 ffkk kkkk Encoding: 1110 1000 11kk kkkk
Description: The 6-bit literal ‘k’ is added to the Description: The 6-bit literal ‘k’ is added to the
contents of the FSR specified by ‘f’. contents of FSR2. A RETURN is then
Words: 1 executed by loading the PC with the
Cycles: 1 TOS.
The instruction takes two cycles to
Q Cycle Activity:
execute; a NOP is performed during
Q1 Q2 Q3 Q4
the second cycle.
Decode Read Process Write to This may be thought of as a special
literal ‘k’ Data FSR case of the ADDFSR instruction,
where f = 3 (binary ‘11’); it operates
only on FSR2.
Example: ADDFSR 2, 23h Words: 1
Before Instruction Cycles: 2
FSR2 = 03FFh Q Cycle Activity:
After Instruction Q1 Q2 Q3 Q4
FSR2 = 0422h
Decode Read Process Write to
literal ‘k’ Data FSR
No No No No
Operation Operation Operation Operation
Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s).
MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2, Decrement FSR2
Syntax: MOVSS [zs], [zd] Syntax: PUSHL k
Operands: 0 ≤ zs ≤ 127 Operands: 0 ≤ k ≤ 255
0 ≤ zd ≤ 127
Operation: k → (FSR2),
Operation: ((FSR2) + zs) → ((FSR2) + zd) FSR2 – 1→ FSR2
Status Affected: None Status Affected: None
Encoding:
Encoding: 1111 1010 kkkk kkkk
1st word (source) 1110 1011 1zzz zzzzs
2nd word (dest.) 1111 xxxx xzzz zzzzd Description: The 8-bit literal ‘k’ is written to the data
memory address specified by FSR2. FSR2
Description The contents of the source register are
is decremented by ‘1’ after the operation.
moved to the destination register. The
This instruction allows users to push values
addresses of the source and destination
onto a software stack.
registers are determined by adding the
7-bit literal offsets ‘zs’ or ‘zd’, Words: 1
respectively, to the value of FSR2. Both Cycles: 1
registers can be located anywhere in
the 4096-byte data memory space Q Cycle Activity:
(000h to FFFh). Q1 Q2 Q3 Q4
The MOVSS instruction cannot use the Decode Read ‘k’ Process Write to
PCL, TOSU, TOSH or TOSL as the data destination
destination register.
If the resultant source address points to
an indirect addressing register, the Example: PUSHL 08h
value returned will be 00h. If the
Before Instruction
resultant destination address points to
FSR2H:FSR2L = 01ECh
an indirect addressing register, the Memory (01ECh) = 00h
instruction will execute as a NOP.
Words: 2 After Instruction
FSR2H:FSR2L = 01EBh
Cycles: 2 Memory (01ECh) = 08h
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Determine Determine Read
source addr source addr source reg
Decode Determine Determine Write
dest addr dest addr to dest reg
SUBFSR Subtract Literal from FSR SUBULNK Subtract Literal from FSR2 and Return
Syntax: SUBFSR f, k Syntax: SUBULNK k
Operands: 0 ≤ k ≤ 63 Operands: 0 ≤ k ≤ 63
f ∈ [ 0, 1, 2 ] Operation: FSR2 – k → FSR2
Operation: FSRf – k → FSRf (TOS) → PC
Status Affected: None Status Affected: None
Encoding: 1110 1001 ffkk kkkk Encoding: 1110 1001 11kk kkkk
Description: The 6-bit literal ‘k’ is subtracted from Description: The 6-bit literal ‘k’ is subtracted from the
the contents of the FSR specified by contents of the FSR2. A RETURN is then
‘f’. executed by loading the PC with the TOS.
Words: 1 The instruction takes two cycles to
execute; a NOP is performed during the
Cycles: 1
second cycle.
Q Cycle Activity:
This may be thought of as a special case of
Q1 Q2 Q3 Q4 the SUBFSR instruction, where f = 3 (binary
Decode Read Process Write to ‘11’); it operates only on FSR2.
register ‘f’ Data destination Words: 1
Cycles: 2
Q Cycle Activity:
Example: SUBFSR 2, 23h
Q1 Q2 Q3 Q4
Before Instruction
FSR2 = 03FFh Decode Read Process Write to
After Instruction register ‘f’ Data destination
FSR2 = 03DCh No No No No
Operation Operation Operation Operation
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
6.0V
5.5V
5.0V PIC18FX455/X550
4.5V
Voltage
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
48 MHz
Frequency
6.0V
5.5V
5.0V PIC18LFX455/X550
4.5V
4.2V
4.0V
Voltage
3.5V
3.0V
2.5V
2.0V
Frequency
Note: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application.
Param
Symbol Characteristic Min Max Units Conditions
No.
VIL Input Low Voltage
I/O ports (except RC4/RC5 in
USB mode):
D030 with TTL buffer VSS 0.15 VDD V VDD < 4.5V
D030A — 0.8 V 4.5V ≤ VDD ≤ 5.5V
D031 with Schmitt Trigger buffer VSS 0.2 VDD V
RC3 and RC4 VSS 0.3 VDD V
D032 MCLR VSS 0.2 VDD V
D032A OSC1 and T1OSI VSS 0.3 VDD V XT, HS,
HSPLL modes(1)
D033 OSC1 VSS 0.2 VDD V EC mode(1)
VILU D+/D- input — 0.8 V VDD = 4.35V,
USB suspended(5)
VIH Input High Voltage
I/O ports (except RC4/RC5 in
USB mode):
D040 with TTL buffer 0.25 VDD + 0.8V VDD V VDD < 4.5V
D040A 2.0 VDD V 4.5V ≤ VDD ≤ 5.5V
D041 with Schmitt Trigger buffer 0.8 VDD VDD V
RC3 and RC4 0.7 VDD VDD V
D042 MCLR 0.8 VDD VDD V
D042A OSC1 and T1OSI 0.7 VDD VDD V XT, HS,
HSPLL modes(1)
D043 OSC1 0.8 VDD VDD V EC mode(1)
VIHU D+/D- input 2.4 — V VDD = 4.35V,
USB suspended(5)
IIL Input Leakage Current(2,3)
D060 I/O ports — ±1 μA VSS ≤ VPIN ≤ VDD,
Pin at high-impedance
D061 MCLR — ±5 μA Vss ≤ VPIN ≤ VDD
D063 OSC1 — ±5 μA Vss ≤ VPIN ≤ VDD
IPU Weak Pull-up Current
D070 IPURB PORTB weak pull-up current 50 400 μA VDD = 5V, VPIN = VSS
Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PICmicro® device be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: Parameter is characterized but not tested.
5: D+ parameters per USB Specification 2.0.
Param
Sym Characteristics Min Typ Max Units Comments
No.
D300 VIOFF Input Offset Voltage — ±5.0 ±10 mV
D301 VICM Input Common Mode Voltage* 0 — VDD – 1.5 V
D302 CMRR Common Mode Rejection Ratio* 55 — — dB
300 TRESP Response Time*(1) — 150 400 ns PIC18FXXXX
300A — 150 600 ns PIC18LFXXXX,
VDD = 2.0V
301 TMC2OV Comparator Mode Change to — — 10 μs
Output Valid*
* These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions
from VSS to VDD.
Param
Sym Characteristics Min Typ Max Units Comments
No.
D310 VRES Resolution VDD/24 — VDD/32 LSb
D311 VRAA Absolute Accuracy — 1/4 1 LSb Low Range (CVRR = 1)
— — 1/2 LSb High Range (CVRR = 0)
D312 VRUR Unit Resistor Value (R)* — 2k — Ω
310 TSET Settling Time*(1) — — 10 μs
* These parameters are characterized but not tested.
Note 1: Settling time measured while CVRR = 1 and CVR3:CVR0 transitions from ‘0000’ to ‘1111’.
Param
Sym Characteristics Min Typ Max Units Comments
No.
D323 VUSBANA Regulator Output Voltage* 3.0 — 3.6 V
D324 CUSB External Filter Capacitor 220 — — nF Must hold sufficient charge
Value* for peak load with minimal
voltage drop
* These parameters are characterized but not tested. Parameter numbers not yet assigned for these
specifications.
VHLVD
VHLVD
HLVDIF
VDD/2
RL Pin CL
VSS
CL
Pin
RL = 464Ω
VSS CL = 50 pF for all pins except OSC2/CLKO
and including D and E outputs as ports
OSC1
1 3 3 4 4
2
CLKO
Param
Device Min Typ Max Units Conditions
No.
INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz(1)
PIC18LF2455/2550/4455/4550 -2 +/-1 2 % +25°C VDD = 2.7-3.3V
-5 — 5 % -10°C to +85°C VDD = 2.7-3.3V
-10 +/-1 10 % -40°C to +85°C VDD = 2.7-3.3V
PIC18F2455/2550/4455/4550 -2 +/-1 2 % +25°C VDD = 4.5-5.5V
-5 — 5 % -10°C to +85°C VDD = 4.5-5.5V
-10 +/-1 10 % -40°C to +85°C VDD = 4.5-5.5V
(2)
INTRC Accuracy @ Freq = 31 kHz
PIC18LF2455/2550/4455/4550 26.562 — 35.938 kHz -40°C to +85°C VDD = 2.7-3.3V
PIC18F2455/2550/4455/4550 26.562 — 35.938 kHz -40°C to +85°C VDD = 4.5-5.5V
Legend: Shading of rows is to assist in readability of the table.
Note 1: Frequency calibrated at 25°C. OSCTUNE register can be used to compensate for temperature drift.
2: INTRC frequency after calibration.
3: Change of INTRC frequency as VDD changes.
OSC1
10 11
CLKO
13 12
14 19 18
16
I/O pin
(Input)
17 15
20, 21
Note: Refer to Figure 28-4 for load conditions.
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out 32
Oscillator
Time-out
Internal
Reset
Watchdog
Timer
Reset 31
34 34
I/O pins
VDD BVDD
35
VBGAP = 1.2V
VIRVST
Enable Internal
Reference Voltage
Internal Reference
Voltage Stable 36
TABLE 28-12: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
Symbol Characteristic Min Typ Max Units Conditions
No.
T0CKI
40 41
42
T1OSO/T13CKI
45 46
47 48
TMR0 or
TMR1
CCPx
(Capture Mode)
50 51
52
CCPx
(Compare or PWM Mode)
53 54
SS
70
SCK
(CKP = 0)
71 72
78 79
SCK
(CKP = 1)
79 78
80
75, 76
SS
81
SCK
(CKP = 0)
71 72
79
73
SCK
(CKP = 1)
80
78
75, 76
74
Note: Refer to Figure 28-4 for load conditions.
SS
70
SCK
(CKP = 0) 83
71 72
78 79
SCK
(CKP = 1)
79 78
80
75, 76 77
TABLE 28-17: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param
Symbol Characteristic Min Max Units Conditions
No.
70
SCK 83
(CKP = 0)
71 72
SCK
(CKP = 1)
80
75, 76 77
SDI
MSb In bit 6 - - - -1 LSb In
74
Note: Refer to Figure 28-4 for load conditions.
SCL
91 93
90 92
SDA
Start Stop
Condition Condition
91 92
SDA
In
110
109 109
SDA
Out
SCL
91 93
90 92
SDA
Start Stop
Condition Condition
SDA
Out
RC6/TX/CK
pin
121 121
RC7/RX/DT/SDO
pin
120
122
Note: Refer to Figure 28-4 for load conditions.
RC6/TX/CK
pin
125
RC7/RX/DT/SDO
pin
126
90%
VCRS
10%
OESPP
CSSPP
ToeF2adR ToeF2daR
BSF ADCON0, GO
(Note 2)
131
Q4
130
A/D CLK 132
ADIF TCY(1)
GO DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.
This allows the SLEEP instruction to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
XXXXXXXXXXXXXXXXX PIC18F2455-I/SP e3
XXXXXXXXXXXXXXXXX 0510017
YYWWNNN
XXXXXXXXXXXXXXXXXXXX PIC18F2550-E/SO e3
XXXXXXXXXXXXXXXXXXXX 0510017
XXXXXXXXXXXXXXXXXXXX
YYWWNNN
XXXXXXXXXXXXXXXXXX PIC18F4455-I/P e3
XXXXXXXXXXXXXXXXXX 0510017
XXXXXXXXXXXXXXXXXX
YYWWNNN
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
XXXXXXXXXX PIC18F4550
XXXXXXXXXX -I/PT e3
XXXXXXXXXX 0510017
YYWWNNN
XXXXXXXXXX PIC18F4550
XXXXXXXXXX -I/ML e3
XXXXXXXXXX 0510017
YYWWNNN
28-Lead Skinny Plastic Dual In-line (SP) – 300 mil Body (PDIP)
E1
2
n 1 α
E
A2
L
c
β A1 B1
eB B p
E
E1
p
B
2
n 1
h
α
45°
c
A A2
φ
β L A1
E1
2 α
n 1
A A2
L
c
β B1
A1
eB B p
E
E1
#leads=n1
D1 D
2
1
B
n
CH x 45°
α
A
c
φ
β A1 A2
L F
E EXPOSED
METAL PAD K
(NOTE 2)
D D2
2 B
1
n PIN 1
OPTIONAL INDEX ON E2
INDEX AREA EXPOSED PAD L
(NOTE 1) (PROFILE MAY VARY)
A3 A1
E F
Effect on Standard PIC Instructions ................................... 75 Fail-Safe Clock Monitor ........................................... 285, 300
Effect on Standard PIC MCU Instructions ........................ 354 Exiting the Operation ............................................... 300
Electrical Characteristics .................................................. 361 Interrupts in Power-Managed Modes ...................... 301
Enhanced Capture/Compare/PWM (ECCP) .................... 149 POR or Wake-up from Sleep ................................... 301
Associated Registers ............................................... 162 WDT During Oscillator Failure ................................. 300
Capture and Compare Modes .................................. 150 Fast Register Stack ........................................................... 60
Capture Mode. See Capture (ECCP Module). Firmware Instructions ...................................................... 307
Outputs and Configuration ....................................... 150 Flash Program Memory ..................................................... 79
Pin Configurations for ECCP1 ................................. 150 Associated Registers ................................................. 87
PWM Mode. See PWM (ECCP Module). Control Registers ....................................................... 80
Standard PWM Mode ............................................... 150 EECON1 and EECON2 ..................................... 80
Timer Resources ...................................................... 150 TABLAT (Table Latch) Register ........................ 82
Enhanced Universal Synchronous Asynchronous TBLPTR (Table Pointer) Register ...................... 82
Receiver Transmitter (EUSART). See EUSART. Erase Sequence ........................................................ 84
Equations Erasing ...................................................................... 84
A/D Acquisition Time ................................................ 264 Operation During Code-Protect ................................. 87
A/D Minimum Charging Time ................................... 264 Protection Against Spurious Writes ........................... 87
Calculating the Minimum Required Reading ..................................................................... 83
A/D Acquisition Time ....................................... 264 Table Pointer
Errata ................................................................................... 5 Boundaries Based on Operation ....................... 82
EUSART Table Pointer Boundaries .......................................... 82
Asynchronous Mode ................................................ 247 Table Reads and Table Writes .................................. 79
12-Bit Break Transmit and Receive ................. 253 Unexpected Termination of Write .............................. 87
Associated Registers, Receive ........................ 251 Write Sequence ......................................................... 85
Associated Registers, Transmit ....................... 249 Write Verify ................................................................ 87
Auto-Wake-up on Sync Break Character ......... 252 Writing To .................................................................. 85
Receiver ........................................................... 250 FSCM. See Fail-Safe Clock Monitor.
Setting up 9-Bit Mode with
Address Detect ........................................ 250 G
Transmitter ....................................................... 247 GOTO .............................................................................. 328
Baud Rate Generator
Operation in Power-Managed Modes .............. 241
H
Baud Rate Generator (BRG) .................................... 241 Hardware Multiplier ............................................................ 95
Associated Registers ....................................... 242 Introduction ................................................................ 95
Auto-Baud Rate Detect .................................... 245 Operation ................................................................... 95
Baud Rate Error, Calculating ........................... 242 Performance Comparison .......................................... 95
Baud Rates, Asynchronous Modes ................. 243
High Baud Rate Select (BRGH Bit) ................. 241
Sampling .......................................................... 241
Synchronous Master Mode ...................................... 254
Associated Registers, Receive ........................ 256
Associated Registers, Transmit ....................... 255
Reception ......................................................... 256
Transmission ................................................... 254
W
Watchdog Timer (WDT) ........................................... 285, 297
Associated Registers ............................................... 298
Control Register ....................................................... 297
During Oscillator Failure .......................................... 300
Programming Considerations .................................. 297
WCOL ...................................................... 225, 226, 227, 230
WCOL Status Flag ................................... 225, 226, 227, 230
WWW Address ................................................................. 423
WWW, On-Line Support ...................................................... 5
X
XORLW ............................................................................ 347
XORWF ............................................................................ 348
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________ FAX: (______) _________ - _________
Application (optional):
Would you like a reply? Y N
Questions:
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
10/31/05