; generated by ARM C/C++ Compiler, 5.

03 [Build 76]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave
-o.\flash\obj\stm32f10x_pwr.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\
--depend=.\flash\obj\stm32f10x_pwr.d --cpu=Cortex-M3 --apcs=interwork -O0
--diag_suppress=870 -I..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include
-I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\User\bsp
-I..\..\User\bsp\inc -I..\..\uCOS-II\uCOS-II\Ports\ARM-Cortex-M3\Generic\RealView
-I..\..\uCOS-II\uCOS-II\Source -I..\..\uCOS-II\uC-LIB -I..\..\uCOS-II\uC-
LIB\Ports\ARM-Cortex-M3\RealView -I..\..\uCOS-II\uC-CPU -I..\..\uCOS-II\uC-CPU\ARM-
Cortex-M3\RealView -I..\..\User -I..\..\Libraries\CMSIS\Include
-IC:\Keil\ARM\RV31\INC -IC:\Keil\ARM\CMSIS\Include -IC:\Keil\ARM\Inc\ST\STM32F10x
-D__MICROLIB -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD
..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_pwr.c]
THUMB

AREA ||i.PWR_BackupAccessCmd||, CODE, READONLY, ALIGN=2

PWR_BackupAccessCmd PROC
;;;129 */
;;;130 void PWR_BackupAccessCmd(FunctionalState NewState)
000000 4901 LDR r1,|L1.8|
;;;131 {
;;;132 /* Check the parameters */
;;;133 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;134 *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
000002 6208 STR r0,[r1,#0x20]
;;;135 }
000004 4770 BX lr
;;;136
ENDP

000006 0000 DCW 0x0000

|L1.8|
DCD 0x420e0000

AREA ||i.PWR_ClearFlag||, CODE, READONLY, ALIGN=2

PWR_ClearFlag PROC
;;;292 */
;;;293 void PWR_ClearFlag(uint32_t PWR_FLAG)
000000 4903 LDR r1,|L2.16|
;;;294 {
;;;295 /* Check the parameters */
;;;296 assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
;;;297
;;;298 PWR->CR |= PWR_FLAG << 2;
000002 6809 LDR r1,[r1,#0]
000004 ea410180 ORR r1,r1,r0,LSL #2
000008 4a01 LDR r2,|L2.16|
00000a 6011 STR r1,[r2,#0]
;;;299 }
00000c 4770 BX lr
;;;300
ENDP

00000e 0000 DCW 0x0000

|L2.16|
DCD 0x40007000
 AREA ||i.PWR_DeInit||, CODE, READONLY, ALIGN=1

PWR_DeInit PROC
;;;117 */
;;;118 void PWR_DeInit(void)
000000 b510 PUSH {r4,lr}
;;;119 {
;;;120 RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
000002 2101 MOVS r1,#1
000004 0708 LSLS r0,r1,#28
000006 f7fffffe BL RCC_APB1PeriphResetCmd
;;;121 RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
00000a 2100 MOVS r1,#0
00000c f04f5080 MOV r0,#0x10000000
000010 f7fffffe BL RCC_APB1PeriphResetCmd
;;;122 }
000014 bd10 POP {r4,pc}
;;;123
ENDP

AREA ||i.PWR_EnterSTANDBYMode||, CODE, READONLY, ALIGN=2

PWR_EnterSTANDBYMode PROC
;;;241 */
;;;242 void PWR_EnterSTANDBYMode(void)
000000 480a LDR r0,|L4.44|
;;;243 {
;;;244 /* Clear Wake-up flag */
;;;245 PWR->CR |= PWR_CR_CWUF;
000002 6800 LDR r0,[r0,#0]
000004 f0400004 ORR r0,r0,#4
000008 4908 LDR r1,|L4.44|
00000a 6008 STR r0,[r1,#0]
;;;246 /* Select STANDBY mode */
;;;247 PWR->CR |= PWR_CR_PDDS;
00000c 4608 MOV r0,r1
00000e 6800 LDR r0,[r0,#0]
000010 f0400002 ORR r0,r0,#2
000014 6008 STR r0,[r1,#0]
;;;248 /* Set SLEEPDEEP bit of Cortex System Control Register */
;;;249 SCB->SCR |= SCB_SCR_SLEEPDEEP;
000016 4806 LDR r0,|L4.48|
000018 6800 LDR r0,[r0,#0]
00001a f0400004 ORR r0,r0,#4
00001e 4904 LDR r1,|L4.48|
000020 6008 STR r0,[r1,#0]
;;;250 /* This option is used to ensure that store operations are completed */
;;;251 #if defined ( __CC_ARM )
;;;252 __force_stores();
000022 bf00 NOP
000024 bf00 NOP
;;;253 #endif
;;;254 /* Request Wait For Interrupt */
;;;255 __WFI();
000026 bf30 WFI
;;;256 }
000028 4770 BX lr
;;;257
 ENDP

00002a 0000 DCW 0x0000

|L4.44|
DCD 0x40007000
|L4.48|
DCD 0xe000ed10

AREA ||i.PWR_EnterSTOPMode||, CODE, READONLY, ALIGN=2

PWR_EnterSTOPMode PROC
;;;202 */
;;;203 void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
000000 b510 PUSH {r4,lr}
;;;204 {
000002 4602 MOV r2,r0
;;;205 uint32_t tmpreg = 0;
000004 2000 MOVS r0,#0
;;;206 /* Check the parameters */
;;;207 assert_param(IS_PWR_REGULATOR(PWR_Regulator));
;;;208 assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
;;;209
;;;210 /* Select the regulator state in STOP mode
---------------------------------*/
;;;211 tmpreg = PWR->CR;
000006 4b0c LDR r3,|L5.56|
000008 6818 LDR r0,[r3,#0]
;;;212 /* Clear PDDS and LPDS bits */
;;;213 tmpreg &= CR_DS_MASK;
00000a f0200003 BIC r0,r0,#3
;;;214 /* Set LPDS bit according to PWR_Regulator value */
;;;215 tmpreg |= PWR_Regulator;
00000e 4310 ORRS r0,r0,r2
;;;216 /* Store the new value */
;;;217 PWR->CR = tmpreg;
000010 6018 STR r0,[r3,#0]
;;;218 /* Set SLEEPDEEP bit of Cortex System Control Register */
;;;219 SCB->SCR |= SCB_SCR_SLEEPDEEP;
000012 4b0a LDR r3,|L5.60|
000014 681b LDR r3,[r3,#0]
000016 f0430304 ORR r3,r3,#4
00001a 4c08 LDR r4,|L5.60|
00001c 6023 STR r3,[r4,#0]
;;;220
;;;221 /* Select STOP mode entry
--------------------------------------------------*/
;;;222 if(PWR_STOPEntry == PWR_STOPEntry_WFI)
00001e 2901 CMP r1,#1
000020 d101 BNE |L5.38|
;;;223 {
;;;224 /* Request Wait For Interrupt */
;;;225 __WFI();
000022 bf30 WFI
000024 e000 B |L5.40|
|L5.38|
;;;226 }
;;;227 else
;;;228 {
;;;229 /* Request Wait For Event */
;;;230 __WFE();
000026 bf20 WFE
|L5.40|
;;;231 }
;;;232
;;;233 /* Reset SLEEPDEEP bit of Cortex System Control Register */
;;;234 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
000028 4b04 LDR r3,|L5.60|
00002a 681b LDR r3,[r3,#0]
00002c f0230304 BIC r3,r3,#4
000030 4c02 LDR r4,|L5.60|
000032 6023 STR r3,[r4,#0]
;;;235 }
000034 bd10 POP {r4,pc}
;;;236
ENDP

000036 0000 DCW 0x0000

|L5.56|
DCD 0x40007000
|L5.60|
DCD 0xe000ed10

AREA ||i.PWR_GetFlagStatus||, CODE, READONLY, ALIGN=2

PWR_GetFlagStatus PROC
;;;266 */
;;;267 FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
000000 4601 MOV r1,r0
;;;268 {
;;;269 FlagStatus bitstatus = RESET;
000002 2000 MOVS r0,#0
;;;270 /* Check the parameters */
;;;271 assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
;;;272
;;;273 if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
000004 4a03 LDR r2,|L6.20|
000006 6852 LDR r2,[r2,#4]
000008 420a TST r2,r1
00000a d001 BEQ |L6.16|
;;;274 {
;;;275 bitstatus = SET;
00000c 2001 MOVS r0,#1
00000e e000 B |L6.18|
|L6.16|
;;;276 }
;;;277 else
;;;278 {
;;;279 bitstatus = RESET;
000010 2000 MOVS r0,#0
|L6.18|
;;;280 }
;;;281 /* Return the flag status */
;;;282 return bitstatus;
;;;283 }
000012 4770 BX lr
;;;284
ENDP
 |L6.20|
DCD 0x40007000

AREA ||i.PWR_PVDCmd||, CODE, READONLY, ALIGN=2

PWR_PVDCmd PROC
;;;142 */
;;;143 void PWR_PVDCmd(FunctionalState NewState)
000000 4901 LDR r1,|L7.8|
;;;144 {
;;;145 /* Check the parameters */
;;;146 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;147 *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
000002 6108 STR r0,[r1,#0x10]
;;;148 }
000004 4770 BX lr
;;;149
ENDP

000006 0000 DCW 0x0000

|L7.8|
DCD 0x420e0000

AREA ||i.PWR_PVDLevelConfig||, CODE, READONLY, ALIGN=2

PWR_PVDLevelConfig PROC
;;;163 */
;;;164 void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
000000 4601 MOV r1,r0
;;;165 {
;;;166 uint32_t tmpreg = 0;
000002 2000 MOVS r0,#0
;;;167 /* Check the parameters */
;;;168 assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
;;;169 tmpreg = PWR->CR;
000004 4a03 LDR r2,|L8.20|
000006 6810 LDR r0,[r2,#0]
;;;170 /* Clear PLS[7:5] bits */
;;;171 tmpreg &= CR_PLS_MASK;
000008 f02000e0 BIC r0,r0,#0xe0
;;;172 /* Set PLS[7:5] bits according to PWR_PVDLevel value */
;;;173 tmpreg |= PWR_PVDLevel;
00000c 4308 ORRS r0,r0,r1
;;;174 /* Store the new value */
;;;175 PWR->CR = tmpreg;
00000e 6010 STR r0,[r2,#0]
;;;176 }
000010 4770 BX lr
;;;177
ENDP

000012 0000 DCW 0x0000

|L8.20|
DCD 0x40007000

AREA ||i.PWR_WakeUpPinCmd||, CODE, READONLY, ALIGN=2

PWR_WakeUpPinCmd PROC
;;;183 */
;;;184 void PWR_WakeUpPinCmd(FunctionalState NewState)
000000 4901 LDR r1,|L9.8|
;;;185 {
;;;186 /* Check the parameters */
;;;187 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;188 *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
000002 6008 STR r0,[r1,#0]
;;;189 }
000004 4770 BX lr
;;;190
ENDP

000006 0000 DCW 0x0000

|L9.8|
DCD 0x420e00a0

;*** Start embedded assembler ***

#line 1 "..\\..\\Libraries\\STM32F10x_StdPeriph_Driver\\src\\stm32f10x_pwr.c"
AREA ||.rev16_text||, CODE, READONLY
THUMB
EXPORT |__asm___15_stm32f10x_pwr_c_0c2a8b75____REV16|
#line 114 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h"
|__asm___15_stm32f10x_pwr_c_0c2a8b75____REV16| PROC
#line 115

rev16 r0, r0
bx lr
ENDP
AREA ||.revsh_text||, CODE, READONLY
THUMB
EXPORT |__asm___15_stm32f10x_pwr_c_0c2a8b75____REVSH|
#line 128
|__asm___15_stm32f10x_pwr_c_0c2a8b75____REVSH| PROC
#line 129

revsh r0, r0
bx lr
ENDP

;*** End embedded assembler ***