Int. J. Electron. Commun.

(AEÜ) 117 (2020) 153120

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International Journal of Electronics and

Communications (AEÜ)
journal homepage: www.elsevier.com/locate/aeue

Regular paper

Ultra low-power electronically tunable current-mode instrumentation

amplifier for biomedical applications
Costas Psychalinos a,⇑, Shahram Minaei b, Leila Safari c
a
Department of Physics, Electronics Laboratory, University of Patras, Patras GR-26504, Greece
b
Department of Electronics and Communications Engineering, Dogus University, Kadikoy, 34722 Istanbul, Turkey
c
Department of Industrial and Information Engineering and Economics, University of L’Aquila, L’Aquila, Italy

a r t i c l e i n f o a b s t r a c t

Article history: In this paper, a new current-mode instrumentation amplifier with electronic tuning and low-voltage
Received 4 January 2020 operation capabilities is presented. Simplicity is other important feature so that the whole circuit is com-
Accepted 7 February 2020 posed of only 20 transistors. All the above have been achieved using MOS transistors biased in the sub-
threshold region. The required current-controlled gain stage has been implemented using an appropriate
translinear loop which is fed by the output of a current subtraction stage, realized through the employ-
Keywords: ment of flipped voltage follower based current-mirrors. The performance of the presented amplifier is
Low-voltage circuits
evaluated through simulation results, using the Cadence suite and MOS transistors models provided by
Low-power circuits
Biomedical circuits
the Austria Mikro Systeme 0:35 lm CMOS process. The differential gain was 20—40 dB, the Common-
Translinear circuits Mode Rejection Ratio (CMRR) was 44:4—48:9 dB, achieved at power dissipation 72:75—386:1 nW. The
Current-mode circuits bandwidth was 7 kHz and the Total Harmonic Distortion (THD) was 2% for an input signal with ampli-
Electronic tuning tude equal to 550 pA. As an application example, the proposed current-mode instrumentation amplifier
Instrumentation amplifiers has been employed for removing the noise component in electrocardiogram signals.
Ó 2020 Elsevier GmbH. All rights reserved.

1. Introduction conveyor (ECCII). By setting an appropriate value of control volt-

Soon after the introduction of current-mode signal processing
[1], current-mode instrumentation amplifiers (CMIAs) become
attractive alternatives of the voltage-mode instrumentation ampli-
fiers (VMIAs). In comparison to conventional op-amp based VMIAs
[2], CMIAs offer many advantages: simple structures, alleviating
the need for matched resistors, low supply voltage requirement
etc. [3–15].
CMIAs with electronic tuning capability are very attractive
because of the absence of external variable resistors for achieving
the desired value of differential mode gain, a fact making them
suitable for implementation in fully integrated form. Literature
survey shows that two main methods have been employed to
achieve electronic tunablity in CMIAs. The electronically tunable
CMIAs reported in [5,8,11–13] are based on current-mode active
building blocks where some of their features such as current gain,
input impedance etc. are controllable by means of a bias current or
voltage. For example, in [8] an electronically tunable CMIA is pre-
sented based on electronically variable second generation current
⇑ Corresponding author.
E-mail address: cpsychal@upatras.gr (C. Psychalinos).
age, the current gain of ECCII is varied in order to change the gain
of CMIA. Similarly in [5], electronically variable current mirror is
used to change the current gain. The main drawback of this
method is that increasing bias current results in large power con-
sumption. The second method used in [6,7,9,14] is based on elec-
tronically variable resistors. In this method, large gain is achieved
by increasing the value of resistor by means of bias voltage. All the
aforementioned topologies have been implemented using MOS
transistors biased in the strong inversion region leading to the
requirements of increased minimum supply voltage and/or dc
power dissipation.
Choosing the operation of MOS transistors in the sub-threshold
region it is an attractive solution, because such solution offers
higher energy efficiency with regards to the operation in the other
regions, due to the highest bandwidth per ampere and the lower
power supply voltage requirement [16]. In the operation of an
MOS transistor in the sub-threshold region, the gate-source voltage
(V GS Þ is smaller than the threshold voltage (V th ), i.e. V GS < V th , while
in order the transistor to behave as a voltage controlled current
source (saturation region) the drain-source voltage (V DS ) must ful-
fill the condition V DS  4V T , where V T is the thermal voltage with a
value about 26mV at room temperature. Under these conditions,
the drain current of a MOS transistor is given by (1)

https://doi.org/10.1016/j.aeue.2020.153120
1434-8411/Ó 2020 Elsevier GmbH. All rights reserved.
2 C. Psychalinos et al. / Int. J. Electron. Commun. (AEÜ) 117 (2020) 153120
Fig. 1. Functional block diagram of the proposed CMIA amplifier.
Fig. 2. Implementation of the input stage using FVF based current-mirrors.
Fig. 3. Implementation of the gain stage through the utilization of a translinear loop.
Fig. 4. Full circuitry of the proposed CMIA.
  V V
W GS th
iD ¼ ID0   e nV T ; ð1Þ
L
with W and L being the channel width and length, respectively, n
being the sub-threshold slope factor (1 < n < 2), and ID0 being a
process parameter given by the formula: ID0 ¼ 2  n  l  C ox  V 2T ,
where l is the mobility of the carrier and C ox is the gate-oxide
capacitance per unit area [17–19]. The effective gate-source voltage
V GS;eff ¼ V GS  V th is negative in the case of the sub-threshold oper-
ation, allowing the operation in a low-voltage environment. The
transconductance in the sub-threshold region, for a dc bias current
IDQ , is given by (2)
IDQ
gm ¼ ; ð2Þ
nV T
and it linearly depends on the bias current, instead of the square
root dependency that holds in the case of the strong inversion oper-
ation. That allows smaller dc bias currents with those required for
achieving the same value of transconductance with MOS biased in
the strong inversion region. In order to achieve a large g m , the bias
current must be increased but this could push the transistor into
the strong inversion region, loosing the benefit of the low-voltage
operation. In order to avoid this situation, the aspect ratio of the
MOS transistor (W=L) must be appropriately large, leading into
increased parasitic capacitances and, consequently, into reduced
bandwidth of operation.
 C. Psychalinos et al. / Int. J. Electron. Commun. (AEÜ) 117 (2020) 153120 3

Table 1 Table 2
Values of aspect ratio of the transistors in Fig. 4. Values of CMRR and dc power dissipation of the CMIA at various levels of gain.

Transistors Aspect ratio Control current (IC ) CMRR Power dissipation

Mn1–Mn4 10 lm=2 lm 5 nA 48:9 dB 72:75 nW
Mn5–Mn8 1 lm=1 lm 10 nA 47:4 dB 104:25 nW
Mpc1–Mpc2 1 lm=2 lm 20 nA 46 dB 174:6 nW
Mp1–Mp4 60 lm=2 lm 30 nA 45:4 dB 241:05 nW
40 nA 45:5 dB 315 nW
50 nA 44:4 dB 386:1 nW

Fig. 5. Frequency responses of the proposed CMIA (a) differential gain, and (b) common-mode gain.
4 C. Psychalinos et al. / Int. J. Electron. Commun. (AEÜ) 117 (2020) 153120
The proposed CMIA is constructed from MOS transistors biased
in the sub-threshold region. Due to its simple circuitry, it offers the
attractive benefit of reduced dc power dissipation, with regards to
the structures where MOS transistors biased in the strong inver-
sion region have been utilized. Another attractive characteristic
of the proposed CMIA is the offered electronic tuning of the gain
and this is originated from the employment of a translinear loop
formed by appropriately configured transistors [20,21]. It must
be mentioned at this point that IA structures, where MOS transis-
tors in the sub-threshold region are utilized, are proposed in
[22,23], but they are actually voltage or trans-resistance-mode cir-
cuits. According to the best knowledge of authors, there is not any
pure CMIA structure (i.e. with both input and output signal being
currents), already published in the literature, where MOS transis-
tors biased in the sub-threshold region have been utilized.
The organization of this paper is as follows: In Section 2, the
functional block diagram as well as the intermediate stages of
the proposed CMIA are presented, while the whole circuitry is
demonstrated in Section 3. The behavior of the proposed CMIA is
evaluated in Section 4 along with a biomedical application exam-
ple. The simulations have been performed using MOS transistor
models provided by the Austria Mikro Systeme 0:35 lm CMOS pro-
cess and the Cadence suite.
2. Functional block diagram of the proposed CMIA
The functional block diagram of the proposed CMIA is depicted
in Fig. 1. According to this, the structure is composed of a current-
mode stage which produces difference between the input currents.
Therefore, common-mode currents are rejected at input stage
while differential-mode ones are summed. The output of input
stage is amplified by a electronically controlled gain stage, imple-
mented using the translinear principle, in order to produce the out-
put of the whole amplifier.
The realization of the input stage is demonstrated in Fig. 2,
where flipped voltage follower (FVF) based low-voltage
Fig. 6. Plot of the THD vs the amplitude of the input signal..
current-mirrors [24] are used. The simple current-mirror, con-
structed from transistors Mpc1-Mpc2, is used for subtracting the
two input currents (iINþ and iIN ) and, therefore, the unwanted
common-mode input currents will be eliminated in the output sig-
nal because it is given by the expression: iOUT ¼ iINþ  iIN .
The realization of the gain stage is given in Fig. 3. Considering
that the MOS transistors are biased in the sub-threshold region
and assuming that Mp1-Mp4 are matched, then by applying the
translinear principle [20,21] it is derived that
tGS1 þ tGS2 ¼ tGS3 þ tGS4 : ð3Þ
Using (1), the expression in (3) can be re-written as
ðiIN þ IB Þ  IC ¼ IB  ðiOUT þ IC Þ; ð4Þ
Performing a simple algebra, (4) takes the form of (5)
 
IC
iOUT ¼  iIN : ð5Þ
IB
Thus, the output current is a scaled version of the input current and
the scaling factor is determined by the ratio of the dc bias currents
IC and IB . It must be mentioned at this point that pMOS transistors
are used for implementing the translinear loop in order to avoid the
body effect (in a twin well process), which decreases the perfor-
mance of the amplifier in terms of the accuracy.
The minimum supply voltage requirement of the topology in
Fig. 2 is tGS þ 2tDS;sat , where tGS is the gate-source voltage of
Mpc1-Mpc2 and tDS;sat ¼ 4V T ’ 100mV is the drain-source satura-
tion voltage of the transistors Mn2 and Mn6. Accordingly, the min-
imum supply voltage requirement of the topology in Fig. 3 is
2tGS þ tDS;sat . In a typical 0:35 lm technology, the values of
threshold voltage of nMOS and pMOS transistors are 500 mV and
600 mV, respectively, while the nominal value of the power sup-
ply voltage is 3.3 V. Assuming a reasonable value of 250 mV of the
gate-source voltage, the minimum supply voltage of the CMIA will
be about 600 mV, offering the advantage of low-voltage operation.
 C. Psychalinos et al. / Int. J. Electron. Commun. (AEÜ) 117 (2020) 153120 5

Fig. 7. Monte-Carlo analysis results (N = 200 runs) about the (a) differential, and (b) common-mode gain.
6 C. Psychalinos et al. / Int. J. Electron. Commun. (AEÜ) 117 (2020) 153120

Table 3
Comparison results of the performance of the proposed CMIA.

Ref. Region of operation No. of elements CMRRðdBÞ Ad ðdBÞ SupplyðVÞ Power dissipation
MOS resistors
[6] strong 52 0 64.5 26–48 1.5 4.93 mW
[12]a strong 34 0 52.8–64.7 25–27.6 0.9 1.15–1.30 mW
[12]b strong 34 0 52.8–64.7 31–33.6 0.9V 1.15–1.30 mW
[10] strong 30 1 51.2 4.7–18 0.9 864lW
[9] strong 29 2 36–54.2 6.9–25 0.9 760lW
[5] strong 20 0 91 9.5–46 0.8 486lW
[3] strong 39 0 147 50–200 2.5 N/A
[4] strong 34 0 94 13–17 1.5 4.43 mW
[8] strong 42 0 42 0–27 0.9 0.97–1.73 mW
New sub-threshold 20 0 44.4–48.9 20–40 0.75 72.75–386.1 nW

Fig. 8. Noiseless ECG signals applied at the (a) non-inverting and (b) inverting inputs of the CMIA.

3. Proposed CMIA Owing to the class-A operation of the CMIA, the amplitude of
the input currents must be smaller than the dc bias curreht
The topology of the proposed CMIA is depicted in Fig. 4. Ideally, IA , while the output current must be smaller than the dc bias
the output current is given by (6) curret IC .
  Considering that the (non-ideal) gain of the current-mirror
IC formed by Mn1-Mn2 and Mn5-Mn6 is a1 , while the gains of the
iOUT ¼  ðiINþ  iIN Þ: ð6Þ
IB current-mirrors formed by Mpc1-Mpc2 and Mn3-Mn4/Mn7-Mn8
 C. Psychalinos et al. / Int. J. Electron. Commun. (AEÜ) 117 (2020) 153120 7

Fig. 9. Noisy ECG signals (SNR ¼ 6 dB) applied at the (a) non-inverting and (b) inverting inputs of the CMIA.

 
are a2 and a3 , respectively, then the current iG which feds the elec- iOUT IC
Ac  ¼  ða3  a1 a2 Þ: ð10Þ
tronically controlled gain stage can be expressed as iCM IB
iG ¼ a3 iINþ  a1 a2 iIN : ð7Þ Using (9) and (10) the derived expression of the Common-Mode
Substituting (7) into (5) the resulted of the output current of the Rejection Ratio (CMRR) is
CMIA is
Ad 1 a3 þ a1 a2
  CMRR  j j¼ j j: ð11Þ
IC Ac 2 a3  a1 a2
iOUT ¼  ða3 iINþ  a1 a2 iIN Þ: ð8Þ
IB
Inspecting (9) and (10) it is derived that both Ad and Ac are depen-
In the case of the differential-mode of operation, i.e. iINþ ¼ iIN ¼ dent on the values of IB and IC , while CMMR is independent from the
iDM =2, the current gain (Ad ), derived from (8) will be values of the dc bias currents. According to (11), only the perfor-
  
iOUT IC a3 þ a1 a2  mance of the employed current-mirrors is critical for achieving a
Ad  ¼  ; ð9Þ high value of CMRR. It must be also mentioned, that the non-
iDM IB 2
idealities of the current controlled gain stage do not affect the value
while in the case of common mode operation, i.e. iINþ ¼ iIN ¼ iCM , of CMRR because they affect in the same way the values of both dif-
the corresponding gain (Ac ) will be ferential and common-mode gains.
8 C. Psychalinos et al. / Int. J. Electron. Commun. (AEÜ) 117 (2020) 153120

Fig. 10. Noisy ECG signals(SNR ¼ 0 dB) applied at the (a) non-inverting and (b) inverting inputs of the CMIA..

Also, the input resistance of the IA, considering that the current
source is formed by a simple current-mirror is: Rin ¼ 2=g m1 g m5 ro5 ,
with g m1 ; g m5 being the transconductances of Mn1 and Mn5,
respectively, and r o5 being the output resistance of Mn5 [24]. The
output resistance of the IA is given by the formula:
Rout ¼ r o4 ==r oc , where r o4 is the output resistance of Mp5 and roc is
the output resistance of the current-mirror employed for imple-
menting the current source IC .
4. Simulation results
4.1. Performance evaluation of the CMIA
The performance of the proposed circuit is evaluated through
the Cadence software and the Design Kit provided by the Austria
Mikro Systeme (AMS) 0:35 lm CMOS technology. The power sup-
ply voltages are V DD ¼ V SS ¼ 0:75 V and V DC ¼ 0 V. The dc bias
currents are set to be IA ¼ 5 nA, and IB ¼ 0:5 nA, while the dc bias
current IC is variable. The aspect ratio of the transistors in Fig. 4
are summarized in Table 1. The distribution of the dc bias currents
(IA ; IB ; IC ) is performed using current mirrors formed by nMOS
transistors with aspect ratio 5 lm=2 lm and pMOS transistors
with aspect ratio 50 lm=2 lm. The values of aspect ratios of the
transistors have been appropriately selected in order to achieve
the targeted sub-threshold operation and, also, to improve the per-
formance of the structure in terms of the effect of the finite output
resistance as well as for matching purposes.The estimated layout
area of the CMIA is about 100 lm  75 lm.
Considering differential input signals, the derived frequency
domain responses of the gain (Ad ), for values of the control
 C. Psychalinos et al. / Int. J. Electron. Commun. (AEÜ) 117 (2020) 153120
Fig. 11. Output waveforms in the cases of noiseless (Fig. 8) and and noisy (Figs. 9 and 10) ECG input signals.
current IC given by the set f5 nA; 10 nA; 20 nA; 30 nA; 40 nA; 50 nAg,
are demonstrated in the plots of Fig. 5a. The measured values
of the differential gain were f9:9; 19:8; 39:8; 59:3; 79:5; 99:7g,
with the corresponding theoretically predicted values being
f10; 20; 40; 60; 80; 100g. The bandwidth of operation under these
conditions was about 7 kHz. The common-mode frequency
responses are depicted in Fig.5b, where the values of the
common-mode gain were f0:036; 0:084; 0:2; 0:32; 0:42; 0:6g. The
calculated values of the CMRR as well asthe values of the dc power
dissipation are summarized in Table 2.
The linear performance of the CMIA is evaluated in the case that
IC ¼ 10 nA (i..e differential gain equal to 20) by applying a differen-
tial input signal of frequency 1 Hz and variable amplitude. The
Total Harmonic Distortion (THD) plot, derived using the Periodic
Steady State (PSS) analysis offered by the Analog Design Environ-
ment of the Cadence suite, is demonstrated in Fig. 6. According
to this plot, the level of the THD is equal to 2% for an input signal
with amplitude equal to 550pA.
The rms value of the input referred noise, integrated in the
range 0.1 Hz–7 kHz, was 11.2 pA.The Dynamic Range (DR) is deter-
mined by the following expression
 
iin;rms
DR  20  log ; ð12Þ
inoise;rms
where iin;rms is the rms value of the input signal for a specific THD
level and inoise;rms is the rms value of the input referred noise, inte-
grated within the bandwidth of interest. Using (12), the calculated
value of the DR is 30.8 dB. Also, the simulated value of the Power
Supply Rejection Ratio (PSRR) of the amplifier, derived through
the transfer function (XF) analysis of the Analog Design Environ-
ment, was 146 dB.
The sensitivity of the proposed CMIA, in terms of process param-
eters variations and MOS transistors mismatching, is evaluated
using the Monte-Carlo analysis tool (N = 200 runs) offered by the
Analog Design Environment. The obtained statistical plot about the
differential and common-mode gain are provided in Fig. 7. The sim-
ulated values of the standard deviation were 0:02 dB and 2:97 dB,
with the mean values being 25:77 dB and 22:04 dB, respectively.
9
The performance of the proposed CMIA is compared with those
of the corresponding circuits already published in the literature,
and the derived results are summarized in Table 3. It must be men-
tioned at this point that information about the DR, the input
referred noise, and PSRR, is not provided for the already published
circuits. According to the provided results, the proposed CMIA is
the first one in the literature which is implemented using MOS
transistors biased in the sub-threshold region and, consequently,
it offers minimum power dissipation with regards to those already
published, keeping also the number of the required MOS transis-
tors in low level. Therefore, this stage would be suitable for imple-
menting implantable biomedical signal processing devices and this
will be demonstrated in the next sub-section through an appropri-
ate design example.
4.2. Biomedical application example
The time-domain performance of the proposed CMIA will be
evaluated by considering that the clean electrocardiogram (ECG)
signals [25], depicted in Fig. 8, will be initially applied at the inputs
of the amplifier.
These signals will become noisy, with Signal-to-Noise Ratio
(SNR) values equal to 6 dB and 0 dB. This has been performed
through the utilization of an appropriate routine in MATLAB, where
white Gaussian noise has been added in both signals of Fig. 8.The
resulted noisy ECGs are depicted in Figs. 9 and 10, respectively.
The obtained outputs (for IC ¼ 10 nA), are demonstrated in
Fig. 11, where it is evident the efficiency of the proposed CMIA
for handling noisy biomedical signals.
In addition, low frequency (50 Hz) noise emulated as sinusoidal
with amplitude values 50 pA; 75 pA; 100 pA has been applied at the
inputs of the proposed CMIA. This noise could be the noise created
from the power line inference. For demonstration purposes, the
signals that are applied at the non-inverting input of the CMIA
are depicted in Fig. 12. The derived output waveforms are provided
in Fig. 13, where the capability of the proposed CMIA for removing
the artifacts of the ECG which are originated from the power line
interference is verified.
10 C. Psychalinos et al. / Int. J. Electron. Commun. (AEÜ) 117 (2020) 153120

Fig. 12. ECG signals applied at the non-inverting input of the CMIA considering noise with 50 Hz frequency and amplitude (a) 50 pA, (b) 75 pA, and (c) 100 pA.
 C. Psychalinos et al. / Int. J. Electron. Commun. (AEÜ) 117 (2020) 153120
Fig. 13. Output waveforms in the cases of noiseless (Fig. 8) and noisy (Fig. 12) ECG input signals.
5. Conclusion
The proposed CMIA is designed and simulated in 0:35 lm
CMOS technology usinga supply voltage of 0:75 V. The achieved
common mode rejection ratio (CMRR) is about 45 dB while the
differential mode gain is controllable up to 40 dB by varying bias
current. The maximum value of the power consumption is
386 nW and the total harmonic distortion (THD) remains below
to 2% for a maximum amplitude of 550 pA. Therms value of the
input referred noise, integrated in the range 0.1 Hz–7 kHz, was
11.2 pA. The dynamic range of the proposed CMIA was 30.8 dB,
while the PSRR was 146 dB. Monte-Carlo analysis is also provided
which proves that the amplifier has reasonable sensitivity charac-
teristics. The efficiency of the proposed CMIA for handling noisy
biomedical signals has been verified through its stimulation by
noisy ECGs, where the derived output signal were noise free.
Therefore, it can be considered as an attractive candidate for
implementing high performance biomedical signal processing
systems [26].
Declaration of Competing Interest
The authors declare that they have no known competing finan-
cial interests or personal relationships that could have appeared to
influence the work reported in this paper.
References
[1] Wilson B, Lidgey F, Toumazou C. Current mode signal processing circuits. In:
IEEE International Symposium on Circuits and Systems (ISCAS). IEEE; 1988. p.
2665–8.
[2] Hsu Y-P, Liu Z, Hella MM. A 1.8lW -65 dB THD ECG acquisition front-end IC
using a bandpass instrumentation amplifier with class-AB output
configuration. IEEE Trans Circuits Syst II Express Briefs 2018;65(12):
1859–63.
[3] Maheshwari S. High CMRR wide bandwidth instrumentation amplifier using
Current Controlled Conveyors. Int J Electron 2003;89(12):889–96.
[4] Chanapromma C, Tanaphatsiri C, Siripruchyanun M. An electronically
controllable instrumentation amplifier based on CCCCTAs. In: 2008
International Symposium on Intelligent Signal Processing and
Communications Systems. IEEE; 2008. p. 1–4.
11
[5] Safari L, Minaei S. A novel resistor-free electronically adjustable current-
mode instrumentation amplifier. Circuits Syst Signal Process 2013;32
(3):1025–38.
[6] Pandey R, Pandey N, Paul SK. Electronically tunable transimpedance
instrumentation amplifier based on OTRA. J Eng 2013;2013:1–5. https://doi.
org/10.1155/2013/648540.
[7] Safari L, Yuce E, Minaei S. A new transresistance-mode instrumentation
amplifier with low number of MOS transistors and electronic tuning
opportunity. J Circuits Syst Comput 2016;25(04):1650022.
[8] Safari L, Minaei S. ECCII-based electronically controllable current-mode
instrumentation amplifier with high frequency performance. In: 2017
European Conference on Circuit Theory and Design (ECCTD). New: IEEE;
2017. p. 1–4.
[9] Safari L, Minaei S. A novel COA-based electronically adjustable current-mode
instrumentation amplifier topology. AEU-Int J Electron Commun
2017;82:285–93.
[10] Safari L, Minaei S, Ferri G, Stornelli V. Analysis and design of a new COA-based
current-mode instrumentation amplifier with robust performance against
mismatches. AEU-Int J Electron Commun 2018;89:105–9.
[11] Agrawal D, Maheshwari S. Cascadable current-mode instrumentation
amplifier. AEUE-Int J Electron Commun 2018;94:91–101.
[12] Chaturvedi B, Kumar A. Electronically tunable current-mode instrumentation
amplifier with high CMRR and wide bandwidth. AEU-Int J Electron Commun
2018;92:116–23.
[13] Dikbasß MC, Ayten UE. Current and transimpedance mode instrumentation
amplifier using a single new active component named CDTRA. AEU-Int J
Electron Commun 2018;91:24–36.
[14] Oruganti S, Pandey N, Pandey R. Electronically tunable high gain current-
mode instrumentation amplifier. AEU-Int J Electron Commun 2018;95:
16–23.
[15] Safari L, Ferri G, Minaei S, Stornelli V. Current-mode instrumentation
amplifiers. Springer; 2019.
[16] Sharpeshkar R. Ultra low power bioelectronics: fundamentals, biomedical
applications, and bio-inspired system. Cambridge: Cambridge University
Press; 2010.
[17] Vittoz E, Fellrath J. CMOS analog integrated circuits based on weak inversion
operation. IEEE J Solid-State Circuits 1977;12(3):224–31.
[18] Enz CC, Krummenacher F, Vittoz EA. An analytical MOS transistor
model valid in all regions of operation and dedicated to low-voltage
and low-current applications. Analog Integr Circ Sig Process 1995;8
(1):83–114.
[19] Tsividis Y, McAndrew C. Operation and modeling of the MOS transistor, Vol.
2. Oxford: Oxford University Press; 1999.
[20] Andreou AG, Boahen KA. Translinear circuits in subthreshold MOS. Analog
Integr Circuits Sig Process 1996;9(2):141–66.
[21] Serrano-Gotarredona T, Linares-Barranco B, Andreou AG. A general translinear
principle for subthreshold MOS transistors. IEEE Trans Circuits Syst I:
Fundamental Theory Appl 1999;46(5):607–16.
[22] Eldeeb MA, Ghallab YH, Ismail Y, El-Ghitani H. Design of low power CMOS
subthreshold current mode instrumentation amplifier based on CCII. In: 2016
IEEE 59th international Midwest Symposium on Circuits and Systems
(MWSCAS). IEEE; 2016. p. 1–4.
12 C. Psychalinos et al. / Int. J. Electron. Commun. (AEÜ) 117 (2020) 153120

[23] Eldeeb MA, Ghallab YH, Ismail Y, El-Ghitani H. A 0.4-V miniature CMOS current
mode instrumentation amplifier. IEEE Trans Circuits Syst II Express Briefs
2017;65(3):261–5.
[24] Carvajal RG, Ramírez-Angulo J, López-Martín AJ, Torralba A, Galán JAG,
Carlosena A, Chavero FM. The flipped voltage follower: a useful cell for low-
voltage low-power circuit design. IEEE Trans Circuits Syst I Regul Pap 2005;52
(7):1276–91.
[25] Goldberger AL, Amaral LA, Glass L, Hausdorff JM, Ivanov PC, Mark RG, Mietus
JE, Moody GB, Peng C-K, Stanley HE. Physiobank, physiotoolkit, and physionet:
components of a new research resource for complex physiologic signals.
Circulation 2000;101(23):e215–20.
[26] Stornelli V, Ferri G. A single current conveyor-based low voltage low power
bootstrap circuit for electrocardiography and electroencephalography
acquisition systems. Analog Integr Circuits Sig Process 2014;79(1):171–5.