Reg. No.

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TERM END EXAMINATIONS (TEE) – May 2021

Programme : B.Tech Semester : Winter 2020-2021
Course Name : Digital Logic Design Code : ECE2002
Faculty Name : Dr. Manoj Prabhakaran.K Slot/Class No. : C21+C22+C23/0084
Time : 1½ hours Max. Marks : 50

Answer ALL the Questions

Q. No. Question Description Marks

PART - A ( 30 Marks)
1 (a) Determine the following Number Conversion System are: 10
a. The binary value is (10011011)2, and calculate the Binary to Decimal, Octal
and Hex-decimal.
b. The Decimal value is (53)10, and calculate the Decimal to Binary, Octal and
Hex-decimal
c. The Octal value is (752)10, and calculate the Octal to Decimal, Binary and
Hex-decimal
d. The Hexa-decimal value is (A3F)16, and calculate the Hexa-decimal to Binary,
Octal and Decimal
OR
(b) Design the logical circuit diagram of 16:1 MUX and 1:16 DEMUX, also determine 10
the Boolean expression of it.
2 (a) Explain the types of Parity checker and determine the Boolean expression of it, which 10
has the binary range value from 0 to 15.
OR
(b) Describe the SR-Flip Flop with logic diagram, characteristic table, excitation table 10
and state diagram

3 (a) Design any two methods of the 3-bit Synchronous Counters with logic diagram and 10
state diagram
OR
(b) Design the sequence detector 110 or 101 using Melay code 10

PART - B (20 Marks)

4 Simplify the logic function F(A, B, C, D) = π(3, 5, 6, 11, 13, 14, 15) + d(4, 9, 10) 10
using K-Map in SOP and POS form
5 Write the Verilog HDL code for Decoder and Encoder 10

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