CMOS low dropout regulator with dynamic Adc ð1 þ sCout Resr Þð1 þ sðgmf C1 =gm1 gm2 ÞÞ

Ll ðsÞ ’ ð1Þ
zero compensation ð1 þ ðs=P1 l ÞÞð1 þ sððCa R1 gm2 R2 gmp Resr
þ C2 R2 þ C1 R1 Þ=ðCa =Cout ÞðR1 gm2 R2 gmp þ 1ÞÞ
C.-L. Chen, W.-J. Huang and S.-I. Liu þ s2 ððC1 R1 C2 R2 Þ=ðCa =Cout ÞR1 gm2 R2 gmp þ 1ÞÞ

The output capacitor and its equivalent series resistance (ESR) often where Adc ¼ (RF2=(RF1 þ RF2)) gm1R1gm2R2gmpRout is the DC loop gain
limit the stability of a conventional low dropout regulator (LDR). A and p1 l ¼ 1=(CaR1gm2R2gmpRout þ CoutRout) is the dominant pole of the
CMOS LDR with dynamic zero compensation is presented to tolerate LDR in the light load.
the wide range of the output capacitor and the ESR. The stability
The unity-gain frequency is approximated as
constraints for the output capacitor with the ESR are derived. The
measured LDR is stable for the output capacitor 2nF–47uF with ESR
RF2 g 1
of 0.1–50 O. The maximum quiescent current of this LDR with a UGF1 ¼  m1  ð2Þ
bandgap reference is 43.2uA and its maximum output current is RF1 þ RF2 Ca 1 þ ðCout =Ca R1 gm2 R2 gmp Þ
150 mA for the output voltage of 1.8V.
For the light load, two zeros, 1=ResrCout and gm1gm2=gmfC1, in (1) are
much higher than the unity-gain frequency of (2) and their effects are
neglected. From the second-order polynomial in the denominator of (1),
the natural frequency and the damping factor are calculated as
Introduction: Low dropout regulators (LDRs) [1–4] are widely used sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
in power management integrated circuits and systems. A conventional Ca gm2 gmp þ ðCout =R1 R2 Þ
LDR needs a large output capacitor to reduce output ripples. However, on ¼ and
Cout C1 C2
the output capacitor and its equivalent series resistance (ESR) often ð3Þ
affect the stability of the LDR. In [4], it is indicated that the allowable 1 Ca gm2 gmp Resr þ ðC2 =R1 Þ þ ðC1 =R2 Þ
z ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
range of ESR is limited, such as 0.2–9 O, for a typical LDR. To extend 2 C1 C2 ððCa =Cout Þgm2 Gmp þ ð1=R1 R2 ÞÞ
the allowable range of the output capacitor and its ESR, an LDR with
dynamic zero compensation is presented. To guarantee the stability in the light load, the non-dominant poles
should be higher than the unity-gain frequency, and the damping factor
should be designed appropriately to ensure that the ESR and output
Circuit description: The proposed LDR with dynamic zero compen- capacitor do not affect the phase margin. From (2) and (3), the
sation is shown in Fig. 1 (the bandgap voltage reference is not shown). following constraint should be satisfied.
It is composed of three gain stages, a current follower [3, 5, 6] with a
Miller compensation capacitor Ca, and a feedback resistor network. 1
Cout > Ca gm2 gmp R1 R2
The dynamic zero compensation is realised by a PMOS transistor, Mz, 2
2 ffi3
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
and a capacitor, Cz. It introduces a dynamic low-frequency zero,  2  2 ð4Þ
41 þ 1 þ 4 m1 g R
which is dependent on the output current, Iout. As the output current is F2
R 1 R 2 C1 C2 5
zero, both the power PMOS transistor, Mp, and Mz are turned off, and Ca RF1 þ RF2
this zero is not active. As the output current is increased, Mp and Mz
are turned on. Then, the low-frequency zero is realised to enable the
Equation (4) indicates that there is a lower bound of the output capacitor
pole-zero elimination. It extends the useful range of the output
in this proposed LDR. In this case, the output capacitor is designed to
capacitor and the ESR for the proposed LDR.
be around several nF.
When the LDR is in the heavy load (i.e. Iout is large), the loop
transfer function is

Adc ð1 þ sCz Rz Þð1 þ sCout Resr Þ

ð1 þ sðCa =gma ÞÞð1 þ sðgmf C1 =gm1 gm2 ÞÞ
Lh ðsÞ ’ ð5Þ
ð1 þ ðs=P1 h ÞÞð1 þ ðs=ðgma gm2 gmp Resr ðR1 ==Rz Þ=C2 Þ
þðgma =Ca ÞÞð1 þ sC1 þ Rz Þ½1 þ sðCz Rz þ Cout Resr Þ
þ s2 ðCz Rz Cout Resr þ ððCz Rz
þ Cz R1 ÞC2 Cout =Ca R1 gm2 gmp ÞÞ

Five poles and four zeros are given in (5). The dominant pole is
p1 h ¼ 1=CaR1gm2 R2gmpRout and the unity-gain frequency in the heavy
load is UGFh ¼ RF2gml=(RF1 þ RF2)Ca. For the heavy load, two zeros,
gma=Ca and gm1gm2=gmfC1, and two non-dominant poles, ((gmagm2
gmpRear (Rl==Rz)=C2) þ (gma=Ca) and 1=RzC1, in (5) are much higher
than the unity-gain frequency of UGF h and their effects are neglected.
Fig. 1 Proposed LDR Assume Resr is large and the following equation is satisfied:

C2
To understand the design issues, the following analysis is derived. Resr
ð6Þ
gm1, gm2 and gmp, are the transconductances of the first, second and the Ca ðR1 ==Rz Þgm2 gmp
output stage, respectively. R1, R2 and Rp are output resistances of the
first, second and the output stage, respectively. C1 and C2 are output According to (6), the second-order polynomial in the denominator of
parasitic capacitance of the first and second stage, respectively. gma and (5) can be decomposed as (1 þ sCzRz) (1 þ sCoutResr). Then, two
gmf are the transconductances of the PMOS transistor, Ma, and the pole-zero pairs can be eliminated. Therefore, the stability of this LDR
NMOS one, MF, respectively. Rz is the equivalent source-to-drain in the heavy load is ensured when Resr is large.
resistance of the transistor Mz. Cz and Ca are the compensation When Resr is small, one of the poles in the second-order polynomial
capacitors. Cout is the output capacitor with the associated ESR, Resr . in the denominator of (5) is shifted to a lower frequency. This pole is
Rout is the total equivalent output resistance, which is equal to RL == Rp expressed as
== (RF1 þ RF2), where RL is the load resistor, and RF1 and RF2 are the
feedback resistors. 1
Pnondom h lowESR ¼ ð7Þ
Assume Cout
(Cz, Ca, C2)
C1, gmp
(gm1, gm2, gma, gmf), and Cout Resr þ ðC2 Cout =Ca gm2 gmp ðR1 ==Rz ÞÞ
(gm1R1, gm2R2, gmp Rout)
1. Based on the above assumptions, the loop
transfer function of the proposed LDR in the light load (i.e. Iout is small) To ensure stability, this non-dominant pole must be higher than the
is given as unity-gain frequency. It results in the following constraint as

ELECTRONICS LETTERS 5th July 2007 Vol. 43 No. 14

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 RF1 þ RF2 Ca 1
Cout <  
RF2 gm1 Resr þ ðC2 =Ca gm2 gmp ðR1 ==Rz ÞÞ
Equation (8) shows the upper bound of the output capacitor. Since this
LDR only has a dominant pole within the unity-gain frequency, stability
is guaranteed in the heavy load when Resr is small. Based on (4) and (8),
the allowable range of the output capacitor and the ESR for the LDR
will be extended.
To verify the stability of the proposed LDR, Fig. 2 shows its
root-locus plot with varying output currents. When the constraints in
(4) and (8) are satisfied, the solid line shows that all the poles of the
proposed LDR lie in the left-hand plane with the output current of
Iout ¼ 0 mA–Iout ¼ 150 mA. When the constraints in (4) and (8) are not
satisfied, the dotted line shows the complex poles move into the right-
hand plane with the output current of Iout ¼ 0.3 mA–Iout ¼ 30 mA. It
results in an unstable system as the output current varied.
Fig. 2 Root-locus of proposed LDR
Arrows indicate the direction, which the output current increases
Solid line: (4) and (8) satisfied; dotted line: (4) and (8) not satisfied
Experimental results: To verify the above analysis, the proposed LDR
with a bandgap reference has been fabricated in a 0.35 um CMOS
process.
For the proposed LDR, the measured line regulations at the output
current Iout ¼ 0 and Iout ¼ 150 mA are 0.134 and 0.100%=V, respec-
tively. The measured maximum load regulation is 92.54 ppm=mA at
Vin ¼ 3.3 V. Fig. 3 shows the measured transient response of the LDR at
the supply of 3.3 V under the output current switching from 0 to 20, 50,
and 150 mA. Fig. 3a shows the result for Cout ¼ 47 mF with Resr ¼ 50 O
and Fig. 3b shows the result for Cout ¼ 2nF with Resr ¼ 0.1 O. It shows
that this LDO can recover the output voltage within 20 ms within the
error of 0.5% for switching the output current of 150 mA.
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ð8Þ
Fig. 3 Transient response of LDR for Cout ¼ 47 mF and Resr ¼ 50 O
(Fig. 3a) Cout ¼ 2nF and Resr ¼ 0.1 O (Fig. 3b) Vout: 500 mV=div., 10us=div.
Conclusions: A CMOS LDR with a dynamic zero compensation is
presented. The experimental results confirm that this LDR with
dynamic zero compensation can be stable for a wide range of the
output capacitor and the ESR.
# The Institution of Engineering and Technology 2007
13 April 2007
Electronics Letters online no: 20071063
doi: 10.1049/el:20071063
C.-L. Chen, W.-J. Huang and S.-I. Liu (Graduate Institute of Electro-
nics Engineering and Department of Electrical Engineering, National
Taiwan University, Taipei, Taiwan 10617, Republic of China)
E-mail: lsi@cc.ee.ntu.edu.tw
References
1 Leung, K.N., and Mok, P.K.T.: ‘A capacitor-free CMOS low-dropout
regulator with damping-factor-control frequency compensation’, IEEE J.
Solid-State Circuits, 2003, 38, pp. 1691–1702
2 Hazucha, P., Karnik, Y., Bloechel, B., Parsons, C., Finan, D., and
Borkar, S.: ‘An area-efficient integrated linear regulator with ultra-fast
load regulation’. Dig. Tech. Pprs, Symposium on VLSI Circuits, June
2004 pp. 218–221
3 Huang, W.J., Lu, S.H., and Liu, S.I.: ‘A CMOS low dropout linear
regulator with single Miller capacitor’, Electron. Lett., 2006, 42,
pp. 216–217
4 Bang Lee, S.: ‘Technical review of low dropout voltage regulator
operation and performance’, (Application Reports, Texas Instruments
Inc., Literature number SLVA072)
5 Lee, H., and Mok, P.K.T.: ‘Advances in active-feedback frequency
compensation with power optimization and transient improvement’,
IEEE Trans. Circuits Syst. I, 2004, 51, pp. 1690–1696
6 Ahuja, B.K.: ‘An improved frequency compensation technique for
CMOS operational amplifiers’, IEEE J. Solid-State Circuits, 1983, 18,
pp. 629–633