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    13 views23 pages

    LCExperiment6 60013190029 TarjiniMehta

    Uploaded by

    Mahek Vora

    Copyright:

    © All Rights Reserved
    Download as PDF or read online from Scribd
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    STO fe RE 60013190024 Eiomedcott Expevinnent 6 design of Adder and subtractor A) To design and smplement half and foul adder To design and implement hat and foll subtractor Eqpipmonts/ + LTSpice WII (Zeis a free open source software) SoPtwaxe, Theo ONO] noe adder The half adder civeutt has 2 inputs: A and & which add 2 input digits ond genevates a carry and a sum. Wesdieraudtiay [a | 8 [gum | @ry ololo lo lowes One i a oe eS SEIKO) \ sum eo x & B 9} 0 1 iaee| s S= AB + AB = A@B Corry: S ®lo 0) | o u C= AB FOR EDUCATIONAL USE @ || Pw adder The ful adder civcutt has 3 inputs: A, Band C which add 3 i puts and generates aA sum and corny. a series cl bo 11 Wears 20) iD \ o Ea @O) \ peer 4 VO. ‘a: BuO R a [50%], 1 veatow hizo 1 MAB a Retis hc er Pa 8 ima bo | SZ i= 1 _—$§£§|__—__ = ‘ r : + —- Was | = ee fea SBYs Coxsys =e oo os se ooo sto Orn |yO | 2} p10 Wih\ie Sees. |. 70] ‘fo fae kata ic + ABC FABC FAB C=ARB + BC FAC Be c) + A(BeC) FOREDUCATIONALUSE == @4B)C FAB Wolf Subtractor The halt cubtractor circuit has 2 ‘inputs = A and & which generates a ff foxenice and borrow output for those 2 iviputs tS Borrow | Diffuence 1 HE le olo|-b Vis 1 L 1 —— hs D=AOs 5 = = e =p,= 28 is = eo L “dl lat D= ABL AB ; [ro] =hosB a 1 nay es ; fo | Bo = AB i Le | 3 FOREDUCATIONALUSE z Te fll subtvacter has 3 “inputs = A,B and C which generates differen Jand borrow for those 3 inputs | Bou soptractor AB Cc DFP ference BevtOW fo jofo o ° (ss ae Lh \ 1 | “ Oso NO. I 1 eee ° | a Yeo Le I 0 3 : MIRON! oO ° 2 \ \ . ° oO : t Tae { a : Niippe DEO —— : @) 2 eee Go= F/e ee + ABC + ABC + ABC Bo = AB + AC+Bc Cc) + a (BOO) = A(Bac) + Bc FOR EDUCATIONAL USE BAe btn ws 5 OFA eels) oe ee | E | a 3 Ls) Z = : £1c}e}e] 4 of=|-|-Jol-|-|-]o] a of = ol A 5 z al s ee ee cat) Sia a 9 Je iz eI e lets ct Dl 0) 1 |= 15) =] oloi| 4 4} - ++ -}o Of el =} a] =| a -| 5] =| o| =| 4 45] -| 3] =| e =| =| 0 mle} of =| =| of of -|—Jolo} | -|o/o] 4— Lt Sale ©) © [Fou Adder and Fou cwwacer vsing “Mode Contol Sum /piference (Sfp) : 1 nao ee oo Of [alo al] olo Ciao a0 Ty | ° tof] 0 [0 tea s/> ABC + ARC +ABC tARe A(BOC) + A (Rc) A@® ROC Cavey/porrow (c/8s) = ue ao pawn” 9 iy . Pie: ° oO oO Ce Ye | » reo | we} © [Lt yo [ivy = 8 BC+ MACY Mags MAc +Mae Bc + C(M@®A) + B(M@Ad a = Bc +CM@A)(Brc) Wot Adder and Hat Cobbactor _usivig Mode Control ¥ 4 g pea al>= hOB Targ 7B, = Vene FOR EDUCATIONAL USE Sum / Difference (sf): Bees ip 6 | o [fteu] © TERS Ret an S/D = AR + AB - n@e Design of Adder and Subtractor Procedure: 10. 11. 12. 13. (Open New Schematic in LT Spice XVII Go to Edit and select Components For half adder and half subtractor: Select 1 EX-OR and 1 AND gate for half adder. Select 1 EX-OR, 1 NOT and 1 AND gate for half subtractor. Put them on the schematic. For full adder and full subtractor: Select 2 €X-OR, 2 OR and 2 AND gates for full adder. Select 2 EX-OR, 2 OR, 1 NOT and 2 AND gates for full subtractor. Put them on the schematic. For FA and FS using mode control and HA and HS using mode control: Select 3 EX-OR, 2 OR ‘and 2 AND gates for FA and FS using mode control. Select 2 EX-OR and 1 AND gates for HA and HS using mode control. Put them on the schematic. Click on Label Net in toolbar. For half adder and half subtractor: For half adder, write A, 8 and select input port type Place it near the inputs as per the circuit diagram. Select port type as output and write (sum), C{carry) and place it as per the circuit diagram. For half subtractor, rename the output port as Ddifference) and BO(borrow) For full adder and full subtractor: For full adder, write A, B, C and select input port type. Place it near the inputs as per the circuit diagram. Select port type as output and write Sum and Carry and place it as per the circuit diagram. For full subtractor, rename the output ports as Difference and Borrow. For FA and FS using mode control and HA and HS using mode control: For FA and FS using mode control, write M, A, 8, C. Select input port type. Place it near the inputs as per the circuit diagram. Select port type as output and write S/D and C/BO. Place it as per the circuit diagram. For HA and HS using mode control, write M, A and B. Select input port type and place it near the inputs as per the circuit diagram. Select port type as output and write S/D and C/B0 and place it as per the circuit diagram. For half adder and half subtractor: in Components, type voltage and click OK. Add 2 voltage sources to the schematic. For full adder, full subtractor, HA and HS using mode control: In Components, type voltage and click OK. Add 3 voltage sources to the schematic. For FA and FS using mode control: In Components, type voltage and click OK. Add 4 voltage sources to the schematic. Click on ground and add it on all voltage sources. Go to Label Net. Select port type as output and place them near the voltage sources as per the number of input ports in the circuit diagram. Right click on a voltage source and click on Advanced. Select Pulse and set the pulse parameters. Repeat this process for the other voltage sources. Click on Run. A new Transient window will open. Set the Stop Time as i) Sms (for half adder and half subtractor) ii) 9 ms (for full adder, full subtractor, HA and HS using mode control) ill) 17 ms (for FA and FS using mode control) and click OK. To add waveforms in waveform window, using the red probe that appears on the screen, click on the input ports and output port. Waveforms will appear in window. Right click on waveform window and select Add Plot Panes. Repeat this process till there are {as many plot panes as the total number of inputs and outputs. Drag Plot Labels to appropriate place and observe input and output waveforms. Adder and Subtractor Pulse Parameters 1. Half Adder and Half Subtractor A B Viinitial) 0 0 v{on) 5 5 T(delay) 0 oO T(rise) 0.1n 0.in T (fall) 0.in 0.in Ton) 2m im T(period) 4m 2m N cycles - - 2. Full Adder, Full Subtractor, HA and HS using mode control A/M B/A c/B V(initial) 0 0 0 V(on) 5 5 5 T(delay) 0 0 0 T(rise) Q.in O.1n O.1n Tifall) Q.in O.1n .1n T(on) 4m 2m im T(period) 8m 4m 2m N cycles. - - - 3. FA and FS using made control M A B c Viinitial) oO oO oO oO v(on) 5 5 5 5 T(delay) 0 0 0 0 T(rise) Ln 0.n .1n Q.1n T(fall) in 0.4n 0.4n Q.in T(on) 3m 4m 2m im T(period) 16m 8m 4m 2m N cycles - - - - A No ‘iB ee PULSE(0 5 0 0.1n 0.1n 2m 4m) PULSE(0 5 0 0.in 0.in im 2m) 7 \" B> wy ic .tran 5m PF Uspice XVM - Halt Ader) FB ble ew potsenags simuaton Tools Window Help BS ETF SQQQR EO SSBe se M/S Te rata C ratacaer LSM FER VOGVOOCMOMS vee ver 2 Uispice Xvil - [Full adder) - o x Bl le View Pot Setings Smuston Tools Window Helo ag Dek TF 9 RQQR RG Sse seem asso os s3 Beato < Fulda Vex ‘o.oms 0.gms ‘me 2.7ms 3.6ms. 4.3ms ‘Sams. 6.3ms. Tams 8.ims 9.0m a omer PULSE(O 5 0 0.1n 0.1n 2m 4m) PULSE(O 5 0 0.1n 0.1n 1m 2m) -tran 5m PF Lispice xvi - Halt Subtractor} - @ IB fae View Pot Senge Simuston Took Window Help BSE TF 6 AQQRQ SG BSE sBRM OO LLP s +3 FOVO OME A Be ratsasau Ha nace tre Cams Toms Tom Zam Tame Sm 3am some tans Sons 2B Uspice XVI\- (Full subtractor.ase] a fit Herchy ow Simlte Tools Wadow Heb SUT FO AIQRE SERA SS CEMS43 e0G00 Ane ibactr Furs PULSE(0 5 0 0.1n 0.1n 4m 8m) PULSE(0 5 0 0.1n 0.1n 2m 4m) PULSE(0 5 0 0.1n 0.1n im 2m) .tran 9m BF Lispice Xvi - [Full subtraccor) - @ x Bl ble View PotSetings Simistion Too Window te aie BSiPlT 4 9 QQQQ RG RSs) ABea OSi2L92 +3 S090 OC mime a Futeubracer < Ful sbtactor se voy @ Vieorow] 0.gms 1.8ms 2.7m 3.6ms 4.5ms Sams 6.3m 7ams 8.tms 9.0me ers it Wrachy View Simulate ‘Tools Wadow Heb Be RT 49 QQQRe BS sEea Ss Comes 3 e0G0 Anse 2t4sub made cen -< Ful 3 ub nnd PULSE(0 5 0 0.1n 0.1n 8m 16m) PULSE(O 5 0 0.in 0.1n 4m 8m) PULSE(0 5 0 0.1n 0.1n 2m 4m) PULSE(0 5 0 0.1n 0.1n im 2m) tran 17m HF Uspice XVII - [Full add sub mode control] om BE fie View PlotSetings ‘Seustion Tools Window Heo DSU TFS CQQR LT SSS BOA SH LL 2 43 SOS mia Fut 28 aib ode conte < Fen ob rex cenic ase 0 2 ve) 28 5.0) 25 6.0 2.5) p.0v 5.0V- ome ‘2ms ams ms ‘ams toms 12ms 14ms tems ee a) (4 v2 cy vi ©) PULSE(0 5 0 0.1n 0.1n 4m 8m) PULSE(O 5 0 0.1n 0.1n 2m 4m) PULSE(0 5 0 0.1n 0.1n im 2m) tran 9m Eka! Re MAD LIPS s 3 SOVOD A = ‘B 2 is/D> BN ALY +} —c/B0 PF Lispice xvi - [Halt Adder and Halt Subtractor using Mode Cont] - a BB Ble Wen Borsetims Smustion Too! Wndow Help sla BSE TF SAQQR SU SRY Bea OO sos +3 OVID mime "Hata an at Saat vig Mode Coot EX Pade nd Fsbneb hg nae Coral ; tn a : Vey a e Ta e TE Concwsion? *) Halt adder and full adder were designed and implem— ented successfully = BME svbtracior and Au subbyactor uve destqned de plemented

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