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    LC Rough Journal - Final

    Uploaded by

    Mahek Vora

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    © All Rights Reserved
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    ‘SHRI ViLEPARLE KELAYANI MANDAL'S . @ DWARKADAS J. SANGHVI COLLEGe OF ENGINEERING ‘Approved by AICTE sad Affliate t de University of Mumbai, DEPARTMENT OF BIOMEDICAL ENGINEERING Rough Journal in the subject of ~bogic-Cirenitg » 1G Name: TAL ELEC TRo Mes MSVTAL EL SAP ID: Year: __ Semester ; Academic Year : onsen remeneEtTE Prepared by: Prof. Mangal S. Dandekar _U:15. JUHU SCHEME, BHARTIVEDANTA SWAMI MARG, VILEPARLE (WEST) MUMBAI 400055 PLOT HO. in ong AhiconBaior ng Wisi we dicor org 4933500012610 700/260 1461. Fo :491 0222619 4988 Erin Qipen ogre Te: 691 02 DEPARTMENT OF BIOMEDICAL ENGINEERING . S.E. Semester IV (CBGS) > Subject: Logic Circuits ’ List of Experiments Expt. No. Title of the Experiment 1 | Study of Logic Gates 2 | Design of Basic Gates Using Universal Gates 3° | Binary to Gray and Gray to Binary code converter 4 BCD to Excess-3 Code Converter 3 | Parity Generator and Parity Checker © | Design of Adder and Subtractor 7 | Design of two bit magnitude comparator using multiplexer 8 | Design of full adder using 1:8 demultiplexer. 9 Flip-Flops - 10 | Asynchronous Counters 1 ‘Asynchronous Decade Counter 12 | Synchronous Counter PLOT NO. U-15, JUHU SCHEME, BHAKTIVEDANTA SWAMI MARG. VILEPARLE WEST. MUMBAT 400 056, “Tek: +91 0224253 500012610 7010 £2610 7461 Fax :491 0222619 4988 Ema: info@ijvoe.ongsdpeou@iicot. on, Website :wnmndcoe. or, PIN DIAGRAN © PIN piRanAn— Uy 3 2" lo 3 y 3 Ve Wob 4 8 * [bP Ty] BES Ly Ic 7hos_ Ie 743E / PPL Peo] LPL OP a : 12 ae 5 be 1234 56 ARA 8B R MB i Wt lo 4 6 4 By 0 4 & Ne Ll Gt L + rervoy \CTheo Poe pie! [PLP j an t t P2aa ser ,2S45 6 F “he AB C— hop wa 4 kh pipu lb 4 ¢ Me [ed Lt _| fe L_by| = then Tortse reo eo ou rp cy Gyo 5 +t ' ae 123456 # 12 2426 ties” * + Nec Ty Ts Tg Ty 8) Ae AConse IS M13 2 fe 4 “Two ofp's of (C , oo Y= ackve tugh We= actve [no's ¥ \C7MS1 GROUNDED v AB OG Lope I L Voc Do Dy % 3 VO TMSB 3 Ss GD “Oo SAN Dz GND +++ + 6 7by Ww 4 8B Ih 13 12 be z& t : tt — = Nee We | \C 7h 20 | \C7MI0 ] | 46ND [Y] Gan ae ta \ RB & 5b FF 4 Ss # Vet WO Os ae a BG oR Dp oy ie q = n \C7 Th rae — LL _ Jee van Bip cot i . — Preset(®) Din) Chien) Cénie Za_ Gand 1» 4, 8) aud “ke @, @ Ja 7 is 14h B 2 0 te 4 Lc7416 RS = clear SB Preset —_ — t | 123458 4 8 ax $1 Rt OT Vee CU su 2 Ji\e 5 Vs Ri b 4 _ y Ts Pe: [by AICTE col Aftiinted to the eee OF BIOMEDICAL ENGINEERING = 'VILEPARLE KELAVANI MANDAL'S: DWARKADAB J. SANGHVI COLLEGE OF ENGINEERING Date: Experiment No.1: Title :Study of Logic Gates Aim To study various logic gate ICs and implement their truth tables. Equipments | Breadboard, IC7400, IC7402,IC7404, 1C7408, C7432, IC7486, LED /Softwares | Board, 5 Volts power supply, connecting wires. Theory To be written by students from reference books. (Description of AND, OR, NOT, NAND, NOR and EX-OR gates and their ICs) Circuit To be drawn by students Diagram _| (Pin Diagrams of various ICs and truth tables of AND, OR, NOT, NAND, NOR and EX-OR gates) Procedure To be written by the students. Conclusion | Thus the various logic gate ICs were studied and truth tables of various gates were verified. References 1. R.P.Jain, “Modern Digital Electronics,” Tata McGraw Hill, 1984 2. Malvino & Leach, “Digital Principal and Applications”, Tata McGraw Hill, 1991. Grade: Signature of Faculty: [BHAKTIVEDANTA SWAMI MARG. VILEPARLE (WEST). MUMBAI 400 056 SCHEME, PLOT HO. U1S 2619 4988. Ema :ino@scoe org sdicou@dvcon.ne Website won ong ‘Tat :491 022 4283 5000 2610 7010 /2610 7461 Fax :¥91 022 SS ose \ Expt 4: StuDY OF LOC GATES @ | D AND (1¢1408) A B Dey. A.B 2 OR ( 107432) A ap Y=A+B Nor (1¢ 7404) NAD (1C-7400) A — ) Nor (167402) — Y=AtB © Ex-or (107486) RK Y=A@B= AB+AS B - 4) Exe NoR Y= AQB= AR+AR gs) AICTE and Aftiated to the University of Mechel DEPARTMENT OF BIOMEDICAL ENGINEERING ‘SHRI VILEPARLE KELAVANI MANDAL'S DWARKADAS J. SANGHVI COLLEGE OF ENGINEERING Approved by Date: Experiment No. 2 Title : Design of Basic Gates Using Universal Gates Aim To design and implement basic gates, Ex-OR and EX-NOR gates using universal gates. Equipments | Breadboard, IC7400, 1C7402, LED Board, 5 volts power supply, / Softwares _| connecting wires. Theory To be written by students using reference books. Procedure | To be written by students using reference books. Conclusion | Basic gates, Ex-OR and EX-NOR gates using universal gates were designed and implemented. References 1. R.P.Jain, “Modern Digital Electronics,” Tata McGraw Hill, 1984 2. Malvino & Leach, “Digital Principal and Applications”, Tata McGraw Hill, 1991. Grade: Signature of Faculty: SWAMI MARG. VILEPARLE (WEST. MUMBAT 400 056 PLOT NO. U-15, JUHU SCHEME, BRAKTIVEDANTA i zw a ‘To o91.0224283 $0 2610 701012610 7461 Fa :¥91 02226194968 Ema inlo@ijeoengdpen@ieonont Web , Loe bo Ext 2. DESian OF BASIC GATES, ExoR, ©) a — BYENOR UsiNG UNIVERSAL GATES | 4 PNT USin& NAND DNoT vsSin@ NoR A—H[pteRarA Appel MRER Vorby Rats table of woTaate | Nemiby burt tabte of NoTgdte Pa pet | fo fa] on wt DAND USING NAND —— AAS YeRE — Vovthy truut table of AnD SPA pert hi e of Column 3= ColumnS Column a — 7 OR USING NAND column 3= column + Column Column A AYE = Verihy frets tbl a> Ss of a goede. ° column 3 = Column S Coluvnn3 ColuwnnS DEROR USING Nandy yRs) (KE Nenify Piatt to Bee of, Ex-oR gee. Scanned with CamScanner edo soe) £ bed dda nrss 1 . baad > u a® iE Ae, EPI EET ITT ITE TTT Te a be oR aete ME [Rae [At tT }o to oO o ! 1 1 + I o | o * Giiwan 3 = Column fi) ~ Ex NOR MaNG Nand a Up)-Be = a — ae iis Scanned with CamScanner * 2 Faitones Scanned with CamScanner -eweuvuewvwvuvwvewrr eee ee ee H > AND use NAD ys AR t—) J spy op dy AND wSingNeR ys AB > Pp a =~ 9 Kor vay NAND a A—de3 oa © Not usarq Ne a ~~ MN= 58 aes ki) 2 Ex-cR usivg NAND py Ve ABYAB = : . Scanned with CamScanner ep py! “yy, CUVTCTCCTCCEC ECC CCS Scanned with CamScanner / Exenor Using No & ® Y= aQ+aR ie » (FR pS reap tpt Scanned with CamScanner & SHRI VILEPARLE KELAVANI MANDAL'S DWARKADAS J. SANGHVI COLLEGE OF ENGINEERING ‘Apprevedby AICTE and Affilsted tthe Unhersity of Mumbal DEPARTMENT OF BIOMEDICAL ENGINEERING Date: ] Experiment No.3 Title : Binary to Gray and Gray to Binary code converter ‘Aim ‘A. To design and implement a 4 bit binary to gray code converter. B. To design and implement a 4 bit gray to binary code converter. Equipments | Breadboard, IC 7486, LED board, 5 volts power supply, connecting wires. 1 Softwares Theory To be written by students using reference books. Procedure | To be written by students SS ni Conclusion | A four bit binary to gray code converter and a four bit gray to binary converter was designed and implemented successfully. References 1, RP Jain, “Modern Digital Electronics,” Tata McGraw Fill, 1984 2. Malvino & Leach, “Digital Principal and Applications”, Tata McGraw Hill, 1991. Grade: Signature of Faculty: Scanned with CamScanner EXOT NO-2:- BiNAgy “To GRAY AND GRAY To Bwnaay CoDE CONVERTER oes so Gyo Le 5 Copy MSB ef Binary: DT Has bit, add next adiacent bit of Cinary tode bo eek Sum 2% wate the Summ aay code - ) Repeak Kre step Ril alt bis are Considered. eallle in "bi Aan to Eras cod 27 OD bison ay Gray (ode Bx ws a “Pisa a. hLrULULl by bo ode Ona al Craghect Akg oy Cureghick cal) AY Repeat steps Z ve eas} (to ‘peg Gaany [2201 od gayto bone a 1 0 Gray PA? Bony IAA Aya qo Bown Q Y) Cony MSB Code - , es ot oR eee sad were fe bit - Waite we it o| wt cade. Nog Neg 2 my 37 To of bi ey z bit ef col - a sum W ceont ena code + oO aee Conny Scanned with CamScanner Scanned with CamScanner Kinaay to @xvay Converter. Ga ceeit Diagram 3) By By 8 ‘° 16,® Scanned with CamScanner B= aft G8, OG, ez + G,6,5, ? Ge ‘wow 8, BE fife* 8 a2: Aco ot N ol }fo ft]! | & oe ciea a ae = -5, (Bs 65)+6 Se * wei oritifo fe Hite Lull 2 | - G,(4,04,)- &,( 6,06) = (6,66,)+ 6,(Z SG ) . g. = GOGO G aa we bebe +6.4.4.6. co Jol L fo i 8. GGG, Gg + G28 V2 Fy ov tpie | lie + Ga Ret eGR " aE ] + G66 Ost 6, 6,6,4, ° of) Lie Tifo! + GGG (4.444, Boe &, 3% (Gat 4%, +6, (8% G+ a0) | * 4516, (G 4" 418) +S (BE GG.) | * =4,[6,(4@6)+ 6,(Zaa,)| 442 E\+ &(4.EE ) Scanned with CamScanner “fs (ee) S, Ess / agasedeegegugssvseeuesegveseeceeeeeweeeesweeer"rrr?r"*"r"rr" Scanned with CamScanner SHRI VILEPARLE KELAVANI MANDAL'S DWARKADAS J. SANGHVI COLLEGE OF ENGINEERING ‘Agprevedy AICTE amd Afiated tthe Unbersity of Mural DEPARTMENT OF BIOMEDICA INEERING ] Experiment No. 4 Title : BCD to Excess-3 Code Converter To Design and implement BCD to and NAND gates. code converter using g Equipments | Brea “iboard, 1C7400, IC7410, LED Board, 5 volts power supply, /Softwares | connecting wires. Theory To be writien by students using reference books. Procedure | To be written by students. Conclusion | BCD to Excess-3 code converter using basic gates and NAND gates was designed and implemented successfully. References 1. RP Jain, “Modern Digital Electronics,” Tata MeGraw Hill, 1984 2. Malvino & Leach, “Digi Hill, 1991. | Principal and Applications”, Tata McGraw ‘Signature of Faculty: PLOT MO. 0.15, JUMU SCHEME. BRAKTIVEDANTA SWAMT Mame Wit FDAB# # qwrreT MITMAL 400 056 Scanned with CamScanner Pee nae \ i L&D Nowahon 7 o 0} 0 10 c ( ° ’ c ° \ 0 ne) 1 \ ° ° ioral {| 0 | | toto jo jr o0;o0 {I & As B+ BC Expy Bed - Axel Ia, + 6 oO ° lo L¥CESS-3 CODE ConvERTER ‘nado aa sca Scanned with CamScanner ‘ S lcm c l ¥ ~| CANNOT PERFORIN - 4 Tus AS Bip oR . Po GNTE\S NOT Dp PVALABLE IN LAB i ye ch inet Li We ferhguon cba E2 e, sadivduall 03 rere are et of WAe Cone Bend t 3s onus : SHRI VILEPARLE KELAVANI MANDAL'S: DWARKADAS J. SANGHVI COLLEGE OF ENGINEERING ‘Agyrovedy AICTE wk Affitated to the University of Mioxbal DEPARTMENT OF BIOMEDICAL ENGINEERING Date: Experiment No. 5 Title : Parity Generator and Parity Checker ‘Aim To design and implement: A. Even Parity Genarator for 4 bit data B. Odd Parity Generator for 4 bit data C. Even and Odd Parity Generator using Mode control for 4 bit data D. Odd Parity Checker using 3 bit data E. Even Parity Checker using 4-bit data Equipments | Breadboard, C7486, IC7404, LED Board, 5 volts power supply, /Softwares _| connecting wires. Theory To be written by students using reference books. Procedure | To be written by students. Conclusion | Following circuits were designed and implemented successfully: A. Even Parity Genarator for 4 bit data B. Odd Parity Generator for 4 bit data C. Even and Odd Parity Generator using Mode control for 4 bit data D. Odd Parity Checker using 3 bit data E. Even Parity Checker using 4-bit data RP Jain, “Modem Digital Electronics,” Tata MeGraw Hill, 1984 References 1 . Malvino & Leach, “Digital Principal and Applications”, Tata McGraw Hill, 1991. Grade: Signature of Faculty: PLOT NO. U-1S. JUHU SCHEME, BRAKTIVEDANTA SWAMI MARG. VILEPARLE (WEST. MUMBAI 400056 ab :491 0724253 $00 26107010 (26107461 Fax 991 0222619 4988 Ema inking Abcoe icon me Website econ org Ext No-S:- PARITY GENERATOR AND PARITY CHECKER, Pret A SB: - A Exmn Naosty quncrcdot. het A hit Dada Cf, B. Oa pasty gow [pt Abit dada Cf) eve oF Fe AgBec ed ; Ku O tan Lente tHe oN y deriynbies CDN 00 91 N10 f= Aezeced = A@BOCOD &, f,. xs 4= BeceRECo +R ART ABCD 4+ ABED+ o)* *(8e ZB+ ae aEepe m(neBece3) SMF Me= | ABCD Aecb seep + Bede ik Kawzs +B (OveD coS|RE Rezp+ Rech Ge = (AOBOCO » = ™ (A@BaCeD ) = Y= 444o = ™(AoRecod)+ M(AORSCOD) = MOAGROCOD (ioe 75) ( (cxeB)| gop Bed =) . -A\® COPIED) [+ ABCD +¥(con)| Seen] ses} AYRE sEJ > A[Boe\+ A (BeBe) | = K[ROE|+A (SOE) = APOBOE = AOR OCAD= AGReCeDd cana mA % = > | | _ +} 3 1 MeAOROCOT 2 - Odd Yaaity Ch . 5 AS ecker Using 3 brt dota Pi deaken Crtut 33 Dee Cees enol . fee recewed Wed THe janity Gt 3s ayslied to panty jpookor ig | becker £0 Vax’ farihy 3 bit dech- Oudpuck) be Totoh & bi deaths Sborken uxlt deck party of received werd ene Modu eats ofp: _ “tte y Here, hart tramawitied WAd 28 ODD jhe hort ae Re eta wad unt, eDdD hos & connect wards Q rode with even parity ad cartel IRA - fe of party checker ckt ss elenoted of FEO. cai Goes iaogext so received A bit werd hog oven pewty) . a0 (ib there 3A v0 CMe, Le Neceived A bt wWetd a8 odd {\ ashy’) B | ® PEO BBO oo of NW to oo |t |o|\jo ov jol{!t jo}! L jo ly jo i 1 0 [o oO PB, gh RO -PRBPRO= FORO OF, PeR t—)>—* y PEO IH Re® PoBo8 e8, “ <£:- Dew Tanity UnerKer uadiog bit data - eases 70-0 (Ah Hrere da no enrct Le Recored Sb werd hos even flow’ eal (31 wer Pered, 22 recewed 5 bit wotd as_odd Hr) ee eB. f Ba “ 8 BB ve ot 1 aq: ae eel vial eat oo |o;iiol! a or fifo [i fe 1a w foft fo [I |__.O —T vw {tfo}] 1° 4 =P (2,88, 08,08.) is o Ps | PB 1 BiXoo or un to oe vo {i [ot To 3 ot oft oll L_jlo WV (folio 1 ° lo o}l oll a ——— = =e “y= PCR oR 68,08, ) oo} lt PEo= 44 o ft I = 68,08 68 of, \ PEO BR | Pe Ren oR ek, =e VILERARLE KELAVANIMANDAL'S ARKADAS J. SANGHVI C F ENGINEERIN oe RS ot poem DEPARTMENT OF BIOMEDICAL ENGINEERING { Date: Experiment No. 6 Title : Design of Adder and Subtractor ‘Aim ‘A. To design and implement half adder and full adder. B, To design and implement half subtractor and full subtractor. Fquipments | Breadboard, 1C7486, 1C7408, 1C7432, IC7404, LED Board, 5 volts power | Softwares | supply, connecting wires. Theory To be written by students using reference books. Procedure | To be written by students. Conclusion ‘A. Half adder and full adder were designed and implemented successfully. B. Half subtractor and full subtractor were designed and implemented | successfully. | References: 1. RPJain, “Modem Digital Electronics,” Tata McGraw Hill, 1984 . Malvitio & Leach, “Digital Principal and Applications”, Tata McGraw Hill, 1991. Grade: Signature of Faculty: ‘PLOT NO. U-15, THU SCHEME, BHAKTIVEDANTA SWAMI MARG. VILEPARLE (WEST). MUMBAI 400 056 ‘ToL :991 0224233 $000 12610 7010/2610 2461 Fax : 491 022 26194988 Eon :ino@ipcon org dscon@con.org Website: wndicoe. org ENT 6:- ADDER- SUBTRACTOR Sam(S)= KBAR Conny (0)= AB = A@R® ips Doe Fast Adder : - < A CG A[B{¢ i Se rR - ong 0 | 0 ° oO oO oo OO NW \o £8 55 oL WW 1o olettity fo fojeli te ]o ojo | oif\ oft fol + o }yis]ei jo v Lo IQ TD ofiit - tet ce AOR OC Canny = an te on Be Fore = ABCH ABC This with require 3 '{i fo fo [4 * ARC ABT YP oR gate whidh is TIVTU py] 28 (8ec)+ ACRE) upd yt Se notawatle | in lal . ARB “Couved = (AAR) C+ AB T° ye Sum= A@Boc pepe pe CaeB)C Canny = AB+ (ABYC cf VY AB Difference ) aR Bom (B,) 2 aft oo o1 WN to CNo0 oy WV te ofofrjotl ° iE ojo \ tlo}\jo Vi ° De ABC+ARE B= AB+ ACHE ABCHABC Ths will equine % =K(Bed)+AC Bee) Ip oR gede 9 Dh as = ABO vot available mM lab “Bee Aer + BC Be ACRre+ Be. yl Adder amd “batt Subtract Using Mone Contret , BON 22 01 to oo fol hilfe o TN o lo fit] uv fo Toye \o [oO |o SP = ABZ4ABC+ARCHART > ACBOC)+R( BOC) = ASBOC Conny [By wo ol Wolo | co [elo ojo} | ot fe lit] ° liry uw [ft L to fo fhifio ih Canny R= BC+ MACH HAR + : MAC+MAB . =RC+ C(ma@n)+B(MOR = BC+ (Men) (BrC) Nee ay S[D= A@BOC _ Canny [B, = BEr(mony (BE sil Adder Biol Subbadet Using Made Contre! any s}> MAL o | e}o jo; o \ LH ol @] J Conny |, B, A=B and A Connecting wires, LED Board, 5 volts Power supply, function | Benerator, IC 7476, (dual JK Alipflop), 107400 To be written by students using reference books. | To be-writen by studenies Asynchronous counters using EK flip lops were designed and implemented successfully ics,” 1, 1984 S 1. RP Jain, “Modern Digital Electronics,” Tata McGraw Hill, Reference: as - _ 2. Malvino& Leach, “Digital Principal and Applications”, Tata Me‘ Hill, 1991, L jgnature of Faculty: Grade: EXPT No. leASpbovens Coders aU Counters, CLOCK Square wave, chron’, SyYoits eak-> jeak) Pycaat Di yo D AU CLOK. nn dear (one > ) nod & Asyocbdonous Down Couser- | LSB CLotl aL Clean. Cloner) wa: Ga P As a Counter ~ Dmod-3 Asynobsanous UP under *- Shade diacpe — Jy ood- 5 Asynebroncus VP counter: - SHRI VILEPARLE DWARKADAS J. SANG! 'KELAVANIMANDAL' Peart COLLEGE OF ENGINEERING . Sd Aft handy of ch DEPARTMENT OF BIOMEDICAL ENGINEERING Experiment No. 1 Title : Asynchronous Decade Counter Fy Bound, Power supply, Resistor (1K) for, IC 7476, 17400, 17408. Breadboard, eomnecting wires, capacitor ( IpF), function generat ‘ndenis using reference books. To be written by st To be written by students. iy designed. MeGraw Hill, ‘Tata McGraw jecade counter was ‘successfull “Asynchronous de 7984

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