Effect of Compression Loads on the Solder Joint Reliability of Flip Chip BGA Packages

Luke Garner, Charles Zhang, Keh Shin Beh, Kayleen Helms, and Yew Lip Tan
Intel Corporation
5000W Chandler Blvd, CH5-157, Chandler AZ 85226
1uke.j.garner@intel.com

Abstract conduction. This compression load must be maintained

Rising power dissipation requirements in modern
semiconductor devices have created a need for high
performance thermal solutions. These thermal solutions
require increasing amounts of compression loading to ensure
good conductance of thermal interface materials and retention
of massive heat sinks in shock conditions. The impact of these
loads on the reliability of the package solder joints has
typically not been considered in both finite-element-based and
statistical-based assessment methodologies for fatigue of
solder joints. The goal of this work is to provide an
understanding of the effects of these loads and provide new
methods to characterize the limits of these loads for reliable
operation throughout the life of the component.
This paper discusses the critical impact of the thermal
compression loads on solder joint reliability for both fatigue
and creep. In this work, a new experimental test method is
described. This method utilizes a fixture that simulates the
thermal solution load during life testing. The fixture design
allows the load and support conditions to be varied and their
effects studied. Testing of surface mounted components has
been conducted and implications to the standard statistical life
prediction methods are discussed.
In addition, finite-element-based modeling assessments
for the loading conditions have been performed. The analysis
shows the impact of the thermal compression load on discrete
solder joints for both thermal cycling and long duration high
temperature (bake) testing. The implications of compression
loading to analytical and statistical life prediction methods are
discussed. Based on the experimental and modeling data, load
and support boundary condition limits are proposed as the
hest way to prevent solder joint failures.
Thermal Compression Loading
The exponential rise in computer performance is expected
to continue into the foreseeable future. This performance
typically increases the power densities of microprocessors.
"his in turn drives a need for more effective thermal
dissipation technology. This technology commonly has two
features that are of concern from a reliability standpoint. (1)
The mass of the thermal solution has been steadily increasing.
The increased mass poses a risk during shipping and handling
due to shock and vibration. To counter these effects a
retention mechanism is often employed which compresses the
thermal solution against the integrated circuit package to
prevent separation during shock. (2) The other involves the
use of thermal interface materials to enhance thermal
conductivity. These thermal interface materials may consist of
conductive particles suspended in a polymer matrix.
Compressive loading of the interface material improves
thermal conductivity by allowing particle-to-particle
throughout the life of the product.
While many of these high performance thermal solutions
have been in use for many years for microprocessors, they are
now required in new applications. These include high
performance memory controller hubs and network processors.
Unlike many of the microprocessor packages, which are
typically placed in sockets these packages are most likely
surface mount ball grid arrays (BGA) packages. The effect of
substantial compression loading on the reliability of s801der
joints has not been widely studied. A recent study by Eyman
and Kromann did establish that compression loading has a
detrimental effect on the thermal cycle reliability of plastic
ball grid array components [l]. However, many of the classic
reliability assessment methods (both analytical and
computational) do not include these effects.
High performance thermal solutions pose many risks to
the associated electronic components. These risks include
excessive board flexure during shock and vibration due to the
acceleration of large heat sink masses. These conditions could
lead to solder joint fracture and fatigue, respectively. The
compression loading itself will induce creep in the solder
joint. Over time the creep of the solder joint could lead to
electrical shorts if two adjacent balls should contact each
other. Also, the compression loading will change the thermo-
mechanical fatigue behavior of the solder joint during power
cycling. This paper will specifically address these last two
failure mechanisms and their effect on the long-term
reliability of solder joints in flip chip, ball grid array packages
(FCBGA).
Experimental Approach
A generic loading fixture has been developed to
experimentally evaluate the compression load effects. Figure
1 shows a schematic of this fixture. It consists of a top loading
plate with multiple hole patterns so the effect of support span
can be studied. The top plate is used to compress a low
stiffness spring and react the corresponding load from the
circuit board through for bolts that are bolts placed in a square
pattern at the corners of the FCBGA package. The spring
used has a low stiffness such that any creep deformation of
the board will have a minimal effect on the load. A simple
aluminum disk is used to transfer the spring load to the top of
the exposed silicon die of the FCBGA package and simulates
the heat sink. Thermal grease is used to prevent damage to
the die from handling and fretting in thermal cycle.
Using the generic fixture, there are multiple ways to apply
compression load to the package and the board. Figure 1
shows one configuration of the fixture that represents the
most common setup. In this configuration, the board is
allowed to deflect between the four support points. This is the
type of configuration that would be expected from simple

02004 IEEE
0~7803-8365-6/04/$20.00 692 2004 Electronic Components and Technology Conierence
stamped metal or bent wire heat sink clips. To minimize over
constraining the board, the fixture uses dome washers to
support the board from one side only.
The thermal solution hardware may also include a stiff
back plate to minimize board flexure. To simulate this type of
thermal solution, a thick back plate with threaded through
holes is used instead of the dome washers and nuts.
Tlrennal Grpm
P
KTB
Board
induced electrical shorting or into thermal cycle chambers for
thermo-mechanical fatigue.
Finite Element Analysis
To firther understand the mechanisms of failure, finite
element analysis (FEA) has been used. Figure 2 shows a
typical mesh of the board and FCBGA package. The elements
used are reduced integration 2nd order elements: bricks
(C3D20R) and wedges (used only in the die fillet). The
ABAQUS standard solver has been used for all simulations.
The symmetry of the load and the package allow the use of a
quarter-symmetric model. As the most critical solder joints
are those near the die corner and the package comer, the mesh
was refined in these areas to improve accuracy, as shown in
Figure 3. For this sensitivity analysis, the details of the solder
joint pad design have been excluded.

Figure 1. Compression loading test fixture, full flexure

configuration.

‘The load is applied to the fixture by means of a hydraulic

load frame. The fixture is placed in the frame with a plate
supporting the bottom of the fixture and a platen is used to
displace the top plate. When the desired load is reached, the
load frame cross head is locked. The nuts are then tightened
on the bolts until 50% of the load has been removed from the
load frame load cell. This action tensions the bolts so that --I

when the cross head is raised the desired load continues to be Figure 2. Quarter symmetric finite element model of the
applied to the component. The 50% load reduction technique FCBGA package on test boards.
was determined through experimentation using a load cell as
the component in the fixture.
‘me loaded fixture is then placed into the accelerated
thermal testing chambers. The thermal mass of the fixture has
been minimized; however the use of the fixture does
adwrsely affect the chamber capacity. All chambers were
profiled to ensure that the component temperatures were
with in the accelerated test specification. Two standard
JEDEC thermal cycle conditions were used: TCQ (-25 to
100°C and TCJ (0 to 100°C). High-end temperature was
limiired to 100 O C to avoid exceeding the board glass
transition temperature which would cause excessive damage
to the joints and board. The high-end temperature was kept
the same in both thermal cycle conditions to eliminate the
introduction of high-end temperature effect suggested by
some three-parameter solder fatigue models [2]. The two Figure 3. Detail of solder joint mesh: 4 layers of second order
thennal cycle conditions also have the same fiequency that elements, 5 elements per layer. Top layer used for averaging.
allows a single parameter model to be used for reliability
prediction. Linear elastic constitutive models are used for all package
At each thermal cycle readout, both electrical test and components expect for the solder joints. The solder behavior
dye & pry failure analysis were conducted to monitor the is simulated by a model from Hong and Burrell [3]. This
performance of the BGA solder joints. The test package and model includes isotropic hardening plasticity and power law
board were designed in such way that all of the solder joints creep. Since the board is known to creep during these tests,
in the critical areas (under the die and package corners) can be the long-term Young’s modulus is used for the board
hlly tested electrically. In addition, dye and pry provides an properties. Internal tests have noted that the long-term
accurate measurement of solder joint fatigue crack area. modulus is about 80% of the instantaneous modulus.
Lrsing these test fixtures, surface-mounted test vehicles Two basic analyses were run, one for solder joint creep
were loaded into either “bake” conditions to assess creep shorting and the other for thermal cycle fatigue. In both
693 2004 Electronic Components and Technology Conference
 :
analyses, the thermally induced stresses from board surface board thickness, the expected maximum sustained 13GA
mount and package assembly were included by first temperature and enabling hardware stiffness.
completing a cool down step from the reflow temperature to
room temperature. After the cool down from assembly, the
compression load is applied to the top of the die and the board
constrained at the desired support point. These support
locations are highlighted in Figure 2. For each analysis, all of
the nodes in one of the highlighted elements were constrained
in the vertical direction only. For models where a back plate
is included, all nodes on the bottom surface of the board were
constrained in the vertical direction. For the creep tests, the
model was then ramped to the desired uniform temperature
q
04

01
4
and held until a BGA short was detected. For thermal fatigue,
the model simulates three complete thermal cycles to allow
the creep and plasticity response to stabilize. The dwell time
at the high and low ends of the thermal cycling were included I O'
R a d hrt #

i
2.67 1.33 2.67 1.33 2.67 Load Rccel
to capture creep effects.
. 1.13 1.33 1.67 Tew
Solder Joint Creep Results 1 I 1 I I
As mentioned previously, a primary concern of high
compression loads on FCBGA packages is the risk of creep -
Legend
FEAMdel
+ exp.daia
induced ball shorting. It has been difficult to fit the results of
accelerated creep tests with standard statistical reliability Figure 4. Comparison of finite element prediction with creep
models. A finite element model is therefore used to make the test results for ball-to-ball gap for various temperature and
reliability assessment. Five experimental test legs were used load conditions over time.
to validate the creep model for the PbSn eutectic solder.
These included three elevated temperatures and two elevated
loads. Elevated loads and temperatures were used to ensure 1
that measurable amounts ball deformation would occur during U 0.9
the testing period. The lowest temperature and load
w
= 0.8
combination was not included since little creep was expected E 0.7
0
in the duration of the test. For each test leg, the specimens & 0.6
were removed at defined time intervals, and x-ray 0 0.5
measurements were taken to measure the minimum ball-to- c3
7 0.4
ball gap. Figure 4 shows the experimental results of these
tests compared to the prediction of the finite element model. 0.3
B
Using the Hong and Burrell creep model referenced above, = 0.2
the fit of the FEA model is reasonably good. The model 0.1
appears to become more conservative for lower temperatures, 0
which should lead to conservative estimates for reliability in
use, where lower solder ball temperatures are expected.
Since the temperatures used in this test were near the glass
transition temperature of the board, the back plate Figure 5 Comparison of solder joint creep with and without
configuration of the fixture was used. In some systems the back plate support.
board may be allowed to deflect. A FEA simulation was done Thermo-mechanical Fatigue Results
to compare the relative risk of failure with and without the
back plate. With a rigid back plate, the solder joints beneath Package Corner Analysis
the die deformed most. Without the back plate, the solder When no compression load is applied on a FCBGA
joints at the package corners had the greatest creep package, the solder joints at greatest risk for thermo-
deformation due to the board flexure. Figure 5 shows the mechanical fatigue are those under the die. In this area, there
comparison results. The gap decreases faster for the center is a local coefficient of thermal expansion (CTE) mismatch
joints with a back plate than for the comer joints without a created by the silicon being tightly bonded to the substrate.
back plate. The back plate extends the time to failure 50%. The solder joints in this area see additional shear and axial
The calibrated creep model can be used predict the risk of strain due to this mismatch. The solder joints at the package
electrical shorting as a function of load, expected solder joint corner are not likely to fail since there is no significant CTE
temperature, and board support configuration. Compression mismatch between the FR4-like substrate and the very similar
load limits should be specified for the component to prevent board materials. This very unlike the behavior observed in
solder joint shorts. This load limit will be a function of the ceramic packages. In these packages, the large package-board
CTE mismatch leads to fatigue cracking at the package
corners.

694 2004 ElectronicComponents and Technology Coriference

 In FCBGA packages, the failure location shifts when
compression load is applied during thermal cycling. Rather
than being only in the die shadow area, failures are also noted
near the package comers. In some more extreme conditions
the p,ickage comer failure may occur very early in the thermal
cycling. As this behavior cannot be explained by ' * ---
mismatch the tnip C R I I S P miiqt he identified cr
TOgain further insight into these early failures, a designed
experiment was conducted using finite element analysis. The
input variables of interest for the modeling experiment were
compression load magnitude, board thickness, and support
span. The experiment design was a full factorial with a center
point added, identifying nine cases. Three different results
were extracted from the model in each case. These results
were the increment in a strain or energy quantity from the
second to the third thermal cycle. These were the inelastic
strain energy density (ISED) increment, the axial strain
increinent, and the increment in the shear strain normal to the
board plane. These results were extracted at the centroid of
each element and then averaged by element volume over the
top layer of elements in each BGA. Two solder joint locations
along the diagonal of the package were used for comparison.
The first joint was located under the die near the edge of the
die (die shadow). The second joint was the located the
package comer.
The results at both locations for all variables were fit with
a polynomial response surface model (RSM). The fit of the
model was quite good with most variables being fit with an R2
of 1.00 comparing FEA to RSM predicted values. The worst
fit was still very good with R2=0.98. Using the RSM,
predictions for any case in the range of the input variables can
be quickly calculated.
A:$part of the thermal cycle evaluation, boards of select
thicknesses were thermal cycled through their equivalent life
with varied loads. For this study the largest support span was
used without the back plate, which allowed for the greatest
degree of board flexure. For each experimental case, the ISED
increment was calculated using the RSM.
Fi,pre 6 shows the fit of the experimentally observed
failurc rate to the ISED increment. The failure rate shown is
for electrical failure at the life equivalent readout for the
accelerated thermal cycle test (-40 to 85OC). All the failures in
these tests occurred at the package comers. Test legs without
any fzilures were assigned an arbitrary failure rate of 0.1 for
the purposes of visibility in the figure, but these points were
not used to calculate the fit. A power law for the increment in
ISED was used as has been suggested by Darveaux [4]. From
the figure, it can be seen that the fit is quite good with an R2
value of 0.97.
Using the above RSM and failure rate relation, the failure
rate for differing load, span and board thickness boundary
conditions can be calculated. Figure 7 shows the effect of the
'
board thickness for a fixed span and load. Both the load and
span are relatively large in this case leading to a high failure
rate fix thin boards. It can be observed that the board
thickness has asymptotic behavior with the failure rate. This
result agrees with experimental observation indicating that the
695
corner solder joints on the thin board specimens exhibited
gross solder joint deformation.
P I
m
0.1 1 .o
ISED (Normalized)
Figure 6 Fit of FEA to failure rate data for all experimental
legs.
The effect of the load is shown in Figure 8. Again, as
expected, higher loads will increase the loading of the outer
solder joints leading to a shorter fatigue life. Figure 9 shows
the 'effect of support span, Here the fit with the experimental
data is not as good. However, both the model and the test data
show that reducing the support span greatly improves the
reliability of the solder joints.
With these functional understandings of the load, span and
board thickness, it is now possible to better control the impact
of the required compressive load on reliability of the solder
joints. First, since board thickness in most likely to be
dictated by the need for electrical routing and performance
and cannot be considered to be a design variable, load and
span limits will have to be set for common board thicknesses.
Second, while the effect of an increased load could be
countered by a decreased span, the upper bound for the
compressive load will be limited by creep behavior discussed
above. Last, while board electrical routing would benefit from
additional space created by increasing the support span, this
will adversely impact the reliability of the solder joints for the
same compressive load.
Although it is true that larger loads and wider spans
exhibit larger board deflections and reduced fatigue life,
deflection limits have not been suggested here for three
reasons. First, limited testing data has shown poor correlation
between board deflection and reliability. Second, in a fully
assembled system it may not be feasible to measure the
deflection of the board, since the back of the board is
inaccessible. Last, the board deflection will not remain
constant under a constant load, but will increase over time due
to the viscoelastic nature of the board, creating uncertainty in
the meaning of the deflection limit..
2004 Electronic Components and Technology Conference
 Solder Joint Strain State
The above discussion relates only to the package corner
solder joints under compression loads. For smaller
compressive loads and span conditions, cracks and
subsequent failures occur in both the die shadow and the
package corner as indicated in Figure 10. This figure shows
measured solder joint damage in individual solder joints
through the thermal cycle test. The damage growth at the die
shadow is faster than the package comer damage growth for
this moderate loading condition.

Board Thickess
Figure 7 Effect of board thickness for fixed span and
compression load on failure rate for experimental data and
FEA simulation predictions.

500 750 875 1025

2.5
Cycle Caunt
2.0
Figure 10 Measured solder joint damage progression through
1.5 thermal cycling comparing solder joint damage for die
shadow and package corner
1.o

0.5 This observation does not agree at first pass with the FEA
model. Figure 11 shows the ratio of the per cyclme. ISED
0.0 increment between the package corner and the die shadow.
0 0.2 0.4 0.6 0.8 1 1.2 1.4 For even very low loads this ratio is very large. Theory would
predict much faster growth at the package comer than at the
Load (Normalized)
die shadow. While this is true in high load and span cases in
Figure 8 Effect of compression load for fixed span and more a moderate case such as the one shown in Figure 10, it
thickness on failure rate for experimental data and FEA is not. A closer examination of the loading state of the solder
simulation predictions. joints may be able to explain this inconsistency.

14 6.0 I
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0
.-
s 6
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-$m 4
.-
k 2

0
0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 0.0 0.5 1.o 1.5
Thermal Load (Normalized)
Support Span (Normalized)
Figure 11 Comparison of predicted ISED between di.e region
Figure 9 Effect of support span for fixed board thickness and and package corner as function of load.
compression load on failure rate for experimental data and
FEA simulation predictions. The predicted axial strains between the package comer
and die shadow behave quite differently. Figure 12 shows the

696 2004 Electronic Components and Technology Conference

solder joint axial and shear strain increment predictions on the
solder joint as a function of load. Under the die shadow the
per cycle axial strain increment prediction is slightly tensile
due to the substrate warpage caused by the die and substrate
CTIZ mismatch. This strain increment is not significantly
affected by the compression load for the range of load
magnitudes simulated. At the package corner the flexure of
the board imposes a large compression load on the solder
joint in the simulation. The tensile strain under the die
shadow may serve to accelerate the crack propagation
whereas the compression strain under the package comer may
help to slow crack growth. The elastic strain energy
calculation shown in Figure 11, does not distinguish between
t e n d e and compressive strains. The compressive strains at
the corner will lead to high ISED values, but this strain state
may not contribute to the fatigue crack growth in the same
proportion as under the die shadow.
Similarly the predicted shear strains increments shown in
Figure 12 are quite different. The corner joint experiences a
large amount of shear strain due to the board flexure. As the
board bends, the relative motion of the substrate to the board
causes a “rotation” of the solder joint leading to a high shear
strain. Under the die shadow the shear strain is driven by the
local CTE mismatch, which is small and not affected by the
applied compressive load.
-1.2
+Shear Strain - Die
-1.o +-Axial Strain - Comer
! ” / I
.- -0.8
m
b
$ -0.6
al
-N
.-
E -0.4
b
z -0.2
0.0
I I
I I
0.2 I ,
0.0 0.5 1 .o 1.5
Thermal Load (Normalized)
Figure 12. Predicted strain state for the package comer and
die shadow solder joints as a function of load
These significant spatial differences in the strain state may
require that a more advanced fatigue law be developed. To
adequately predict behavior, the fatigue law must account for
the multi-axial loading state of the solder balls under load and
the distribution loading states within the solder joint array.
Failure rate predictions in Figures 7-9 show that an energy-
based model may still be used to gain understanding and
predict solder joint performance. However, the model
gene)-atedcannot be applied to other areas in the BGA array
where the loading state is dissimilar. For the energy-based
methods to work, a predictive model would have to be created
at each location in the array.
697
Implication to the Reliability Model
Loading Effect
The above section has described how compression loading
effects may be predicted by FEA models. The impact of the
compression load on the reliability statistics modeling
methodology should also be understood. Two thermal cycle
conditions were used to evaluate load effect on solder joint
reliability performance using loading configurations outlined
in previous sections. Figures 13 and 14 both show the
comparison of normalized solder joint damage for loaded and
unloaded samples on as function of thermal cycles. Figure 13
shows the effect for thermal cycle condition TCQ (-25 to 100
“C). Figure 14 shows the same for condition TCJ (0 to
100°C). The load and support span used were within the
limits discussed in the previous section. The full array of
solder joints was examined under a microscope. Solder joint
damage was observed both die shadow and package corners.
However, the maximum solder joint damage was always at
the die shadow regardless of the loading condition or thermal
cycle condition. For this comparison, the maximum damage at
an! ;older ball in a package was recorded.
Loaded 1 Unloaded
Readout within Loading, Ib
Figure 13. Comparison of normalized solder joint damage for
load vs unload configuration as function of thermal cycles.(-
25 to 100°C)
As shown in Figure 13 and 14, both loading conditions
exhibited very similar solder joint damage behavior
characterized by two stages. In Stage I, no visual damage was
observed. This stage ends with the initiation of a crack. Stage
I covers -40% of the total thermal cycle test period in this
study. Stage I1 is solder crack propagation. The crack
propagation had a linear relationship with number of cycles
after initiation in all conditions tested except for the loaded
TCJ condition.
The load appears to change the solder joint damage
behavior for less severe thermal cycle condition TCJ. Instead
of having a linearly proportional relationship, the damage
appears to be decelerated by the load. This is not the case in
TCQ, which has a lower low-end temperature. As mentioned
above, a tensile load is imposed on the joints in the die
2004 Electronic Components and Technology Conference
shadow. This load increases as the temperature decreases
from the assembly temperature. It can be speculated that for
the higher low-end temperature condition, the tensile loads for
the substrate warpage may be partially canceled by the
mechanical load. At the lower low-end temperature condition,
the substrate warpage may overwhelm this effect. The
implication for the use condition with much higher low-end
temperatures, is that solder joint fatigue may be retarded
significantly by the mechanical loads.
I Loaded I Unloaded
I work.
Readout within Loading, Ib
Figure 14 Comparison of normalized solder joint damage for
load vs unload configuration in as function of thermal cycles
(0 to l0O0C)
Crack Propagation Model Fitting
The damage growth behavior is modeled based on their
experimentally observed behavior. Both linear and
transformed square models produced a very good fit as
indicated in Table 1. By using the fitted models, the number
of cycles needed for crack initiation and damage growth to
failure were calculated and summarized in Table 1.
thermo-mechanical fatigue results collected in this stuey the
first approach has been selected, as two stages of fatigue
crack initiation and damage growth were clearly seen.
Conclusions
Compressive loads alter both the distribution of loads and
the loading state of the solder joints within the array. Energy-
based life prediction techniques can be applied but are limited
spatially to areas of the array with similar loading states. Load
and support span limits can be applied to prevent premature
solder joint fatigue failures under compressive loads.
For the reliability models, compressive load has a more
significant effect on crack propagation for thermal cycle
conditions with higher low-end temperatures; however, for
large temperature amplitudes, compressive load helps to delay
crack initiation. Solder joint crack initiation and propagation
can be predicted by a fatigue life prediction model.
Acknowledgments
The authors would like to thank Intel management for
there support of this effort. They would also like to thaink the
failure analysis lab for their timely and quality support of the
measurements discussed in this paper. Luke would especially
like to thank his family for their patience and support of his
References
1. Eyman, M L, “Investigation of Heat Sink .4ttach
Methodologies and the Effects on Package Structural
Integrity and Interconnect Reliability of the 119-Lead
Plastic Ball Grid Array” Proc. Elect. Comp. and Tech.
Conf. 1997, pp. 1068-1075.
2. J. H. Lau, Thermal Stress and Strain in Mecroelectonics
Packaging. New York: Van Nostrand Reinhold, 1993
3. Hong B Z, and Burrell, L G, “Modeling Thermally
Induced Viscoplastic Dformation and Low Cycle Fatigue
of CBGA Solder Joints in a Surface Mount Package”,
IEEE Trans. on Comp., Packaging, and Manu. Tech. -
Part A, Vol20. No 3, 1997, pp. 280-285.

1 I 1 I:I 1
4. Darveaux, R, “Effect of Simulation Methodology on
Solder Joint Crack Growth Correlation”, Proc. Elect.
Table 1 Damage Growth Model Fitting Summarv
Comp. and Tech. Conf. 1997, pp. 1068-1075.
Cyc1esto Cycles to
Model Fitting
Condition
Initiation
Transformed
LoadedTCJ
5:
IUnloadedTCJl
I
Linear I
I
0.88 I
I
540 I
I
2350 I
LoadedTCQ I Linear I 0.93 I 550 I 1700
Unloaded
Linear 0.94 485 1700
TCQ

The fitting model presented above will further yield the

acceleration factor and fatigue life prediction. Traditionally,
solder fatigue life prediction methodologies have two basic
approaches. The first approach is to predict the initiation and
I 0 COLOR
Your accompanying CDROM contiins a
I
early growth of cracks, and generally assumes that the solder version of this paper with color imaiges.
joint is initially pristine. The other approach assumes that a I http:/ICAMMI.cpmt.org/proceedings/ I
crack already exists at the critical location. Based on the
698 2004 Electronic Components and Technology Conference