AterPS & GPU - GP Dimensioning

Ater PS and GPU/GP Dimensioning in B9 &
Ater Optimization in B10
Eugen Marza
GSM Engineering team
2008
1
Agenda
1. MFS Overview
2. PS Signaling Architecture
3. Ater PS Dimensioning
4. Ater Optimization
5. Parameters
2
1
MFS Overview
3 | AterPS & GPU/GP | 2008 © Alcatel-Lucent , d.r., 2008
3
Ater PS and GPU/GP Dimensioning
MFS Overview
BSS Architecture in B9
TC
MT120
SMU TRCU TRCU TRCU
A speech
MT120
Air SMU TRCU TRCU TRCU
A-bis BSC
CS TR X 1
TC H
TC H
CS
traffic
TR X 2
Abis Ater CS
M -EG C H link 1 G CH Basic TSU TSU
G CH Basic
PS TR X 3 M -EG C H link 2 Dynam ic
traffic Abis
G CH B onus
G CH Extra
Abis
TSU
Ater
TSU
A-ter mux
allocation
TR X n M -EG C H link n G CH Extra
Abis Ater
BTS TSU TSU CS+ PS MFS
GPU board
data
PS DSP DSP DSP DSP
GPU board Gb
DSP DSP DSP DSP
4
MFS Overview
BSS Architecture in B9 with Mx Platform
TC
MT120
SMU TRCU TRCU TRCU
A speech
MT120
A-bis MxBSC
CS TR X 1
TC H
TC H
CS
traffic
TR X 2 G CH Basic
CCP CCP CS
M -EG C H link 1 board board
G CH Basic
traffic Abis
G CH B onus
G CH Extra
SSW
board
TP
board
A-ter mux
allocation
LIU LIU
BTS board board CS+ PS
MxMFS
data
GP board
PS DSP DSP DSP DSP
GP board Gb
DSP DSP DSP DSP
Capacity
1 GP = 4xGPU
(B9 MR4)
5
MFS Overview
BSS Architecture in B10
TC
MT120
SMU TRCU TRCU TRCU
A speech
MT120
A-bis BSC
CS TR X 1
TC H
TC H
CS
traffic Abis Ater CS
TR X 2 M -EG C H link 1 G CH Basic TSU TSU
G CH Basic
traffic Abis
G CH B onus
G CH Extra
Abis
TSU
Ater
TSU
A-ter mux
allocation
Abis Ater
BTS TSU TSU CS+ PS MFS
GPU board
data
PS DSP DSP DSP DSP
GPU board Gb
DSP DSP DSP DSP
Ater
optimization
GB over IP
6
MFS Overview
BSS Architecture in B10 with Mx Platform
TC
MT120
SMU TRCU TRCU TRCU
A speech
MT120
A-bis MxBSC
CS TR X 1
TC H
TC H
CS
traffic
TR X 2 G CH Basic
CCP CCP CS
M -EG C H link 1 board board
G CH Basic
PS TR X 3 M -EG C H link 2 Dynam ic More cells per
traffic Abis
G CH B onus
G CH Extra
SSW
board
TP
board
A-ter mux MFS
allocation
LIU LIU
BTS board board CS+ PS
MxMFS
data
GP board
PS DSP DSP DSP DSP
GP board Gb
DSP DSP DSP DSP
Ater
optimization
GB over IP
More cells per
GP board
7
MFS Overview
MFS Basics
General Packet Radio Service part of a BSS network handled by the Packet
Control Unit function, which manages
Radio Link Control & Medium Access Layer levels
Access network functions (Radio Resource Management)
Packet Data CHannel scheduling, power control, ...

Transmission errors detection & selective automatic retransmission (ARQ)
Interface with SGSN (Gb)
Specific radio link functions are managed by Channel Control Unit, located
in the BTS
Radio channel coding, radio measurements...
8
MFS Overview
MFS A9135
HW Architecture
Control Station
Ethernet LAN
IP/Ethernet
Switch
to OMCR
From/to
BSC and TC
Atermux
GPU
Interfaces Gb interface
From/to
Atermux GPU SGSN
Interfaces
Gb interface
…
Atermux GPU
Interfaces Gb interface
9
MFS Overview
MFS HW versions and capacities:
A9135 MFS (first generation)

– MFS can accommodate from 1 to 2 telecommunication sub-racks.
– One GPU board per sub-rack is always dedicated to the n+1 redundancy
feature.
– One MFS can control up to 22 BSCs.
– One MFS can manage up to 2000 cells.
MFS based on DS10 systems
– can house up to 32 GPU boards
– 2*(15+1)
MFS based on AS800 systems
– can house up to 24 GPU boards
– 2*(11+1)
10
MFS Overview
A9135 MFS
GPU board
The GPU supports the Packet Control Unit (PCU), as defined by GSM. The PCU
handles Gb-related functions, Radio Resource Allocation functions and protocol
exchanges with the Mobile Stations.
Each GPU consists of 4 DSPs, which are in charge of the RLC/MAC functions as well
as the EGCH protocol exchanges with the BTSs. Each DSP supports 120 GCH.
The GPU handles less than 480 GCH to avoid blocking the DSP.
Each GPU board is connected to only one BSC.
But one BSC can be connected to several GPU (up to 6), depending on packet
traffic. These GPUs can belong to different MFS sub-racks.
There are a maximum of 16 PCM links (AterMux & Gb) per GPU board.
11
MFS Overview
GPU board
Cell Mapping
All the GPRS traffic of one cell is handled by one, and only one, GPU.
– The BSC is transparent to this behaviour and ignores this mapping.
•Sub-BSS 1
•cell1
•cell4 •cell2
•cell3
•MFS
•BSC
•Sub-BSS2
•
•GSL1 •GPU
•cell5 1
•cell6
•cell7 •GSL2 •GPU

2
•Sub-BSS3
•GSL3 •GPU
•cell8 3
•cell9 •cell10
•cell11 •GSL4
•GPU
•cell13 •cell12 4
•cell14
•cell15
•GPU1: cell1, cell2, cell3, cell4
•GPU2: cell5, cell6, cell7
•GPU3: cell8, cell9, cell10, cell11 cell12, cell13
•Sub-BSS4
•GPU4: cell14, cell15
12
MFS Overview
GPU board connectivity

Max 480 GCH
simultaneously
allocated per GPU
AterMux AterMux
Mix CS/PS Mix CS/PS
Min 1 GSL
Recommended 2
Y to TC
Max 4 GSL
X
to BSC GPU
Min 1 link Z to SGSN
Recommended 2
Min 2 links
Max 8 links
AterMux Gb Max 8 links
Dedicated PS
Max 16 links for all AterMux (BSC, TC) and Gb interfaces

(X + Y + Z <=16)
13
MFS Overview
MxMFS (A9130 MFS Evolution)
HW Architecture
MFS Evolution
• SSW: Switch Gigabit Ethernet
• GP: Radio Processing board for
MFS to manage the user plane
processing
• OMCP: O&M control
• E1 (LIU) Shelf: Up to 256 E1 ports
SSWw GP1
Muxr
(duplicated)
Mux1
Radio Network links
SSWr GPn
LIU1
E1
OMCPw
LIUn OMCPr
LIU Shelf
(21 slots) ATCA Shelf (14 slots)
External Ethernet Links
14
MFS Overview
MxMFS
From G2 MFS to MxMFS
GP Board
GPU GPU
MxMFS
G2MFS NE1oE
GbEthernet
In B9(MR4)/B10 GP capacity = GPUx4
15
MFS Overview
MxMFS
MxMFS HW configurations
MFS MFS
stand-alone stand-alone Rack sharing
TRU TRU TRU
MFS stand alone

Equipment
MFS 9 GP 21 GP
SSW 2
FS
ATCA OMCP 2
M
Shelf 1 GP 1 to 9 9
Spare GP 1
MFS BSC ATCA SSW 2
Shelf 2 GP 1 to 12
E1/LIU Mux 2
Termination shelf LIU board 8 16
Shelf MFS
Termination Termination Termination
Shelf Shelf Shelf BSC
Standard config Large config BSC + MFS config
16
MFS Overview
MxMFS
MxMFS Capacity
Configuration Standard: up to 9+1 GP boards (1 LIU Shelf)
Configuration Large: up to 21+1 GP boards (2 LIU Shelfs)
One A9130 MFS Evolution
can manage up to 3000 cells.
can control up to 21 BSCs.
The maximum number of external links per A9130 MFS is 256.
1xLIU Shelf manage 16xLIU boards
– 1xLIU board for 16xE1 (Tx/Rx)
17
MFS Overview
MxMFS
Synchronisation with two clock modes:
Autonomous timing mode

This mode uses the frequency extracted from one of the 16 PCM to synchronise the
GP and only the GP.
The selected clock is not transmitted to the other GPUs.
The source of synchronisation is by priority order: TC then SGSN then MXBSC which
have both a high accuracy clock.
Centralized timing mode
A GP, synchronised on an external PCM reference, synchronises the other GPs.
The source of synchronisation is by priority order: TC then SGSN then MXBSC which
have both a high accuracy clock.
18
MFS Overview
MxMFS
Dimensioning Rules
One A9130 MFS Evolution can control up to 21 BSCs.
One GP board can support:
– 12 E1 links per GP board for all cases
– up to 16 E1 links (A-ter + Gb), with a maximum of 16 GP board per MFS.
– When the number of GP boards in the MFS is more than 16, the number of
external links per GP is limited, so that the total number of links per MFS
is not exceeded (12 per GP for the maximum MFS configuration of 21 GP).
The maximum number of links from one GP board to the SGSN is 8.
One GP board consists of 4 DSPs. Each DSP supports 480 GCH.
The GP handles less than 1920 GCH to avoid blocking the DSP.
19
MFS Overview
MxMFS
Ater Allocation on LIU boards for Stand-alone MFS with autonomous

synchronization mode (12 E1 per GP)
21 x GPU
9 x GPU
LIU 1 LIU 2 LIU 3 LIU 4 LIU 5 LIU 6 LIU 7 LIU 8 LIU 9 LIU 10 LIU 11 LIU 12 LIU 13 LIU 14 LIU 15 LIU 16
1 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240
2 1 17 33 49 65 81 97 113 129 145 161 177 193 209 225 241
3 2 18 34 50 66 82 98 114 130 146 162 178 194 210 226 242
4 3 19 35 51 67 83 99 115 131 147 163 179 195 211 227 243
5 4 20 36 52 68 84 100 116 132 148 164 180 196 212 228 244
6 5 21 37 53 69 85 101 117 133 149 165 181 197 213 229 245
7 6 22 38 54 70 86 102 118 134 150 166 182 198 214 230 246
8 7 23 39 55 71 87 103 119 135 151 167 183 199 215 231 247
9 8 24 40 56 72 88 104 120 136 152 168 184 200 216 232 248
10 9 25 41 57 73 89 105 121 137 153 169 185 201 217 233 249
11 10 26 42 58 74 90 106 122 138 154 170 186 202 218 234 250
12 11 27 43 59 75 91 107 123 139 155 171 187 203 219 235 251
13 12 28 44 60 76 92 108 124 140 156 172 188 204 220 236 252
14 13 29 45 61 77 93 109 125 141 157 173 189 205 221 237 253
15 14 30 46 62 78 94 110 126 142 158 174 190 206 222 238 254
16 15 31 47 63 79 95 111 127 143 159 175 191 207 223 239 255
Exemples for 3 configurations for 4, 9, and 21 GPUs

Colors shown affectation of LIU per GPU
GPU 1, 5, 9, 13, 17, 21
GPU 2, 6, 10, 14, 18
GPU 3, 7, 11, 15, 19
GPU 4, 8, 12, 16, 20
20
MFS Overview
MxMFS
Ater Allocation on LIU boards for Rack-shared MFS with autonomous

synchronization mode (16 E1 per GP)
8 x GPU
LIU 1 LIU 2 LIU 3 LIU 4 LIU 5 LIU 6 LIU 7 LIU 8
1 1 17 33 49 65 81 97 113
2 2 18 34 50 66 82 98 114
3 3 19 35 51 67 83 99 115
4 4 20 36 52 68 84 100 116
5 5 21 37 53 69 85 101 117
6 6 22 38 54 70 86 102 118
7 7 23 39 55 71 87 103 119
8 8 24 40 56 72 88 104 120
9 9 25 41 57 73 89 105 121
10 10 26 42 58 74 90 106 122
11 11 27 43 59 75 91 107 123
12 12 28 44 60 76 92 108 124
13 13 29 45 61 77 93 109 125
14 14 30 46 62 78 94 110 126
15 15 31 47 63 79 95 111 127
16 16 32 48 64 80 96 112 128
Configurations for 8 GPUs

Colors shown affectation of LIU per GPU
GPU 1, 5
GPU 2, 6
GPU 3, 7
GPU 4, 8
21
MFS Overview
Ater Interface
Dimensioning rules
On the Ater interface, from one up to 8 E1 links can be connected to each GPU
board (A9135 MFS), and up to 13 E1 to each GP board (case with 13 Ater + 3Gb for
A9130 MFS). Each PCM link can be dedicated to packet traffic or shared between
CS and PS traffic.
For security reasons, the timeslots assigned to PS traffic should be spread among
different Ater PCMs. However, when there is enough PS traffic to fill 2 or more
PCMs, there is an advantage to dedicate complete PCMs to PS rather than mixing
PS with CS traffic, and thus avoids wasting TC resource.
It is possible to set PS timeslots on all Ater links coming from BSC; indeed, this can
be useful in the case of configurations with only 2 Ater in order to ensure better
security.
However, it is recommended not to carry PS traffic on the first Ater PCM so that it
can be connected directly to the transcoder in order to enable MFS installation
without O&M interruption on the BSC.
22
MFS Overview
GP board connectivity
Max 1560 GCH
simultaneously
allocated per GP
AterMux AterMux
Mix CS/PS Mix CS/PS
Min 1 GSL
Recommended 2
Y to TC
Max 8 GSL
X
to BSC GP
Min 1 link Z to SGSN
Recommended 2
Min 2 links
Max 13 links
AterMux Gb Max 8 links
Dedicated PS
Max 12, 14 or 16 links for all AterMux (BSC, TC) and Gb interfaces,
depending on MFS configuration (X + Y + Z <= 10/12/14/16)
23
MFS Overview
Gb Interface
The Gb interface connects between the MFS and the SGSN or between the
MSC and the SGSN, in order to exchange the PS signaling and traffic data.
The Gb interface is based on Frame Relay protocol, whether or not an actual
Frame Relay network is set.
On the physical layer, the Gb interface is supported by 2MBit/s PCM links of 32 TS
at 64Kbit/s.
Gb Frame Relay Gb
1) Through a FR Network MFS
Netwok
SGSN
Gb
2) Direct MFS - SGSN connections MFS
Gb
Gb
3) Through NSS transmission network MFS MSC/VLR MSC/VLR
Different types of Gb interface connections
24
MFS Overview
Gb Interface
The maximum number of E1 links handled by a GPU board is 16:

these links have to be shared between AterMux and Gb interfaces.
The maximum number of Gb links from one GPU board to the SGSN is 8.
At least 2 Gb links per GPU are recommended for security reason.
In a multi-GPU configuration, the minimum number of Gb links from one

GPU board to the SGSN is 1 (Secured single Gb feature).
In case of GPU synchronisation by SGSN, this feature is not available.
25
MFS Overview
MFS Capacity
MFS Max Nb of cells in B9 Max Nb of cells in B10

Legacy MFS 2000 cells 2000 cells
MxMFS 3000 cells 4000 cells
GPU/GP Max Nb of cells in B9 Max Nb of cells in B10

GPU 264 cells 264 cells
GP 264 cells 500 cells
Note:
New Gb transport option (B10 MR2)
Gb over UDP/IP/Ethernet as an optional feature
available with MFS (DS10) and with MxMFS
26
2
PS Signaling Architecture
27
Signaling Architecture
PS Signaling protocols
TC
HDLC SCCP/MTP A GSM
CS Signaling Core NW
MCB
RSL for nTRX + 1OML
(n = 1 to 4) N7
Air
AterMUX-CS
BTS Abis
MS Cell TRX
RSL for 1TRX BSC
(FR or HR)
AterMUX-PS
BCCH, CCCH, LAPD GSL
SDCCH, SACCH, Gb
FACCH GPRS
BSCGP MFS
PS Signaling GPU Core NW
Signaling on GSL
- Request the BSC to allocate/de-allocate a PDCH
- Notify the BSC whether there is a MPDCH
- Carry paging, channel request, and access grant if there is no MPDCH
- Receive cell state change information and BSC status
- Load notification (BSC to MFS)
28
BSCGP BSSGP
BSCGP
RRM RRM
Network
service
RLC/MAC
L2-GSL L2-GSL L2-MEGCH L2 - FR

L1-GSL L1-GSL L1-GCH L1 - E1
relay relay
physical physical
layer physical layer layer
RSL GSL
MS BTS BSC MFS

Um Abis Ater Gb
29
Mx BSC PS telecom modules

GPRS
OMCP Telecom
Supervision
V-SCPR
TCH
Resource
Mgt
CCP V-TCU GPRS Radio V-DTC

Frequency GPRS APP
Management
Device Device
Handler Handler
Lapd
Lapd
TP-GSM
Switch
HDLC HDLC
Management
RSL GSL
BTS MFS
30
PS signaling processing in GPU

PMU is managing:
- RRM, PDCH
- BSCGP stack
- PS paging
BSC GPU/GP Board - Gb stack
(with 1 to 6
GPU/GP
boards)
PPC
supports SGSN
GSL PMU, LCU
Gb
RSL AterMux
MS BTS Abis DSP

(cells)
Um supports
MEGCH GCH PTU
PTU is managing:
- RLC/MAC layer
4 DSPs per GPU - L2EGCH layer
- L1EGCH layer
31
Ater PS Signalling in B9
Number of GSL channels

Each GPU or GP board requires at least one GSL channel.
There can be 0 or 1 GSL per A-ter link.
The required number of GSL channels depends on the traffic.
For security reason, it is recommended to have at least 2 GSL channels per GPU or
GP board.
The maximum number of GSL per GPU is 4.
The maximum number of GSL per GP is 8.
The maximum number of GSL per BSC is minimum (12, 4*nbGPU).
The maximum number of GSL per MxBSC is 24.
32
Max Nb of GSL per BSC
Platform Configuration Max GSL

Conf1 4
Conf2 6
Conf3 10
G2
Conf4 12
Conf5 16
Conf6 18
200TRX 16
400TRX 24
MX 600TRX 24
800TRX 24
1000TRX 24
33
The GSL (GPRS signaling links) transports the signaling between the BSC and
the MFS for PS services.
Each GPU or GP board requires at least one GSL channel. For security
reason, it is recommended to have at least 2 GSL channels per GPU or GP
board.
There can be 0 or 1 GSL per A-ter link.

There can be up to:
4 GSL per GPU board
8 GSL per GP board
18 GSL per G2 BSC (due to max 18 Ater links)
24 GSL per BSC Evolution (due to nb of HDLC dedicated for GSL on TPGSM)
34
3
Ater PS Dimensioning
35
Dimensioning methods
At BSC level for AterMux PS dimensioning

Method:
•INPUT •METHOD OUTPUT

Signaling Traffic
Required
GSL Nb of
Nb of
Traffic Erlang C required required PS
GSL per BSC links per
BSC
QoS:
quantile
delay Final nb of
Choose required
“Max” AterMUX-PS
User Traffic value
links per
BSC
Required
GCH Nb of
Nb of
Traffic Erlang C required required PS
GCH per BSC links per
BSC
QoS:
quantile
delay
36

Needed counters for GCH:
– P100c or GAAGCHUST (GPRS_transmission_GCH_busy_time),
– P383a or GQAGALCTT (GPRS_GPU_Ater_cong_time),
– P384 or GQRGPUCDT (GPRS_GPU_DSP_cong_time),
Needed counters for GSL:
– P41 or GTALAPDLN (GPRS_LAPD_DL_traffic_sent_to_BSC),
– P42 or GTALAPULN (GPRS_LAPD_UL_traffic_received_from_BSC).
37

Method for GCH:
P100c
Measured _ GCH _ traffic =
3600
P 383a P 384
%GCH _ Ater _ cong = × 100% %GCH _ GPU _ cong = × 100 %
3600 3600
%GCH _ cong = Max (%GCH _ Ater _ cong ,%GCH _ GPU _ cong )
Measured _ GCH _ traffic

Re quired _ GCH _ traffic =
1− Min (%GCH _ cong ; 30%)
Nb of Re quired GCH = InverseErlangC (Required_GCH_traffic; quantile; delay )
 Nb _ required _ GCH 
Nb _ required _ AterPS _ TSs =  
 4
 No _ required _ AterPS _ TSs 

Nb _ required _ AterPS _ links =  
 28 
38

Method for GSL:
Max ( P 41, P 42 )
Measured _ GSL _ traffic =
28800
Re quired _ GSL _ traffic = Measured _ GSL _ traffic + 30%m arg in
Nb of Re quired GSL = InverseErlangC (Required_GSL_traffic; quantile; delay )
GSL load checking

Measured _ GSL _ traffic
Measured _ traffic _ 1GSL =
Nb of required GSL
Measured _ traffic _ 1GSL
GSL _ load = × 100%
GSL _ Capacity ( = 0.78Erlangs )
It is recommended to increase the number of GSL per GPU if GSL load is greater
than 80%.
The final number of required AterMux PS links is the maximum value between the
number of links needed for signaling traffic (GSL) and for user traffic (GCH).
39
At BSC level for GPU dimensioning

Method:

Signaling Traffic
Required
GSL Nb of
Nb of
Traffic Erlang C required required
GSL per BSC GPU
per BSC
QoS:
quantile
delay Final nb of
Choose required
“Max” GPU boards
User Traffic value
per BSC
Required
GCH Nb of
Nb of
Traffic Erlang C required required
GCH per BSC GPU
per BSC
QoS:
quantile
delay
40

Method: User Traffic (from AterMux PS dimensioning)
 Nb of Required GCH 
Nb of Re quired GPU/GP board =  
 GPU/GP board GCH Capacity 
GPU Capacity is of max 480 GCH.

GP Capacity is of max 1560 GCH.
N_ATER_TS_MARGIN_GPU resources must not be taken into account. So, the max
number of GCH per GPU/GP is:
480 – N_ATER_TS_MARGIN_GPU*4 (for legacy MFS)
1560 – N_ATER_TS_MARGIN_GPU*4 (for Mx MFS)
41

Method: Signaling Traffic (from AterMux PS dimensioning)
 Nb of Required GSL 
 4 
At least 2 GSLs are recommended to be defined per GPU/GP due to security

reason.
Up to 4/8 GSLs can be defined per GPU/GP.
The final number of required GPU/GP boards per BSC is the maximum value
between the number of boards needed for signaling traffic (GSL) and for user
traffic (GCH).
42
At MFS level for GPU dimensioning

Input (counters values):
MS context average
MS context max
DSP congestion
GSL traffic
Average & Max CPU load
BSS failures rate
Output:
Max DL GCH Capacity
Max UL GCH Capacity
Max DL PDCH Capacity
Max UL PDCH Capacity
GSL load
MCS usage
43
GPU limitation
PMU PTU
PPC/CPU DSP
Power Limitation Memory Limitation Power Limitation Memory Limitation
P76a
Dimensioning P392a P201 (thr_1 )
P77a P384
indicators P392b P202 (thr_2 )
=> P402 (thr )
QoS
P105e UL TBF estab P203 P105c
indicators
P105f BSS Failure P204 P105d
(TBF establ)
CPU Cong BSS Fail DSP Load DSP Cong
MFS parameters:
Thr = PMU_CPU_Overload (Default=95%)
Thr_1 = DSP_Load_Thr_1 (Default=85%)
Thr_2 = DSP_Load_Thr_2 (Default=95%)
44

Method:

Signaling Traffic
Required
GSL Nb of
÷
Nb of required PS
Traffic Erlang C required links per
GSL per BSC GPU board
QoS:
quantile Final nb of
delay Choose required
“Max” AterMUX-PS
value
User Traffic links per
GPU
Required
GCH Nb of Nb of
Nb of required required PS
Traffic Erlang C required GPU boards links per
GCH per BSC per BSC GPU board
QoS:
quantile
delay
45

Method: GCH
INPUT METHOD
OUTPUT
GPU_for_MS_context_handling (= 0/1)
User Traffic
Required
+ +
GCH
÷
Traffic Number
Erlang C Needed
of GPU
GCH
boards
QoS:
quantile
delay GCH
capacity GPU_for_Power_Limitation (= 0/1)
of GPU
46

Method: GCH
Needed counters:
P100c or GAAGCHUST (GPRS_transmission_GCH_busy_time),
P383a or GQAGALCTT (GPRS_GPU_Ater_cong_time),
P384 or GQRGPUCDT (GPRS_GPU_DSP_cong_time),
P392b or GTRGPUM (GPRS_MS_idle_context_max),
P201 or GTRGPULDLT (GPRS_DSP_CPU_load_time),
P202 or GTRGPULDOLT (GPRS_DSP_CPU_overload_time),
P402 or GTRGPUOT (GPRS_PMU_overload_time).
47

Method: GCH
P100c
Measured _ GCH _ traffic =
3600
P 383a P 384
%GCH _ Ater _ cong = × 100% %GCH _ DSP _ cong = × 100 %
3600 3600
Max ( P 201, P 202 ) P 402
%DSP _ load = x100 % %CPU _ overload = x100 %
3600 3600
%GCH _ cong = Max(% Ater _ cong ,%DSP _ cong ,%DSP _ load ,%CPU _ overload )
Measured _ GCH _ traffic

Re quired _ GCH _ traffic =
1− Min (%GCH _ cong ; 30%)
Nb of Re quired GCH = InverseErlangC (Required_GCH_traffic; quantile; delay )
 Nb of Required GCH 
GPU/GP board GCH Capacity 
48

Method: GCH
Final number of required GPU/GP =
= Number of required GPU/GP board (from user traffic) +
+ GPU_for_MS_context_handling +
+ GPU_for_Power_Limitation
where:
GPU_for_MS_context_handling = 0 if P392b < 1000 for GPU (4000 for GP)
GPU_for_MS_context_handling = 1 if P392b = 1000 for GPU (4000 for GP)
GPU_for_Power_Limitation = 0 if P402/3600 < 0.1%
GPU_for_Power_Limitation = 1 if P402/3600 > 0.1%
49

Method: GSL
INPUT METHOD •OUTPUT

Signaling Traffic
Required
÷
GSL Nb of
Traffic Nb of required
Erlang C
required GSL links
GSL per BSC per GPU
QoS:
quantile
delay Nb of
required
GPU boards
per BSC
Needed counters:
P41 or GTALAPDLN (GPRS_LAPD_DL_traffic_sent_to_BSC),
P42 or GTALAPULN (GPRS_LAPD_UL_traffic_received_from_BSC).
50

Method: GSL
Number of required GSL per BSC comes from Signaling Traffic value (from
AterMux PS dimensioning)
Number of required GPU board per BSC comes from previous calculations
 Nb of Required GSL per BSC 

Nb of Re quired GSL per GPU/GP =  
 Nb of Re quired GPU/GP board 
If the result is greater than 4 (8), we must increase the number of GPU
(GP) boards with 1, and redo the calculations.
51

Method: GCH
Number of required GCH per BSC comes from previous calculations
Number of required GPU board per BSC comes from previous calculations
 ( Nb _ required _ GCH ) / 112 

Nb _ required _ AterPS _ links _ per _ GPU / GP =  
 Nb _ required _ GPU / GP board 
52
Gb link dimensioning at PVC level

Input (counters values):
PVC downlink Traffic
PVC uplink Traffic
PVC downlink average throughput
PVC uplink average throughput
Customer requirements for QoS (delay and quantile)
Output:
Nb of Gb TS
53

Method:
•INPUT •METHOD •OUTPUT
Required Gb
Traffic
•Erlang C Nb of required
Gb Timeslot per
QoS: link
% Quantile of x
delay sec
Needed counters:
P45 or GTGPVCDLN (GPRS_PVC_DL_traffic_from_SGSN),
P46 or GTGPVCULN (GPRS_PVC_UL_traffic_to_SGSN).
54

Method:
max( P 45,P 46 )
Measured _ Gb _ traffic =
28800
Re quired _ Gb _ traffic = Measured _ Gb _ traffic + 15%m arg in
No _ Gb _ TS _ per _ link = ErlangC (Re quired _ Gb _ traffic ; quantile; delay )
The maximum number of Gb links from one GPU/GP board to the SGSN is 8.
Maximum 31 Gb TS (TS no. 1 to 31) can be configured per one Gb link.
55
Gb over FR configuration
Parameters:
Tc (Measurement interval) = 1s
CBS (Committed Burst Size)
Bit rate
CIR (Committed Information Rate) ACCESS_RATE_BC
EIR
CIR = (CBS*8)/Tc
NIR (Normal Information Rate) EBS
NIR ≥ CIR NIR
CIR
EBS (Excess Burst Size) CBS
EIR (Excess Information Rate)
T time
EIR = CIR+EBS*8/Tc
AC (Access Rate Bearer Channel)
AC ≥ CIR(1+EBS/CBS)
NbGbTS = AC/64kbps
56
Rules if no direct access is used between MFS and SGSN:
CIR ≤ NIR ≤ CIR x (1 + EBS/CBS) ≤ ACCESS_RATE_BC
Example:
Parameter value unit

Tc 1 s
CBS 124 kbyte
CIR 992 kbps
NIR ≥ 992 kbps
EBS 2 kbyte
EIR 1008 kbps
AC ≥ 1008 kbps
NbGbTS 16 number
57
Rules if direct access is used between MFS and SGSN:
CIR = 0 <=> CBS = 0 => EBS > 0 (mandatory)
NIR = 0 (recommanded)
EBS = ACCESS_RATE_BC (expressed in kbit/s)/8, if CIR = 0 (recommanded)
Example:
For CBS = 0; CIR = 0 and NIR = 0:
Parameter value unit

Tc 1 s
EBS 160 kbyte
AC ≥ 1280 kbps
EIR 1280 kbps
NbGbTS 20 number
58
4
Ater PS Optimization
59
Ater optimization
Ater optimization goals:

To globally increase the ratio “actual Gb throughput / Ater resources
needed” on the GPUs
The optimization of the total amount of Ater resources needed on the GPU to
support its PS traffic will allow to reduce the number of Ater links of the GPUs.
To decrease the number of TBF establishment failures due to lack of Ater
resources (for a fixed amount of Ater resources available)
A non-optimal usage of Ater resources can lead to failure/blocking situations for
the incoming traffic on the GPU due to the Ater congestion.
60
Ater optimization
Algorithmic changes:
The purpose of the technical corrections is to establish (at most) n GCHs for
each short TBF (“short TBF” meaning signalling or short data transfer TBF),
n being a low number.
Definition of the MS transfer of a given MS:
2 possible values: “short data” or “data”.
An MS transfer is considered to be “short data” as long as less than
N_DATA_BYTES_MAX_TRANS bytes have been transferred in both directions (since
the TBF establishment(s)).
Else, if more than N_DATA_BYTES_MAX_TRANS bytes have been transferred in at
least one direction, the MS transfer is considered to be “data”.
A “short data” MS transfer is supposed to cover both the GMM traffic case
(signalling case) and the cases of short “actual” data (e.g. short blackberry
terminal transfers).
61
Ater optimization
Algorithmic changes:
Definition of the MS transfer of a given MS:
For an MS, only a transition from “short data” to “data” MS transfer is

possible (but not from “data” to “short data”) as long as it is in Packet
Transfer Mode.
UL TBF TBF TBF

time
DL TBF TBF TBF
MS transfer short data NA short data NA

data data
In DL, both the bytes sent (from RRM to RLC) and the bytes of the DL LLC PDUs
currently queued for the MS (but not yet sent from RRM to RLC) shall be counted.
In UL, only the bytes received (by RRM from RLC) are counted.
62
Ater optimization
Behaviour when there are only MSs in “short data” transfer on a TRX
The maximum allowed (M)CS during a “short data” transfer is (M)CS2 in UL
and (M)CS1 in DL (even if there are more than 1 GCH established on the
TRX).
Min_Nb_GCH = 1, whatever the number of “short data” MS transfers on the

TRX.
Target_Nb_GCH = number of GCHs necessary so that each “short data”
EGPRS transfer can benefit from MCS1/2 on 3 PDCHs, i.e. 3 GCHs for each
“short data” EGPRS transfer.
Examples:
On a TRX supporting 2 “short data” TBFs, Target_Nb_GCH = 2 MSs x 3 GCHs = 6.
On a TRX supporting 4 “short data” TBFs, Target_Nb_GCH = 8 (4 MSs x 3 GCHs is
truncated to 8 because a 9th or more GCH would remain unused due to 8
PDCH/TRX and Max (M)CS =2).
63
Ater optimization
Behaviour when there are only MSs in “data” transfer on a TRX:

The maximum allowed (M)CS of the TBF is computed as in the current B9
algorithms. Idem for Min_Nb_GCH and Target_Nb_GCH.
64
Ater optimization
Behaviour when there are both MSs in “short data” and “data” transfer on a
TRX:
The total number of GCHs targeted for the TRX is the sum of the number of
GCHs targeted for the MSs in “data” transfer and of the number of GCHs
targeted for the MSs in “short data” transfer.
The goal is here to avoid that a (long) “data” traffic is disturbed by
(potentially many) “short data” traffics on the same TRX.
Example:
If, on a given TRX, 1 EGPRS TBF in “data” MS transfer is established on 4 PDCHs
and 1 EGPRS TBF in “short data” MS transfer is established on the remaining 4
PDCHs, then Target_Nb_GCH = 18 (for the “data” TBF) + 3 (for the “short data”
TBF) = 21.
(If only 18 GCHs were targeted instead of 21 GCHs, there would be no guarantee
for the “data” EGPRS TBF traffic not to be disturbed by “short data” TBF traffics,
especially in case of MCS-9 used on the 4 PDCHs of the “data” EGPRS TBF).
65
Ater optimization
Behaviour on transition from “short data” to “data” transfer for a given MS:
The maximum allowed (M)CS of the TBF is immediately reassessed (in order
to be increased immediately, if it is possible according to the current
number of GCHs established on the TRX).
Additional GCH establishments are also triggered.
66
Ater optimization
The previous algorithmic changes will only be applied when the global usage
of Ater resources in the GPU has reached a certain level:
A new threshold called Ater_Usage_Threshold_Short_Data is defined: “threshold
(percentage of used Ater nibbles in a GPU) above which the Ater usage is
optimized for short data TBF traffic”.
The optimizations will only be applied to the TBFs established while above this
threshold. Otherwise (i.e. while below this threshold), MS transfers are always
considered as “data”.
This will have for advantages that:
Ping times (measured in basic conditions where there is little or no PS traffic in
the GPU) are not degraded (e.g. 1000-byte pings),
Data transfers are not delayed if the new Ater_Usage_Threshold_Short_Data
threshold is not reached.
Even if it is not recommended (for the above reasons), this threshold can be set
to 0% in order to always activate the optimizations.
67
Ater optimization
PS traffic degradations expected:

Data transfer (PS setup time, Ping, FTP) impacted by some delays in the
order of several twenties of ms depending on the scheme and on the MS
reaction time.
Those degradations will only appear when the Ater consumption has
reached a certain level in the GPU (Ater_Usage_Threshold_Short_Data
threshold customizable by the operator).
When the Ater consumption is below this threshold, there is no
degradation compared to the current B9 algorithms.
68
5
Telecom Parameters
69
Telecom Parameters
New telecom parameters

Ater_Usage_Threshold_Short_Data: threshold (percentage of used Ater
nibbles, in a GPU) above which the Ater usage is optimized for “short data”
MS transfers,
N_DATA_BYTES_MAX_TRANS (= 150 bytes by default): number of bytes

below which an MS transfer is considered to be “short data”,
MAX_GPRS_CS_SHORT_DATA_UL (= CS-2 by default): maximum allowed
CS of the “short data” UL GPRS TBFs,
MAX_GPRS_CS_SHORT_DATA_DL (= CS-1 by default): maximum allowed

CS of the “short data” DL GPRS TBFs,
70
Telecom Parameters

MAX_EGPRS_MCS_SHORT_DATA_UL (= MCS-2 by default): maximum
allowed MCS of the “short data” UL EGPRS TBFs,
MAX_EGPRS_MCS_SHORT_DATA_DL (= MCS-1 by default): maximum

allowed MCS of the “short data” DL EGPRS TBFs,
INIT_PDCH_SHORT_DATA_EGPRS (= 3 by default): number of PDCHs on

which the above Max MCSs are targeted when establishing GCHs for a
“short data” EGPRS TBF.
INIT_PDCH_SHORT_DATA_GPRS (= 2 by default) (similar definition for

GPRS).
71
Telecom Parameters
OMC-R Default
System Name Instance Unit Min Max Definition
modifiable Value
Threshold (percentage of used Ater nibbles, in a
Ater_Usage_Threshold_Short_Data None (DLS) MFS % 0 100 100 GPU) above which the Ater usage is optimized
for “short data” MS transfers.
Number of PDCHs on which
MAX_GPRS_CS_SHORT_DATA_DL and
INIT_PDCH_SHORT_DATA_GPRS None (DLS) MFS None 1 8 2 MAX_GPRS_CS_SHORT_DATA_UL are
targeted when establishing GCHs for a GPRS
TBF associated to a “short data” MS transfer.
Number of PDCHs on which
MAX_EGPRS_MCS_SHORT_DATA_DL and
INIT_PDCH_SHORT_DATA_EGPRS None (DLS) MFS None 1 8 3 MAX_EGPRS_MCS_SHORT_DATA_UL are
targeted when establishing GCHs for an EGPRS
TBF associated to a “short data” MS transfer.
Maximum coding scheme used for the UL GPRS
MAX_GPRS_CS_SHORT_DATA_UL None (DLS) MFS None 1 4 2
TBFs associated to a “short data” MS transfer.
Maximum coding scheme used for the DL GPRS
MAX_GPRS_CS_SHORT_DATA_DL None (DLS) MFS None 1 4 1
TBFs associated to a “short data” MS transfer.
Maximum Modulation and Coding Scheme used
MAX_EGPRS_MCS_SHORT_DATA_UL None (DLS) MFS None 1 9 2 for the UL EGPRS TBFs associated to a “short
data” MS transfer.
Maximum Modulation and Coding Scheme used
MAX_EGPRS_MCS_SHORT_DATA_DL None (DLS) MFS None 1 9 1 for the DL EGPRS TBFs associated to a “short
data” MS transfer.
72
Telecom Parameters
OMC-R Default
System Name Instance Unit Min Max Definition
modifiable Value
Number of bytes below which an MS
N_DATA_BYTES_MAX_TRANS None (DLS) MFS byte 20 10000 150
transfer is considered to be “short data”.
Number of bytes above which a transition
from “short data” to “long data” MS transfer
N_DATA_BYTES_MAX_TRANS_PERIODIC None (DLS) MFS byte 100 100000 10000 shall be periodically reattempted (only useful
in the rare cases where such a transition
previously failed).
Multiplication factor used in the computation
of the maximum number of UL TBFs allowed
TBF_GCH_RATIO_UL None (DLS) MFS none 0.1 5 1 to be established on a TRX for a given
number of GCHs on this TRX (i.e. in the M-
EGCH link of this TRX).
Multiplication factor used in the computation
of the maximum number of DL TBFs allowed
TBF_GCH_RATIO_DL None (DLS) MFS none 0.1 5 1 to be established on a TRX for a given
number of GCHs on this TRX (i.e. in the M-
EGCH link of this TRX).
73
Telecom Parameters
Parameter settings:
Ater_Usage_Threshold_Short_Data: threshold (percentage of used Ater nibbles,
in a GPU) above which the Ater usage is optimized for “short data” MS transfers.
Subsystem = MFS, instance = MFS, category = Network (CDE), OMC-R = None (DLS),
range 0% .. 100%, default value = 100% (corrections “disabled” by default).
Recommended value when not “disabled”: 30%.
A low value will be beneficial to long data transfers (because no GCHs will be
"wasted" due to "signalling" or short data traffics in other cells),
A high a value will tend to avoid the degradations (compared to the current B9
algorithms) induced by the proposed evolutions.
“Ater_Usage_Threshold_Short_Data <= Ater_Usage_Threshold – 30%” is
recommended.
0% = the Ater optimizations are always « ON ».
100% = the Ater optimizations are always « OFF ».
For Ater resource saving, a low value of Ater_Usage_Threshold_Short_Data is
coherent with a low value of the T_GCH_INACTIVITY and T_GCH_INACTIVITY_LAST
timers.
74
Telecom Parameters
Ater usage:
GCH reduction factor

Reduced
appliedfactor
for allapplied
Data
for
(likeallinData
B9)
Nb GCH used
Ater usage is high
Ater_Usage_Threshold
always «OFF» 100%
Ater usage is low
Reduced GCH allocation

for Short Data (B10)
Ater_Usage_Threshold_Short_Data delays may occur
30%
Normal GCH allocation

(like in B9)
no degradation
always «ON» 0%
PS Traffic
75
Telecom Parameters
Parameter settings:
N_DATA_BYTES_MAX_TRANS: number of bytes below which an MS transfer is
considered to be “short data”.
Subsystem = MFS, instance = MFS, category = Network (CDE), OMC-R = None (DLS),
default value = 150 bytes.
Decreasing (respectively increasing) the value of N_DATA_BYTES_MAX_TRANS will
tend:
– to make the Ater resource optimization worse (respectively better) when
the Ater usage of the GPU is above Ater_Usage_Threshold_Short_Data,
– to reduce (respectively make higher) the PS throughput degradations at
the beginning of MS traffics when the Ater usage of the GPU is above
Ater_Usage_Threshold_Short_Data.
In case of usage of MCS-6 (i.e. TBF_UL/DL_INIT_MCS = MAX_EGPRS_MCS_SHORT_
DATA_UL/DL = MCS-6), N_DATA_BYTES_MAX_TRANS = 148 bytes can be slightly
more efficient in terms of performances than 150 bytes.
76
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Ater PS and GPU/GP Dimensioning in B9 &

Ater Optimization in B10

3 | AterPS & GPU/GP | 2008 © Alcatel-Lucent , d.r., 2008

4 | AterPS & GPU/GP | 2008 © Alcatel-Lucent , d.r., 2008

BSS Architecture in B9 with Mx Platform

5 | AterPS & GPU/GP | 2008 © Alcatel-Lucent , d.r., 2008

BSS Architecture in B10

6 | AterPS & GPU/GP | 2008 © Alcatel-Lucent , d.r., 2008

BSS Architecture in B10 with Mx Platform

7 | AterPS & GPU/GP | 2008 © Alcatel-Lucent , d.r., 2008

Packet Data CHannel scheduling, power control, ...

8 | AterPS & GPU/GP | 2008 © Alcatel-Lucent , d.r., 2008

9 | AterPS & GPU/GP | 2008 © Alcatel-Lucent , d.r., 2008

MFS HW versions and capacities:

A9135 MFS (first generation)

10 | AterPS & GPU/GP | 2008 © Alcatel-Lucent , d.r., 2008

11 | AterPS & GPU/GP | 2008 © Alcatel-Lucent , d.r., 2008

•cell7 •GSL2 •GPU

12 | AterPS & GPU/GP | 2008 © Alcatel-Lucent , d.r., 2008

GPU board connectivity

Max 16 links for all AterMux (BSC, TC) and Gb interfaces

13 | AterPS & GPU/GP | 2008 © Alcatel-Lucent , d.r., 2008

MxMFS (A9130 MFS Evolution)

External Ethernet Links

14 | AterPS & GPU/GP | 2008 © Alcatel-Lucent , d.r., 2008

From G2 MFS to MxMFS

In B9(MR4)/B10 GP capacity = GPUx4

15 | AterPS & GPU/GP | 2008 © Alcatel-Lucent , d.r., 2008

MFS stand alone

Standard config Large config BSC + MFS config

16 | AterPS & GPU/GP | 2008 © Alcatel-Lucent , d.r., 2008

17 | AterPS & GPU/GP | 2008 © Alcatel-Lucent , d.r., 2008

Synchronisation with two clock modes:

Autonomous timing mode

18 | AterPS & GPU/GP | 2008 © Alcatel-Lucent , d.r., 2008

19 | AterPS & GPU/GP | 2008 © Alcatel-Lucent , d.r., 2008

Ater Allocation on LIU boards for Stand-alone MFS with autonomous

Exemples for 3 configurations for 4, 9, and 21 GPUs

20 | AterPS & GPU/GP | 2008 © Alcatel-Lucent , d.r., 2008

Ater Allocation on LIU boards for Rack-shared MFS with autonomous

Configurations for 8 GPUs

21 | AterPS & GPU/GP | 2008 © Alcatel-Lucent , d.r., 2008

22 | AterPS & GPU/GP | 2008 © Alcatel-Lucent , d.r., 2008

23 | AterPS & GPU/GP | 2008 © Alcatel-Lucent , d.r., 2008

Different types of Gb interface connections

24 | AterPS & GPU/GP | 2008 © Alcatel-Lucent , d.r., 2008

The maximum number of E1 links handled by a GPU board is 16:

In a multi-GPU configuration, the minimum number of Gb links from one

25 | AterPS & GPU/GP | 2008 © Alcatel-Lucent , d.r., 2008

MFS Max Nb of cells in B9 Max Nb of cells in B10

GPU/GP Max Nb of cells in B9 Max Nb of cells in B10

26 | AterPS & GPU/GP | 2008 © Alcatel-Lucent , d.r., 2008

27 | AterPS & GPU/GP | 2008 © Alcatel-Lucent , d.r., 2008

28 | AterPS & GPU/GP | 2008 © Alcatel-Lucent , d.r., 2008

L2-GSL L2-GSL L2-MEGCH L2 - FR

MS BTS BSC MFS

29 | AterPS & GPU/GP | 2008 © Alcatel-Lucent , d.r., 2008

Mx BSC PS telecom modules