HW 3.

Draw the next-state map for the followingsystem.:

HW 4.

What is the internal (state) variable? What is it importance?

A state variable is one of the set of variables that are used to describe the mathematical "state" of a
dynamical system. An internal (state) variable is needed to completely describe the behavior of the
network.

Compare the Mealy and Moore type of sequential network models!

Completethe truth table of an JK latch.What is the most important difference between the JK
and RS latches?
K J Qn+1
0 0 n
0 1 1
1 0 0
1 1 Q

Differencies:
Compare the synchronous and asynchronous networks!

Asynchronous sequential networks

•The change at the input can cause the states and outputs to change at any time

•Asynchronous operation

•The behavior of the circuit is influenced by unpredictable external factors

•Due to the unwanted timing effects unstable states, race and oscillation may occur

•Carefull design techniques needed to implement an asynchronous logic network

Synchronous sequential networks

•The effects of uncontrollable time-delay in synchronous circuits can be eased by the use of
synchronization signal

•Circuits where a clock signal is used to control operation are called synchronous sequential circuits

•The state changes can occur at the synchronization intervals specified by the clock

•The effect of the input change is not immediate only produces effect on the next clock period

–Considering the transient time the clock period has to be chosen to be long enough

–After the transienttimethe signals are static

•In the inactive clock period the primary and secondary variables prepare to the next cycle
HW5

How many memory cells would you put in a cell row, if the stored information is typically 2 bytes?

16

Draw the general structure of a memory.

What kind of memory would you use in an embedded equipment (e.g. hand-held blood pressure
measurement device)? Explain your answer (parallel/serial, independent/universal lines). What kind
of memory would you use in a laptop for system memory? Again, explain your answer.

a) serial, independent, because: - slow, but it doesn’t matter(+some things I can’t find RN)
b) serial, universal, beacuse: -less energy, -fast (+some things I can’t find RN)

Draw the scheme of creating a 16k * 16 memories from two 16k * 8 memories.:

same as here, just write 16k to one of the blocks, and ignore the numbers
Draw the scheme of creating a 16k * 16 memories from two 8k * 16memories.

Same as here, just use only 2 blocks in the drawning, and in the schamethic too. Also, change the
numbers to 2x 8k*16 = 16k*16
HW 6.

Draw the schematic of a DDL inverter:

there’s no inverter in diode logic.

Draw the schematic of a DTL NOR gate.

Draw the schematic of a TTL NAND gate.

What are the general properties of TTL circuits?

Statical behavious

•Well-separatedlogicallevels, relatively good resistence against noise

Draw the schematic of an inverter realized with NMOS FET.

(I guess)
Draw the schematic of an inverter realized with PMOS FET

What are the benefits of FET circuits?

High input resistance(almost ideally voltage-controlled)

Relatively insensitive(from several aspect)

 Homework 7
Draw the schematic of a CMOS inverter created from an NMOS and a PMOS
transistor.

Draw the schematic of a CMOS NOR gate.

How would you realize a CMOS AND gate? Draw it.

What is the benefit of a pull-up/pull-down resistor? Explain it briefly.

For those V1 ..Vn input combinations that provide logical 1 on the output, Vdd and
Vout are connected. Otherwise: break between Vdd and Vout
For those V1 ..Vn input combinations that provide logical 0 on the output GND and
Vout are connected – Otherwise: break between GND and Vout
The floating CMOS input results in uncertain output
A TTL gate considers floating input to logical 1
MOS transistor might fail
Floating inputs should not be used, not even for unused gates!
A pull-up or pull-down resistor is the simplest solution
Explain the phenomena of hysteresis.
The gate operates in region 2 for relatively long time: ID ≠ 0 → substantial power
requirement – Noise superposed on the input signal might result in multiple changes
Similar problem to the analogous comparator, can be solved the same way
We need to form a transfer characteristic with hysteresis » By modifying gate circuits
» Two comparison levels » Schmitt trigger
How would you connect a TTL and a CMOS circuit?
Load can be directly connected („lightbulb”, relay etc.)
The output can be connected to supply voltage that is different from that of the
driving circuit
Logical families with different supply voltages can be interfaced
Wired AND connection is possible
Bus lines
What problems arise when using bus lines? Explain the solutions (tri-state
output, bidirectional driving)
Bus-hold: If all of the tree-state output is high impedance („Z”) Floating input in the
inverter
In contrast to TTL, floating input in CMOS should be always avoided
Bi-directional bus Needs special (bi-directional) bus driving circuits – Normal buffer +
– Tri-state buffer
 Homework 8

Draw the process for development of digital circuits.

Specification:
Defines at different levels what tasks needs to be done
How is it structured
Specification of modules and subsystems
HW description:
Developer source code (HDL)
Behavior given in the specification described with HDL syntax
Module representations, bus and wire connectivity
Formal check (typically built-in syntax check) » Correct syntax does not mean, that it
can be synthesized » Digital electronics will realize the description
Synthesis:
HW description, the plan is „compiled” to physical hardware components
he function given in the plan is realized with physical digital electronics
Result is a connectivity list » IC, ASIC: IC design at transistor or gate level »
Programmable logic: List of connection between components, initializations
(configuration file, software)

What are the main components of an FPGA? Explain their functions.

Configurable logic blocks (CLBs):elements, capable to implement logic functions and
storage function
Input/Output blocks (IOBs): They realize the data flow on the in- and output
(environment) and between the inner logic elements. They provide two-way and 3-
state interfaces and connections between digital signals with different communication
standards and different voltage levels.
Block RAM: Memory elements capable to store data.
Multiplier: Elements, capable to fast multiply two binary number on 18 bit.
Digital clock manager block (DCM): Programmable element for clock handling.
Functionalities: delay, frequency multiplication/division, phase shift.
Which type of programmable logic device would you use to implement the
following items?
Explain your answer.
Digital switch PLA
MP3 player CPLD
Wi-Fi router CPLD
Rocket control FPGA
What are the differences between white box and black box testing?
Black box testing: Testing without knowing the internal structure of code/program • A-
priori knowledge is not necessary • Focusing on functionality • Can be run in
application environment • (Typically used in high level testing)
White box testing: Testing by knowing the internal structure of code/program • Needs
a-priori information and programming knowledge • Focusing on internal behaviour •
Can be run only in development environment • (Typically used in low level testing)
Which test cases would you use to test the following conditions by using
boundary value analysis?
a > x ; b < x ; c > y , where x and y are variables, a, b, and c are constants.