CS302 MCQS

Which sequential circuits are applicable for counting pulses?

 a: Counters b: Flip Flops c: Registers d: Latches
A decimal counter has ______ states.
a: 5  b: 10  c: 15 d: 20
A counter is implemented using three (3) flip-flops, possibly it will have ________
maximum output status.
a: 3  b: 7 c: 8 d: 15
Counter is a ____________ .
 a: Combinational circuit b: Sequential circuitc: Both d: None
One of the major drawbacks to the use of asynchronous counters is that
____________
a: Low-frequency applications are limited because of internal propagation delays b:
High-frequency applications are limited because of internal propagation delays c:
Asynchronous counters do not have major drawbacks and are suitable for use in high-
and low-frequency counting applications d: Asynchronous counters do not have major
drawbacks and are suitable for use in high- and low-frequency counting applications
Divide-by-32 counter can be acheived by using    

Flip-Flop and DIV 10 

Flip-Flop and DIV 16 
Flip-Flop and DIV 32 
DIV 16 and DIV 32
Divide-by-160 counter is acheived by using  
Flip-Flop and DIV 10 
Flip-Flop and DIV 16 
DIV 16 and DIV 32 
DIV 16 and DIV 10

A Divide-by-20 counter can be acheived by using  

Flip-Flop and DIV 10 
Flip-Flop and DIV 16 
Flip-Flop and DIV 32 
Div 10 and DIV 16

Divide-by-160 counter is acheived by using

  Flip-Flop and DIV 10

   Flip-Flop and DIV 16
  DIV 16 and DIV 32
  DIV 16 and DIV 10

the terminal count of a modulus-13 binary counter is  

0000 
1111 
1101 
1100

the terminal count of a modulus-11 binary counter is  1010

the terminal count of a typical modulus-10 binary counter is  1001

To implement the counter using S-R flip-flops instead of J-K flip-flops, the _S-
R____ transition table is used.
Bi-stable devices remain in either of their two states unless the inputs force the
device to switch its state
We have a digital circuit. Different parts of circuit operate at different clock
frequencies (4MHZ, 2MHZ and 1MHZ), but we have a single clock source
having a fix clock frequency (4MHZ), we can get help by
___________
►Using S-R Flop-Flop
►D-flipflop
►J-K flip-flop
►T-Flip-Flop

An Astable multivibrator is known as an Oscillator which does not have any

stable state. Therefore it continuously changes from one unstable state to the
other without any external trigger
The power consumed by a flip-flop is defined by P = Vcc x Icc.

Assume a J-K flip-flop has 1s on the j and k inputs. The next clock pulse will
cause the output to- Toggle

Once the state diagram of the sequential circuit is defined, a Next-State Table is
derived

  An Asynchronous Down-counter is implemented (Using J-K flip-flop) by

connecting______  

Q output of all flip-flops to clock input of next flip-flops 

Q’ output of all flip-flops to clock input of next flip-flops 
Q output of all flip-flops to J input of next flip-flops 
Q’ output of all flip-flops to K input of next flip-flops

when the same clock signal arrives at different times at different clock
inputs to propagation delay Clock skew

For a down counter that counts from (111 to 000), if current state is "101" the next
state will be  _______    

111 
110 
010 
none of given options

Answer is 100

In positive edge trigerred when s=1 r=0 then Q is 1

The terminal count of a 4-bit binary counter in up-mode is 1111, and 0000 in
down-mode.
In gated D-latch when EN=1 and D=1 then Q is 1
One-shot mono-stable contains NOR,RESISTER,CAPACITOR,NOT
A counter is implemented using three (3) flip-flops, possibly it will
have ______  maximum output status.  
3 
7 
8 
15
  __________ is said to occur when multiple internal variables change due to change
in one input variable  
Hold and Wait 
Clock Skew 
Race condition 
Hold delay
The Sequential circuit whose output depends on the current state and
the input is known as Mealy Machine.
 Three cascaded modulus-10 counters have an overall modulus of    
30 
100 
1000 
10000
 four cascaded modulus-10 counters have an overall modulus of    
30 
100 
1000 
10000
A synchronous decade counter will have _____ flip-flops.  
3 
4 
7 
10
RCO stands for ________  
Reconfiguration Counter Output 
Ripple Counter Output 
Reconfiguration Clock Output 
Ripple Clock Output
A 4- bit UP/DOWN counter is in DOWN mode and in the 1010 state. on the next
clock pulse, to what state does the counter go?

1001 
1011 
0011 
1100
In a 4-bit binary counter, the next state after the terminal count in the DOWN
mode is__________
       0000
       1111
       0001
       10000
The flip-flop is connected to +5 volts and it draws 5 mA of current
during its operation, therefore the power dissipation of the flip-flop is 25 mW.
Flip-Flops are synchronous bi-stable devices, known as bi-stable multivibrators.
A decade counter is  ________  
Mod-3 counter 
Mod-5 counter 
Mod-8 counter 
Mod-10 counter
A positive edge-triggered flip-flop changes its state on a low-to-high transition of
the clock and a negative edge-triggered flip-flop changes its state on a high-to-
low transition of the clock
In case of cascading Integrated Circuit counters, the enable inputs and RCOof
the Integrated Circuit counters allow cascading of multiple counters together
True 
False
Thus, when the 1 Hz sampling interval is selected, the signal at the output of the
J-K flip-flop has a time period of 2 seconds
The n flipflops store 2n states.
The minimum time required for the input logic levels to remain stable before the
clock transition occurs is known as the Set-up time
The synchronous counters are also known as Ripple Counters
false(asynchronous)
A 4-bit binary UP/DOWN counter is in the binary state zero. the next state in the
DOWN mode is___________  

0001 
1111 
1000 
1110
  A flip-flop is presently in SET stae and must remain SET on the next cliock pulse.
What must j and K be?  
J = 1, K = 0 
J = 1, K = X(Don't care) 
J = X(Don't care), K = 0 
J = 0, K = X(Don't care)
in master-slave flip-flop clock signal is connected to slave flip-flop
using.NOT.....gate
Master-Slave flips have two stages each stage works in one half of the clock
signal
If the S and R inputs of the gated S-R latch are connected together using a NOT
gate then there is only a single input to the latch.
The minimum time for which the input signal has to be maintained at the input
is the Hold time of the flip-flop.
If a circuit suffers “Clock Skew “ problem, the output of circuit can’t be
guarantied.
Select correct option:
            True 
            False
If data is brought into the J terminal and its complement to the K terminal, a J-
K flip-flop operates as a(n) __D FLIP FLOP______.
In gated SR latch,what is the value of output if EN=1,S=0,and R=0 Qt

The low to high or high to low transition of the clock is considered to be

a(n)--------------.

Ans. Edge

Two states are said to be equal if they have exactly same output

A mono-stable device only has a single stable state and it remains in its stable
state true
the Asynchronous input overrides the Synchronous input
Master-Slave flip-flops have become obsolete
The characteristic equation of D-flipflop implies that _next state is independent
of present state____.
The counter states or the range of numbers of a counter is determined by the
formula. (“n” represents the total number of flip-flops (2 raise to power n)
The 74HC163 is a 4-bit Synchronous Counter.it has.......4.......data output pins 
In synchronous digital circuits the output of one flip-flop is connected to the
input of a second flip-flop,
Design of state diagram is one of many steps used to design any counter
A synchronous decade counter will have ___4__ flip - flops
 ___asynchronous______ Counters as the name indicates are not triggered simultaneously

Karnaugh map is used in designing.  

a clock 
a counter 
an UP/DOWN counter 
All of the above
The glitches due to "Race Condition" can be avoided by using a ___Negative-Edge triggered
flip-flops______  
A decade counter can be implemented by truncating
the counting sequence of a MOD-20 counter. false
The 3-bit up counter can be implemented using ---- S-R flip-flops and D flip-flops----
In Master-Slave flip-flop setup, the master flip flop operates at Both Master-Slave
operate simultaneously
When both the inputs of edge-triggered j-k flip-flop are set logic zero__the
output of the flip-flop remains unchanged___

The __J-K___ inputs can be directly mapped to Karnaugh maps

The D flip-flop has _1______ input. 2 Outputs

 A  In D flip-flop, if clock input is LOW, the D input _ Has no effect

D flip-flop can be constructed from an __S-R____ flip-flop.

 In D flip-flop, if clock input is HIGH & D=1, then output is _ 0

Which statement describes the BEST operation of a negative-edge-triggered D flip-

flop?The logic level at the D input is transferred to Q on NGT of CLK

Which of the following is correct for a gated D flip-flop?Q output follows the input D
when the enable is HIGH

 With regard to a D latch _The Q output follows the D input when EN is

HIGH_______

Which of the following describes the operation of a positive edge-triggered D flip-

flop? The output will follow the input on the leading edge of the clock