Converting CY7C630XX/1XX Designs to the CY7C637XX
Introduction
This application note describes the differences between the
CY7C630xx/1xx and the CY7C637xx and how to convert
designs using the CY7C630xx/1xx Universal Serial Bus
(USB) controller to the CY7C637xx USB microcontroller. The
document starts with an introduction to the CY7C630xx/1xx
and the CY7C637xx USB controllers, followed by the
Hardware Differences section, and ending with the
Suggested Firmware Changes section.
This application note assumes that the reader is familiar with
the CY7C630xx/1xx USB controller and the USB. The
CY7C630xx/1xx and CY7C637xx data sheets are available
from the Cypress web site at www.cypress.com. USB
documentation can be found at the USB Implementers Forum
web site at www.usb.org.
Introduction to the CY7C630xx/1xx
The CY7C630xx/1xx is an 8-bit RISC microcontroller with an
integrated USB Serial Interface Engine (SIE). The archi-
tecture implements 34 commands. The CY7C630xx/1xx has
built-in clock oscillator and timers as well as programmable
current drivers, and pull-up resistors at each I/O line.
Clock Circuit
The CY7C630xx/1xx has a built-in clock oscillator and
PLL-based frequency doubler. This circuit allows a 6MHz
ceramic resonator to be used externally while the on-chip
RISC core runs at 12 MHz.
USB Serial Interface Engine
The internal SIE simplifies the interface to the USB bus for the
user. In the receive mode, USB packet decode and data
transfer to the endpoint FIFO are automatically done by the
SIE. The SIE then generates an interrupt request to invoke a
service routine after a packet is unpacked.
In the transmit mode, data transfer from the endpoint and the
assembly of the USB packet are handled automatically by the
SIE.
General Purpose I/O
The CY7C630xx/1xx has up to 12 general purpose I/O
(GPIO) lines divided into two ports: Port 0 and Port 1. Each
GPIO can be configured in current sink mode, resistive, or
Hi-Z mode as shown in Table 1.
Table 1. Programmable Output State
Port Data Bit Port Pull-up Bit Output State
0 X sink current “0”
1 0 pull-up resistor “1”
1 1 High-Z
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Writing a “0” to the Data Register will drive the output low and
allow it to sink current. Instead of supporting a fixed output
drive, the CY7C630xx/1xx allows the user to select an output
current level for each I/O line. The sink current of each output
is controlled by a dedicated 8-bit Isink Register. The lower
four bits of this register allow the developers to select one of
16 sink current levels. The upper four bits are reserved and
must be written as 0s. The output sink current levels of the
two GPIO ports are different. For Port 0 outputs, the lowest
drive strength (0000) is about 0.2 mA and the highest drive
strength (1111) is about 1.0 mA. Port 1 outputs are specially
designed to drive high-current applications such as LEDs.
Each Port 1 output is much stronger than their Port 0 counter
parts at the same drive level setting. The lowest and highest
drive for Port 1 pins are 3.2 mA and 16 mA, respectively.
Each GPIO is capable of generating an interrupt to the RISC
core. Interrupt polarity is selectable on a per bit basis using
the Port Pull-up Register. Setting a Port Pull-up Register bit
to “1” selects a rising edge trigger for the corresponding GPIO
line. Conversely, setting a Port Pull-up Register bit to “0”
selects a falling edge trigger. The interrupt triggered by a
GPIO line is individually enabled by a dedicated bit in the Port
Interrupt Enable Registers. All GPIO interrupts are further
masked by the Global GPIO Interrupt Enable Bit in the Global
Interrupt Enable Register.
The Port Pull-up Registers are located at I/O address 0x08
and 0x09 for Port 0 and Port 1, respectively. The Port 0 and
Port 1 Data Registers are located at address 0x00 and 0x01
respectively. The Port 0 and Port 1 Interrupt Enable Registers
are at addresses 0x04 and 0x05, respectively.
Wake-up Interrupt
Power management is paramount in many USB applications.
To conserve power, the CY7C630xx/1xx supports an exter-
nally programmable interrupt input to wake up the microcon-
troller from the suspend mode. The suspend mode causes
the microcontroller to shut down most of its functions such as
the RISC core, the timer, and part of the SIE. In the mouse
application, a high percentage of the power is consumed by
the LEDs. Therefore, the CY7C630xx/1xx should be
programmed to power off the LEDs before entering the
suspend mode. With the LEDs powered off, the
CY7C630xx/1xx can no longer detect any mouse movements
although button closures are still recognized because
pressing a button could cause a GPIO interrupt to wake up
the microcontroller. Upon wakening, the device can check for
any changes and return to suspend mode if desired.
The wake-up interrupt can be implemented by connecting the
CEXT pin to VCC with a resistor and to GND with a capacitor.
Before the firmware puts the microcontroller into the suspend
mode, it writes a 0 to the Cext register at address 0x22 to
discharge the external capacitor. Then, to start timing, a 1 is
written to the Cext register to allow the RC circuit to begin
charging. A wake-up interrupt is generated to the RISC core
• San Jose, CA 95134 • 408-943-2600
October 30, 2003, rev. 0.A
 Converting CY7C630XX/1XX Designs to the CY7C637XX
when the external capacitor is charged up to nominal 2.75V
(45%–65% of VCC) by the external resistor. The duration
between successive wake-ups is controlled by the RC
constant of the external resistor and capacitor.
Introduction to the CY7C637xx
The CY7C637xx is an 8-bit RISC microcontroller with an
integrated USB SIE. The architecture executes general
purpose instructions that are optimized for USB applications.
The CY7C637xx has a built-in clock oscillator and timers as
well as programmable drive strength and pull-up resistors on
each I/O line. High-performance, low-cost human-interface-
type computer peripherals can be implemented with a
minimum of external components and firmware effort.
Clock Circuit
The CY7C637xx has a crystalless internal oscillator circuit that
eliminates the need for an external resonator or crystal. This
also frees up an additional input on the XTALIN line. At
power-up the internal oscillator operates within 5% of nominal
6 MHz. Then as USB traffic starts up, the internal oscillator will
tune itself to within 1.5% of the 6 MHz. An external oscillator
can be used if the application demands standalone clock
accuracy. In either mode, an internal clock doubler provides 12
MHz for the RISC core.
USB SIE
The internal SIE simplifies the interface to the USB bus for the
user. In the receive mode, USB packet decode and data
transfer to the endpoint FIFO are automatically done by the
SIE. The SIE then generates an interrupt request to invoke the
service routine after a packet is unpacked. In the transmit
mode, data transfer from the endpoint and the assembly of the
USB packet are handled automatically by the SIE.
General Purpose I/O
The CY7C637xx is available with 10 or 16 GPIO pins divided
into two ports: Port 0 and Port 1.
A GPIO pin can have two selectable drive strengths: CMOS
and resistive. CMOS mode is a general purpose mode used
for driving logic and other relatively fast signaling. In resistive
mode, the pin is pulled up internally via a 14-kΩ resistor.
The CY7C637xx also has three sink modes including a super
strong 50-mA mode for driving hard-to-drive components such
as optics. It should be noted that this microcontroller has a
current sink limit of 70-mA total on all I/O pins at one time.
In addition to these output modes, the CY637xx has two user
selectable input thresholds for interfacing with TTL and CMOS
level signaling.
If the CY7C637xx operates in the internal clock mode, the
XTALIN pin can act as an input.
When the VREG output is disabled, the VREG pin may also
act as an input. The state of the VREG pin can be read at the
Port 2 Data Register. The D+ and D- pins are normally used
for the USB interface. However, these pins can optionally be
configured in Hi-Z mode or with internal pull up resistors to
support PS/2 interface. This means that USB and PS/2 can
coexist on the same signal pins.
2
Voltage Regulator
The CY7C637xx has a built in 3.3V regulator that is designed
to drive the USB D- pull-up resistor. This regulator supplies a
small amount of current and should not be used as a
general-purpose regulator. The output resistance of this
regulator is 200Ω, which necessitates a 1.3-kΩ resistor as a
pull-up on the D- line to create the 1.5-kΩ resistor required by
the USB specification.
The VREG pin is automatically turned off by the SIE during
USB data transmission, so this pin should not be used as a
general purpose voltage reference.
When disabled, the VREG pin can act as an input and is read
via the Port 2 Data Register
The Hardware Differences
Clocking
The CY7C630xx/1xx requires an external oscillator. The
feedback capacitors and bias resistor are integrated into the
chip. Therefore, the CY7C630xx/1xx requires no external
components other than a 6MHz resonator.
The CY7C637xx gives the users the options to operate with
the internal on chip oscillator or an external oscillator. At reset,
the CY7C637xx begins operation using the internal clock by
default. The internal clock is set to a nominal frequency of
6 MHz and requires no external components. The user can
choose to operate from an external oscillator by setting bit 0 of
the Clock Configuration Register to 1. Once this bit is set, the
internal clock is halted, disabled, and the external oscillator is
enabled. In the external clock mode, there are no on-chip
capacitors, so the capacitors must be provided externally with
the 6-MHz oscillator.
While in external clock mode, the chip can be switched to the
internal clock when waking from suspend mode. Clearing bit
0 of the Clock Configuration Register will not reenable the
internal clock until suspend mode is entered. In the internal
clock mode, firmware must set the Precision USB Clocking
Enable bit of the Clock Configuration Register at address 0xF8
to allow the internal clock to precisely tune itself to USB timing
requirements (6 MHz ±1.5%).
Memory Organization
The memory in the CY7C630xx/1xx and CY7C637xx is
organized into user program memory in EPROM space and
data memory in SRAM space.
The CY7C630xx/1xx includes 128 bytes of data RAM. The
upper 16 bytes of the RAM from address 0x70 to 0x7F are
used for Endpoint 0 and Endpoint 1 FIFOs. The rest of the data
RAM from address 0x00 to 0x6F are used for the Program
Stack Pointer (PSP), Data Stack Pointer (DSP), and
user-defined variables.
The CY7C637xx includes 256 bytes of RAM. The upper 24
bytes of the data RAM from address 0xE8 to 0xFF are used
for Endpoint 0, Endpoint 1, and Endpoint 2 FIFOs. The rest of
the lower-data RAM is used for PSP, DSP, and user-defined
variables. Figure 1 below shows the organization of the data
RAM for the CY7C630xx/1xx and CY7C637xx.
 Converting CY7C630XX/1XX Designs to the CY7C637XX
Bottom of RAM Top of RAM
(address 00h) (CY630xx/1xx: 7Fh
CY637xx: 0xFF)
Program Stack Pointer (PSP), Data Stack Pointer Endpoint
(DSP), and user-defined variables FIFOs
Start of FIFO
(CY630xx/1xx: 0x70
CY637xx: 0xE8)
Figure 1. Data Memory (RAM) Organization
The CY7C630xx/1xx is available with 4 Kbytes of EPROM.
The first lower 16 bytes of the EPROM from address 0x0000
to 0x0010 are reserved for interrupt vectors, and the rest of the
EPROM is used for storing program code. The
CY7C630xx/1xx program memory begins at address 0x0011.
The CY7C637xx is available with 8 Kbytes of EPROM. The
first lower 24 bytes of the EPROM from address 0x0000 to
0x0018 are reserved for interrupt vectors. Due to some added
features, the CY7C637xx supports more interrupts than the
CY7C630xx/1xx. The CY7C637xx program memory begins at
address 0x0019. Figure 2 below shows the organization of the
EPROM for the CY7C630xx/1xx and CY7C637xx.
After Reset Top of EPROM
(address 00h)
Interrupt On-chip program Memory
Vectors
Program memory starts
(CY630xx/1xx: 0x0011
CY637xx: 0x0019)
Figure 2. Program Memory (EPROM) Organization
Reset
When a reset occurs, all registers are restored to their default
states, the USB device address is set to 0, all interrupts are
disabled, and both the CY7C630xx/1xx and CY7C637xx
microcontrollers resume execution from address 0x00.
The CY7C630xx/1xx supports three types of resets:
Power-On Reset (POR), USB Bus Reset, and Watchdog
Reset (WDR).
The CY7C637xx supports three types of resets: Low-Voltage
Reset (LVR), Brown-Out Reset (BOR), and Watchdog Reset
(WDR).
The CY7C630xx/1xx POR is triggered every time the device
is switched on. At the end of POR, the CY7C630xx/1xx is
automatically placed in suspend mode and waits for a USB
Bus Reset, or USB bus activities (D- is LOW) to terminate the
suspend mode; the microcontroller then begins execution from
ROM address 0x00.
When the CY637xx is switched on, the LVR is triggered. This
LVR stays asserted until Vcc rises above Vlvr (3.5V < Vlvr <
4.0V). At this point, the CY7C637xx automatically enters a
partial suspend state for TSTART ms (24 ms < TSTART< 60ms).
3
This TSTART delay timer gives Vcc time to stabilize before begin
executing code. After a TSTART delay, the microcontroller starts
executing code from the ROM address 0x00.
In addition to the LVR, the CY7C637xx features a BOR which
is automatically turned on when LVR is disabled. In suspend
mode, only BOR is active, giving a reset if Vcc drops below
approximately 2.5V. In this mode, the chip consumes very little
power. Since the device is suspended and code is not
executing, this lower voltage is safe for retaining the state of
all registers and memory.
The CY7C630xx/1xx USB Bus Reset occurs when a Single
Ended Zero (SE0) condition persists for 8 to 16 µs. The
CY7C630xx/1xx treats the USB Bus Reset as a hard reset
where it resets all the internal registers to their default values
and executes code from address 0x00.
The CY7C637xx treats the USB Bus Reset as an interrupt.
Whenever the host sends an USB Bus Reset, the CY7C637xx
USB Bus Reset interrupt is generated. This interrupt stays as
a pending interrupt and will be serviced when the USB Bus
Reset Interrupt bit is enabled in the Global Interrupt Enable
Register at address 0x20.
The CY7C630xx/1xx and CY7C637xx Watchdog Resets are
similar. A WDR occurs whenever the internal Watchdog Timer
rolls over. Writing any value to the Watchdog Reset Register
clears the timer.
Wake-up Circuitry
Wake-up interrupt is used to perform periodic checks on any
changes to the device while the microcontroller is placed in the
suspend mode.
The CY7C630xx/1xx uses an external RC timing circuit to
trigger a wake-up interrupt at the Cext pin. By changing the
values of the external resistor and capacitor, the user can tune
the rate of these interrupt events.
The CY7C637xx has a wake-up timer integrated. This timer
generates periodical interrupts when it is activated. The rate of
these wake-up interrupts can be adjusted by the user through
the Wake-up Timer Adjust bits in the Clock Configuration
Register. The wake-up timer functions as the RC Cext circuit
of the CY7C630xx/1xx with no external parts needed.
Power-up
When the CY7C630xx/1xx is first powered up, the POR
automatically puts the chip into the suspended mode. The chip
stays suspended until a USB Bus Reset, or USB Bus activity,
or an external interrupt occurs.
When the CY7C637xx is switched on LVR automatically puts
the chip into the partial suspended mode for a TSTART ms
(24 ms < Tstart < 60 ms). After this TSTART period, the micro-
controller begins execution from ROM address 0x0000.
Suspend
While in the suspended mode, the CY7C630xx/1xx can only
be awaken by external events such as a GPIO interrupt, USB
activity, or Cext interrupt.
In suspend mode, the CY7C637xx can be awaken by either
the internal wake-up timer, or an external event such as a
GPIO interrupt or USB activity (D- LOW).
 Converting CY7C630XX/1XX Designs to the CY7C637XX

GPIO Table 4. CPU B Instructions Only

The CY7C630xx/1xx is available in 20- or 24-pin packages. Instruction Opcode Description
The 20-pin package has 12 GPIOs, and the 24-pin package
has 16 GPIOs. CALL 5xh Call address from lower 4K to
upper 4 KB of ROM
The CY7C637xx is available in 18- and 24-pin packages. The
18-pin package features 10 GPIOs, and the 24-pin package CALL 9xh Call address from lower 4K to
features 16 GPIOs. If the chip operates in the internal clock lower 4 KB of ROM
mode, the XTALIN pin at Port 2 can be used as input port. DI 70h Disable Interrupts
Each GPIO pin of the CY7C630xx/1xx is integrated with an EI 72h Enable Interrupts
Isink DAC for sink current capability. The user can select 16
levels of current sink by setting the Isink bits of the Port Isink MOV X,A 40h Move A into X
Register. MOV A,X 41h Move X into A
The CY7C637xx does not have the DAC feature. Instead, Port MOV PSP,A 60h Move A into Program Stack
Mode Registers are implemented to determine the driving Pointer
state of each pin. RETI 73h Return from Interrupt
The driving state of each GPIO pin of the CY7C630xx/1xx is
determined by the state of its associated Port Pull-up Register The interrupt enable/disable mechanism was revised in CPU
bit and Data Register bit. The DAC on Port 0 can sink up to B. The mechanism combines hardware and software control
1.5 mA, and Port 1 can sink up to 24 mA. without writing over the Global Interrupt Enable register
(0x20), thus eliminating the need to restore its contents prior
The driving state of each GPIO pin of the CY7C637xx depends
to returning from the ISR (required for CPU A). The hardware
on its associated Data Register bit and its Port Mode bits.
control disables interrupt when an interrupt is acknowledged
Depending on the mode, the CY7C637xx can sink 2, 8, or up
and enables interrupts when the ‘RETI’ instruction is executed
to 50 mA.
at the end of an ISR.
Vreg Interrupts can be enabled by the ‘EI’ instruction or disabled by
For device detection purposes, the USB specification requires the ‘DI’ instruction. While interrupts are automatically disabled
low-speed devices to have a 1.5 KΩ resistor connected when entering an ISR, they can be reenabled before the end
between D- and Vreg of approximately 3.3V, or equivalent. of the ISR with an ‘EI’ instruction if desired.
The CY7C637xx has an integrated voltage regulator which The ‘CALL’ instruction allows the firmware to call subroutines
can be used to pull up D-. Since the Vreg output pin has an in the upper 4K of ROM.
internal series resistance of approximately 200Ω, the external The added ‘MOV’ instructions allow more flexible usage of the
pull-up resistor needed is 1.3 KΩ. ‘X’ register, and the ‘MOV PSP, A’ instruction allows the
firmware to initialize the program stack pointer.
CPU Version
The CY7C630xx/1xx contains CPU version A while the Endpoint
CY7C637xx contains CPU version B. The differences The CY7C630xx/1xx has two endpoints: Endpoint 0 for control
between CPU A and CPU B are in their instruction sets. The transfer and Endpoint 1 for interrupt transfer. There are three
below tables show the differences in the instruction set. registers used to control communication to/from the endpoints:
the USB Endpoint RX Register, USB Endpoint TX Register,
Table 2. CPU A and B Instructions That Are Different and USB Status and Control Register.
Instruction Opcode Description The CY7C637xx has three endpoints: endpoint 0 for control
RET 3Fh Return transfer, Endpoint 1 and 2 for interrupt transfers. Communi-
(flags handled differently as cation to/from the endpoints is controlled by three registers:
explained below) USB Endpoint Mode Register, USB Endpoint Counter
Register, and USB and Status Control Register.
CPU A restores the C and Z flags from stack when ‘RET’ is
executed. CPU B does not alter the C and Z flags when ‘RET’ SIE
is executed. The SIE is integrated in both of the CY7C630/1xx and
CY7C637xx. The SIE’s responsibility is to simplify the
Table 3. CPU A Instructions Only interface between the USB bus and the microcontrollers.
Instruction Opcode Description Some of the responsibilities of the SIE are:
IPRET 1Eh I/O write, pop, return • Detects new incoming transaction, determines its type
(set-up, IN, or OUT) and flags the microcontrollers.
The IPRET instruction combines three instructions which are • For received data, translates the encoded received data and
IOWR GLOBAL_INTERRUPT, POP A, and RET to ensure the data toggle state from the bus and stores them in the
stacks are restored at the end of interrupt service before endpoint’s buffer and data toggle bit in the microcontroller.
another interrupt can occur.
• For transmitted data, translates data in the endpoint’s buffer
to a format used by the USB bus. Sends data toggle bit with
the data onto the bus.

4
 Converting CY7C630XX/1XX Designs to the CY7C637XX
• Calculates the CRC error checking bits upon receiving or
transmitting data and flags the microcontroller if erroneous
data is received.
• Sends handshake packets (ACK, NAK, STALL) to the host.
• Triggers interrupts.
The CY7C630/1xx SIE’s responses to the USB transactions
depend on the contents of the USB Endpoint RX Registers,
Endpoint TX Configuration Registers, and USB Status and
Control Register. For example, setting the INEN bit (bit 7 in the
Endpoint TX Register) enables the SIE to respond to IN
packets.
The CY7C637xx SIE’s responses to the USB packets depend
on the Endpoint Mode Register and Endpoint Counter
Register. The Mode Bits, Bits[3:0] in the USB Endpoint Mode
Registers (address 0x12, 0x14 and 0x16) are crucial bits that
put the endpoints in different modes which determine how the
endpoints respond to USB packets sent from the host. Details
about the CY7C637xx Endpoint Modes can be obtained from
the USB Mode Tables of the CY7C637xx data sheet.
An advanced feature of the CY7C637xx’s SIE is the Register
Locking Function. The CY7C637xx Endpoint 0 Mode and
Counter Registers are locked from CPU write operations
Table 5. The Differences between CY7C630xx/1xx and CY7C637xx
Item CY7C630xx/1xx
Clocking External Clock required. The Xtalin pin cannot
be used as input
Memory Organization 128 Bytes RAM/Up to 4 KBytes ROM
Reset POR, WDR, and USB Bus Reset
Wake-up Circuitry External R-C timing circuit generates Cext
interrupts
Power-Up At power-up, POR puts the chip in suspend
mode. D- LOW wakes the chip up
Suspend An external event wakes the chip
GPIO Sink Current Less output configuration choices. DAC is
implemented. Depending on the Port, 16
levels of sink current ranging from 0.2 to
24-mA
GPIO Source Current Pull-up with Rup resistor only
SIE The SIE’s responses to USB packets depend
on the contents of the USB Endpoint RX and
TX Registers. No register locking function
Interrupts The first lower 16 bytes of EPROM are
reserved for interrupt vector. Cext interrupt is
replaced with Wake-up interrupt
When servicing an interrupt, hardware
disables all interrupts by clearing the Global
Interrupt Enable Register (GIER).
“ipret” instruction is used to exit ISR with inter-
rupts reenabled.
5
whenever their contents have been updated by the SIE. This
is usually the result of the host sending a new set-up, IN, or
OUT packet to the device. Performing an ‘IORD’ to these
registers will un-lock them. The purpose of performing this
‘IORD’ is to ensure that the device has acknowledged the
update and avoid new set-up data being over written.
Additional Features of The CY7C637xx
The CY7C637xx has some additional features that the
CY7C630xx/1xx does not have. Because the main purpose of
this application note is to provide help on migrating the
CY7C630xx/1xx designs to the CY7C637xx, these added
features will not be discussed in detail.
• Serial Peripheral Interface (SPI)
The CY7C637xx is SPI compatible. SPI circuit supports
byte serial transfer in either Master or Slave mode.
• Capture timers
The CY7C637xx Capture Timer Registers can be used to
mark the time at which GPIO events occur.
Table 5 below summarizes the differences.
CY7C637xx
External or Internal Clock. Xtalin is available as input
if the chip is in internal clock mode
256 Bytes RAM/Up to 8 Kbytes ROM
LVR, BOR, WDR (USB Bus Reset is treated as an
interrupt)
Internal Wake-up Timer is programmed to wake the
microcontroller periodically
At power-up, LVR puts the microcontroller in a partial
suspend mode for a TSTART ms. After this TSTART
delay, the chip starts executing from address 0x00
An external event or an internal wake-up interrupt
wakes the chip
Different drive strengths, pull-up resistances and
modes. No DAC. Depending on the mode, Isink
ranges from 2 to 50 mA
Pull-up with 14K or 2-mA source current
The SIE’s responses to USB packets are determined
by the endpoint modes. Register locking function is
implemented
The first lower 24 bytes of EPROM are reserved for
interrupt vector. Additional interrupts such as SPI
interrupt, Bus Reset Interrupt, Capture Timer A/B
interrupts and Endpoint 2 interrupt with different
priority order
When servicing an interrupt, the hardware disables
interrupts by clearing bit 2 in the Processor Status and
Control Register; the contents of GIER stay
unchanged.
DI, EI, RETI instructions are used to enable/disable
interrupts.
 Converting CY7C630XX/1XX Designs to the CY7C637XX
Table 5. The Differences between CY7C630xx/1xx and CY7C637xx (continued)
Item CY7C630xx/1xx
Global Interrupt Enable All interrupts are masked by the GIER,
Register (GIER) including endpoint interrupts
Vreg No Vreg. 7.5K Ohms is connected between
Vcc and D- as a work-around solution
CPU CPU version A
Endpoint Two endpoints
Additional features of N/A
CY7C637xx
Suggested Firmware Changes
It is strongly recommended that developers use the
CY7C637xx framework as a starting point when migrating their
designs. The CY7C637xx framework provides a clean USB
enumeration firmware; therefore, starting with the framework
ensures that the developers start with a known enumerated
device and avoid migrating the bulky enumeration code.
Contact us at www.cypress.com/support for the framework. In
this application note, the CY7C63000 mouse reference design
firmware is used as an example.
In the sample firmware below, the old CY7C630xx/1xx mouse
code is always commented out with a “;Cy630/1xx” label.
The “;CY637xx” labels signal the beginning of the substitution
code for the old CY7C630xx/1xx. The “;CY630/1xx and
CY637xx” labels mean the code stays unchanged because
they work for both the CY7C630xx/1xx and CY7C637xx. And
the “;CY637xx only” labels mean that the code is specific to
the CY7C637xx family only.
Initialization
Almost all of the CY7C630xx/1xx registers are located at
different locations in the CY7C637xx. In addition, there are
some I/O registers that are available in the CY7C630xx/1xx
but not in the CY7C637xx such as the USB Endpoint TX
Configuration Register, USB Endpoint RX Register, Cext
Register, Port Pull-up Register, and Port Isink Register. Some
of the I/O registers are specially available in the CY7C637xx
such as Port Mode Registers, Endpoint Counter Registers,
Endpoint Mode Registers, Endpoint Interrupt Enable Register,
Clock Configuration Register.
There are some bits in the I/O registers that both the
CY7C630xx/1xx and the CY7C637xx use in the USB commu-
nication such as DATA_VALID, BUS_ACTIVITY,
DATA_TOGGLE bits,...etc. The locations of these bits in the
CY7C637xx registers are different, so they should be taken
into consideration when migrating the code.
The CY7C637xx framework includes the header file that
defines the definitions of the CY7C637xx bits and registers. As
a result, starting with the CY7C637xx framework helps avoid
any errors caused by the above mentioned differences.
The CY7C630xx/1xx sample firmware chooses the end of the
user defined variable memory block at address 0x70 as the
starting point for the DSP. The CY7C637xx framework, on the
other hand, reserves the first lower 32 bytes of the data RAM
from address 0x00 to 0x20 for the DSP and PSP (some appli-
cations might need a bigger stack size). Either way works for
6
CY7C637xx
Endpoint interrupts are masked by Endpoint Interrupt
Enable Register. Other interrupts are masked by the
GlER
Vreg is integrated on chip. 1.3KΩ connected from D-
to Vreg is required to pull D- up
CPU version B
Three endpoints
SPI, 12 bit Capture Timers, PS/2
either microcontrollers. Using the CY7C637xx framework,
developers must ensure that no user variables accidentally fall
in the lower first 32 bytes memory block assigned to the DSP
and PSP. Because of this difference, developers might have to
reorganize the RAM allocation in the design.
The CY7C630/1xx has two 8-byte endpoint FIFOs starting
from address 0x70 to 0x7F in the data RAM. The CY7C637xx
has three 8-byte endpoint FIFOs starting from address 0xE8
to 0xFF. These FIFOs serve as buffers to send or receive data
from the host. In the CY7C63000 mouse reference design
particularly, endpoint 1 is configured as an IN endpoint. When
the device detects any movement or button clicks, it loads the
new data into endpoint 1 FIFO to report to the host through
three variables, namely button_position, horiz_position, and
vert_position. The values of these variables correspond to the
addresses of endpoint 1 FIFO. Since the CY7C630/1xx and
CY7C637xx endpoint FIFO locations are different, any
variables associated with the endpoint FIFO locations should
be changed to ensure data is loaded to the correct CY7C637xx
endpoint FIFOs in the RAM space. Below is an example.
;CY630/1xx 78h is the starting address of the
;endpoint 1 FIFO.
;button_position: equ 78h
;CY637xx. F0h is the location of the first byte
;in the CY7C637xx endpoint 1 FIFO.
button_position: equ F0h
;In the CY7C630xx mouse design, the same
;changes are needed for horiz_position and
;vert_position
Reset Routine
The CY7C630xx/1xx supports three types of resets: POR,
USB Bus Reset, and WDR. The CY7C637xx also supports
three types of reset: LVR, BOR, and WDR. One of the big
differences between these families of microcontrollers is that
the CY7C637xx treats an USB Bus Reset as an interrupt while
the CY7C630xx/1xx considers a USB Bus Reset as another
hardware reset, which puts all the registers into their default
state. Figure 3. below summarizes how resets are handled in
the CY7C63000 mouse reference design and its suggested
CY7C637xx conversion. Note that, in these diagrams, inter-
rupts are not shown except the USB Bus Reset interrupt of the
CY7C637xx.
 Converting CY7C630XX/1XX Designs to the CY7C637XX

POR LVR
Partial
Suspend Suspend

USB Bus Reset After Tstart

or D- is LOW
POR LVR
!Bus Reset Reset
Reset Bus Reset or
POR, or WDR
WDR
USB Bus
WDR or
Wait Initialization Reset Interrupt
Bus Rst
Was a USB Was not a USB
Bus Reset Bus Reset
USB Bus Reset
Interrupt
Bus Reset EP 1 has not
been configured Wait
EP 1 hasn’t
EP1 has been EP 1 has been configured USB Bus Reset
configured been configured Interrupt.
Bus Reset Interrupt (Enable Vreg,
enable USB Address
reset PSP, ...)
Main Task Loop

CY7C63000 Mouse CY7C637xx Converted Version

Figure 3. Resets in The CY7C63000 Mouse Design and Its Converted CY7C637xx

Upon reset, DSP and PSP are reset to 0x00. The DSP grows
down with a predecrement, while the PSP grows upward with
post-increment. The user’s firmware must set the DSP to an
appropriate address to avoid DSP overwriting the endpoint
FIFO. As discussed above, in the CY7C630/1xx designs, the
firmware may set the DSP to the start of endpoint 0 FIFO while
in the CY7C637xx, the first lower bytes of RAM are normally
used for the DSP and PSP and the user selects the starting
address for the DSP. In the example below, 0x1F is chosen to
be the starting address for the DSP, allocating 32 bytes for the
stacks. In other words, 0x00 to 0x1F of data RAM are now
reserved for the DSP and PSP.
Reset:
;CY630/1xx, DSP is set to the start of
;endpoint 0 and swap to avoid dsp writing
;over endpoint 1 FIFO
;mov A, endpoint_0
;swap A, dsp
;CY637xx. In this example DSP is set to 1Fh.
mov A, 1Fh
swap A, dsp
At power-up, the CY7C637xx runs in the internal clock mode
by default. Firmware can enable/disable the output of the
internal oscillator at the XTALOUT pin, or run with an external
oscillator by setting the Clock Configuration Register at
address 0xF8. Note that the Precision USB Clocking Enable
bit must be set to ‘1’ to cause the internal clock to automatically
precisely tune to USB timing requirements (6 MHz ±1.5%).
The Wake-up Timer Adjust Bits are used to program the
periodical wake-up interval when the microcontroller goes into
suspend mode. The below example sets the microcontroller to
operate with the internal oscillator and this setting should be
done by firmware at reset as below.
;CY7C637xx only. Set for use with internal
;oscillator. Wake-up Adjust Bits are used to
;programmed the internal wake-up interrupt.
mov A, (WakeUp_Adjust2 | WakeUp_Adjust0 |
INTERNAL_CLK | CLK_PRECISION_ENABLE)
iowr Clock_Config
The GPIO configurations are usually being done at reset. The
CY7C630xx/1xx uses the Port Pull-up Register and Port Data
Register to configure each GPIO pin as an input or output. The
CY7C630xx/1xx driving capability of each GPIO pin is
programmed by setting the Isink bits of the Port Isink Register.
In the CY7C637xx, the Port Pull-up Register, Port Data
Register, and Port Isink Register are not implemented and
should be commented out from the code. On the other hand,
the CY7C637xx features Port Mode Registers and Port Data
Registers to configure each GPIO pin. Note that the DAC is
not implemented on the CY7C637xx. Below is an example of
how to set Port 1 pin 1 to sink up to 50mA for the LED.
;CY630/1xx. LED_Current equals 0x0f which is
;maximum current drive
;mov A, LED_Current.
;iowr Port1_Isink0
;Port Pull up Registers are not implemented on
;the CY637xx, and should be commented out from
;the converted CY637xx codes.
;mov A, 0h
;iowr Port1_Pullup

7
 Converting CY7C630XX/1XX Designs to the CY7C637XX
;CY7C637xx. LED_Current_mode0 = 01h, and
;LED_Current_mode1 = 01h. This sets Port 1 pin
;1 to mode 11 which is capable of sinking 50 mA
;for the LED and other pins in Port 1 to mode
;00 which is Hi-Z
mov A, LED_Current_mode0
iowr Port1_Mode0
mov A, LED_Current_mode1
iowr Port1_Mode1
;turn on the LED on Port 1 bit[0]
mov A, 0feh
iowr Port1_Data
All the variable initializations should stay unchanged since
they are not affected by the types of microcontrollers used.
The CY7C630xx/1xx USB Device Address Register at
address 0x12 contains a 7-bit USB address that the host
assigns the device. The most significant bit, bit 7, is unused.
The CY7C637xx USB Device Address Register at address
0x10 has the same functionality, but the 7th bit is used to
enable/disable this register. The CY7C637xx firmware must
set this bit to ‘1’ for the SIE to respond to any USB traffic to this
address. Below is the code that enables the CY7C637xx USB
Device Address.
;CY637xx. Enabling the USB Device Address
mov A, ADDRESS_ENABLE
iowr USB_Device_Address
The CY7C637xx features an integrated voltage regulator set
at approximately 3.3V for pulling D- up in USB applications. In
order to utilize this feature, the firmware must set the VREG
Enable bit of the USB Status and Control Register (address
0x1F) to ‘1’ to allow the 3.3V output voltage to appear on the
Vreg pin of the chip. Below is the code that enables Vreg.
;CY7C637xx. Enable Vreg pin.
mov A, VREG_ENABLE
iowr USB_Status_Control
In the CY7C63000 mouse reference design, when a reset
occurs, the firmware performs the following routines:
1. Initializes variables and I/O registers.
2. Determines what type of reset has occurred by reading the
bits in the Status and Control Register, and takes appro-
priate reaction.
a. If a USB Bus Reset has occurred, the firmware stays in
a loop and waits for endpoint 1 to be configured. The
1-ms_interrupt and enpoint0_interrupt are enabled to
respond to the enumeration process happening at
endpoint 0.
b. If a WDR has occurred, the firmware stays in an infinite
loop and waits for a USB Bus Reset. The 1-ms_interrupt
is enabled to put the chip into the sleep mode if there is
no bus activity in 3 ms.
c. Otherwise, the firmware puts the microcontroller into
suspend mode by writing 0x09 to the Status and Control
Register.
3. Jumps to the “main” function as soon as endpoint 1 is
enabled (enumeration process is done).
8
As mentioned above, the CY7C637xx treats the USB Bus
Reset as an interrupt. Because of this difference, the flow of
the converted CY7C637xx firmware should be changed as
follows.
1. Initializes variables.
2. Enables USB Device Address and Vreg.
3. Stays in a loop and waits for endpoint 1 to be configured.
4. Jumps to the “main” function as soon as endpoint 1 is
enabled (enumeration process is done).
In the CY7C637xx, the USB Bus Reset interrupt is masked by
bit 0 of the Global Interrupt Enable Register. The interrupt will
stay as a pending interrupt and will not generate an interrupt
request until the USB Bus Reset bit (bit 0) of the Global
Interrupt Enable Register is set to ‘1’. At the end of the USB
Reset ISR, there is a “jmp” instruction to a reset routine.
Because the USB Bus Reset ISR does not perform a “ret” or
“reti” at the end of the ISR, firmware must reset the PSP to
remove the two bytes program counter that the hardware
automatically pushes onto the PSP stack as part of servicing
the interrupt.
Interrupt Service Routines
Due to the differences in architectures and some new added
features of the CY7C637xx, the interrupt vectors of the
CY7C637xx and the CY7C630/1xx are different. The
CY7C637xx has some additional interrupts such as USB Bus
Reset interrupt, Endpoint 2 interrupt, and Capture Timer A/B
interrupts. While converting firmware, the user should ensure
that all the CY7C637xx firmware includes all the interrupts in
a correct order. Unused interrupts should be serviced by a
“DoNothing_ISR” interrupt service routine which does nothing
but return with interrupts enabled.
In the CY7C630xx/1xx, all interrupts are masked by the Global
Interrupt Enable Register, including endpoint interrupts. The
CY7C637xx separates endpoint interrupts with others by
having the Endpoint Interrupt Enable Register specially
designed for masking endpoint 0, endpoint 1, and endpoint 2
interrupts. Other CY7C637xx interrupts are masked by the
Global Interrupt Enable Register. Therefore, modifying the
CY7C630/1xx Global Interrupt Enable Register is equivalent
to modifying both the Endpoint Interrupt Enable Register and
Global Interrupt Enable Register of the CY637xx as the
example below illustrates.
;CY7C630/1xx. Enable 1ms and endpoint 0
;interrupts by writing to the Global Interrupt
;Enable Register.
;mov A, 1MS_INT_AND_EP0_INT
;mov [interrupt_mask],A
;iowr Global_Interrupt
;CY7C637xx. Enable 1ms Interrupt in the Global
;Interrupt Enable Reg and EP0 interrupt in the
;Endpoint Interrupt Register
mov A, 1MS_INT
iowr Global_Interrupt
mov A, EP0_INT
iowr Endpoint_Interrupt
ei
 Converting CY7C630XX/1XX Designs to the CY7C637XX
The CY7C630xx/1xx is a type A CPU. When servicing an
interrupt, the CY7C630xx/1xx hardware first disables all inter-
rupts by clearing all the bits in the Global Interrupt Enable
Register. As a result, in order to restore the interrupts that were
enabled before entering the ISR, the CY7C630xx/1xx
firmware usually keeps a shadow of the Global Interrupt
Enable Register and writes this shadow to the Global Interrupt
Enable Register to reenable interrupts when necessary. The
CY7C637xx, on the other hand, is a type B CPU, which
handles interrupts differently. When servicing an interrupt, the
CY7C637xx hardware disables all interrupts by clearing the
internal interrupt enable control bit (or Interrupt Enable Sense
bit). The state of this bit can be read at bit 2 of the Processor
Status and Control Register (0xFF). This internal Interrupt
Enable Sense bit is a read-only bit. Therefore, writing over this
bit has no effects. Instructions ‘DI’, ‘EI’, and ‘RETI’ are used to
manipulate this bit to enable/disable the interrupts in the
Global Interrupt Enable Register and Endpoint Interrupt
Enable Register. Below is an example of an interrupt service
routine which does nothing but returns with interrupts
reenabled.
DoNothing_ISR:
;CY7C630/1xx. Return with interrupts enabled.
;interrupt_mask is used to keep a copy of the
;Global Interrupt Enable Reg. Firmware should
;reenable interrupts before leaving the ISR.
;“ipret” instruction is used in type A CPU only
;push A
;mov A, [interrupt_mask]
;ipret Global_Interrupt
;CY637xx. Return with interrupts enabled.
;In type B CPU, when servicing an interrupt,
;the bits in the Global Interrupt Enable
;Register are not cleared. “reti” sets bit 2
;of the Processor Status and Control Register
;to “1” which enables interrupts.
reti
The CY7C637xx has a register locking feature that is not
available in the CY7C630xx/1xx. The Endpoint 0 Mode and
Endpoint 0 Counter Registers are locked from CPU write
operations whenever their bits have been updated by the SIE.
This is usually the result of the host sending a new
set-up/IN/OUT packet to the device. Performing an ‘IORD’ to
these registers will unlock them. The purpose of doing this
‘IORD’ is to ensure that the device has acknowledged the
update and avoid new data being over written. When migrating
firmware, writing to the CY7C630xx/1xx RX and TX Registers
is equivalent to updating the CY7C637xx Mode and Counter
Registers, and because of the locking feature at Endpoint 0
Mode and Counter Registers, the CY7C637xx firmware
should carefully handle the locking mechanism on the control
endpoint. An example of how to handle the Endpoint 0 Mode
and Counter Registers locking mechanism is included in the
CY7C637xx framework.
9
Endpoint 0 ISR is primarily responsible for the enumeration
and configuration of the device. The endpoint 0 ISR parses
set-up packets and determines how to respond to these
control transfer requests. Starting with the CY7C637xx
framework, developers do not need to convert the enumer-
ation code because it has already been done in the framework.
The USB_EP1_ISR interrupt service routine handles most of
the USB communications at endpoint 1. In the
CY7C630xx/1xx mouse design, this interrupt is generated
after the mouse has transmitted a packet from endpoint 1 and
has received an ACK from the host. In the CY7C637xx, this
interrupt is generated even if the device is in NAK_IN mode
and has NAKed the IN request from the host. Therefore, in the
CY7C637xx design, the endpoint 1 ISR should only update the
Data Toggle bit when the interrupt is a result of a successful
ACK transaction. In this example, the data to be sent is loaded
into the endpoint 1 FIFO outside of the ISR, so this routine
mainly updates the Data Toggle bit for the next packet. It is
recommended that developers use the endpoint 1 ISR in the
CY7C637xx framework and migrate necessary code.
The 1-ms interrupt service routine is the place to enter
suspend mode if there is no bus activity in 3 ms. Most of this
code stays unchanged because this routine mainly manipu-
lates data RAM variables which are not processor specific.
Developers should only migrate what is necessary for their
specific applications.
The Wake-up interrupt is used to force the host to resume due
to a mouse movement or a button press. The CY7C630xx/1xx
mouse reference design uses Cext and an RC circuit to wake
the part up from sleep mode and sends a resume request to
the host if there are changes at the GPIOs. The CY7C637xx
is implemented with a wake-up timer which internally wakes
the part up periodically. When converting the firmwares, Cext
and its related variables should be commented out from the
code. Note that the frequency of the wake up interrupts in the
CY7C637xx is set by the Wake-up Adjust bits in the Clock
Configuration Register.
Main Routine
The “main” routine of the CY7C630xx/1xx mouse reference
design calls ReadButtons, CheckHorizontal, and CheckVer-
tical subroutines to update any button press or movement of
the mouse. These subroutines are not processor specific, so
no changes are required. The “main” routine then calls
send_packet subroutine to send any new data to the host.
Because the CY7C630xx/1xx uses the TX and RX Registers
while the CY7C637xx uses the Endpoint Mode and Endpoint
Counter Registers to control the endpoint’s responses to USB
traffic, the send_packet needs to be modified. Below is an
example of the modified send_packet function.
send_packet:
;CY630/1xx. Check if previous packet has
;been sent. If not, return to main routine.
;iord USB_EP1_TX_Config
;and A, 80h
;cmp A, 80h
;jz Nosend
;CY637xx. Check if previous packet has been
;sent. If not, return to main routine.
iord Endpoint1_Mode
and A, 0fh
 Converting CY7C630XX/1XX Designs to the CY7C637XX

;If packet has been sent, the mode should

;have been changed to NAK_IN.
;CY630/1xx and CY637xx. Code unchanged.
cmp A, ACK_IN ;If it received a new idle
mov A,[new_idle_flag]
jz Nosend
;Period 4 ms before the previous one
cmp A,0
;Cy630/1xx and CY637xx. Codes unchanged.
;Loading new data to endpoint 1 FIFO ;Counted finishes, need to upgrade
mov A, [horizontal] jz reset_idle_period_counter
mov [horiz_position], A mov A,[new_idle_period]
mov A, [vertical] mov [idle_period],A
mov [vert_position], A mov A,0
mov A, [buttons] mov [new_idle_flag],A
mov [button_position], A jmp reset_idle_period_counter
reset_idle_period_counter:
;CY630/1xx. Load Data Toggle, set to send 3 mov A,0
;bytes. mov [idle_period_counter],A
;iord USB_EP1_TX_Config
;Keep the data 0/1 bit mov [horizontal], A
;and A, DataToggle mov [vertical], A
;Enable transmit 3 bytes
mov [button_flag], A

;or A, 93h
;iowr USB_EP1_TX_Config Nosend:
jmp main
;CY637xx. Load Data Toggle, set to send 3
;bytes. Conclusions
iord Endpoint1_Count The CY7C630xx/1xx and CY7C637xx are functionally similar,
;Load Data Toggle Bit. This bit is updated but the CY7C637xx incorporates many useful features such
;in EP1_ISR as crystal-less oscillator, a “brown-out” detector, embedded
3.3V regulator, and integrated wake-up circuitry. This appli-
and A, DataToggle cation note together with the CY3654 + P05 development tool
;Set to send 3 bytes (for a mouse) will simplify the task of migrating the CY7C630xx/1xx designs
to the CY7C637xx to utilize additional useful features of the
or A, 3h
CY7C637xx.
iowr Endpoint1_Count
;Set the mode to ACK_IN to send data when
;the host issues an IN. After data has been All product and company names mentioned in this document are the trademarks of their
respective holders.
;sent, the SIE changes the mode to NAK_IN.
mov A, ACK_IN Approved AN074 10/30/03 kkv
iowr Endpoint1_Mode

10