Course Outcomes – EC8095-VLSI DESIGN

After successful Completion of the Course, the Students should be able to

CO1 Realize the concepts of digital building blocks using CMOS Transistors
CO2 Design Combinational MOS CIRCUITS and Power Stratergies
CO3 Design and construct Sequential circuits and Timing Systems
CO4 Design Arithmatic Building Blocks and Memory systems
CO5 Apply and Implement FPGA design flow and Testing

Knowledge Level (Blooms Taxonomy)

Applying
(Application
K1 Remembering (Knowledge) K2 Understanding (Comprehension) K3
of
Knowledge)
Creating
K4 Analysing (Analysis) K5 Evaluating (Evaluation) K6
(Synthesis)

Part Question Mapping with Course Outcomes and Knowledge Level

Part -A
Question No. 1 2 3 4 5 6 7 8 9 10
Course Outcome CO1 CO1 CO2 CO2 CO3 CO3 CO4 CO4 CO5 CO5
Knowledge Level K3 K3 K4 K3 K3 K3 K3 K3 K2 K3
Part Part –B Part - C
Question No. 11 (a) 11(b) 12(a) 12(b) 13(a) 13(b) 14(a) 14(b) 15(a) 15(b) 16 (a) 16(b)
Course Outcome CO1 CO1 CO2 CO2 CO3 CO3 CO4 CO4 CO5 CO5 CO3 CO1
Knowledge Level K3 K4 K4 K4 K4 K3 K4 K4 K3 K3 K4 K5
 Saveetha Nagar, Thandalam, Chennai –
602105
MODEL EXAM #4 – June 2021
Degree : B.E / Branch : ECE / Semester :VI Sem Date : 12.06.2021/Session :AN/ Duration : 3 hours
EC8095/ VLSI DESIGN Time : 4.PM to 7PM
Total Marks: 100

PART – A 10X2 = 20 marks

1. Determine the operating region of MOSFET biased with Vgs=1.5 V , Vds=2V,Vds(sat)=0.6V, Vt=0.4V.
2. What is Stick Diagram? Sketch the Stick Diagram for 3 input NAND Gate.
3. Compare Static CMOS ,Pseudo NMOS ,and Dynamic Inverter.
4. Show that CMOS gates are Power Efficient.
5. Define Clock skew and clock jitter.
6. Draw TSPCR.
7. What is propagation delay of n-bit ripple array multiplier?
8. Draw the Structure of 6T-SRAM cell.
9. What is a signature analyzer ?
10. Classify the Types of Stuck –at – Faults.

PART – B 13X5 = 65 marks

11(a) Explain the non-ideal characteristics of an n-MOS transistor in detail.

(or)
11(b) Analyze linear delay model and hence obtain the propagation delay of a unit CMOS inverter driving h-identical copies of itself.

12(a) Explain the operation of Domino logic and Dual rail Domino logic with necessary examples.
(or)

´
12(b) (i)Realize X = A . B+C ´ ´ ) . D as cascaded dynamic gates and explain its operation ( 5 Marks)
and Y = ( A . B+C
(ii)Apply inputs A=B=C=D=1. Draw the timing diagram depicting nodes X and Y. Identify and analyze the issues faced during cascading.
Suggest and explain an alternative circuit to eliminate the issues while cascading (8 Marks).
13(a) Discuss how pipelining is used to optimize sequential circuits. Design and construct NORA-CMOS logic pipelined structured
(or)

13(b) (i)Define Schmitt trigger and its properties. (6)

(ii) Realize CMOS implementation of Schmitt Trigger with neat diagram and explain its operation (7)

14(a) (i) Describe ripple carry adder and derive the expression for worst case delay. (6)
(ii)Explain Carry Bypass adders and derive the expression for worst case delay. (7)

(or)
14(b) (i) Construct a 3T Dynamic RAM and explain its read and write operation with necessary diagrams(7)
(ii) Explain Read/Write operation of 1T Dynamic RAM cell with necessary diagrams (6)

15 (a) Explain in detail the Manufacturing test principles which are deployed to screenout defective parts before the IC’s are shipped to customers
(or)
15 (b) Write short notes on the following :
(i) Ad-hoc Testing ( 3 Marks)
(ii) IDDQ Testing ( 5 Marks)
(iii) Stuck-at Faults model ( 5 marks)

PART – C 15X1 = 15 marks

16 (a) The timing parameters of the sequential circuit given as tc-q = 0.2ns, tsu =4ns, thold = 6ns , tlogic = 7ns
(i) Explain Clock skew with suitable timing diagrams. If δ = 0.25ns, determine the constraint on Minimum clock period .(6
Marks)
(ii) Explain Clock jitter with suitable timing diagrams. If tjitter1 = tjitter2 = 0.2ns, determine the constraint on Minimum clock
period .(6 Marks)
(iii)Determine the constraint on Minimum clock period considering both temporal and spatial variations in CLK. ( 3 Marks)
 (or)

´ + D).
16 (b) Consider the design of a CMOS compound OR-OR-AND-INVERT (OAI22) gate computing F=( A+ B)·(C
(i) Sketch a transistor-level schematic (4 Marks)
(ii) Sketch a stick diagram (5 Marks)
(iii) Sketch the Layout diagram (6 Marks)