EL320-Digital Design Lab # 03

Lab # 03
Hierarchical Design Using Gate Level Modeling

Objectives:
 Understand top-down and bottom-up design methodologies for digital design.
 Learning to make hierarchical designs using gates.
 Simulation of complex gate hardware models.
 Explain differences between modules and module instances in Verilog.
 Creating Instantiation of objects.

Explanation:
Hierarchical Design:
Another form of abstraction that allows us to manage design complexity is hierarchical composition.
This involves developing a subcircuit that performs some relatively simple function, then treating it
as a “black box.” Provided we adhere to assumptions made in designing the subcircuit, we can then
use it in a larger circuit that performs a more complex function. As an example, the subcircuit might
be a small liquid-crystal display (LCD) controller, which is used as part of the user interface of a
cordless phone.

Gate Level Modelling:

Verilog has built in primitives like gates, transmission gates, and switches. These are rarely used in
design (RTL Coding), but are used in post synthesis world for modelling the ASIC/FPGA cells; these
cells are then used for gate level simulation, or what is called as SDF simulation. Also, the output
netlist format from the synthesis tool, which is imported into the place and route tool, is also in
Verilog gate level primitives.

Module Instantiation in Verilog:

A module provides a template from which you can create actual objects. When a module is invoked,
Verilog creates a unique object from the template. Each object has its own name, variables,
parameters, and I/O interface.
The process of creating objects from a module template is called instantiation, and the objects are
called instances. Each instance is a complete, independent and concurrently active copy of a module.
A module can be instantiated in another module thus creating hierarchy.

Usman jan 15p-6444 Section EE-B

EL320-Digital Design Lab # 03

Task: 01
Half adder Module:

Test Fixture:

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EL320-Digital Design Lab # 03

Result:
The Output wave form shows that the module and test fixture is working well and give us the
addition of two bits.

Usman jan 15p-6444 Section EE-B

EL320-Digital Design Lab # 03

Task # 02

Full adder using two half adders through module instantiation.

Test Fixture:

Usman jan 15p-6444 Section EE-B

EL320-Digital Design Lab # 03

Usman jan 15p-6444 Section EE-B

EL320-Digital Design Lab # 03

Result:
The Output shows the actual behaviour of the module.

Task: 03
4x1 multiplexer using logic gates and simulating the results.

Usman jan 15p-6444 Section EE-B

EL320-Digital Design Lab # 03

Result:
Working as 4x1 Mux as given in the screenshot.

Checked by: __________________________________ Date: _________________

Marks: _______________________________________

Usman jan 15p-6444 Section EE-B